NXP Semiconductors LPC824M201JHI33, LPC822M101JHI33, LPC824M201JDH20, LPC822M101JDH20 User Manual

UM10800

LPC82x User manual

Rev. 1.2 — 5 October 2016 User manual

Document information

Info Content
Keywords LPC82x, LPC824M201JHI33, LPC822M101JHI33, LPC824M201JDH20,

LPC822M101JDH20, LPC82x UM, LPC82x user manual, LPC820

Abstract LPC82x User manual

NXP Semiconductors

UM10800

LPC82x User manual

Revision history

Rev Date Description

1.2 20161005 LPC82x User manual.
Modifications: • Updated Table 383 “Error codes”: added error codes 0x0006 0009 and 0x0006 000A.

• Added bits: 24 - ADC_RST_N; 29 - DMA_RST_N to Table 23 “Peripheral reset control register

(PRESETCTRL, address 0x4004 8004) bit description”.

• Added Section 12.5.7 “Channel chaining”.

1.1 20160524 LPC82x User manual.
Modifications: • Removed internal comments from Section 16.6.24 “SCT event enable registers 0 to 7”

• Changed main clock to system clock in the first paragraph in Section 26.5.1.1 “Param0: system PLL

input frequency and Param1: expected system clock”.

• Updated Section 25.6.2 “IAP commands”.

• Updated Table 308 “LPC82x flash configuration”: corrected the page num be rs of secto rs 21 - 31.

• Updated Section 16.6 “Register description” to fix the polarity for REGMODE.

– REGMODEn = 0: Registers operate as match and reload registers.
– REGMODEn = 1: Registers operate as capture and capture control registers.

• Changed signature generation start address (corresponds to AHB byte address bits[20:4]) to

signature generation start address (corresponds to AHB byte address bits[18:2]).

• Added a note to Table 236 “SCT DMA 0 request register (DMAREQ0, address 0x5000 405C) bit

description” and Table 237 “SCT DMA 1 request register (DMAREQ1, address 0x5000 C060) bit
description”.

• Changed the ISP entry pin in Section 31.5.2 “Debug connections for SWD” to PIO0_20; was

PIO0_1.

• Added reserved blocks in Table 222 “Register overview: State Configurable Timer SCT/PWM (base

address 0x5000 4000)”: 0x220 to 0x2FF before EV0_STATE 0x340 to 0x4FF before OUT0_SET

1 20140918 Initial revision. LPC82x User manual.

Contact information

For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [e-mail]

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User manual Rev. 1.2 — 5 October 2016 2 of 487

1.1 Introduction

UM10800

Chapter 1: LPC82x Introductory information

Rev. 1.2 — 5 October 2016 User manual

The LPC82x are an ARM Cortex-M0+ based, low-cost 32-bit MCU family operating at
CPU frequencies of up to 30 MHz. The LPC82x support up to 32 KB of flash memory and
8 KB of SRAM.

2

The peripheral complement of the LPC82x includes a CRC engine, four I
interfaces, up to three USARTs, up to two SPI interfaces, one multi-rate timer,
self-wake-up timer, and state-configurable timer with PWM function (SCTimer/PWM), a
DMA, one 12-bit ADC and one analog comp arator, function-configurable I/O port s through
a switch matrix, an input pattern match engine, and up to 29 general-purpose I/O pins.

C-bus

1.2 Features

Remark: For additional documentation, see Section 35.2 “References”

.

• System:

– ARM Cortex-M0+ processor (revision r0p1), running at frequencies of up to

30 MHz with single-cycle multiplier and fast single-cycle I/O port.

– ARM Cortex-M0+ built-in Nested Vectored Interrupt Controller (NVIC).
– System tick timer.
– AHB multilayer matrix.
– Serial Wire Debug (SWD) with four break points and two watch points. JTAG

boundary scan (BSDL) supported.

– Micro Trace Buffer (MTB)

• Memory:

– Up to 32 KB on-chip flash programming memory with 64 Byte page write and

erase. Code Read Protection (CRP) supported.

– 8 KB SRAM.

• ROM API support:

– bootloader.
– On-chip ROM APIs for ADC, SPI, I2C, USART, power configuration (power

profiles) and integer divide.

– Flash In-A pp licatio n Pro gr a mm in g (IAP ) an d In- Sys te m Pro gr a mmin g (ISP).

• Digital peripherals:

– High-spe e d GPI O in te r fac e co nn ec te d to the ARM Cort ex -M 0 + IO bu s wit h up t o

32 General-Purpose I/O (GPIO) pins with configurable pull-up/pull-down resistors,
programmable open-drain mode, input inverter, and glitch filter. GPIO direction
control supports independent set/clear/toggle of individual bits.

– High-current source output driver (20 mA) on four pins.
– High-current sink driver (20 mA) on two true open-drain pins.

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Chapter 1: LPC82x Introductory information

– GPIO interrupt generation capability with boolean pattern-matching feature on

eight GPIO inputs.

– Switch matrix for flexible configuration of each I/O pin function.
– CRC engine.
– DMA with 18 channels and 9 trigger inputs.

UM10800

• Timers:

– State Configurable Timer (SCTimer/PWM) with input and output functions

(including capture and match) for timing and PWM applica tio ns .

– Four channel Multi-Rate Timer (MRT) for repetitive interrupt generation at up to

four programmable, fixed rates.

– Self-Wake-up Timer (WKT) clocked from either the IRC, a low-power,

low-frequency internal oscillator, or an external clock input in the always-on power
domain.

– Windowed Watchdog timer (WWDT).

• Analog peripherals:

– One 12-bit ADC with up to 12 input channels with multiple internal and external

trigger inputs and with sample rates of up to 1.2 Msamples/s. The ADC supports
two independent conversion sequences.

– Comparator with four input pins and external or internal reference voltage.

• Serial peripherals:

– Three USART interfaces with pin functions assigned through the switch matrix and

one common fractional baud rate generator.

– Two SPI controllers with pin functions assigned through the switch matrix.

2

– Four I

on two true open-drain pins and listen mode. Three I2Cs support data rates up to
400 kbit/s on standard digital pins.

C-bus interfaces. One I2C supports Fast-mode plus with 1 Mbit/s data rates

• Clock generation:

– 12 MHz internal RC oscillator trimmed to 1.5 % accuracy that can optionally be

used as a system clock.

– Crystal oscillator with an operating range of 1 MHz to 25 MHz.
– Programmable watchdog oscillator with a frequency range of 9.4 kHz to 2.3 MHz.
– PLL allows CPU operation up to the maximum CPU rate without the need for a

high-frequency crystal. May be run from the system oscillator, the external clock
input, or the internal RC oscillator.

– Clock output function with divider that can reflect all internal clock sources.

• Power control:

– Integrated PMU (Power Management Unit) to minimize power consumption.
– Reduced power modes: Sleep mode, Deep-sleep mode, Power-down mode, and

Deep power-down mode.

– Wake-up from Deep-sleep and Power-down modes on activity on USART, SPI,

and I2C peripherals.

– Timer-controlled self-wake-up from Deep power-down mode.
– Power-On Reset (POR).

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– Brownout detect (BOD).

• Unique device serial number for identification.

• Single power supply (1.8 V to 3.6 V).

• Operating temperature range -40 °C to +105 °C.

• Available in a HVQFN33 (5x5) package.

1.3 Ordering options

UM10800

Chapter 1: LPC82x Introductory information

Table 1. Ordering information

Type number Package

LPC824M201JHI33 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no leads;

LPC822M101JHI33 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no leads;

LPC824M201JDH20 TSSOP20 plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360-1
LPC822M101JDH20 TSSOP20 plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360-1

Table 2. Ordering options

Type number Flash/KBSRAM/KBUSART I2C SPI ADC

LPC824M201JHI33 32 8 3 4 2 12 Y 29 HVQFN33
LPC822M101JHI33 16 4 3 4 2 12 Y 29 HVQFN33
LPC824M201JDH20 32 8 3 4 2 5 Y 16 TSSOP20
LPC822M101JDH20 16 4 3 4 2 5 y 16 TSSOP20

Name Description Version

n/a

33 terminals; body 5  5  0.85 mm

n/a

33 terminals; body 5  5  0.85 mm

Comparator GPIO Package

channels

1.4 General description

1.4.1 ARM Cortex-M0+ core configuration

The ARM Cortex-M0+ core runs at an operating frequency of up to 30 MHz. Integrated in
the core are the NVIC and Serial Wire Debug with four breakpoints and two watch points.
The ARM Cortex-M0+ core supports a single-cycle I/O enabled port (IOP) for fast GPIO
access at address 0xA000 0000. The ARM Cortex M0+ core version is r0p1.

The core includes a single-cycle multiplier and a system tick timer (SysTick).

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1.5 Block diagram

UM10800

Chapter 1: LPC82x Introductory information

LPC82xM

29 x

SWITCH
MATRIX

SWCLK, SWD

29 x
PIO0

HIGH-SPEED

PIN INTERRUPTS/
PATTERN MATCH

SCT_PIN[3:0]

SCT_OUT[6:0]

TXD, RTS

RXD, CTS

SCLK

SCK, SSEL
MISO, MOSI

SCL

SDA

XTALOUT

XTALIN

RESET, CLKIN

CLKOUT

GPIO

SCTIMER/

INPUT MUX

USART0/1/2

SPI0/1

I2C0/1/2/3

XTAL

PWM

TEST/DEBUG

INTERFACE

CORTEX-M0+

slave

AHB TO APB

SYSCON

ARM

BRIDGE

FLASH

16/32 KB

slave slave

AHB-LITE BUS

slave master

MULTI-RATE TIMER

ALWAYS-ON POWER DOMAIN

SRAM

4/8 KB

CRC

WWDT

IOCON

PMU

SELF

WAKE-UP TIMER

slave

DMA

ROM

ADC_[11:0]

ACMP_I[4:1]

VDDCMP

ACMP_O

ADC

COMPARATOR

IRC

WDOsc

BOD

POR

CLOCK

GENERATION,

POWER CONTROL,

SYSTEM

FUNCTIONS

clocks and

controls

aaa-014399

Grey-shaded blocks show peripherals that can provide hardware triggers for DMA transfers or
have DMA request lines.

Fig 1. LPC82x block diagram

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User manual Rev. 1.2 — 5 October 2016 6 of 487

UM10800

Chapter 2: LPC82x memory mapping

Rev. 1.2 — 5 October 2016 User manual

2.1 How to read this chapter

The memory mapping is identical for all LPC82x parts. Different LPC82x parts support
different flash and SRAM memory sizes.

2.2 General description

The LPC82x incorporates several distinct memory regions. Figure 2 shows the overall
map of the entire address space from the user program viewpoint following reset.

The APB peripheral area is 512 KB in size and is divided to allow for up to 32 peripher als.
Each peripheral is allocated 16 KB of space simplifying the address decoding.

The registers incorporated into the ARM Cortex-M0+ core, such as NVIC, SysTick, and
sleep mode control, are located on the private pe rip h er al bus.

The GPIO port and pin interrupt/pattern match registers are accessed by the ARM
Cortex-M0+ single-cycle I/O enabled port (IOP).

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2.2.1 Memory mapping

UM10800

Chapter 2: LPC82x memory mapping

4 GB

1 GB

0.5 GB

0 GB

LPC82x

reserved

private peripheral bus

reserved

GPIO PINT

GPIO

reserved

DMA

SCTimer/PWM

CRC

reserved

APB peripherals

reserved

reserved

12 KB boot ROM

reserved

4 KB MTB registers

reserved

4 KB SRAM1

4 KB SRAM0

reserved

32 KB on-chip flash

0xFFFF FFFF

0xE010 0000

0xE000 0000

0xA000 8000

0xA000 4000

0xA000 0000

0x5000 C000

0x5000 8000

0x5000 4000

0x5000 0000

0x4008 0000

0x4000 0000

0x2000 0000

0x1FFF 3000

0x1FFF 0000

0x1400 1000

0x1400 0000

0x1001 2000

0x1000 1000

0x1000 0000

0x0000 8000

0x0000 0000

APB peripherals

30 - 31 reserved

29

28

27

26

25

24

23

22

21

20

19

system control (SYSCON)

18

17

16
15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

active interrupt vectors

flash controller

DMA TRIGMUX

analog comparator

self wake-up timer

I2C3

I2C2

USART2

USART1

USART0

reserved

SPI1

SPI0

I2C1

I2C0

reserved

IOCON

reserved

reserved

reserved

reserved

input mux

PMU

12-bit ADC

reserved

reserved

reserved

switch matrix

MRT

WWDT

0x0000 00C0

0x0000 0000

0x4008 0000

0x4007 8000

0x4007 4000

0x4007 0000

0x4006 C000

0x4006 8000

0x4006 4000

0x4006 0000

0x4005 C000

0x4005 8000

0x4005 4000

0x4005 0000

0x4004 C000

0x4004 8000

0x4004 4000

0x4004 0000

0x4003 C000

0x4003 8000

0x4003 4000

0x4003 0000

0x4002 C000

0x4002 8000

0x4002 4000

0x4002 0000

0x4001 C000

0x4001 8000

0x4001 4000

0x4001 0000

0x4000 C000

0x4000 8000

0x4000 4000

0x4000 0000

The private peripheral bus includes the ARM Cortex-M0+ peripherals such as the NVIC, SysTick, and the core control registers.

Fig 2. LPC82x Memory mapping

2.2.2 Micro Trace Buffer (MTB)

The LPC82x supports the ARM Cortex-M0+ Micro Trace Buffer. See Section 31.5.4.

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UM10800

Chapter 3: LPC82x Boot ROM

Rev. 1.2 — 5 October 2016 User manual

3.1 How to read this chapter

The bootloader is identical for all parts.

3.2 Features

• 12 KB on-chip boot ROM

• Contains the bootloader with In-System Programming (ISP) facility and the following

APIs:

– In-Application Programming (IAP) of flash memory
– Power profiles for optimizing power consumption and system performance
– USART driver
– ADC driver
– SPI driver
– I2C driver
– Integer divide routines

3.3 Basic configuration

The clock to the ROM is enabled by default. No configuration is required to use the ROM
APIs.

3.4 Pin description

When the ISP entry pin is pulled LOW on reset, the part enters ISP mode and the ISP
command handler starts up. In ISP mode, pin PIO0_0 is connected to function U0_RXD
and pin PIO0_4 is connected to function U0_TXD on the USART0 block.

Table 3. Pin location in ISP mode

ISP entry pin USART RXD USART TXD

PIO0_12 PIO0_0 PIO0_4

3.5 General description

3.5.1 Bootloader

The bootloader controls initial operation after reset and also provides the means to
accomplish programming of the flash memory via USART. This could be initial
programming of a blank device, erasure and re-programming of a previously programmed
device, or programming of the flash memory by the application program in a running
system.

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The bootloader code is executed every time the part is powered on or reset. The
bootloader can execute the ISP command handler or the user application code. A LOW
level after reset at the ISP entry pin is consider ed as an external ha rdware requ est to st art
the ISP command handler via USART.

UM10800

Chapter 3: LPC82x Boot ROM

For details on the boot process, see Section 3.6.2 “
Remark: SRAM location 0x1000 0000 to 0x1000 0050 is not used by the bootloader and

the memory content in this area is retained during reset. SRAM memory is not retained
when the part powers down or enters Deep power-down mode.

Assuming that power supply pins are at their nominal levels when the rising edge on
RESET
the decision whether to continue with user code or ISP handler is made. The bootloader
performs the following steps (see Figure 4

Remark: The sampling of pin the ISP entry pin can be disabled through programming
flash location 0x0000 02FC (see Section 25.5.3 “

pin is generated, it may take up to 3 ms before the ISP entry pin is sampled and

1. If the watchdog overflow flag is set, the bootloader checks whether a valid user code
is present. If the watchdog overflow flag is not set, the ISP entry pin is checked.

2. If there is no request for the ISP command handler execution (ISP entry pin is
sampled HIGH after reset), a search is made for a valid user program.

3. If a valid user program is found then th e exec ution contr ol is transferred to it. If a valid
user program is not found, the bootloader attempts to load a valid user program via
the USART interface.

3.5.2 ROM-based APIs

Boot process”.

):

Code Read Protection (CRP)”).

Once the part has booted, the user can access several APIs located in the boot ROM to
access the flash memory, optimize power consumption, and operate the USART and I2C
peripherals.

The structure of the boot ROM APIs is shown in Figure 3

.

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Ptr to ROM Driver table

Reserved

Reserved

Reserved

…

Ptr to Device Table n

Ptr to Function 2

Ptr to Function 0

Ptr to Function 1

…

Ptr to Function n

Device n

ROM Driver Table

0x1FFF 1FF8

+0x0

+0x4

+0x8

+0x10

+0x14

+0xC

Device 3
Power profiles API function table

IAP calls

Ptr to IAP

0x1FFF 1FF1

Pointer to power profiles

function table

+0x18

Device 7
SPI driver routines function table

Device 8
ADC driver routines function table

Device 9
USART driver routines function table

Reserved

+0x1C

Pointer to SPI driver function table

+0x20

Pointer to ADC driver function table

+0x24

Pointer to USART driver

routines function table

+0x28

Reserved

+0x2C

Reserved

Device 4
Integer Divide routines function table

Pointer to 32-bit integer divide routines

Pointer to I2C driver routine function

table

Device 5
I2C driver routines function table

UM10800

Chapter 3: LPC82x Boot ROM

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User manual Rev. 1.2 — 5 October 2016 11 of 487

Fig 3. Boot ROM structure

NXP Semiconductors

The boot rom structure should be included as follows:

typedef struct {

} LPC_ROM_API_T;

#define ROM_DRIVER_BASE (0x1FFF1FF8UL)

Table 4. API calls

API Description Reference

Flash IAP Flash In-Application programming Table 330
Power profiles API Configure system clock and power consumption Table 343
Integer divide routines 32-bit integer divide routines Table 399
I2C driver I2C ROM driver Table 364
SPI driver SPI ROM driver Table 356
ADC driver ADC ROM driver Table 385
UART driver USART ROM driver Table 346

UM10800

Chapter 3: LPC82x Boot ROM

const uint32_t reserved0; /*!< Reserved */
const uint32_t reserved1; /*!< Reserved */
const uint32_t reserved2; /*!< Reserved */
const PWRD_API_T *pPWRD; /*!< Power API function table base address */
const ROM_DIV_API_T *divApiBase; /*!< Divider API function table base address */
const I2CD_API_T *pI2CD;/*!< I2C driver routines functions table */
const uint32_t reserved5; /*!< Reserved */
const SPID_API_T *pSPID; /*!< SPI driver API function table base address */
const ADCD_API_T *pADCD; /*!< ADC driver API function table base address */
const UARTD_API_T *pUARTD; /*!< USART driver API function table base address */

3.6 Functional description

3.6.1 Memory map after any reset

The boot block is 12 KB in size. The boot block is located in the memory region starting
from the address 0x1FFF 0000. The bootloader is designed to run from this memory area,
but both the ISP and IAP software use parts of the on-chip RAM. The RAM usage is
described in Section 25.7.2 “
vectors residing in the boot block of the on-chip flash memory also become active after
reset, i.e., the bottom 512 bytes of the boot block are also visible in the memory region
starting from the address 0x0000 0000.

3.6.2 Boot process

During the boot process, the bootloader checks if there is valid user code in flash. The
criterion for valid user code is as follows:

The reserved Cortex-M0+ exception vector location 7 (offset 0x0000 001C in the vector
table) should contain the 2’s complement of the check-sum of table entries 0 through 6.
This causes the checksum of the first 8 table entries to be 0. The bootloader code
checksums the first 8 locations in sector 0 of the flash. If the result is 0, then execution
control is transferred to the user code.

Memory and interrupt use for ISP and IAP”. The interrupt

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If the signature is not valid, the auto-baud routine synchronizes with the host via serial po rt
USART0. The host should send a ’?’ (0x3F) as a synchronization character and wait for a
response. The host side serial port settings should be 8 data bits, 1 stop bit and no parity.
The auto-baud routine measures the bit time of the received synchronizatio n character in
terms of its own frequency (the 12 MHz IRC frequency) and programs the baud rate
generator of the serial port. It also sends an ASCII string ("Synchronized<CR><LF>") to
the host. In response, the host should send the same string ("Synchronized<CR><LF>").

The bootloader auto-baud routine looks at the received characters to verify
synchronization. If synchronization is verified then "OK<CR><LF>" string is sent to the
host. The host should respond by sending the crysta l fr equen cy ( in kHz) at which th e part
is running. The response is required for backward compatibility of the bootloader code
and, on the LPC800, is ignored. The bootloader configures the part to run at the 12 MHz
IRC frequency.

Once the crystal frequency response is received, the part is initialized and the ISP
command handler is invoked. For safety reasons an "Unlock" command is required be fore
executing the commands resulting in flash erase/write operations and the "Go" command.
The rest of the commands can be executed without the unlock command. The Unlock
command is required to be executed once per ISP session. The Unlock command is
explained in Table 313 “

UM10800

Chapter 3: LPC82x Boot ROM

UART ISP Unlock command”.

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RESET

INITIALIZE

RECEIVE CRYSTAL FREQUENCY

(2)

RUN UART ISP COMMAND HANDLER

RUN AUTO-BAUD

(1)

CRP1/2/3

ENABLED?

WATCHDOG

FLAG SET?

CRP3/NO_ISP

ENABLED?

ENTER ISP

MODE?
(ISP ENTRY PIN
= LOW)

USER CODE

VALID?

USER CODE

VALID?

AUTO-BAUD

SUCCESSFUL?

EXECUTE INTERNAL

USER CODE

ENABLE DEBUG

yes

yes

yes

yes

yes

yes

yes

no

no

no

no

nono

no

no

A

A

boot from

UART

UM10800

Chapter 3: LPC82x Boot ROM

3.6.3 Boot process flowchart

(1) The boot-code is implementing auto-baud in software.
(2) This step is included for backward compatibility and the response is ignored by the bootloader.

Fig 4. Boot process flowchart

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UM10800

Chapter 4: LPC82x Nested Vectored Interrupt Controller (NVIC)

Rev. 1.2 — 5 October 2016 User manual

4.1 How to read this chapter

The NVIC is identical on all LPC82x parts.

4.2 Features

• Nested Vectored Interrupt Controller that is an integral part of the ARM Cortex-M0+.

• Tightly coupled interrupt controller provides low interrupt latency.

• Controls system exceptions and peripheral interrupts.

• The NVIC supports 32 vectored interrupts.

• Four programmable interrupt priority levels with hardware priority level masking.

• Software interrupt generation using the ARM exceptions SVCall and PendSV (see

Ref. 3

).

• Support for NMI.

• ARM Cortex M0+ Vector table offset register VTOR implemented.

4.3 General description

The Nested Vecto red Interrupt Controller (NVIC) is an integral p art of the Cortex-M0+. The
tight coupling to the CPU allows for low interrupt latency and efficient processing of late
arriving interrupts.

4.3.1 Interrupt sources

Table 5 lists the interrupt sources for each peripheral function. Each peripheral device

may have one or more interrupt lines to the Vectored Interrupt Controller. Each line may
represent more than one interrupt source. Interrupts with the same priority level are
serviced in the order of their interrupt number.

See Ref. 3

Table 5. Connection of interrupt sources to the NVIC

Interrupt
number

0 SPI0_IRQ SPI0 interrupt See Table 193 “

1 SPI1_IRQ SPI1 interrupt Same as SPI0_IRQ
2 - Reserved ­3 UART0_IRQ USART0 interrupt See Table 179 “

Name Description Flags

for a detailed description of the NVIC and the NVIC register description.

SPI Interrupt Enable read and Set
register (INTENSET, addresses 0x4005 800C (SPI0),
0x4005 C00C (SPI1)) bit description”.

USART Interrupt Enable read and set
register (INTENSET, address 0x4006 400C (USART0),
0x4006 800C (USART1), 0x4006C00C (USART2)) bit
description”

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UM10800

Chapter 4: LPC82x Nested Vectored Interrupt Controller (NVIC)

Table 5. Connection of interrupt sources to the NVIC

Interrupt
number

4 UART1_IRQ USART1 interrupt Same as UART0_IRQ
5 UART2_IRQ USART2 interrupt Same as UART0_IRQ
6 - Reserved ­7 I2C1_IRQ I2C1 interrupt See Table 209 “

8 I2C0_IRQ I2C0 interrupt See Table 209 “

9 SCT_IRQ State configurable timer

10 MRT_IRQ Multi-rate timer interrupt Global MRT interrupt.

11 CMP_IRQ Analog comparator interrupt COMPEDGE - rising, falling, or both edges can set the bit
12 WDT_IRQ Windowed watchdog timer

13 BOD_IRQ BOD interrupts BODINTVAL - BOD interrupt level
14 FLASH_IRQ flash interrupt ­15 WKT_IRQ Self-wake-up timer interrupt ALARMFLAG
16 ADC_SEQA_IRQ ADC sequence A

17 ADC_SEQB_IRQ ADC sequence B

18 ADC_THCMP_IRQ ADC threshold compare ­19 ADC_OVR_IRQ ADC overrun ­20 DMA_IRQ DMA interrupt ­21 I2C2_IRQ I2C2 interrupt See Table 209 “

22 I2C3_IRQ I2C3 interrupt See Table 209 “

23 - Reserved ­24 PININT0_IRQ Pin interrupt 0 or pattern

25 PININT1_IRQ Pin interrupt 1 or pattern

Name Description Flags

Interrupt Enable Clear register
(INTENCLR, address 0x4005 000C (I2C0), 0x4005 400C
(I2C1), 0x4007 000C (I2C2), 0x4007 400C (I2C3)) bit
description”.

Interrupt Enable Clear register
(INTENCLR, address 0x4005 000C (I2C0), 0x4005 400C
(I2C1), 0x4007 000C (I2C2), 0x4007 400C (I2C3)) bit
description”.

EVFLAG SCT event

interrupt

GFLAG0
GFLAG1
GFLAG2
GFLAG3

WARNINT - watchdog warning interrupt

interrupt

-

completion

-

completion

Interrupt Enable Clear register
(INTENCLR, address 0x4005 000C (I2C0), 0x4005 400C
(I2C1), 0x4007 000C (I2C2), 0x4007 400C (I2C3)) bit
description”.

Interrupt Enable Clear register
(INTENCLR, address 0x4005 000C (I2C0), 0x4005 400C
(I2C1), 0x4007 000C (I2C2), 0x4007 400C (I2C3)) bit
description”.

PSTAT - pin interrupt status

match engine slice 0
interrupt

PSTAT - pin interrupt status

match engine slice 1
interrupt

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Chapter 4: LPC82x Nested Vectored Interrupt Controller (NVIC)

Table 5. Connection of interrupt sources to the NVIC

Interrupt
number

26 PININT2_IRQ Pin interrupt 2 or pattern

27 PININT3_IRQ Pin interrupt 3 or pattern

28 PININT4_IRQ Pin interrupt 4 or pattern

29 PININT5_IRQ Pin interrupt 5 or pattern

30 PININT6_IRQ Pin interrupt 6 or pattern

31 PININT7_IRQ Pin interrupt 7 or pattern

Name Description Flags

match engine slice 2
interrupt

match engine slice 3
interrupt

match engine slice 4
interrupt

match engine slice 5
interrupt

match engine slice 6
interrupt

match engine slice 7
interrupt

UM10800

PSTAT - pin interrupt status

PSTAT - pin interrupt status

PSTAT - pin interrupt status

PSTAT - pin interrupt status

PSTAT - pin interrupt status

PSTAT - pin interrupt status

4.3.2 Non-Maskable Interrupt (NMI)

The part supports the NMI, which can be triggered by an peripheral interrupt or triggered
by software. The NMI has the highest priority exception other than the reset.

You can set up any peripheral interrupt listed in Table 5
register in the SYSCON block (Table 48
NMI exception and normal interrupt, disable the interr upt in the NVIC when you configure
it as NMI.

4.3.3 Vector table offset

The vector table contains the reset value of the st ack pointer and the start addresses, also
called exception vectors, for all exception handlers. On system reset, the vector table is
located at address 0x0000 0000. Software can write to the VTOR register in the NVIC to
relocate the vector table start address to a different memory location. For a description of
the VTOR register, see the ARM Cortex-M0+ documentation (Ref. 3

as NMI using the NMISRC

). To avoid using the same peripheral interrupt as

).

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Chapter 4: LPC82x Nested Vectored Interrupt Controller (NVIC)

4.4 Register description

The NVIC registers are located on the ARM private peripheral bus.

offset

Description Reset

value

0 Table 7
interrupts and reading back the interrupt enables for specific
peripheral functions.

0 Table 8
interrupts and reading back the interrupt enables for specific
peripheral functions.

0 Table 9
interrupt state to pending and reading back the interrupt pending
state for specific peripheral functions.

0 Table 10
interrupt state to not pending and reading back the interrupt pending
state for specific peripheral functions.

0 Table 11
current interrupt active state for specific peripheral functions.

0 Table 12
to each interrupt. This register contains the 2-bit priority fields for
interrupts 0 to 3.

0 Table 13
to each interrupt. This register contains the 2-bit priority fields for
interrupts 4 to 7.

0 Table 14
to each interrupt. This register contains the 2-bit priority fields for
interrupts 8 to 11.

0 Table 15
to each interrupt. This register contains the 2-bit priority fields for
interrupts 12 to 15.

0 Table 16
to each interrupt. This register contains the 2-bit priority fields for
interrupts 16 to 19.

0 Table 17
to each interrupt. This register contains the 2-bit priority fields for
interrupts 20 to 23.

0 Table 18
to each interrupt. This register contains the 2-bit priority fields for
interrupts 24 to 27.

0 Table 19
to each interrupt. This register contains the 2-bit priority fields for
interrupts 28 to 31.

Table 6. Register overview: NVIC (base address 0xE000 E000)

Name Access Address

ISER0 RW 0x100 Interrupt Set Enable Register 0. This register allows enabling

- - 0x104 Reserved. - ­ICER0 RW 0x180 Interrupt Clear Enable Register 0. This register allows disabling

- - 0x184 Reserved. 0 ­ISPR0 RW 0x200 Interrupt Set Pending Register 0. This register allows changi ng the

- - 0x204 Reserved. 0 ­ICPR0 RW 0x280 Interrupt Clear Pending Register 0. This register allows changing the

- - 0x284 Reserved. 0 ­IABR0 RO 0x300 Interrupt Active Bit Register 0. This register allows reading the

- - 0x304 Reserved. 0 ­IPR0 RW 0x400 Interrupt Priority Registers 0. This register allows assigning a priority

IPR1 RW 0x404 Interrupt Priority Registers 1 This register allows assigning a priority

IPR2 RW 0x408 Interrupt Priority Registers 2. This register allows assigning a priority

IPR3 RW 0x40C Interrupt Priority Registers 3. This register allows assigning a priority

IPR4 RW 0x410 Interrupt Priority Registers 4. This register allows assigning a priority

IPR5 RW 0x414 Interrupt Priority Registers 5. This register allows assigning a priority

IPR6 RW 0x418 Interrupt Priority Registers 6. This register allows assigning a priority

IPR7 RW 0x41C Interrupt Priority Registers 7. This register allows assigning a priority

Reference

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4.4.1 Interrupt Set Enable Register 0 register

The ISER0 register allows to enable peripheral interrupts or to read the enabled state of
those interrupts. Disable interrupts through the ICER0 (Section 4.4.2

The bit description is as follows for all bits in this register:

Write — Writing 0 has no effect, writing 1 enables the interrupt.
Read — 0 indicates that the interrupt is disabled, 1 indicates that the interrupt is enabled.

Table 7. Interrupt Set Enable Register 0 register (ISER0, address 0xE000 E100) bit

Bit Symbol Description Reset value

0 ISE_SPI0 Interrupt enable. 0
1 ISE_SPI1 Interrupt enable. 0
2- Reserved. ­3 ISE_UART0 Interrupt enable. 0
4 ISE_UART1 Interrupt enable. 0
5 ISE_UART2 Interrupt enable. 0
6- Reserved. ­7 ISE_I2C1 Interrupt enable. 0
8 ISE_I2C0 Interrupt enable. 0
9 ISE_SCT Interrupt enable. 0
10 ISE_MRT Interrupt enable. 0
11 ISE_CMP Interrupt enable. 0
12 ISE_WDT Interrupt enable. 0
13 ISE_BOD Interrupt enable. 0
14 ISE_FLASH Interrupt enable. 0
15 ISE_WKT Interrupt enable. 0
16 ISE_ADC_SEQA Interrupt enable. 0
17 ISE_ADC_SEQB Interrupt enable. 0
18 ISE_ADC_THCMP Interrupt enable. 0
19 ISE_ADC_OVR Interrupt enable. 0
20 ISE_SDMA Interrupt enable. 0
21 ISE_I2C2 Interrupt enable. 0
22 ISE_I2C3 Interrupt enable. 0
23 - Reserved. ­24 ISE_PININT0 Interrupt enable. 0
25 ISE_PININT1 Interrupt enable. 0
26 ISE_PININT2 Interrupt enable. 0
27 ISE_PININT3 Interrupt enable. 0
28 ISE_PININT4 Interrupt enable. 0
29 ISE_PININT5 Interrupt enable. 0
30 ISE_PININT6 Interrupt enable. 0
31 ISE_PININT7 Interrupt enable. 0

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description

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4.4.2 Interrupt clear enable register 0

The ICER0 register allows disabling the peripheral interrupts, or for reading the enabled
state of those interrupts. Enable interrupts through the ISER0 registers (Section 4.4.1

The bit description is as follows for all bits in this register:

Write — Writing 0 has no effect, writing 1 disables the interrupt.
Read — 0 indicates that the interrupt is disabled, 1 indicates that the interrupt is enabled.

Table 8. Interrupt clear enable register 0 (ICER0, address 0xE000 E180)

Bit Symbol Description Reset value

0 ICE_SPI0 Interrupt disable. 0
1 ICE_SPI1 Interrupt disable. 0
2- Reserved. ­3 ICE_UART0 Interrupt disable. 0
4 ICE_UART1 Interrupt disable. 0
5 ICE_UART2 Interrupt disable. 0
6- Reserved. ­7 ICE_I2C1 Interrupt disable. 0
8 ICE_I2C0 Interrupt disable. 0
9 ICE_SCT Interrupt disable. 0
10 ICE_MRT Interrupt disable. 0
11 ICE_CMP Interrupt disable. 0
12 ICE_WDT Interrupt disable. 0
13 ICE_BOD Interrupt disable. 0
14 ICE_FLASH Interrupt disable. 0
15 ICE_WKT Interrupt disable. 0
16 ICE_ADC_SEQA Interrupt disable. 0
17 ICE_ADC_SEQB Interrupt disable. 0
18 ICE_ADC_THCMP Interrupt disable. 0
19 ICE_ADC_OVR Interrupt disable. 0
20 ICE_SDMA Interrupt disable. 0
21 ICE_I2C2 Interrupt disable. 0
22 ICE_I2C3 Interrupt disable. 0
23 - Reserved. ­24 ICE_PININT0 Interrupt disable. 0
25 ICE_PININT1 Interrupt disable. 0
26 ICE_PININT2 Interrupt disable. 0
27 ICE_PININT3 Interrupt disable. 0
28 ICE_PININT4 Interrupt disable. 0
29 ICE_PININT5 Interrupt disable. 0
30 ICE_PININT6 Interrupt disable. 0
31 ICE_PININT7 Interrupt disable. 0

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4.4.3 Interrupt Set Pending Register 0 register

The ISPR0 register allows setting the pending state of the per iph er al int er ru pts, or for
reading the pending state of those interrupt s. Clear the pending state of interrupts thr ough
the ICPR0 registers (Section 4.4.4

The bit description is as follows for all bits in this register:

Write — Writing 0 has no effect, writing 1 changes the interrupt state to pending.
Read — 0 indicates that the interrupt is not pending, 1 indicates that the interrupt is

pending.

Table 9. Interrupt set pending register 0 register (ISPR0, address 0xE000 E200) bit

Bit Symbol Description Reset value

0 ISP_SPI0 Interrupt pending set. 0
1 ISP_SPI1 Interrupt pending set. 0
2- Reserved. ­3 ISP_UART0 Interrupt pending set. 0
4 ISP_UART1 Interrupt pending set. 0
5 ICE_UART2 Interrupt pending set. 0
6- Reserved. ­7 ISP_I2C1 Interrupt pending set. 0
8 ISP_I2C0 Interrupt pending set. 0
9 ISP_SCT Interrupt pending set. 0
10 ISP_MRT Interrupt pending set. 0
1 1 ISP_CMP Interrupt pending set. 0
12 ISP_WDT Interrupt pending set. 0
13 ISP_BOD Interrupt pending set. 0
14 ISP_FLASH Interrupt pending set. 0
15 ISP_WKT Interrupt pending set. 0
16 ISP_ADC_SEQA Interrupt pending set. 0
17 ISP_ADC_SEQB Interrupt pending set. 0
18 ISP_ADC_THCMP Interrupt pending set. 0
19 ISP_ADC_OVR Interrupt pending set. 0
20 ISP_SDMA Interrupt pending set. 0
21 ISP_I2C2 Interrupt pending set. 0
22 ISP_I2C3 Interrupt pending set. 0
23 - Reserved. ­24 ISP_PININT0 Interrupt pending set. 0
25 ISP_PININT1 Interrupt pending set. 0
26 ISP_PININT2 Interrupt pending set. 0
27 ISP_PININT3 Interrupt pending set. 0
28 ISP_PININT4 Interrupt pending set. 0

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Table 9. Interrupt set pending register 0 register (ISPR0, address 0xE000 E200) bit

Bit Symbol Description Reset value

29 ISP_PININT5 Interrupt pending set. 0
30 ISP_PININT6 Interrupt pending set. 0
31 ISP_PININT7 Interrupt pending set. 0

4.4.4 Interrupt Clear Pending Register 0 register

The ICPR0 register allows clearing the pending state of the peripheral interrupts, or for
reading the pending state of those interrupts. Set the pend in g state of inter ru p ts through
the ISPR0 register (Section 4.4.3

The bit description is as follows for all bits in this register:

Write — Writing 0 has no effect, writing 1 changes the interrupt state to not pending.
Read — 0 indicates that the interrupt is not pending, 1 indicates that the interrupt is

pending.

Table 10. Interrupt clear pending register 0 register (ICPR0, address 0xE000 E280) bit

Bit Symbol Function Reset value

0 ICP_SPI0 Interrupt pending clear. 0
1 ICP_SPI1 Interrupt pending clear. 0
2 - Reserved. ­3 ICP_UART0 Interrupt pending clear. 0
4 ICP_UART1 Interrupt pending clear. 0
5 ICP_UART2 Interrupt pending clear. 0
6 - Reserved. ­7 ICP_I2C 1 Interrupt pending clear. 0
8 ICP_I2C 0 Interrupt pending clear. 0
9 ICP_SCT Interrupt pending clear. 0
10 ICP_MRT Interrupt pending clear. 0
11 ICP_CMP Interrupt pending clear. 0
12 ICP_WDT Interrupt pending clear. 0
13 ICP_BOD Interrupt pending clear. 0
14 ICP_FLASH Interrupt pending clear. 0
15 ICP_WKT Interrupt pending clear. 0
16 ISP_ADC_SEQA Interrupt pendin g clear. 0
17 ISP_ADC_SEQB Interrupt pendin g clear. 0
18 ISP_ADC_THCMP Interrupt pending clear. 0
19 ISP_ADC_OVR Interrupt pending clear. 0
20 ISP_SDMA Interrupt pending clear. 0
21 ISP_I2C2 Interrupt pending clear. 0
22 ISP_I2C3 Interrupt pending clear. 0
23 - Reserved. -

description

description

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…continued

).

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Table 10. Interrupt clear pending register 0 register (ICPR0, address 0xE000 E280) bit

Bit Symbol Function Reset value

24 ICP_PININT0 Interrupt pending clear. 0
25 ICP_PININT1 Interrupt pending clear. 0
26 ICP_PININT2 Interrupt pending clear. 0
27 ICP_PININT3 Interrupt pending clear. 0
28 ICP_PININT4 Interrupt pending clear. 0
29 ICP_PININT5 Interrupt pending clear. 0
30 ICP_PININT6 Interrupt pending clear. 0
31 ICP_PININT7 Interrupt pending clear. 0

4.4.5 Interrupt Active Bit Register 0

The IABR0 register is a read-only register that allows reading the active state of the
peripheral interrupts. Use this register to determine which peripherals are asserting an
interrupt to the NVIC and may also be pending if there ar e en a ble d.

description

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Chapter 4: LPC82x Nested Vectored Interrupt Controller (NVIC)

…continued

The bit description is as follows for all bits in this register:

Write — n/a.
Read — 0 indicates that the interrupt is not active, 1 indicates that the interrupt is active.

Table 11. Interrupt Active Bit Register 0 (IABR0, address 0xE000 E300) bit description

Bit Symbol Function Reset value

0 IAB_SPI0 Interrupt active. 0
1 IAB_SPI1 Interrupt active. 0
2- Reserved. ­3 IAB_UART0 Interrupt active. 0
4 IAB_UART1 Interrupt active. 0
5 IAB_UART2 Interrupt active. 0
6- Reserved. ­7 IAB_I2C1 Interrupt active. 0
8 IAB_I2C0 Interrupt active. 0
9 IAB_SCT Interrupt active. 0
10 IAB_MRT Interrupt active. 0
1 1 IAB_CMP Interrupt active. 0
12 IAB_WDT Interrupt active. 0
13 IAB_BOD Interrupt active. 0
14 IAB_FLASH Interrupt active. 0
15 IAB_WKT Interrupt active. 0
16 ISP_ADC_SEQA Interrupt active. 0
17 ISP_ADC_SEQB Interrupt active. 0
18 ISP_ADC_THCMP Interrupt active. 0
19 ISP_ADC_OVR Interrupt active. 0
20 ISP_SDMA Interrupt active. 0

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Chapter 4: LPC82x Nested Vectored Interrupt Controller (NVIC)

Table 11. Interrupt Active Bit Register 0 (IABR0, address 0xE000 E300) bit description

Bit Symbol Function Reset value

21 ISP_I2C2 Interrupt active. 0
22 ISP_I2C3 Interrupt active. 0
23 - Reserved. ­24 IAB_PININT0 Interrupt active. 0
25 IAB_PININT1 Interrupt active. 0
26 IAB_PININT2 Interrupt active. 0
27 IAB_PININT3 Interrupt active. 0
28 IAB_PININT4 Interrupt active. 0
29 IAB_PININT5 Interrupt active. 0
30 IAB_PININT6 Interrupt active. 0
31 IAB_PININT7 Interrupt active. 0

4.4.6 Interrupt Priority Register 0

The IPR0 register controls the priority of four peripheral interrupts. Each interrupt can
have one of 4 priorities, where 0 is the highest priority.

T able 12. Interrupt Priority Register 0 (IPR0, address 0xE000 E400) bit description

Bit Symbol Description

5:0 - These bits ignore writes, and read as 0.
7:6 IP_SPI0 Interrupt Priority. 0 = highest priority. 3 = lowest priority.
13:8 - These bits ignore writes, and read as 0.
15:14 IP_SPI1 Interrupt Priority. 0 = highest priority. 3 = lowest priority.
21:16 - These bits ignore writes, and read as 0.
23:22 - Reserved.
29:24 - Reserved.
31:30 IP_UART0 Interrupt Priority. 0 = highest priority. 3 = lowest priority.

4.4.7 Interrupt Priority Register 1

The IPR1 register controls the priority of four peripheral interrupts. Each interrupt can
have one of 4 priorities, where 0 is the highest priority.

T able 13. Interrupt Priority Register 1 (IPR1, address 0xE000 E404) bit description

Bit Symbol Description

5:0 - These bits ignore writes, and read as 0.
7:6 IP_UART1 Interrupt Priority. 0 = highest priority. 3 = lowest priority.
13:8 - These bits ignore writes, and read as 0.
15:14 IP_UART2 Interrupt Priority. 0 = highest priority. 3 = lowest priority.
21:16 - These bits ignore writes, and read as 0.
23:22 - Reserved.
29:24 IP_I2C1 Interrupt Priority. 0 = highest priority. 3 = lowest priority.
31:30 - Reserved.

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4.4.8 Interrupt Priority Register 2

The IPR2 register controls the priority of four peripheral interrupts. Each interrupt can
have one of 4 priorities, where 0 is the highest priority.

T able 14. Interrupt Priority Register 2 (IPR2, address 0xE000 E408) bit description

Bit Symbol Description

5:0 - These bits ignore writes, and read as 0.
7:6 IP_I2C0 Interrupt Priority. 0 = highest priority. 3 = lowest priority.
13:8 - These bits ignore writes, and read as 0.
15:14 IP_SCT Interrupt Priority. 0 = highest priority. 3 = lowest priority.
21:16 - These bits ignore writes, and read as 0.
23:22 IP_MRT Interrupt Priority. 0 = highest priority. 3 = lowest priority.
29:24 - These bits ignore writes, and read as 0.
31:30 IP_CMP Interrupt Priority. 0 = highest priority. 3 = lowest priority.

4.4.9 Interrupt Priority Register 3

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Chapter 4: LPC82x Nested Vectored Interrupt Controller (NVIC)

The IPR3 register controls the priority of four peripheral interrupts. Each interrupt can
have one of 4 priorities, where 0 is the highest priority.

T able 15. Interrupt Priority Register 3 (IPR3, address 0xE000 E40C) bit description

Bit Symbol Description

5:0 - These bits ignore writes, and read as 0.
7:6 IP_WDT Interrupt Priority. 0 = highest priority. 3 = lowest priority.
13:8 - These bits ignore writes, and read as 0.
15:14 IP_BOD Interrupt Priority. 0 = highest priority. 3 = lowest priority.
21:16 - These bits ignore writes, and read as 0.
23:22 IP_FLASH Interrupt Priority. 0 = highest priority. 3 = lowest priority.
29:24 - These bits ignore writes, and read as 0.
31:30 IP_WKT Interrupt Priority. 0 = highest priority. 3 = lowest priority.

4.4.10 Interrupt Priority Register 4

The IPR3 register controls the priority of four peripheral interrupts. Each interrupt can
have one of 4 priorities, where 0 is the highest priority.

T able 16. Interrupt Priority Register 4 (IPR4, address 0xE000 E410) bit description

Bit Symbol Description

5:0 - These bits ignore writes, and read as 0.
7:6 IP_ADC_SEQA Interrupt Priority. 0 = highest priority. 3 = lowest priority.
13:8 - These bits ignore writes, and read as 0.
15:14 IP_ADC_SEQB Interrupt Priori ty. 0 = highest priority. 3 = lowest priority.
21:16 - These bits ignore writes, and read as 0.
23:22 IP_ADC_THCMP Interrupt Priority. 0 = highest priority. 3 = lowest priority.
29:24 - These bits ignore writes, and read as 0.
31:30 IP_ADC_OVR Interrupt Priority. 0 = highest priority. 3 = lowest priority.

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4.4.11 Interrupt Priority Register 5

The IPR3 register controls the priority of four peripheral interrupts. Each interrupt can
have one of 4 priorities, where 0 is the highest priority.

T able 17. Interrupt Priority Register 5 (IPR5, address 0xE000 E414) bit description

Bit Symbol Description

5:0 - These bits ignore writes, and read as 0.
7:6 IP_DMA Interrupt Priority. 0 = highest priority. 3 = lowest priority.
13:8 - These bits ignore writes, and read as 0.
15:14 IP_I2C2 Interrupt Priority. 0 = highest priority. 3 = lowest priority.
21:16 - These bits ignore writes, and read as 0.
23:22 IP_I2C3 Interrupt Priority. 0 = highest priority. 3 = lowest priority.
29:24 - Reserved.
31:30 - Reserved.

4.4.12 Interrupt Priority Register 6

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Chapter 4: LPC82x Nested Vectored Interrupt Controller (NVIC)

The IPR6 register controls the priority of four peripheral interrupts. Each interrupt can
have one of 4 priorities, where 0 is the highest priority.

T able 18. Interrupt Priority Register 6 (IPR6, address 0xE000 E418) bit description

Bit Symbol Description

5:0 - These bits ignore writes, and read as 0.
7:6 IP_PININT0 Interrupt Priority. 0 = highest priority. 3 = lowest priority.
13:8 - These bits ignore writes, and read as 0.
15:14 IP_PININT1 Interru pt Priority. 0 = highest priority. 3 = lowest priority.
21:16 - These bits ignore writes, and read as 0.
23:22 IP_PININT2 Interru pt Priority. 0 = highest priority. 3 = lowest priority.
29:24 - These bits ignore writes, and read as 0.
31:30 IP_PININT3 Interru pt Priority. 0 = highest priority. 3 = lowest priority.

4.4.13 Interrupt Priority Register 7

The IPR7 register controls the priority of four peripheral interrupts. Each interrupt can
have one of 4 priorities, where 0 is the highest priority.

T able 19. Interrupt Priority Register 7 (IPR7, address 0xE000 E41C) bit description

Bit Symbol Description

5:0 - These bits ignore writes, and read as 0.
7:6 IP_PININT4 Interrupt Priority. 0 = highest priority. 3 = lowest priority.
13:8 - These bits ignore writes, and read as 0.
15:14 IP_PININT5 Interru pt Priority. 0 = highest priority. 3 = lowest priority.
21:16 - These bits ignore writes, and read as 0.
23:22 IP_PININT6 Interru pt Priority. 0 = highest priority. 3 = lowest priority.
29:24 - These bits ignore writes, and read as 0.
31:30 IP_PININT7 Interru pt Priority. 0 = highest priority. 3 = lowest priority.

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Chapter 5: LPC82x System configuration (SYSCON)

Rev. 1.2 — 5 October 2016 User manual

5.1 How to read this chapter

The system configuration block is identical for all LPC820 parts.

5.2 Features

• Clock control

– Configure the system PLL.
– Configure system oscillator and watchdog oscillator.
– Enable clocks to individual peripherals and memories.
– Configure clock output.
– Configure clock dividers, digital filter clock, and USART baud rate clock.

• Monitor and release reset to individual peripherals.

• Select pins for external pin interrupts and pattern match engine.

• Configuration of reduced power modes.

• Wake-up control.

• BOD configuration.

• MTB trace start and stop.

• Interrupt latency control.

• Select a source for the NMI.

• Calibrate system tick timer.

5.3 Basic configuration

Configure the SYSCON block as follows:

• The SYSCON uses the CLKIN, CLKOUT, RESET, and XTALIN/OUT pins. Configure

the pin functions through the switch matrix. See Section 5.4

• No clock configuration is needed. The clock to the SYSCON block is always enabled.

By default, the SYSCON block is clocked by the IRC.

5.3.1 Set up the PLL

The PLL creates a stable output clock at a higher frequency than the input clock. If you
need a main clock with a frequency higher than the 12 MHz IRC clock, use the PLL to
boost the input frequency.

1. Power up the system PLL in the PDRUNCFG register.

Section 5.6.33 “

2. Select the PLL input in the SYSPLLCLKSEL register. You have the following input
options:

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Power configuration register”

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3. Update the PLL clock source in the SYSPLLCLKUEN register.

4. Configure the PLL M and N dividers.

5. Wait for the PLL to lock by monitoring the PLL lock status.

5.3.2 Configure the main clock and system clock

The clock source for the registers and memories is derived from main clock. The main
clock can be sourced from the IRC at a fixed clock frequency of 12 MHz or from the PLL.

The divided main clock is called the system clock and clocks the core, the memories, and
the peripherals (register interfaces and peripheral clocks).

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Chapter 5: LPC82x System configuration (SYSCON)

– IRC: 12 MHz internal oscillator.
– System oscillator: External crystal oscillator using the XTALIN/XTALOUT pins.
– External clock input CLKIN. Select this pin through the switch matrix.

Section 5.6.9 “

Section 5.6.10 “

Section 5.6.3 “

Section 5.6.4 “

System PLL clock source select register”

System PLL clock source update register”

System PLL control register”

System PLL status register”

1. Select the main clock. You have the following options:

– IRC: 12 MHz internal oscillator (default).
– PLL output: You must configure the PLL to use the PLL output.

Section 5.6.11 “

2. Update the main clock source.

Section 5.6.12 “

3. Select the divider value for the system clock. A divider value of 0 disables the system
clock.

Section 5.6.13 “

4. Select the memories and peripherals that are operating in your application and
therefore must have an active clock. The core is always clocked.

Section 5.6.14 “

Main clock source select register”

Main clock source update enable register”

System clock divider register”

System clock control register”

5.3.3 Set up the system oscillator using XTALIN and XTALOUT

To use the system oscillator with the LPC800, you need to assign the XTALIN and
XT ALOUT pins, which connect to the external crystal, through the fixed-pin function in the
switch matrix. XTALIN and XTALOUT can only be assigned to pins PIO0_8 and PIO0_9.

1. In the IOCON block, remove the pull-up and pull-down resistors in the IOCON
registers for pins PIO0_8 and PIO0_9.

2. In the switch matrix block, enable the 1-bit functions for XTALIN and XTALOUT.

3. In the SYSOSCCTRL register, disable the BYPASS bit and select the oscillator
frequency range according to the desired oscillator output clock.

Related registers:

Table 96 “

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User manual Rev. 1.2 — 5 October 2016 28 of 487

PIO0_8 register (PIO0_8, address 0x4004 4038) bit description”

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Table 95 “PIO0_9 register (PIO0_9, address 0x4004 4034) bit description”
Table 79 “Pin enable regi ster 0 (PINENABLE0, address 0x4000 C1C0) bit description”
Table 26 “System oscillator control register (SYSOSCCTRL, address 0x4004 8020) bit

description”

5.4 Pin description

The SYSCON inputs and outputs are assigned to external pins through the switch matrix.

UM10800

Chapter 5: LPC82x System configuration (SYSCON)

See Section 7.3.1 “

Connect an internal signal to a package pin” to assign the CLKOUT

function to a pin.
See Section 7.3.2

to enable the clock input, the oscillator pins, and the external reset

input.

Table 20. SYSCON pin description

Function Direction Pin Description SWM register Reference

CLKOUT O any CLKOUT clock output. PINASSIGN8 Table 75
CLKIN I PIO0_1/ACMP_I2/CLKIN External clock input to the system

XTALIN I PIO0_8/XTALIN Input to the system oscillator. PINENABLE0 Table 79
XTALOUT O PIO0_9/XTALOUT Output from the system oscillator. PINENABLE0 Table 79
RESET I RESET/PIO0_5 External reset input PINENABLE0 Table 79

PINENABLE0 Table 79
PLL. Disable the ACMP_I2 function
in the PINENABLE register.

5.5 General description

5.5.1 Clock generation

The system control block generates all clocks for the chip. Only the low-power oscillator
used for wake-up timing is controlled by the PMU. Except for the USART clock and the
clock to configure the glitch filters of the digital I/O pins, the clocks to the core and
peripherals run at the same frequency. The maximum system clock frequency is 30 MHz.
See Figure 5

.

Remark: The main clock frequency is limited to 100 MHz.

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User manual Rev. 1.2 — 5 October 2016 29 of 487

NXP Semiconductors

UM10800

Chapter 5: LPC82x System configuration (SYSCON)

XTALIN

XTALOUT

CLKIN

SYSCON

IRC oscillator

watchdog oscillator

IRC oscillator

SYSTEM

OSCILLATOR

SYSPLLCLKSEL

system PLL clock select

MAINCLKSEL

(main clock select)

SYSTEM PLL

main clock system clock

CLOCK DIVIDER
SYSAHBCLKDIV

CLOCK DIVIDER

UARTCLKDIV

7

IRC oscillator

system oscillator

watchdog oscillator

(CLKOUT clock select)

watchdog oscillator

IRC oscillator

SYSAHBCLKCTRL[1:19]

(system clock enable)

FRACTIONAL RATE

GENERATOR

CLOCK DIVIDER

IOCONCLKDIV

CLOCK DIVIDER

CLKOUTDIV

CLKOUTSEL

AHB clock 0
(core, system;
always-on)

19

memories
and peripherals,
peripheral clocks

USART0

USART1

USART2

IOCON
glitch filter

CLKOUT pin

WWDT

WKT

PMU

low-power oscillator

WKT

Fig 5. Clock generati on

5.5.2 Power control of analog components

The system control block controls the power to the analog components such as the
oscillators and PLL, the BOD, and the analog comparator. For details, see the following
registers:

Section 5.6.31 “
Section 5.6.3 “System PLL control register”
Section 5.6.6 “Watchdog oscillator control register”
Section 5.6.5 “System oscillator control register”

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User manual Rev. 1.2 — 5 October 2016 30 of 487

Deep-sleep mode configuration register”