NXP Semiconductors LPC5410x User Manual

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UM10850

LPC5410x User manual

Rev. 2.4 — 13 September 2016 User manual

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Info Content Keywords LPC5410x, ARM Cortex-M4, ARM Cortex-M0+, microcontroller, sensor

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Abstract LPC5410x User Manual

Page 2

NXP Semiconductors

UM10850

LPC5410x User manual

Revision history

Rev Date Description

2.4 20160913

2.3 20160906

• Updated Table 62 “Flash configuration register (FLASHCFG, main syscon: address 0x4000 0124)

bit description”: Changed the system clock rates of the following:

– 2 system clocks flash access time (for system clock rates up to 24 MHz). – 3 system clocks flash access time (for system clock rates up to 48 MHz). – 4 system clocks flash access time (for system clock rates up to 72 MHz). – 5 system clocks flash access time (for system clock rates up to 84 MHz). – Added 0x5, 6 system clocks flash access time (for system clock rates up to 100 MHz).

• Added text and a remark to Section 30.1 “How to read this chapter”.

• Added a remark to Section 30.3 “General description”.

• Added text and a remark to Section 30.4 “API description”.

• Added Table 466 “Power API calls in LPCOpen power library”.

• Renamed section 30.4.1 to Section 30.4.1 “Chip_POWER_SetPLL”.

• Renamed section 30.4.2 to Section 30.4.2 “Chip_POWER_SetVoltage”.

• Deleted Param0: mode and Low power mode; was secti on 30.4.2.1.

• Added Section 30.4.3 “Chip_POWER_EnterPowerMode”.

• Updated Section 30.5 “Functional description”.

2.2 20160331

• Removed Section 4.5.51: Device ID1 regist er va lu e s and mo ved Table 89 “Device ID1 register

values” to section Section 4.5.50 “Device ID1 register”.

• Removed IrDA mode from Section 21.5 “General description” in Chapter 21 “LPC5410x USARTs

(USART0/1/2/3)”.

• Updated Table 307 “USART Configuration register (CFG, offset 0x00) bit description”. Removed

IOMODE from the table.

• Removed the section: IrDA communication in Chapter 21 “LPC5410x USARTs (USART0/1/2/3)”.

• Added the sentence to Section 22.5 “General description”: Set the RXIGNORE bit to only transmit

data and not read the incoming data. Otherwise, the transmit halts when the receiver buffer is full.

• Added the sentence to Table 328 “SPI Transmitter Data and Control register (TXDATCTL, offset

0x18) bit description”, bit 22, RXIGNORE: The SPI collects receive data, according to SPI clocking,

unless RXIGNORE is set; 0: The SPI transmit halts when the receive data FIFO is full.

• Added the sentence to Section 22.7.7 “Data stalls”: The transmitter will be stalled until data is read

from the receive FIFO. Use the RXIGNORE control bit setting, to avoid the need to read the received data.

User manual Rev. 2.4 — 13 September 2016 2 of 464

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UM10850

LPC5410x User manual

Revision history

Rev Date Description

2.1 20151218 • Added Table 89 “Device ID1 register values”.

…continued

• Added text to Section 4.5.47.1 “CPU Control register”: The user can assign Cortex-M0+ to be the

master CPU via this register if needed after it is brought out of reset by Cortex-M4.

• Added text to Section 4.6.3 “Brown-out detection”: On the LPC5410x, the BOD is enabled by

default after power-up. At this time the BOD is set to the lowest value (1.5v) with no factory trimming applied. In the BOD block the interrupt portion is turned off and only the reset portion is on. After POR/BOD resets, the BootROM takes over and applies the factory BOD trim value so that the trip points become accurate. See the LPC5410x data sheet for BOD interrupt/reset voltage levels in the BOD static characteristics.

• Added section Section 12.5.7 “Channel chaining”.

• Updated Figure 53 “System FIFO conceptual block diagram”.

• Updated description of 15:12,TIMEOUT VALUE; Specifies the maximum time value for timeout at

the timer position identified by TimeoutBase. Minimum time TimeoutValue - 1 (clocks of wdt_clk). See Table 383 “Configuration register for USARTn (CFGUSART[0:3], address offset [0x1000:0x1300]) bit description”.

• Updated the values in the sentence: TimeoutValue can be any value from 2 to 15. This gives a

maximum timeout range of 2 counts (too small to be useful) at the bottom end, up to 15 * 32,768 (491,520) counts at the upper end. See Section 24.5.7.1 “Receiver Timeout”

• Updated text in Table 468 “set_voltage routine”: Param1: desired frequency (in Hz); was: Param1:

desired frequency (in MHz).

• Removed text from Section 5.2 “General description”, list 3:

...or for monitoring analog inputs (comparators and internal voltage reference and temperature sensor via one of the comparators).

• Removed comparator from Section 13.5 “General description”: This provides an extremely powerful

control tool - particularly when the SCT inputs and outputs are connected to other on-chip resources (ADC triggers, other timers etc.) in addition to general-purpose I/O.

• Added AHBCLKDIV register should be set to 1 in: List item 2 “Select the IRC as the main clock and

set the AHBCLKDIV register to 1. See Table 45, Table 46, and Table 58.”, Section 5.3.4.2 “Programming Deep-sleep mode”.

• Added AHBCLKDIV register should be set to 1 in: List item 2 “Select the IRC as the main clock and

set the AHBCLKDIV register to 1. See Table 45, Table 46, and Table 58.”, Section 5.3.5.2 “Programming Power-down mode”.

• Added registers, DIRSET0, DIRCLR0, DIRNOT0. See Table 134 “Register overview: GPIO port

(base address 0x1C00 0000)” and Section 9.5.10 “GPIO port direction set registers”, Section 9.5.11 “GPIO port direction clear registers”, and Section 9.5.12 “GPIO port direction toggle registers”.

• Added note to Table 223 “SCT DMA 0 request register (DMAREQ0, address 0x5000 405C) bit

description” and Table 224 “SCT DMA 1 request register (DMAREQ1, address 0x5000 4060) bit description”.

• Added remark to Section 4.5.37.5.1 “System PLL spread spectrum control register 0”: If the 32 kHz

RTC oscillator is used as the reference input to the PLL, then use fixed values SELI=1, SELP=6 and SELR=0, instead of applying the above rules. These values reduce the PLL loop bandwidth to combat the effect of reference oscillator jitter on the PLL output signal.

• In Table 62 “Flash configuration register (FLASHCFG, main syscon: address 0x4000 0124) bit

description” replaced offset in table title to address 0x4000 0124.

User manual Rev. 2.4 — 13 September 2016 3 of 464

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LPC5410x User manual

Revision history

Rev Date Description

2.1 • Added text to Section 17.2 “Features”: 24-bit interrupt timer clocked from CPU clock.

…continued

• Added address to Section 31.3.7.3 “RAM used by IAP command handler”’: Flash programming

commands use the top 32 bytes of on-chip SRAM0, 0x0200 FFE0 - 0x0200 FFFF (see Section

2.1.1 for details of the SRAM configuration). The maximum stack usage in the user allocated stack space is 128 bytes and grows downwards.

• Removed Receiver Idle from Section 21.2 “Features” and replaced with Transmitter Idle.

• Added the text receiver to List item • “A receiver timeout feature (for USART and SPI) provides a

means to get data left for a time in a FIFO that has not reached its threshold to be transferred.” in Section 24.3 “Features”.

• Added List item • “Timeouts: The watchdog oscillator must run for the UART and SPI timeout

counter to work. Enable the watchdog oscillator via the PDRUNCFG register (Table 72).” to the Section 24.2 “Basic configuration”.

• Added text, The source of the timeout clock is the watchdog oscillator with a nominal frequency of

500 kHz to Section 24.5.7.1 “Receiver Timeout”, and Section 24.5.15.1 “Receiver Timeout”.

• Added text to Section 21.5 “General description”: The USART receiver timeout fea ture can also be

used to identify the USART receiver idle state. Set the bit TIMEOUTCONTONEMPTY in the respective CFGUSART register to 1 to allow the timeout to flag idle state of the USART peripheral.

• Fixed the reset value of MSTTIME (Master timing configuration); was 0x77, now 0x56. See

T able 340 “Register overview: I2C0/1/2 (register base addresses 0x4009 4000 (I2C0), 0x4009 8000 (I2C1), 0x4009 C000 (I2C2))”.

• Added the Flash Management Registers FMSSTART and FMSSTOPUpdated to Chapter 28

“LPC5410x Flash signature generator”.

• Typographic errors have been corrected and minor pieces of information added or clarified

throughout the document.

2.0 20150410

• Registers supporting use of dual processors on LPC54102 devices has been added to the Syscon

chapter.

• A Power Management chapter has been added.

• Some pins in the Pin description chapter have the type changed to Z for open drain pins.

• A section has been added to the ADC chapter describing how to configure sample times for

different conversion configurations.

• The ADC operating speed is increased to 5 Ms/s.

• Updated Section 4.5.33 “Flash configuration register” text and Table 62.

• Typographic errors have been corrected and minor pieces of information added or clarified

throughout the document.

1.1 20141121

• In the NVIC chapter, the bit numbers for the priority register fields have been corrected.

• In the Syscon chapter, a functional description section has been added following the register

descriptions to provide additional information about some functions.

• The SCTimer/PWM chapter has been revised to better explain the function.

• Description of the ISP-AP interface and commands is added to the Debug chapter.

• References to Timer 0, 1, 2, 3, and 4 have been updated to use the terminology of the Standard

counter/timers chapter (CT32B0, 1, 2, 3, 4).

• Typographic errors have been corrected and minor pieces of information added or clarified

throughout the document.

User manual Rev. 2.4 — 13 September 2016 4 of 464

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UM10850

LPC5410x User manual

Revision history

Rev Date Description

1.0 20141104 Initial release of the LPC5410x User Manual

…continued

Contact information

For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com

User manual Rev. 2.4 — 13 September 2016 5 of 464

Page 6

1.1 Introduction

UM10850

Chapter 1: LPC5410x Introductory information

Rev. 2.4 — 13 September 2016 User manual

The LPC5410x are ARM Cortex-M4 based microcontrollers for embedded applications. these devices include an optional ARM Cortex-M0+ coprocessor, 104 KB of on-chip SRAM, 512 KB on-chip flash, five general-purpose timers, one State-Configurable Timer with PWM capabilities (SCTimer/PWM), one R TC/alarm timer , one 24-bit Multi-Rate T imer (MRT), a Windowed Watchdog Timer (WWDT), four USARTs, two SPIs, three Fast-mode

plus I

C-bus interfaces with high-speed slave mode, and one 12-bit 5 Msamples/sec

ADC. The ARM Cortex-M4 is a 32-bit core that of fers system enha ncement s such as low power

consumption, enhanced debug features, and a high level of support block integ ration. The ARM Cortex-M4 CPU incorporates a 3-stage pipeline, uses a Harvard architecture with separate local instruction and data buses as well as a third bus for periphe rals, and includes an internal prefetch unit that supports sp eculative branching. The ARM Cortex-M4 supports single-cycle digital signal processing and SIMD instructions. The Cortex-M4 is the Cortex-M4 with the inclusion of the 32-bit Floating Point Unit.

1.2 Features

The ARM Cortex-M0+ coprocessor available on some devices is an energy-efficient and easy-to-use 32-bit core which is code- and tool-compatible with the Cortex-M4 core. The Cortex-M0+ coprocessor offers up to 100 MHz performance with a simple instruction set and reduced code size.

Refer to LPC5410x data sheets for complete details on specific products and configurations.

• Dual processor core: ARM Cortex-M4 and ARM Cortex-M0+ included fo r LPC54102

devices. Cortex-M4 only is present on LPC54101 devices.

• ARM Cortex-M4 CPU:

– ARM Cortex-M4 processor, running at a frequency of up to 100 MHz. – Floating Point Unit (FPU) and Memory Protection Unit (MPU). – The CPU can operate at frequencies of up to 100 MHz. – ARM Cortex -M 4 bu ilt- in Ne ste d Vectored Interrupt Controller (NVIC). – Non-maskable Interrupt (NMI) with a selection of sources. – Serial Wire Debug (SWD) with 8 breakpoints and 4 watchpoints. Includes Serial

Wire Output for enhanced debug capabilities.

– System tick timer.

• ARM Cortex-M0+ CPU (present on LPC54102 devices):

– ARM Cortex-M0+ processor, running at a frequency of up to 100 MHz (using the

same clock as the Cortex-M4).

– The CPU can operate at frequencies of up to 100 MHz. – ARM Cortex-M0+ built-in Nested Vectored Interrupt Controller (NVIC).

User manual Rev. 2.4 — 13 September 2016 6 of 464

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Chapter 1: LPC5410x Introductory information

– Non-maskable Interrupt (NMI) with a selection of sources. – Serial Wire Deb ug (SWD) with 4 br ea kp oin ts and 2 watchp oints. – System tick timer.

UM10850

• On-Chip memory:

– Up to 512 KB on-chi p flash programming memory with flash accelerator and 256

Byte page write and erase.

– Up to 104 KB total SRAM composed of: – Up to 96 KB contiguous main SRAM. – An additional 8 KB SRAM.

• ROM API support:

– Flash In-A pp licatio n Pro gr a mm in g (IAP ) an d In- Sys te m Pro gr a mmin g (ISP). – Power Control API.

• Serial interfaces:

– Four USART interfaces with synchronous mode and 32 kHz mode for wake-up

from Deep-sleep and Power-down modes. The USAR Ts includ e a FIFO buffer, and share a fractional baud-rate generator.

– Two SPI interfaces, each with 4 slave selects and flexible data configuration. The

SPIs include a FIFO buffer. Able to wake up the device from Deep-sleep and Power-down modes when used in slave mode.

– Three I

of up to 1Mbit/s and with multiple address recognitio n an d mo n ito r mo de . Eac h

I able to wake up the device from Deep-sleep and Power-down modes.

C-bus interfaces supporting fast mode and Fast-mode Plus with data rates

C-bus interface also supports High Speed Mode as a slave. The slave function is

• Digital peripherals:

– DMA controller with 22 channels and 20 programmable triggers, able to access all

memories and DMA-capable peripherals.

– Up to 50 General-Purpose I/O (GPIO) pins. Most GPIOs have configurable

pull-up/pull-down resistors, open-drain mode, and input inverter.

– GPIO registers are located on AHB for fast access. – Up to eight GPIOs can be selected as pin interrupts (PINT), triggered by rising,

falling or both input edges.

– Two GPIO grouped interrupts (GINT) enable an interrupt based on a logical

(AND/OR) combination of input states.

– CRC engine.

• Timers

– Five 32-bit standard general purpose timers/counters, four of which support up to 4

capture inputs and 4 compare outputs, PWM mode, and external count input. Specific timer events can be selected to generate DMA requests. The fifth timer does not have external pin connections and may be used for internal timing operations.

– One State Configurable Timer/PWM (SCTimer/PWM) 6 input and 8 output

functions (including capture and match). Inputs and outputs can be routed to/from external pins and internally to/from selected peripherals. Internally, the SCT supports 13 captures/matches, 13 events and 13 states.

User manual Rev. 2.4 — 13 September 2016 7 of 464

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• Analog peripheral: 12-bit ADC with 12 input channels and with multiple interna l and

• Clock generation:

• Power control:

• JTAG boundary scan supported.

• Unique device serial number (128-bit) for identification.

• Single power supply 1.62 V to 3.6 V.

• Operating temperature range of -40°C to +105°C.

• Available in a 3.288 x 3.288 mm WLCSP49 package and LQFP64 package.

UM10850

Chapter 1: LPC5410x Introductory information

– 32-bit Real-time clock (RTC) with 1 s resolution running in the always-on power

domain. A timer in the RTC can be used for wake-up from all low power modes including Deep power-down, with 1 ms resolution.

– Multiple-channel multi-rate 24-bit timer (MRT) for repetitive interrupt generation at

up to four programmable, fixed rates.

– Windowed Watchdog timer (WWDT). – Ultra-low power Micro-tick Timer, running from the Watchdog oscillator, that can be

used to wake up the device from low power modes.

– Repetitive interrupt timer for general purpose use and use with debug

time-stamping.

external trigger inputs and sample rates of up to 5 MS/s. The ADC suppo rts two independent conversion sequences.

– 12 MHz internal RC oscillator, factory trimmed for accuracy, that can optionally be

used as a system clock.

– External clock input for up 24 MHz. – Internal, low-power, watchdog oscillator (WDOSC) with a nominal frequency of 500

kHz.

– 32 kHz low-power RTC oscillator. – System PLL allows CPU operation up to the maximum CPU rate without the need

for a high-frequency external clock. May be run from the internal RC oscillator, the external clock input CLKIN, or the RTC oscillator.

– Clock output function with divider that can reflect many internal clocks. – Frequency measurement unit for measuring the frequency of any on-chip or

off-chip clock signal.

– Integrated PMU (Power Management Unit) to minimize power consumption. – Reduced power modes: Sleep mode, Deep-sleep mode, Power-down mode, and

Deep power-down mode.

– Wake-up from Deep-sleep and Power-down modes on activity on USART, SPI,

– Wake-up from Sleep, Deep-sleep, Power-down, and Deep power-down modes

– Power-On Reset (POR). – Brownout detect.

C peripherals.

and I

from the RTC alarm.

User manual Rev. 2.4 — 13 September 2016 8 of 464

Page 9

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1.3 Block diagram

UM10850

Chapter 1: LPC5410x Introductory information

Fig 1. Block diagram

Grey-shaded blocks show peripherals provide DMA request lines or that can provide hardware triggers for DMA transfers.

User manual Rev. 2.4 — 13 September 2016 9 of 464

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NXP Semiconductors

1.4 Architectural overview

The ARM Cortex-M4 includes three AHB-Lite buses, one system bus and the I-code and D-code buses. One bus is dedicated for instruction fetch (I-code), and one bus is dedicated for data access (D-code). The use of two core buses allows for simultaneous operations if concurrent operations target different devices.

A multi-layer AHB matrix connects the CPU buses and other bus masters to peripherals in a flexible manner that optimizes performance by allowing peripherals on different slaves ports of the matrix to be accessed simultaneously by different bus masters. More information on the multilayer matrix can be found in Section 2.1.3 multilayer matrix are shown in Figure 1

APB peripherals are connected to the AHB matrix via two APB buses using separate slave ports from the multilayer AHB matrix. This allows for better performance by reducing collisions between the CPU and the DMA controller, and also for peripherals on the asynchronous bridge to have a fixed clock that does not track the system clock.

1.5 ARM Cortex-M4 processor

UM10850

Chapter 1: LPC5410x Introductory information

. Connections in the

The Cortex-M4 is a general purpose 32-bit microprocessor, which offers high performance and very low power consumption. The Cortex-M4 offers a Thumb-2 instruction set, low interrupt latency, interruptible/continuable multiple load and store instructions, automatic state save and restore for interrupts, tightly integrated interrupt controller, and multiple core buses capable of simultaneou s accesses.

A 3-stage pipeline is employed so that all parts of the processing and memory systems can operate continuously. Typically , while on e in struction is b eing e xecuted, its successor is being decoded, and a third instruction is being fetched from memory.

Information about Cortex-M4 configuration options can be found in Chapter 32

1.6 ARM Cortex-M0+ processor (present on LPC54102 devices)

The Cortex-M0+ is a general purpose 32-bit microprocessor with extremely low power consumption. The Cortex-M0+ includes the bulk of the Thumb instruction set and a small subset of Thumb-2 Instructions. The Cortex-M0+ has a 2-stage pipeline in order to decrease power consumption, and includes a 32-cycle multiplier.

Information about Cortex-M0+ configuration options can be found in Chapter 32

User manual Rev. 2.4 — 13 September 2016 10 of 464

Page 11

UM10850

Chapter 2: LPC5410x Memory mapping

Rev. 2.4 — 13 September 2016 User manual

2.1 General description

The LPC5410x incorporates several distinct memory regions. Figure 2 shows the overall map of the entire address space from the user program viewpoint following reset.

The APB peripheral area is 512 KB in size and is divided to allow for up to 32 peripherals. Each peripheral is allocated 16 KB of space, simplifying the address decoding.

The registers incorporated into the CPU, such as NVIC, SysTick, and sleep mode control, are located on the private peripheral bus.

2.1.1 Main SRAM

The parts contain up to a tot al 96 KB of contigu ous, on-chip st atic RAM memory (this is in addition to SRAM2 as noted in the next section below, so the total device SRAM can be up to 104 KB). For each SRAM configuration, the SRAM is divi ded into two blocks: SRAM0 (up to 64 KB) and SRAM1 (up to 32 KB). The bottom 8 KB of SRAM can be enabled separately in order to allow saving dat a with minimal power usage during Power-down mode. The remaining portion of SRAM0 and the entire SRAM1 can also be disabled or enabled individually in the SYSCON block to save power. See Section 4.5.22

“AHB Clock Control register 0” and Section 4.5.38 “Power Configuration register”.

Table 1. Main SRAM configuration

SRAM0 SRAM1

(total main SRAM = up to 96 KB)

Size Up to 64 KB Up to 32 KB Address range

Power Control (via Power API)

• Always begins at 0x0200 0000.

• Continues to 0x0200 FFFF (for full 64

KB).

• First 8 KB is has a separate power switch.

• Remaining SRAM0 has a single power

switch.

• Begins at end of SRAM0, 0x0201 0000 when SRAM0

is a full 64 KB.

• Ends at 0x0201 7FFF for 32 KB SRAM1 with 64 KB

SRAM0.

• All of SRAM1 has a single power switch.

2.1.1.1 SRAM2

An additional on-chip static RAM memory, SRAM2, is available that is not contiguous to SRAM0 and SRAM1. This can be used, for example, as the location for the program stack, or any other use. SRAM2 can be disabled or enabled in the SYSCON block to save power. See Section 4.5.22 “

Configuration register”.

AHB Clock Control register 0” and Section 4.5.38 “Power

2.1.1.2 SRAM usage notes

Although always contiguous on all LPC5410x devices, SRAM0 and SRAM1 are placed on different AHB matrix ports. This allows user programs to potentially obtain better performance by dividing RAM usage among the 2 ports. For example, simultaneous access to SRAM0 by the CPU and SRAM1 by the system DMA controller does not result in any bus stalls for either master.

User manual Rev. 2.4 — 13 September 2016 11 of 464

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NXP Semiconductors

Generally speaking, the CPU will read or write all peripheral data at some point, even when all such data is read from or sent to a peripheral by DMA. So, minimizing stalls is likely to involve putting data to/from different peripherals in RAM on each port.

Alternatively, sequences of data from the same peripheral could be alternated between RAM on each port. this could be helpful if DMA fills or empties a RAM buffer, then signals the CPU before proceeding on to a second buffer. the CPU would then tend to access the data while the DMA is using the other RAM.

UM10850

Chapter 2: LPC5410x Memory mapping

User manual Rev. 2.4 — 13 September 2016 12 of 464

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2.1.2 Memory mapping

UM10850

Chapter 2: LPC5410x Memory mapping

Fig 2. Memory mapping

User manual Rev. 2.4 — 13 September 2016 13 of 464

The private peripheral bus includes CPU peripherals such as the NVIC, SysTick, and the core control registers.

Page 14

NXP Semiconductors

2.1.3 AHB multilayer matrix

The LPC5410x uses a multi-layer AHB matrix to connect the CPU buses and other bus masters to peripherals in a flexible manner that optimizes performance by allowing peripherals that are on different slave po rts of the matrix to be accessed simultaneously by different bus masters. Figure 1

2.1.4 Memory Protection Unit (MPU)

The Cortex-M4 processor has a memory protection unit (MPU) that provides fine grain memory control, enabling applications to implement security privilege levels, separating code, data and stack on a task-by-task basis. Such requirements are critical in many embedded applications.

The MPU register interface is located on the private peripheral bus and is described in detail in Ref. 1 “

UM10850

Chapter 2: LPC5410x Memory mapping

shows details of the potential matrix connections.

Cortex-M4 TRM”.

User manual Rev. 2.4 — 13 September 2016 14 of 464

Page 15

UM10850

Chapter 3: LPC5410x Nested Vectored Interrupt Controller (NVIC)

Rev. 2.4 — 13 September 2016 User manual

3.1 How to read this chapter

Available interrupt sources may vary with specific LPC5410x device type.

3.2 Features

• Nested Vectored Interrupt Controller that is an integral part of each CPU.

• Tightly coupled interrupt controller provides low interrupt latency.

• Controls system exceptions and peripheral interrupts.

• The NVIC of the Cortex-M4 supports:.

– 37 vectored interrupts. – 8 programmable interrupt priority levels with hardware priority level masking. – Vector table offset register VTOR. – Software interrupt generation.

• The Cortex- M0+ (present on LPC54102 devices) supports: the first 32 interrupts.

– 32 vectored interrupts. – 4 programmable interrupt priority levels with hardware priority level masking. – Vector table offset register VTOR.

• Support for NMI from any interrupt (see Section 4.5.3).

3.3 General description

The tight coupling to the NVIC to the CPU allows for low interrupt latency and efficient processing of late arriving interrupts.

3.3.1 Interrupt sources

Table 2 lists the interrupt sources for each peripheral function. Each peripheral device

may have one or more interrupt lines to the Vectored Interrupt Controller. Each line may represent more than one interrupt source. The interrupt number does not imply any interrupt priority.

See Ref. 1 “ the NVIC and the NVIC registers.

Table 2. Connection of interrupt sources to the NVIC

Interrupt Name Description Flags

0 WDT Windowed watchdog timer interrupt WARNINT - watchdog warning interrupt 1 BOD BOD interrupt BODINTVAL - BOD interrupt level 2 (reserved) -

3 DMA DMA interrupts Interrupt A and interrupt B, error interrupt

User manual Rev. 2.4 — 13 September 2016 15 of 464

Cortex-M4 TRM” and Ref. 2 “Cortex-M0+ TRM” for detailed descriptions of

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NXP Semiconductors

UM10850

Chapter 3: LPC5410x Nested Vectored Interrupt Controller (NVIC)

Table 2. Connection of interrupt sources to the NVIC

Interrupt Name Description Flags

4 GINT0 GPIO group 0 interrupt Enabled pin interrupts 5 PIN_INT0 Pin interrupt 0 or pattern match engine slice 0 int PSTAT - pin interrupt status 6 PIN_INT1 Pin interrupt 1o r pattern match engine slice 1 int PSTAT - pin interrupt status 7 PIN_INT2 Pin interrupt 2 or pattern match engine slice 2 int PSTAT - pin interrupt status 8 PIN_INT3 Pin interrupt 3 or pattern match engine slice 3 int PSTAT - pin interrupt status 9 UTICK Micro-tick Timer interrupt INTR 10 MRT Multi-rate timer interrupt Global MRT interrupts: GFLAG0, 1, 2, 3 11 CT32B0 Standard counter/timer CT32B0 interrupt Match and Capture interrupts 12 CT32B1 Standard counter/timer CT32B1 interrupt Match and Capture interrupts 13 CT32B2 Standard counter/timer CT32B2 interrupt Match and Capture interrupts 14 CT32B3 Standard counter/timer CT32B3 interrupt Match and Capture interrupts 15 CT32B4 Standard counter/timer CT32B4 interrupt Match and Capture interrupts 16 SCT0 State configurable timer interrupt EVFLAG SCT event 17 UART0 USART0 interrupt See Table 310 18 UART1 USART1 interrupt Same as USART0 19 UART2 USART2 interrupt Same as USART0 20 UART3 USART3 interrupt Same as USART0 21 I2C0 I2C0 interrupt See Table 348 22 I2C1 I2C1 interrupt Same as I2C0 23 I2C2 I2C2 interrupt Same as I2C0 24 SPI0 SPI0 interrupt See Table 325 25 SPI1 SPI1 interrupt Same as SPI0 26 ADC0_SEQA ADC0 sequence A completion. See Table 428 27 ADC0_SEQB ADC0 sequence B completion. See Table 428 28 ADC0_THCMP ADC0 threshold compare and error. See Table 428 29 RTC RTC alarm and wake-up interrupts See Table 276 30 (reserved) -

31 MAILBOX Mailbox interrupt (present on LPC54102 devices) Mailbo x Interrupt

The following interrupts are supported only on the Cortex-M4

32 GINT1 GPIO group 1 interrupt Enabled pin interrupts 33 PIN_INT4 Pin interrupt 4 or pattern match engine slice 4 int PSTAT - pin interrupt status 34 PIN_INT5 Pin interrupt 5 or pattern match engine slice 5 int PSTAT - pin interrupt status 35 PIN_INT6 Pin interrupt 6 or pattern match engine slice 6 int PSTAT - pin interrupt status 36 PIN_INT7 Pin interrupt 7 or pattern match engine slice 7 int PSTAT - pin interrupt status 39:37 (reserved) - 40 RIT Repetitive Interrupt Timer RITINT; masked compare interrupt

. . . .

User manual Rev. 2.4 — 13 September 2016 16 of 464

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UM10850

Chapter 3: LPC5410x Nested Vectored Interrupt Controller (NVIC)

3.4 Register description

The NVIC registers are located on the ARM private peripheral bus.

Table 3. Register overview: NVIC (base address 0xE000 E000)

Name Access Address

ISER0 R/W 0x100 Interrupt Set Enable Register 0. This register allows enabling interrupts

ISER1 R/W 0x104 Interrupt Set Enable Register 1. See ISER0 description. 0 Table 5 ICER0 R/W 0x180 Interrupt Clear Enable Register 0. This register allows disabling

ICER1 R/W 0x184 Interrupt Clear Enable Register 1. See ISER0 description. 0 Table 7 ISPR0 R/W 0x200 Interrupt Set Pending Register 0. This register allows changing the

ISPR1 R/W 0x204 Interrupt Set Pending Register 1. See ISPR0 description. 0 Table 9 ICPR0 R/W 0x280 Interrupt Clear Pending Register 0. This register allows changing the

ICPR1 R/W 0x284 Interrupt Clear Pending Register 1. See ICPR0 description. 0 Table 11

[1]

IABR0

IABR1 IPR0 R/W 0x400 Interrupt Priority Register 0. This register contains the 3-bit priority fields

IPR1 R/W 0x404 Interrupt Priority Register 1. This register contains the 3-bit priority fields

IPR2 R/W 0x408 Interrupt Priority Register 2. This register contains the 3-bit priority fields

IPR3 R/W 0x40C Interrupt Priority Register 3. This register contains the 3-bit priority fields

IPR4 R/W 0x410 Interrupt Priority Register 4. This register contains the 3-bit priority fields

IPR5 R/W 0x414 Interrupt Priority Register 5. This register contains the 3-bit priority fields

IPR6 R/W 0x418 Interrupt Priority Register 6. This register contains the 3-bit priority fields

IPR7 R/W 0x41C Interrupt Priority Register 7. This register contains the 3-bit priority fields

IPR8 R/W 0x420 Interrupt Priority Register 8. This register contains the 3-bit priority fields

IPR9 R/W 0x424 Interrupt Priority Register 9. This register contains the 3-bit priority fields

IPR10 R/W 0x428 Interrupt Priority Register 10. Th is register contains the 3-bit priority field

STIR

RO 0x300 Interrupt Active Bit Register 0. This register allows reading the current

[1]

RO 0x304 Interrupt Active Bit Register 1. See IABR0 description. 0 Table 13

[1]

WO 0xF00 Software Trigger Interrupt Register, allows software to generate

offset

Description Reset

value

0 Table 4

and reading back the interrupt enables for peripheral functions.

0 Table 6

interrupts and reading back the interrupt enables for peripheral functions.

0 Table 8 interrupt state to pending and reading back the interrupt pending state for peripheral functions.

0 Table 10 interrupt state to not pending and reading back the interrupt pending state for peripheral functions.

0 Table 12 interrupt active state for specific peripheral functions.

0 Table 14 for interrupts 0 to 3.

0 Table 15 for interrupts 4 to 7.

0 Table 16 for interrupts 8 to 11.

0 Table 17 for interrupts 12 to 15.

0 Table 18 for interrupts 16 to 19.

0 Table 19 for interrupts 20 to 23.

0 Table 20 for interrupts 24 to 27.

0 Table 21 for interrupts 28 to 31.

0 Table 22 for interrupts 32 to 35.

0 Table 23 for interrupts 36 to 39.

0 Table 24 for interrupt 40.

- Table 25

interrupts.

Reference

[1] This register is not available for the Cortex-M0+.

User manual Rev. 2.4 — 13 September 2016 17 of 464

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Chapter 3: LPC5410x Nested Vectored Interrupt Controller (NVIC)

3.4.1 Interrupt Set-Enable Register 0 register

The ISER0 register allows enabling the first 32 peripheral interrupts, or for reading the enabled state of those interrupts. The rema ining interrupts are enabled via the ISER1 register (Section 3.4.2 registers (Section 3.4.3

Table 4. Interrupt Set-Enable Register 0 register

Bit Name Value Function

0 ISE_WDT 1 ISE_BOD 2 - - Reserved. Read value is undefined, only zero should be written. 3 ISE_DMA 4 ISE_GINT0 5 ISE_PINT0 6 ISE_PINT1 7 ISE_PINT2 8 ISE_PINT3 9 ISE_UTICK 10 ISE_MRT 11 ISE_CT32B0 12 ISE_CT32B1 13 ISE_CT32B2 14 ISE_CT32B3 15 ISE_CT32B4 16 ISE_SCT0 17 ISE_USART0 18 ISE_USART1 19 ISE_USART2 20 ISE_USART3 21 ISE_I2C0 22 ISE_I2C1 23 ISE_I2C2 24 ISE_SPI0 25 ISE_SPI1 26 ISE_ADC0SEQA 27 ISE_ADC0SEQB 28 ISE_ADC0THOV 29 ISE_RTC 30 - - Reserved. Read value is undefined, only zero should be written. 31 ISE_MAILBOX

[1] [1]

[1] [1] [1] [1] [1] [1] [1] [1] [1] [1] [1] [1] [1] [1] [1] [1] [1] [1] [1] [1] [1] [1] [1] [1] [1] [1] [1]

[1]

Watchdog Timer interrupt enable. BOD interrupt enable.

DMA interrupt enable. GPIO group 0 interrupt enable. Pin interrupt / pattern match engine slice 0 interrupt. Pin interrupt / pattern match engine slice 1 interrupt. Pin interrupt / pattern match engine slice 2 interrupt. Pin interrupt / pattern match engine slice 3 interrupt. Micro-Tick Timer interrupt enable. Multi-Rate Timer interrupt enable. Standard counter/timer CT32B0 interrupt enable. Standard counter/timer CT32B1 interrupt enable. Standard counter/timer CT32B2 interrupt enable. Standard counter/timer CT32B3 interrupt enable. Standard counter/timer CT32B4 interrupt enable. SCT0 interrupt enable. USART0 interrupt enable. USART1 interrupt enable. USART2 interrupt enable. USART3 interrupt enable. I2C0 interrupt enable. I2C1 interrupt enable. I2C2 interrupt enable. SPI0 interrupt enable. SPI1 interrupt enable. ADC0 sequence A interrupt enable. ADC0 sequence B interrupt enable. ADC0 threshold and error interrupt enable. Real Time Clock (RTC) interrupt enable.

Mailbox interrupt enable (present on LPC54102 devices).

). Disabling interrupts is done through the ICER0 and ICER1

and Section 3.4.4).

UM10850

[1] Write: writing 0 has no effect, writing 1 enables the interrupt.

Read: 0 indicates that the interrupt is disabled, 1 indicates that the interrupt is enabled.

User manual Rev. 2.4 — 13 September 2016 18 of 464

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Chapter 3: LPC5410x Nested Vectored Interrupt Controller (NVIC)

3.4.2 Interrupt Set-Enable Register 1 register

The ISER1 register allows enabling the second group of peripheral interrupts, or for reading the enabled state of those interrupts. Disabling int er ru pts is done throu g h the ICER0 and ICER1 registers (Section 3.4.3

Table 5. Interrupt Set-Enable Register 1 register

Bit Name Value Function

0 ISE_GINT1 1 ISE_PINT4 2 ISE_PINT5 3 ISE_PINT6 4 ISE_PINT7 7:5 - - Reserved. Read value is undefined, only zero should be written. 8 ISE_RIT 31:9 - - Reserved. Read value is undefined, only zero should be written.

[1] [1] [1] [1] [1]

[1]

GPIO group 1 interrupt enable. Pin interrupt / pattern match engine slice 4 interrupt. Pin interrupt / pattern match engine slice 5 interrupt. Pin interrupt / pattern match engine slice 6 interrupt. Pin interrupt / pattern match engine slice 7 interrupt.

Repetitive Interrupt Timer interrupt enable.

[1] Write: writing 0 has no effect, writing 1 enables the interrupt.

Read: 0 indicates that the interrupt is disabled, 1 indicates that the interrupt is enabled.

and Section 3.4.4).

UM10850

3.4.3 Interrupt Clear-Enable Register 0

The ICER0 register allows disabling the first 32 peripheral interrupts, or for reading the enabled state of those interrupts. The remaining interrupts are disabled via the ICER1 register (Section 3.4.4 registers (Section 3.4.1

Table 6. Interrupt Clear-Enable Register 0

Bit Name Function

31:0 ICE_... Peripheral interrupt disables. Bit numbers match ISER0 registers (Table 4

Write: writing 0 has no effect, writing 1 disables the interrupt. Read: 0 indicates that the interrupt is disabled, 1 indicates that the interrupt is enabled.

). Enabling interrupts is done through the ISER0 and ISER1

and Section 3.4.2).

3.4.4 Interrupt Clear-Enable Register 1 register

The ICER1 register allows disabling the second group of peripheral interrupts, or for reading the enabled state of those interrupts. Enabling inter ru p ts is done throug h th e ISER0 and ISER1 registers (Section 3.4.1

Table 7. Interrupt Clear-Enable Register 1 register

Bit Name Function

31:0 ICE_... Peripheral interrupt disables. Bit numbers match ISER1 registers (Table 5

Write: writing 0 has no effect, writing 1 disables the interrupt. Read: 0 indicates that the interrupt is disabled, 1 indicates that the interrupt is enabled.

and Section 3.4.2).

). Unused bits are reserved.

3.4.5 Interrupt Set-Pending Register 0 register

The ISPR0 register allows setting the pending state of th e first 32 pe ripher al inter rupts, or for reading the pending state of those interrupts. The remaining interrupts can have their pending state set via the ISPR1 register (Section 3.4.6 interrupts is done through the ICPR0 and ICPR1 registers (Section 3.4.7

User manual Rev. 2.4 — 13 September 2016 19 of 464

). Clearing the pending state of

and

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NXP Semiconductors

Chapter 3: LPC5410x Nested Vectored Interrupt Controller (NVIC)

Section 3.4.8).

Table 8. Interrupt Set-Pending Register 0 register

Bit Name Function

31:0 ISP_... Peripheral interrupt pending set. Bit numbers match ISER0 registers (Table 4

Write: writing 0 has no effect, writing 1 changes the interrupt state to pending. Read: 0 indicates that the interrupt is not pending, 1 indicates that the interrupt is pending.

3.4.6 Interrupt Set-Pending Register 1 register

The ISPR1 register allows setting the pending state of the second group of peripheral interrupts, or for reading the pending state of those interrupts. Clearing the pending state of interrupts is done through the ICPR0 and ICPR1 registers (Section 3.4.7

Section 3.4.8

Table 9. Interrupt Set-Pending Register 1 register

Bit Name Function

31:0 ISP_... Peripheral interrupt pending set. Bit numbers match ISER1 registers (Table 5

Write: writing 0 has no effect, writing 1 changes the interrupt state to pending. Read: 0 indicates that the interrupt is not pending, 1 indicates that the interrupt is pending.

UM10850

). Unused bits are reserved.

and

). Unused bits are reserved.

3.4.7 Interrupt Clear-Pending Register 0 register

The ICPR0 register allows clearing the pending state of the first 32 peripheral interrupts, or for reading the pending state of those interrupts. The remaining interrupts can have their pending state cleared via the ICPR1 register (Section 3.4.8 state of interrupts is done through the ISPR0 and ISPR1 registers (Section 3.4.5

Section 3.4.6

Table 10. Interrupt Clear-Pending Register 0 register

Bit Name Function

31:0 ICP_... Peripheral interrupt pendin g clear. Bit numbers match ISER0 registers (Table 4

Write: writing 0 has no effect, writing 1 changes the interrupt state to not pending. Read: 0 indicates that the interrupt is not pending, 1 indicates that the interrupt is pending.

3.4.8 Interrupt Clear-Pending Register 1 register

The ICPR1 register allows clearing the pending state of the second group of peripheral interrupts, or for reading the p ending st ate of those interrupt s. Setting the pe nding st ate of interrupts is done through the ISPR0 and ISPR1 registers (Section 3.4.5

Section 3.4.6

Table 11. Interrupt Clear-Pending Register 1 register

Bit Name Function

31:0 ICP_... Peripheral interrupt pendin g clear. Bit numbers match ISER1 registers (Table 5

Write: writing 0 has no effect, writing 1 changes the interrupt state to not pending. Read: 0 indicates that the interrupt is not pending, 1 indicates that the interrupt is pending.

). Setting the pending

and

). Unused bits are reserved.

and

). Unused bits are reserved.

User manual Rev. 2.4 — 13 September 2016 20 of 464

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Chapter 3: LPC5410x Nested Vectored Interrupt Controller (NVIC)

3.4.9 Interrupt Active Bit Register 0

The IABR0 register is a read-only register that allows reading the active state of the first 32 peripheral interrupts. Bits in IABR are set while the corresponding interrupt service routines are in progress. Additional interrupts can have their active state read via the IABR1 register (Section 3.4.10

Table 12. Interrupt Active Bit Register 0

Bit Name Function

31:0 IAB_... Peripheral interrupt active. Bit numbers match ISER0 registers (Table 4

Read: 0 indicates that the interrupt is not active, 1 indicates that the interrupt is active.

). IABR registers are not available for the Cortex-M0+.

3.4.10 Interrupt Active Bit Register 1

The IABR1 register is a read-only register that allows reading the active state of the second group of peripheral interrupts. Bits in IABR are set while the corresponding interrupt service routines are in progress. IABR registers are not available for the Cortex-M0+.

Table 13. Interrupt Active Bit Register 1

Bit Name Function

31:0 IAB_... Peripheral interrupt active. Bit numbers match ISER1 registers (Table 5

Read: 0 indicates that the interrupt is not active, 1 indicates that the interrupt is active.

UM10850

). Unused bits are reserved.

3.4.11 Interrupt Priority Register 0

The IPR0 register controls the priority of the first 4 periphera l interrupts. Each interr upt can have one of 32 priorities, where 0 is the highest priority.

Table 14. Interrupt Priority Reg is ter 0

Bit Name Function

4:0 - Unused 7:5 IP_WDT Watchdog Timer interrupt priority. 0 = highest priority. 31 (0x1F) = lowest priority. 12:8 - Unused 15:13 IP_BOD BOD interrupt priority. 0 = highest priority. 31 (0x1F) = lowest priority. 20:16 - Unused 23:21 - Reserved. 28:24 - Unused 31:29 IP_DMA DMA interrupt priority. 0 = highest priority. 31 (0x1F) = lowest priority.

3.4.12 Interrupt Priority Register 1

The IPR1 register controls the priority of the second group of 4 peripheral interru pts. Each interrupt can have one of 32 priorities, where 0 is the highest prior ity.

Table 15. Interrupt Priority Reg is ter 1

Bit Name Function

4:0 - Unused 7:5 IP_GINT0 GPIO Group 0 interrupt priority. 0 = highest priority. 31 (0x1F) = lowest priority. 12:8 - Unused

User manual Rev. 2.4 — 13 September 2016 21 of 464

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NXP Semiconductors

UM10850

Chapter 3: LPC5410x Nested Vectored Interrupt Controller (NVIC)

Table 15. Interrupt Priority Reg is ter 1

Bit Name Function

15:13 IP_PINT0 Pin interrupt / pattern match engine slice 0 priority. 0 = highest priority. 31 (0x1F) = lowest priority. 20:16 - Unused 23:21 IP_PINT1 Pin interrupt / pattern match engine slice 1 priority. 0 = highest priority. 31 (0x1F) = lowest priority. 28:24 - Unused 31:29 IP_PINT2 Pin interrupt / pattern match engine slice 2 priority. 0 = highest priority. 31 (0x1F) = lowest priority.

…continued

3.4.13 Interrupt Priority Register 2

The IPR2 register controls the priority of the third group of 4 peripheral interrupts. Each interrupt can have one of 32 priorities, where 0 is the highest prior ity.

Table 16. Interrupt Priority Reg is ter 2

Bit Name Function

4:0 - Unused 7:5 IP_PINT3 Pin interrupt / pattern match engine slice 3 priority. 0 = highest priority. 31 (0x1F) = lowest priority. 12:8 - Unused 15:13 IP_UTICK Micro-Tick Timer interrupt priority. 0 = highest priority. 31 (0x1F) = lowest priority. 20:16 - Unused 23:21 IP_MRT Multi-Rate Timer interrupt priority. 0 = highest priority. 31 (0x1F) = lowest priority. 28:24 - Unused 31:29 IP_CT32B0 Standard counter/timer CT32B0 interrupt priority. 0 = highest priority. 31 (0x1F) = lowest priority.

3.4.14 Interrupt Priority Register 3

The IPR3 register controls the priority of the fourth group of 4 peripheral interrupts. Each interrupt can have one of 32 priorities, where 0 is the highest prior ity.

Table 17. Interrupt Priority Reg is ter 3

Bit Name Function

4:0 - Unused 7:5 IP_CT32B1 Standard counter/timer CT32B1 interrupt priority. 0 = highest priority. 31 (0x1F) = lowest priority. 12:8 - Unused 15:13 IP_CT32B2 Standard counter/timer CT32B2 interrupt priority. 0 = highest priority. 31 (0x1F) = lowest priority. 20:16 - Unused 23:21 IP_CT32B3 Standard counter/timer CT32B3 interrupt priority. 0 = highest priority. 31 (0x1F) = lowest priority. 28:24 - Unused 31:29 IP_CT32B4 Standard counter/timer CT32B4 interrupt priority. 0 = highest priority. 31 (0x1F) = lowest priority.

3.4.15 Interrupt Priority Register 4

The IPR4 register controls the priority of the fifth group of 4 peripheral interrupts. Each interrupt can have one of 32 priorities, where 0 is the highest prior ity.

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Chapter 3: LPC5410x Nested Vectored Interrupt Controller (NVIC)

Table 18. Interrupt Priority Reg is ter 4

Bit Name Function

4:0 - Unused 7:5 IP_SCT0 SCT0 interrupt priority. 0 = highest priority. 31 (0x1F) = lowest priority. 12:8 - Unused 15:13 IP_USART0 USAR T 0 interrupt priority. 0 = highest priority. 31 (0x1F) = lowest priority. 20:16 - Unused 23:21 IP_USART1 USAR T 1 interrupt priority. 0 = highest priority. 31 (0x1F) = lowest priority. 28:24 - Unused 31:29 IP_USART2 USAR T 2 interrupt priority. 0 = highest priority. 31 (0x1F) = lowest priority.

3.4.16 Interrupt Priority Register 5

The IPR5 register controls the priority of the sixth group of 4 peripheral interrupts. Each interrupt can have one of 32 priorities, where 0 is the highest prior ity.

Table 19. Interrupt Priority Reg is ter 5

Bit Name Function

4:0 - Unused 7:5 IP_USART3 USART 3 interrupt priority. 0 = highest priority. 31 (0x1F) = lowest priority. 12:8 - Unused 15:13 IP_I2C0 I2C 0 interrupt priority. 0 = highest priority. 31 (0x1F) = lowest priority. 20:16 - Unused 23:21 IP_I2C1 I2C 1 interrupt priority. 0 = highest priority. 31 (0x1F) = lowest priority. 28:24 - Unused 31:29 IP_I2C2 I2C 2 interrupt priority. 0 = highest priority. 31 (0x1F) = lowest priority.

3.4.17 Interrupt Priority Register 6

The IPR6 register controls the priority of the seventh group of 4 peripheral interrupts. Each interrupt can have one of 32 priorities, where 0 is the highest prior ity.

Table 20. Interrupt Priority Reg is ter 6

Bit Name Function

4:0 - Unused 7:5 IP_SPI0 SPI 0 interrupt priority. 0 = highest priority. 31 (0x1F) = lowest priority. 12:8 - Unused 15:13 IP_SPI1 SPI 1 interrup t prio rity. 0 = highest priority. 31 (0x1F) = lowest priority. 20:16 - Unused 23:21 IP_ADC0SEQA ADC 0 sequence A interrupt priority. 0 = highest priority. 31 (0x1F) = lowest priority. 28:24 - Unused 31:29 IP_ADC0SEQB ADC 0 sequence B interrupt priority. 0 = highest priority. 31 (0x1F) = lowest priority.

3.4.18 Interrupt Priority Register 7

The IPR7 register controls the priority of the eighth group of 4 peripheral interrupts. Each interrupt can have one of 32 priorities, where 0 is the highest prior ity.

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Table 21. Interrupt Priority Reg is ter 7

Bit Name Function

4:0 - Unused 7:5 IP_ADC0THOV ADC 0 threshold and error interrupt priority. 0 = highest priority. 31 (0x1F) = lowest priority. 12:8 - Unused 15:13 IP_RTC Real Time clock (RTC) interrupt priority. 0 = highest priority. 31 (0x1F) = lowest priority. 20:16 - Unused 23:21 - Reserved 28:24 - Unused 31:29 IP_MAILBOX Mailbox interrupt priority. 0 = highest priority. 31 (0x1F) = lowest priority (present on LPC54102

devices).

3.4.19 Interrupt Priority Register 8

The IPR8 register controls the priority of the ninth and last group of 4 peripheral interrupts. Each interrupt can have one of 32 priorities, where 0 is the highest priority.

Table 22. Interrupt Priority Reg is ter 8

Bit Name Function

4:0 - Unused 7:5 IP_GINT1 GPIO Group 1 interrupt priority. 0 = highest priority. 31 (0x1F) = lowest priority. 12:8 - Unused 15:13 IP_PINT4 Pin interrupt / pattern match engine slice 4 priority. 0 = highest priority. 31 (0x1F) = lowest priority. 20:16 - Unused 23:21 IP_PINT5 Pin interrupt / pattern match engine slice 5 priority 0 = highest priority. 31 (0x1F) = lowest priority. 28:24 - Unused 31:29 IP_PINT6 Pin interrupt / pattern match engine slice 6 priority. 0 = highest priority. 31 (0x1F) = lowest priority.

3.4.20 Interrupt Priority Register 9

The IPR9 register controls the priority of the tenth group of 4 peripheral interrupts. Each interrupt can have one of 32 priorities, where 0 is the highest prior ity.

Table 23. Interrupt Priority Reg is ter 9

Bit Name Function

4:0 - Unused 7:5 IP_PINT7 Pin interrupt / pattern match engine slice 7 priority. 0 = highest priority. 31 (0x1F) = lowest priority. 31:8 - Reserved

3.4.21 Interrupt Priority Register 10

The IPR10 register controls the priority of the eleventh group of 4 peripheral interrupts. Each interrupt can have one of 32 priorities, where 0 is the highest priority.

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Table 24. Interrupt Priority Reg is ter 10

Bit Name Function

4:0 - Unused 7:5 IP_RIT Repetitive interrupt Timer interrupt priority. 0 = highest priority. 31 (0x1F) = lowest priority. 31:8 - Reserved

3.4.22 Software Trigger Interrupt Register

The STIR register provides an alternate way for software to generate an interrupt, in addition to using the ISPR registers. This mechanism can only be used to generate peripheral interrupts, not system exceptions. the STIR register is not available for the Cortex-M0+.

By default, only privileged software can write to the STIR register. Unprivileged software can be given this ability if privileged software sets the USERSETMPEND bit in the CCR register.

The interrupt number to be programmed in this register is listed in Table 2

Table 25. Software Trigger Interrupt Register (STIR)

Bit Symbol Description

8:0 INTID Writing a value to this field generates an interrupt for the specified the interrupt number. 31:9 - Reserved. Read value is undefined, only zero should be written.

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4.1 Features

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Chapter 4: LPC5410x System configuration (SYSCON)

Rev. 2.4 — 13 September 2016 User manual

• System and bus configuration.

• Clock select and control.

• PLL configuration

• Reset control.

• Wake-up control.

• BOD configuration.

• High-accuracy frequency measurement function for on-chip and off-chip clocks.

• Uses a selection of on-chip clocks as reference clock.

• Device ID register.

4.2 Basic configuration

Configure the SYSCON block as follows:

• The SYSCON uses the CLKIN, and CLKOUT pins which can be configured through

IOCON. See Section 4.3

• No clock configuration is needed. The clock to the SYSCON block is always enabled.

By default, the SYSCON block is clocked by the IRC.

• Target and reference clocks for the frequency measurement function are selected in

the input mux block. See Table 131

4.2.1 Set up the PLL

The PLL creates a stable output clock at a higher frequen cy than the input clock. If a mai n clock is needed with a frequency higher than the 12 MHz IRC clock, use the PLL to boost the input frequency. The PLL can be set up by calling an API supplied by NXP Semiconductors. Also see Section 4.6.4 “

“PLL registers”.

4.2.2 Configure the main clock and system clock

The clock source for the registers and memories is derived from main clock. The main clock can be selected from the sources listed in step 1 below.

. RESET is a dedicated pin.

PLL functional description” and Section 4.5.37

The divided main clock is called the system clock and clocks the core, the memories, and the peripherals (register interfaces and peripheral clocks).

1. Select the main clock. The following options are available:

– IRC: 12 MHz internal oscillator (default) – CLKIN – Watchdog oscillator – The output of the system PLL

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2. Select the divider value for the system clock. A divider value of 0 disables the system

3. Select the memories and peripherals that are operating in the application and

4.2.3 Measure the frequency of a clock signal

The frequency of any on-chip or off-chip clock signal can be measured accurately with a selectable reference clock. For example, the frequency measurement function can be used to accurately determine the frequency of the watchdog oscillator which varies over a wide range depending on process and temperature.

Chapter 4: LPC5410x System configuration (SYSCON)

– The RTC 32 kHz oscillator

Section 4.5.16 “ source select register B”.

clock.

Section 4.5.29 “

therefore must have an active clock. The core is always clocked.

Section 4.5.22 “ register 1”.

Main clock source select register A” and Section 4.5.17 “Main clock

System clock divider register”

AHB Clock Control register 0” and Section 4.5.23 “AHB Clock Control

UM10850

The clock frequency to be measured and the refe rence clock are selected in the input mux block. See Section 8.6.4 “ and Section 8.6.5 “

Details on the accuracy and measurement process are described in Section 4.6.5

“Frequency measure function”.

To start a frequency measurement cycle and read the result, see Table 61

4.3 Pin description

Table 26. SYSCON pin description

Function Direction Pin Description Reference

CLKOUT O PIO0_21 CLKOUT clock output. Chapter 7 CLKIN I PIO0_22 External clock input. Chapter 7

4.4 General description

4.4.1 Clock generation

The system control block facilitates the clock generation. Many clocking variations are possible. Figure 3 frequency is 100 MHz.

Frequency measure function reference clock select register”

Frequency measure function target clock select register”.

gives an overview of potential clock options. The maximum clock

Remark: In order for any of the clock multiplexers shown in Figure 3 currently selected clock must be running, and the clock to be switched to must also be running. This is so that the multiplexer can gracefully switch between the two clocks without glitches.

User manual Rev. 2.4 — 13 September 2016 28 of 464

to operate, the

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The low-power watchdog oscillator provides a fixed clock of approximately 500 kHz. The accuracy of this clock is limited to +/- 40% over temperature, voltage, and silicon processing variations. To determine the actual watchdog oscillator output, use the frequency measure block. See Section 4.2.3

The part contains one system PL L that can be con figur ed to use a nu mbe r of clock in puts and produce an output clock in the range of 1.2 MHz up to the maximum chip frequency, and can be used to run most on-chip functions. The output of the PLL can be monitored through the CLKOUT pin.

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Chapter 4: LPC5410x System configuration (SYSCON)

Fig 3. Clock generation

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Chapter 4: LPC5410x System configuration (SYSCON)

4.5 Register description

All system control block registers reside on word address boundaries. Details of the registers appear in the description of each function. System configuration functions are divided into 3 groups: Main system configuration at base address 0x4000 0000 (see

Table 27 Table 28

All address offsets not shown in the tables are reserved and should not be written to. Remark: The reset value column shows the reset value seen when the boot loader

executes and the flash contains valid user code. During code development, a different value may be seen if a debugger is used to halt execution prior to boot completion.

Table 27. Register overvie w: Main system configuration (base address 0x4000 0000)

Name Access Offset Description Reset value

AHBMATPRIO R/W 0x004 AHB multilayer matrix priority control 0x0 Table 30 SYSTCKCAL R/W 0x014 System tick counter calibration 0x0 Table 31 NMISRC R/W 0x01C NMI Source Select 0x0 Table 32 ASYNCAPBCTRL R/W 0x020 Asynchronous APB Control 0x1 Table 33 SYSRSTSTAT R/W 0x040 System reset status register Note [2] Table 34 PRESETCTRL0 R/W 0x044 Peripheral reset control 0 0x0 Table 35 PRESETCTRL1 R/W 0x048 Peripheral reset control 1 0x0 Table 36 PRESETCTRLSET0 WO 0x04C Set bits in PRESETCTRL0 - Table 37 PRESETCTRLSET1 WO 0x050 Set bits in PRESETCTRL1 - Table 38 PRESETCTRLCLR0 WO 0x054 Clear bits in PRESETCTRL0 - Table 39 PRESETCTRLCLR1 WO 0x058 Clear bits in PRESETCTRL1 - Table 40 PIOPORCAP0 RO 0x05C POR captured value of port 0 Note [3] Table 41 PIOPORCAP1 RO 0x060 POR captured value of port 1 Note [3] Table 42 PIORESCAP0 RO 0x068 Reset captured value of port 0 Note [4] Table 43 PIORESCAP1 RO 0x06C Reset captured value of port 1 Note [4] Table 44 MAINCLKSELA R/W 0x080 Main clock source select A 0x0 Table 45 MAINCLKSELB R/W 0x084 Main clock source select B 0x0 Table 46 ADCCLKSEL R/W 0x08C ADC clock source select 0x0 Table 47 CLKOUTSELA R/W 0x094 CLKOUT clock source select A 0x0 Table 48 CLKOUTSELB R/W 0x098 CLKOUT clock source select B 0x0 Table 49 SYSPLLCLKSEL R/W 0x0A0 PLL clock source select 0x0 Table 50 AHBCLKCTRL0 R/W 0x0C0 A HB Clock control 0 0x18B Table 51 AHBCLKCTRL1 R/W 0x0C4 A HB Clock control 1 0x0 Table 52 AHBCLKCTRLSET0 WO 0x0C8 Set bits in AHBCLKCTRL0 - Table 53 AHBCLKCTRLSET1 WO 0x0CC Set bits in AHBCLKCTRL1 - Table 54 AHBCLKCTRLCLR0 WO 0x0D0 Clear bits in AHBCLKCTRL0 - Table 55 AHBCLKCTRLCLR1 WO 0x0D4 Clear bits in AHBCLKCTRL1 - Table 56 SYSTICKCLKDIV R/W 0x0E0 SYSTICK clock divider 0x0 Table 57 AHBCLKDIV R/W 0x100 System clock divider 0x1 Table 58 ADCCLKDIV R/W 0x108 ADC clock divider 0x0 Table 59

User manual Rev. 2.4 — 13 September 2016 30 of 464

), Asynchronous system configuration at base address 0x4008 0000 (see ), and Other system registers at base addres s 0x4 00 2 C000 (see Table 29).

[1]

Reference

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Chapter 4: LPC5410x System configuration (SYSCON)

Table 27. Register overvie w: Main system configuration (base address 0x4000 0000) …continued

Name Access Offset Description Reset value

CLKOUTDIV R/W 0x10C CLKOUT clock divider 0x0 Table 60 FREQMECTRL R/W 0x120 Frequency measure register 0x0 Table 61 FLASHCFG R/W 0x124 Flash wait states configuration 0x001A Table 62 FIFOCTRL R/W 0x148 Serial interface FIFO enables 0 Table 63 IRCCTRL R/W 0x184 IRC oscillator control Note [5] Table 64 RTCOSCCTRL R/W 0x190 RTC oscillator 32 kHz output control 0x1 Table 65 SYSPLLCTRL R/W 0x1B0 PLL control 0x8000 Table 66 SYSPLLSTAT RO 0x1B4 PLL status 0x0 Table 67 SYSPLLNDEC R/W 0x1B8 PLL N decoder 0x0 Table 68 SYSPLLPDEC R/W 0x1BC PLL P decoder 0x0 Table 69 SYSPLLSSCTRL0 R/W 0x1C0 PLL spread spectrum control 0 0x0 Table 70 SYSPLLSSCTRL1 R/W 0x1C4 PLL spread spectrum control 1 0x1000 0000 Table 71 PDRUNCFG R/W 0x210 Power configuration register 0xD80500 Table 72 PDRUNCFGSET WO 0x214 Set bits in PDRUNCFG - Table 73 PDRUNCFGCLR WO 0x218 Clear bits in PDRUNCFG - Table 74 STARTER0 R/W 0x240 Start logic 0 wake-up enable register 0x0 Table 75 STARTER1 R/W 0x244 Start logic 1 wake-up enable register 0x0 Table 76 STARTERSET0 WO 0x248 Set bits in STARTER0 - Table 77 STARTERSET1 WO 0x24C Set bits in STAR TER1 - Table 78 STARTERCLR0 WO 0x250 Clear bits in STARTER0 - Table 79 STARTERCLR1 WO 0x254 Clear bits in STARTER1 - Table 80 CPUCTRL R/W 0x300 CPU Control for multiple processors 0x4D Table 81 CPBOOT R/W 0x304 Coprocessor Boot Address 0 Table 82 CPSTACK R/W 0x308 Coprocessor Stack Address 0 Table 83 CPSTAT RO 0x30C Coprocessor Status 0 Table 84 JTAGIDCODE RO 0x3F4 JTAG ID code register see table Table 85 DEVICE_ID0 RO 0x3F8 Part ID register Note [5] Table 86 DEVICE_ID1 RO 0x3FC Boot ROM and device revision register Note [5] Table 88

[1]

Reference

[1] Reset Value reflects the data stored in defined bits only. Reserved bits assumed to be 0. [2] Depends on the source of the most recent reset. [3] Determined by the voltage levels on device pins upon power-on reset. [4] Determined by the voltage levels on device pins when a reset other than power-on reset occurs. [5] Part dependent.

Table 28. Register overview: Asynchronous system configuration (base address 0x4008 0000)

Name Access Offset Description Reset value

[1]

Reference

ASYNCPRESETCTRL R/W 0x000 Async peripheral reset control 0x0 Table 90 ASYNCPRESETCTRLSET WO 0x004 Set bits in ASYNCPRESETCTRL - Table 91 ASYNCPRESETCTRLCLR WO 0x008 Clear bits in ASYNCPRESETCTRL - Table 92 ASYNCAPBCLKCTRL R/W 0x010 Async peripheral clock control 0x0 Table 93 ASYNCAPBCLKCTRLSET WO 0x014 Set bits in ASYNCAPBCLKCTRL - Table 94

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Table 28. Register overview: Asynchronous system configuration (base address 0x4008 0000) …continued

Name Access Offset Description Reset value

ASYNCAPBCLKCTRLCLR WO 0x018 Clear bits in ASYNCAPBCLKCTRL - Table 95 ASYNCAPBCLKSELA R/W 0x020 Async APB clock source select A 0x0 Table 96 ASYNCAPBCLKSELB R/W 0x024 Async APB clock source select B 0x0 Table 97 ASYNCCLKDIV R/W 0x028 Async APB clock divider 0x1 Table 98 FRGCTRL R/W 0x030 USART fractional rate generator control 0xFF Table 99

[1] Reset Value reflects the data stored in defined bits only. Reserved bits assumed to be 0.

[1]

Reference

Table 29. Register overview: Other system configuration (base address 0x4002 C000)

Name Access Offset Description Reset value

BODCTRL R/W 0x44 Brown-Out Detect control 0x0 Table 100

[1] Reset Value reflects the data stored in defined bits only. Reserved bits assumed to be 0.

[1]

Reference

4.5.1 AHB matrix priority register

The Multilayer AHB Matrix arbitrates between several masters, only if they attempt to access the same matrix slave port at the same time. Care should be taken if the value in this register is changed, improper settings can seriously degrade performance.

Priority values are 3 = highest, 0 = lowest. When the priority is the same, the master with the lower number is given priority. An example setting could put the Cortex-M4 D-code bus as the highest priority, followed by the I-Code bus. All other masters could share a lower priority.

Table 30. AHB matrix priority register 0 (AHBMATPRIO, address 0x4000 0004) bit description

Bit Symbol Description Reset value

1:0 PRI_ICODE I-Code bus priority (master 0). Should be lower than PRI_DCODE for proper

3:2 PRI_DCODE D-Code bus priority (master 1). 0 5:4 PRI_SYS System bus priority (master 2). 0 7:6 - Reserved. Read value is undefined, only zero should be written. 9:8 PRI_DMA DMA controller priority (master 5). 0 13:10 - Reserved. Read value is undefined, only zero should be written. 15:14 PRI_FIFO System FIFO bus priority (master 9). 0 17:16 PRI_M0 Cortex-M0+ bus priority (master 10). Present on LPC54102 devices. 0 31:18 - Reserved. Read value is undefined, only zero should be written. -

operation.

4.5.2 System tick counter calibration register

This register allows software to set up a default value for the SYST_CALIB register in the System Tick Timer of each CPU. See Chapter 19

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Chapter 4: LPC5410x System configuration (SYSCON)

Table 31. System tick timer calibration register (SYSTCKCAL, address 0x4000 0014) bit

description

Bit Symbol Description Reset value

23:0 CAL System tick timer calibration value. 0 24 SKEW Initial value for the Systick timer. 25 NOREF Initial value for the Systick timer. 31:26 - Reserved. -

4.5.3 NMI source selection register

The NMI source selection register selects a peripheral interrupts as source for the NMI interrupt of both CPUs. For a list of all peripheral interrupts and their IRQ numbers see

Table 2

Remark: In order to change the interrupt source for the NMI, the NMI source must first be disabled by writing 0 to the NMIEN bit. Then change the source b y updating the IRQN bits and re-enable the NMI source by setting NMIEN.

Table 32. NMI source selection register (NMISRC, address 0x4000 001C) bit description

Bit Symbol Description Reset

5:0 IRQM4 The IRQ number of the interrupt that acts as the Non-Maskable Interrupt (NMI) for the

7:6 - Reserved. Read value is undefined, only zero should be written. 13:8 IRQM0 The IRQ number of the interrupt that acts as the Non-Maskable Interrupt (NMI) for the

29:14 - Reserved. Read value is undefined, only zero should be written. 30 NMIENM0 Write a 1 to this bit to enable the Non-Maskable Interrupt (NMI) source selected by IRQM0.

31 NMIENM4 Write a 1 to this bit to enable the Non-Maskable Interrupt (NMI) source selected by IRQM4. 0

Cortex-M4, if enabled by NMIENM4.

Cortex-M0+, if enabled by NMIENM0. Present on LPC54102 devices.

Present on LPC54102 devices.

. For a description of the NMI functionality, see Ref. 1 “Cortex-M4 T RM”.

value

Remark: If the NMISRC register is used to select an interrupt as the source of Non-Maskable interrupts, and the selected interrupt is enabled, one interrupt request can result in both a Non-Maskable and a normal interrupt. This can be avoided by disabling the normal interrupt in the NVIC.

4.5.4 Asynchronous APB Control register

ASYNCAPBCTRL contains a global enable bit for the asynchronous APB bridge and subsystem, allowing connection to the assoc iat ed per iph e ra ls.

Table 33. Asynchronous APB Control register (ASYNCAPBCTRL, address 0x4000 0020) bit description

Bit Symbol Value Description Reset value

0 ENABLE Enables the asynchronous APB bridge and subsystem. 1

0 Disabled. Asynchronous APB bridge is disabled. 1 Enabled. Asynchronous APB bridge is enabled.

31:1 - - Reserved. Read value is undefined, only zero should be written. -

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4.5.5 System reset status register

The SYSRSTSTAT register shows the source of the latest reset event. The bits are cleared by writing a one to any of the bits. The POR event clears all other bits in this register. If another reset signal - for example the external RESET after the POR signal is negated, then its bit is set to detected. Write a one to clear the reset.

Table 34. System reset status register (SYSRSTSTAT, address 0x4000 0040) bit description

Bit Symbol Value Description

0 POR POR reset status

1 EXTRST Status of the external RESET

2 WDT Status of the Watchdog reset

3 BOD Status of the Brown-out detect reset

4 SYSRST Status of the software system reset

31:5 - - Reserved

UM10850

Chapter 4: LPC5410x System configuration (SYSCON)

pin - remains asserted

0 No POR detected 1 POR detected. Writing a one clears this reset.

pin. External reset status. 0 No reset event detect ed . 1 Reset detected. Writing a one clears this reset.

0 No WDT reset detected 1 WDT reset detected. Writing a one clears this reset.

0 No BOD reset detected 1 BOD reset detected. Writing a one clears this reset.

0 No System reset detected 1 System reset detected. Writing a one clears this reset.

4.5.6 Peripheral reset control register 0

The PRESETCTRL0 register allows software to reset specific peripherals. Writing a zero to any assigned bit in this register clears the reset and allows the specified peripheral to operate. Writing a one asserts the reset.

Table 35. Peripheral reset control register 0 (PRESETCTRL0, address 0x4000 0044) bit description

Bit Symbol Description Reset value

6:0 - Reserved. Read value is undefined, only zero should be written. 0 7 FLASH_RST Flash controller reset control.

8 FMC_RST Flash accelerator reset control.

10:9 - Reserved. Read value is undefined, only zero should be written. 0 11 MUX_RST Input mux reset control.

12 - Reserved. Read value is undefined, only zero should be written. 0 13 IOCON_RST IOCON reset control.

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0 = Clear reset to this function. 1 = Assert reset to this function.

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Table 35. Peripheral reset control register 0 (PRESETCTRL0, address 0x4000 0044) bit description

Bit Symbol Description Reset value

14 GPIO0_RST GPIO0 reset control.

0 = Clear reset to this function. 1 = Assert reset to this function.

15 GPIO1_RST GPIO1 reset control.

0 = Clear reset to this function. 1 = Assert reset to this function. 17:16 - Reserved. Read value is undefined, only zero should be written. 0 18 PINT_RST Pin interrupt (PINT) reset control.

0 = Clear reset to this function. 1 = Assert reset to this function. 19 GINT_RST Grouped interrupt (GINT) reset control.

0 = Clear reset to this function. 1 = Assert reset to this function. 20 DMA_RST DMA reset control.

0 = Clear reset to this function. 1 = Assert reset to this function. 21 CRC_RST CRC generator reset control.

0 = Clear reset to this function. 1 = Assert reset to this function. 22 WWDT_RST Watchdog timer reset control.

0 = Clear reset to this function. 1 = Assert reset to this function. 26:23 - Reserved. Read value is undefined, only zero should be written. 0 27 ADC0_RST ADC0 reset control.

0 = Clear reset to this function. 1 = Assert reset to this function. 31:28 - Reserved. Read value is undefined, only zero should be written. -

4.5.7 Peripheral reset control register 1

The PRESETCTRL1 register allows software to reset specific peripherals. Writing a zero to any assigned bit in this register clears the reset and allows the specified peripheral to operate. Writing a one asserts the reset.

Table 36. Peripheral reset control register 1 (PRESETCTRL1, address 0x4000 0048) bit description

Bit Symbol Description Reset value

0 MRT_RST Multi-rate timer (MRT) reset control.

1 RIT_RST Repetitive interrupt timer (RIT) reset control.

2 SCT0_RST State configurable timer 0 (SCT0) reset control.

8:3 - Reserved. Read value is undefined, only zero should be written. 0 9 FIFO_RST System FIFO reset control.

10 UTICK_RST Micro-tick Timer reset control.

0 0 = Clear reset to this function. 1 = Assert reset to this function.

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Table 36. Peripheral reset control register 1 (PRESETCTRL1, address 0x4000 0048) bit description

Bit Symbol Description Reset value

21:11 - Reserved. Read value is undefined, only zero should be written. 0 22 CT32B2_RST CT32B2 reset control.

0 = Clear reset to this function. 1 = Assert reset to this function.

25:23 - Reserved. Read value is undefined, only zero should be written. 0 26 CT32B3_RST CT32B3 reset control.

0 = Clear reset to this function. 1 = Assert reset to this function.

27 CT32B4_RST CT32B4 reset control.

0 = Clear reset to this function. 1 = Assert reset to this function.

31:28 - Reserved. Read value is undefined, only zero should be written. -

4.5.8 Peripheral reset control set register 0

Writing a 1 to a bit position in PRESETCTRLSET0 sets the corresponding position in PRESETCTRL0. This is a write-only register. For bit assignments, see Table 35

Table 37. Peripheral reset contr ol set regis ter 0 (PRESETCTRLSET0, address 0x4000 004C) bit description

Bit Symbol Description Reset value

31:0 RST_SET0 Writing ones to this register sets the corresponding bit or bits in the PRESETCTRL0

zeroes should be written to them.

4.5.9 Peripheral reset control set register 1

Writing a 1 to a bit position in PRESETCTRLSET1 sets the corresponding position in PRESETCTRL1. This is a write-only register. For bit assignments, see Table 36

Table 38. Peripheral reset contr ol set regis ter 1 (PRESETCTRLSET1, address 0x4000 0050) bit description

Bit Symbol Description Reset value

31:0 RST_SET1 Writing ones to this register sets the corresponding bit or bits in the PRESETCTRL1

zeroes should be written to them.

4.5.10 Peripheral reset control clear register 0

Writing a 1 to a bit position in PRESETCTRLCLR0 clears the corresponding position in PRESETCTRL0. This is a write-only register. For bit assignments, see Table 35

Table 39. Peripheral reset control clear register 0 (PRESETCTRLCLR0, address 0x4000 0054) bit description

Bit Symbol Description Reset value

31:0 RST_CLR0 Writing ones to this register clears the corresponding bit or bits in the

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PRESETCTRL0 register, if they are implemented. Bits that do not correspond to defined bits in PRESETCTRL0 are reserved and only

zeroes should be written to them.

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4.5.1 1 Peripheral reset control clear register 1

Writing a 1 to a bit position in PRESETCTRLCLR1 clears the corresponding position in PRESETCTRL1. This is a write-only register. For bit assignments, see Table 36

Table 40. Peripheral reset control clear register 1 (PRESETCTRLCLR1, address 0x4000 0058) bit description

Bit Symbol Description Reset value

31:0 RST_CLR1 Writing ones to this register clears the corresponding bit or bits in the

PRESETCTRL1 register, if they are implemented. Bits that do not correspond to defined bits in PRESETCTRL1 are reserved and only

zeroes should be written to them.

4.5.12 POR captured value of port 0

The PIOPORCAP0 register captures the state of GPIO port 0 at power-on-r eset. Each bit represents the power-on reset state of one GPIO pin. This register is a read-only register.

Table 41. POR captured PIO status register 0 (PIOPORCAP0, address 0x4000 005C) bit description

Bit Symbol Description Reset value

31:0 PIOPORCAP State of PIO0_31 through PIO0_0 at power-on reset Depends on external circuitry

4.5.13 POR captured value of port 1

The PIOPORCAP1 register captures the state of GPIO port 1 at power-on-r eset. Each bit represents the power-on reset state of one GPIO pin. This register is a read-only register.

Table 42. POR captured PIO status register 1 (PIOPORCAP1, address 0x4000 0060) bit description

Bit Symbol Description Reset value

31:0 PIOPORCAP State of PIO1_31 through PIO1_0 at power-on reset Depends on external circuitry

4.5.14 Reset captured value of port 0

The PIORESCAP0 register captures the state of GPIO port 0 when a reset other than a power-on reset occurs. Each bit represents the reset state of one GPIO pin. This register is a read-only register.

Table 43. Reset captured PIO status register 0 (PIORESCAP0, address 0x4000 0068) bit description

Bit Symbol Description Reset value

31:0 PIORESCAP State of PIO0_31 through PIO0_0 for resets other than POR. Depends on external circuitry

4.5.15 Reset captured value of port 1

The PIORESCAP0 register captures the state of GPIO port 1 when a reset other than a power-on reset occurs. Each bit represents the reset state of one GPIO pin. This register is a read-only register.

Table 44. Reset captured PIO status register 1 (PIORESCAP1, address 0x4000 006C) bit description

Bit Symbol Description Reset value

31:0 PIORESCAP State of PIO1_31 through PIO1_0 for resets other than POR. Depends on external circuitry

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4.5.16 Main clock source select register A

This register selects one of the internal oscillators, IRC, system oscillator, or watchdog oscillator. The oscillator selected is then one of the inputs to the main clock source select register B (see Table 46 the core, memories, and peripherals on the synchronous APB bus are derived from the main clock.

Remark: Note that this selection is internally synchronized: the clock being switched from and the clock being switched to must both be running and have occurred in specific states before the selection actually changes.

Table 45. Main clock source select register A (MAINCLKSELA, addre ss 0x4000 0080) bit

Bit Symbol Value Description Reset value

1:0 SEL Clock source for main clock source selector A 0

31:2 - - Reserved -

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), which selects the clock source for the main clock. All clocks to

description

0x0 IRC Oscillator 0x1 CLKIN 0x2 Watchdog oscillator 0x3 Reserved

4.5.17 Main clock source select register B

This register selects the clock source for the main clock. All clocks to the core, memories, and peripherals are derived from the main clock.

One input to this register is the main clock source select register A (see Table 45 selects one of the three internal oscillators, IRC, system oscillator, or watchdog oscillator.

Table 46. Main clock source select register B (MAINCLKSELB, addre ss 0x4000 0084) bit

description

Bit Symbol Value Description Reset value

1:0 SEL Clock source for main clock source selector B. Selects the

clock source for the main clock.

0x0 MAINCLKSELA. Use the clock source selected in

MAINCLKSELA register. 0x1 System PLL input. 0x2 System PLL output. 0x3 RTC oscillator output. RTC oscillator 32 kHz output.

31:2 - - Reserved -

), which

4.5.18 ADC clock source select register

This register selects a clock source for the 12-bit ADCs that is to the system clock. To use a clock other than the Main clock, select the asynchronous clock mode in the ADC control register.

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Remark: Note that this selection is internally synchronized: the clock being switched from

and the clock being switched to must both be running and have occurred in specific states before the selection actually changes.

Table 47. ADC clock source select (ADCCLKSEL, address 0x4000 008C) bit description

Bit Symbol Value Description Reset value

1:0 SEL ADC clock source. 0

31:2 - Reserved -

4.5.19 CLKOUT clock source select register A

This register pre-selects one of the internal oscillators for the clock sources visible on the CLKOUT pin. The final selection for the CLKOUT clock source is done in the CLKOUT clock source B register.

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0x0 Main clock 0x1 System PLL output 0x2 IRC Oscillator 0x3 reserved

Table 48. CLKOUT clock source select regist er (CLKOUTSELA, address 0x4000 0094) bit

description

Bit Symbol Value Description Reset value

1:0 SEL CLKOUT clock source 0

0x0 Main clock 0x1 CLKIN 0x2 Watchdog oscillator 0x3 IRC oscillator

31:2 - - Reserved -

4.5.20 CLKOUT clock source select register B

This register selects the clock source visible on the CLKOUT pin. The internal oscillators are pre-selected in the CLKOUTSELA register (see Table 48

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Table 49. CLKOUT clock source select regist er (CLKOUTSELB, address 0x4000 0098) bit

Bit Symbol Value Description Reset value

1:0 SEL CLKOUT clock source 0

31:2 - - Reserved -

4.5.21 System PLL clock source select register

This register selects the clock source for the system PLL. Remark: Note that this selection is internally synchronized: the clock being switched from

and the clock being switched to must both be running and have occurred in specific states before the selection actually changes.

T able 50. System PLL clock source select register (SYSPLLCLKSEL, address 0x4000 00A0)

Bit Symbol Value Description Reset value

1:0 SEL System PLL clock source 0

31:2 - - Reserved -

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description

0x0 CLKOUTSELA. Clock source selected in the

CLKOUTSELA register. 0x1 reserved 0x2 reserved 0x3 RTC 32 kHz clock

bit description

0x0 IRC Oscillator 0x1 CLKIN 0x2 Reserved 0x3 RTC 32 kHz clock

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4.5.22 AHB Clock Control register 0

The AHBCLKCTRL0 register enables the clocks to individual system and peripheral blocks. The system clock (bit 0) provides the clock for the AHB, the APB bridge, the CPU, the SYSCON block, and the PMU. This clock cannot be disabled.

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Regarding bits 3 and 4, see Section 2.1.1

Table 51. AHB Clock Control register 0 (AHBCLKCTRL0, address 0x4000 00C0) bit description

Bit Symbol Description Reset value

0 - Reserved. This read-only bit cannot be cleared. 1 1 ROM Enables the clock for the Boot ROM. 0 = Disable; 1 = Enable. 1 2 - Reserved. Read value is undefined, only zero should be written. 0 3 SRAM1 Enables the clock for SRAM1. 0 = Disable; 1 = Enable. 1 4 SRAM2 Enables the clock for SRAM2. 0 = Disable; 1 = Enable. 0 6:5 - Reserved. Read value is undefined, only zero should be written. 0 7 FLASH Enables the clock for the flash controller. 0 = Disable; 1 = Enable. This clock is

8 FMC Enables the clock for the Flash accelerator. 0 = Disable; 1 = Enable. This clock is

10:9 - Reserved. Read value is undefined, only zero should be written. 0 11 INPUTMUX Enables the clock for the input muxes. 0 = Disable; 1 = Enable. 0 12 - Reserved. Read value is undefined, only zero should be written. 0 13 IOCON Enables the clock for the IOCON block. 0 = Disable; 1 = Enable. 0 14 GPIO0 Enables the clock for the GPIO0 port registers. 0 = Disable; 1 = Enable. 0 15 GPIO1 Enables the clock for the GPIO1 port registers. 0 = Disable; 1 = Enable. 0 17:16 - Reserved. Read value is undefined, only zero should be written. 0 18 PINT Enables the clock for the pin interrupt block.0 = Disable; 1 = Enable. 0 19 GINT Enables the clock for the grouped pin interrupt block. 0 = Disable; 1 = Enable. 0 20 DMA Enables the clock for the DMA controller. 0 = Disable; 1 = Enable. 0 21 CRC Enables the clock for the CRC engine. 0 = Disable; 1 = Enable. 0 22 WWDT Enables the clock for the Watchdog Timer. 0 = Disable; 1 = Enable. 0 23 RTC Enables the clock for the RTC. 0 = Disable; 1 = Enable. 0 25:24 - Reserved. Read value is undefined, only zero should be written. 0 26 MAILBOX Enables the clock for the Mailbox. 0 = Disable; 1 = Enable. Present on LPC54102

27 ADC0 Enables the clock for the ADC0 register interface. 0 = Disable; 1 = Enab le. 0 31:28 - Reserved. Read value is undefined, only zero should be written. 0

needed for flash programming, not for flash read.

needed if the flash is being read.

devices

for details of SRAM configuration.

after boot

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4.5.23 AHB Clock Control register 1

The AHBCLKCTRL1 register enables the clocks to individual peripheral blocks.

Table 52. AHB Clock Control register 1 (AHBCLKCTRL1, address 0x4000 00C4) bit description

Bit Symbol Description Reset value

0 MRT Enables the clock for the Multi-Rate Timer. 0 = Disable; 1 = Enable. 0 1 RIT Enables the clock for the repetitive interrupt timer. 0 = Disable; 1 = Enable. 0 2 SCT0 Enables the clock for SCT0. 0 = Disable; 1 = Enable. 0 8:3 - Reserved. Read value is undefined, only zero should be written. 9 FIFO Enables the clock for system FIFOs. 0 = Disable; 1 = Enable. 0 10 UTICK Enables the clock for the Micro-tick Timer. 0 = Disable; 1 = Enable. 0 21:11 - Reserved. Read value is undefined, only zero should be written. 0 22 CT32B2 Enables the clock for CT32B 2. 0 = Disable; 1 = Enable. 0 25:23 - Reserved. Read value is undefined, only zero should be written. 26 CT32B3 Enables the clock for CT32B 3. 0 = Disable; 1 = Enable. 0 27 CT32B4 Enables the clock for CT32B 4. 0 = Disable; 1 = Enable. 0 31:28 - Reserved. Read value is undefined, only zero should be written. -

4.5.24 AHB Clock Control Set register 0

Writing a 1 to a bit position in AHBCLKCTRLSET0 sets the corresponding position in AHBCLKCTRL0. This is a write-only register. For bit assignments, see Table 51

Table 53. Clock control set re gister 0 (AHBCLKCTRLSET0, address 0x4000 00C8) bit description

Bit Symbol Description Reset value

31:0 CLK_SET0 Writing ones to this register sets the corresponding bit or bits in the AHBCLKCTRL0

zeroes should be written to them.

4.5.25 AHB Clock Control Set register 1

Writing a 1 to a bit position in AHBCLKCTRLSET1 sets the corresponding position in AHBCLKCTRL1. This is a write-only register. For bit assignments, see Table 52

Table 54. Clock control set re gister 1 (AHBCLKCTRLSET1, address 0x4000 00CC) bit description

Bit Symbol Description Reset value

31:0 CLK_SET1 Writing ones to this register sets the corresponding bit or bits in the AHBCLKCTRL1

zeroes should be written to them.

4.5.26 AHB Clock Control Clear register 0

Writing a 1 to a bit position in AHBCLKCTRLCLR0 clears the corresponding position in AHBCLKCTRL0. This is a write-only register. For bit assignments, see Table 51

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Table 55. Clock control clear register 0 (AHBCLKCTRLCLR0, address 0x4000 00D0) bit description

Bit Symbol Description Reset value

31:0 CLK_CLR0 Writing ones to this register clears the corresponding bit or bits in the AHBCLKCTRL0

zeroes should be written to them.

4.5.27 AHB Clock Control Clear register 1

Writing a 1 to a bit position in AHBCLKCTRLCLR1 clears the corresponding position in AHBCLKCTRL1. This is a write-only register. For bit assignments, see Table 52

Table 56. Clock control clear register 1 (AHBCLKCTRLCLR1, address 0x4000 00D4) bit description

Bit Symbol Description Reset value

31:0 CLK_CLR1 Writing ones to this register clears the corresponding bit or bits in the AHBCLKCTRL1

zeroes should be written to them.

4.5.28 SYSTICK clock divider register

This register configures the SYSTICK peripheral clock. The SYSTICK timer clock can be shut down by setting the DIV field to zero.

Table 57. SYSTICK clock divider (SYSTICKCLKDIV, address 0x4000 00E0) bit description

Bit Symbol Description Reset value

7:0 DIV SYSTIC K cloc k divider value.

0: Disable SYSTICK timer clock. 1: Divide by 1. to 255: Divide by 255.

31:8 - Reserved. Read value is undefined, only zero should be written. -

4.5.29 System clock divider register

This register controls how the main clock is divided to provide the system clock to the CPU, AHB bus, and memories. The system clock can be shut down completely by setting the DIV field to zero.

Table 58. System clock divider register (AHBCLKDIV, address 0x4000 0100) bit description

Bit Symbol Description Reset value

7:0 DIV System AHB clock divider value.

0: System clock disabled. 1: Divide by 1. to 255: Divide by 255.

31:8 - Reserved. Read value is undefined, only zero should be written. -

0x01

4.5.30 ADC clock source divider register

This register divides the clock to the ADC. The clock can b e shut down by settin g the DIV bits to 0x0.

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Table 59. ADC clock source divider (ADCCLKDIV, address 0x4000 0108) bit description

Bit Symbol Description Reset value

7:0 DIV ADC clock divider value.

31:8 - Reserved. Read value is undefined, only zero should be written. -

4.5.31 CLKOUT clock divider register

This register determines the divider value for the clock signal on the CLKOUT pin.

T able 60. CLKOUT clock divider register (CLKOUTDIV, address 0x4000 010C) bit

Bit Symbol Description Reset value

7:0 DIV CLKOUT clock divider value.

31:8 - Reserved. Read value is undefined, only zero should be written. -

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0 0: Disable ADC clock. 1: Divide by 1. to 255: Divide by 255.

description

0: Disable CLKOUT clock divider. 1: Divide by 1. to 255: Divide by 255.

4.5.32 Frequency measure function control register

This register starts the frequency measurement function and stores the result in the CAPVAL field. The target frequency can be calculated as follows with the frequencies given in MHz:

= (CAPVAL - 2) x F

target

reference

Select the target and reference frequencies using the

Table 61. Frequency measure function control register (FREQMECTRL, address 0x4000 0120) bit descript ion

Bit Symbol Description Reset value

13:0 CAPVAL Stores the capture result which is used to calculate the frequency of the target clock. This

30:14 - Reserved. Read value is undefined, only zero should be written. 31 PROG Set this bit to one to initiate a frequency measurement cycle. Hardware clears this bit

field is read-only.

when the measurement cycle has completed and there is valid capture data in the CAPV AL field (bits 13:0).

See Section 4.2.3 “Measure the frequency of a clock signal”, Section 4.6.5 “Frequency

measure function”, Section 8.6.4 “Frequency measure function reference clock select register”, and Section 8.6.5 “Frequency measure function target clock select register” for

4.5.33 Flash configuration register

Depending on the system clock frequency, access to the flash memory can be configured with various access times by writing to the FLASHCFG r egister. It is recommended to use the set_voltage Power API (see Section 30.4.2 achieve lower power operation. However , flash timing can also be set up by user software as shown in the table.

Enabling buffering, acceleration, and prefetch will substantially improve performance. Buffering saves power by allowing previously accessed information to b e reused without a flash read. Acceleration saves power by reducing CPU stalls. Prefetch typically has a small power cost due to some flash reads being pe rfo rm e d th at ul tim at ely ar e no t ne ed e d

Remark: Improper setting of this register may result in incorrect operation of the flash memory. Do not change the flash access time when using the power API in low-power mode.

Table 62. Flash configuration register (FLASHCFG, main syscon: address 0x4000 0124) bit description

Bit Symbol Value Description Reset

1:0 FETCHCFG Instruction fetch configuration. This field determines how flash accelerator buffers are

3:2 DATACFG Data read configuration. This field determines how flash accelerator buffers are used

4 ACCEL Acceleration enable. 1

5 PREFEN Prefetch enable. 0

6 PREFOVR Prefetch override. This bit only applies when PREFEN = 1 and a buffered instruction

used for instruction fetches.

00 Instruction fetches from flash are not buffered. Every fetch request from the CPU

results in a read of the flash memory. This setting may use significantly more power

than when buffering is enabled. 01 One buffer is used for all instruction fetches. 10 All buffers may be used for instruction fetches. 11 Reserved setting, do not use.

for data accesses. 00 Data accesses from flash are not buffered. Every data access from the CPU results

in a read of the flash memory. 01 One buffer is used for all data accesses. 10 All buffers may be used for data accesses. 11 Reserved setting, do not use.

0 Flash acceleration is disabled. Every flash read (including those fulfilled from a

buffer) takes FLASHTIM + 1 system clocks. This allows more determinism at a cost

of performance. 1 Flash acceleration is enabled. Performance is enhanced, depen dent on other

FLASHCFG settings.

0 No instruction prefetch is performed. 1 If the FETCHCFG field is not 0, the next flash line following the current execution

address is automatically prefetched if it is not already buffered.

is completing for which the next flash line is not already buffered or being prefetched. 0 Any previously initiated prefetch will be completed. 1 Any previously initiated prefetch will be aborted, and the next flash line following the

current execution address will be prefetched if not already buffered.

) to configure device operation in order to

value

0x2

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Table 62. Flash configuration register (FLASHCFG, main syscon: address 0x4000 0124) bit description

Bit Symbol Value Description Reset

value

11:7 - - Reserved 15:12 FLASHTIM Flash memory access time. The number of system clocks used for flash accesses is

equal to FLASHTIM +1. 0x0 1 system clock flash access time (for system clock rates up to 12 MHz). 0x1 2 system clocks flash access time (for system clock rates up to 24 MHz). 0x2 3 system clocks flash access time (for system clock rates up to 48 MHz). 0x3 4 system clocks flash access time (for system clock rates up to 72 MHz). 0x4 5 system clocks flash access time (for system clock rates up to 84 MHz). 0x5 6 system clocks flash access time (for system clock rates up to 100 MHz). others “Value” + 1 system clocks flash access time.

31:16 - - Reserved -

0x0

4.5.34 FIFO control register

This register is used to enable the System FIFO to provide DMA requests for individual peripheral FIFOs. This replaces the specific peripheral DMa request.

Table 63. FIFO control register (FIFOCT RL, address 0x4000 0148) bit description

Bit Symbol Description Reset value

0 U0TXFIFOEN USART0 transmitter FIFO enable 0 1 U1TXFIFOEN USART1 transmitter FIFO enable 0 2 U2TXFIFOEN USART2 transmitter FIFO enable 0 3 U3TXFIFOEN USART3 transmitter FIFO enable 0 4 SPI0TXFIFOEN SPI0 transmitter FIFO enable 0 5 SPI1TXFIFOEN SPI1 transmitter FIFO enable 0 6 - Reserved 7 - Reserved 8 U0RXFIFOEN USART0 receiver FIFO enable 0 9 U1RXFIFOEN USART1 receiver FIFO enable 0 10 U2RXFIFOEN USART2 receiver FIFO enable 0 11 U3RXFIFOEN USART3 receiver FIFO enable 0 12 SPI0RXFIFOEN SPI0 receiver FIFO enable 0 13 SPI1RXFIFOEN SPI1 receiver FIFO enable 0 31:14 - Reserved -

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4.5.35 IRC control register

This register is used to trim the on-chip 12 MHz oscillator. The trim value is factory-preset and written by the boot code on start-up.

Table 64. IRC control register (IRCCTRL, address 0x4000 0184) bit description

Bit Symbol Description Reset value

7:0 TRIM Trim value Initially 0x80. Boot code will alter to a device-specific

31:8 - Reserved -

4.5.36 RTC oscillator control register

This register enables the 32 kHz output of the RTC oscillator. This clock can be used to create the main clock when the PLL input or output is selected as the clock source to the main clock.

T able 65. RTC oscillator control register (RTCOSCCTRL, address 0x4000 0190) bit

Bit Symbol Value Description Reset value

0 EN RTC 32 kHz clock enable. 1

31:1 - - Reserved 0

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value. Users should not write to this register.

description

0 Disabled. RTC clock off. 1 Enabled. RTC clock on.

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4.5.37 PLL registers

The PLL provides a wide range of frequencies and can potentially be used for many on-chip functions. the PLL can be used with or without a spread spectrum clock generator . See Section 4.6.4 “

4.5.37.1 System PLL control register

The SYSPLLCTRL register provides most of the control over basic selections of PLL modes and operating details.

Table 66. System PLL control register (SYSPLLCTRL, address 0x4000 01B0 bit description

Bit Symbol Value Description Reset

3:0 SELR Bandwidth select R value 9:4 SELI Bandwidth select I value 14:10 SELP Bandwidth select P value 15 BYPASS PLL bypass control 1

16 BYPASS

CCODIV2

17 UPLIMOFF Disable upper frequency limiter.

18 BANDSEL PLL filter control. Set this bit to one when the spread spectrum controller is disabled

19 DIRECTI PLL0 direct input enable 0

20 DIRECTO PLL0 direct output enable 0

31:21 - Reserved. Read value is undefined, only zero should be written. -

0 Disabled. PLL CCO is used to create the PL L output. 1 Enabled. PLL is bypassed, the PLL input clock is routed directly to the PLL output

(default). Bypass feedback clock divide by 2. 0

0 Divide by 2. The CCO feedback clock is divided by 2 in addition to the programmed

M divide.

1 Bypass. The CCO feedback clock is divided only by the programmed M divide.

For spread spectrum mode: SEL_EXT = 0, BANDSEL = 0, and UPLIMOFF = 1. 0 Normal mode. 1 Upper frequency limiter disabled.

or at low frequencies.

For spread spectrum mode: SEL_EXT = 0, BANDSEL = 0, and UPLIMOFF = 1. 0 SSCG control. The PLL filter uses the parameters derived from the spread spectrum

controller. 1 MDEC control. The PLL filter uses the programmable fields SELP, SELR, and SELI

in this register to control the filter constants.

0 Disabled. The PLL input divider (N divider) output is used to drive the PLL CCO. 1 Enabled. The PLL input divider (N divider) is bypassed. the PLL input clock is used

directly to drive the PLL CCO.

0 Disabled. The PLL output divider (P divider) is used to create the PLL output. 1 Enabled. The PLL output divider (P divider) is bypassed, the PLL CCO output is

used as the PLL output.

PLL functional description” for additional details of PLL operation.

value

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4.5.37.2 System PLL status register

The read-only PLL0_STAT SYSPLLSTAT register provides the PLL lock status Remark: The lock status does not reliably indicate the PLL status for the following two

configurations: spread-spectrum mode or fractional enable d or low input clock frequencies such as 32 kHz. In these cases, refer to the PLL lock times listed in the specific device data sheet to obtain appropriate wait times for the PLL to lock.

Table 67. System PLL status register (SYSPLLSTAT, address 0x4000 01B4) bit description

Bit Symbol Description Reset value

0 LOCK PLL0 lock indicator 0 31:1 - Reserved -

4.5.37.3 System PLL N-divider register

Remark: The PLL N-divider register does not use the direct binary representation of N

divide value directly. Instead, it uses an encoded version NDEC. Remark: While the PLL0 output is in use, do not change the NDEC value. Changing the

NDEC value changes the FCCO frequency and can cause the system to fail.

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• The valid range for N is 1 to 2^8. This value is encoded into a 10-bit NDEC value. The

relationship can be expressed through the following pseudo-code:

N_max=0x00000100, x=0x00000080; switch (N) { case 0: x = 0xFFFFFFFF; case 1: x = 0x00000302; case 2: x = 0x00000202;

default: for (i = N; i <= N_max; i++) x = (((x ^ (x>>2) ^ (x>>3) ^ (x>>4)) & 1) << 7) |

((x>>1) & 0x7F); }

NENC[9:0] = x;

Table 68. System PLL N-divider register (SYSPLLNDEC, address 0x4000 01B8) bit description

Bit Symbol Description Reset value

9:0 NDEC Decoded N-divider coefficient value 0 10 NREQ NDEC reload request. When a 1 is written to this bit, the NDEC value is loaded into the

31:11 - Reserved. Read value is undefined, only zero should be written. -

0 PLL. Must be cleared by software for any subsequent load, or the PLL can be powered down and back up via the PDEN_SYS_PLL bit in the PDRUNCFG register if the NDEC value is changed.

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4.5.37.4 System PLL P-divider register

Remark: The PLL P-divider register does not use the direct binary representation of P

divide value directly. Instead, it uses an encoded version PDEC. Remark: While the PLL0 output is in use, do not change the PDEC value. Changing the

PDEC value changes the PLL output frequency and can cause the system to fail.

• The valid range for P is from 1 to 2^5. This value is encoded into a 7-bit PDEC value.

The relationship can be expressed through the following pseudo-code:

P_max=0x20, x=0x10; switch (P) { case 0: x = 0xFFFFFFFF; case 1: x = 0x00000062; case 2: x = 0x00000042;

default: for (i = P; i <= P_max; i++) x = (((x ^ (x>>2)) & 1) << 4) | ((x>>1) & 0xF); } PDEC[6:0] = x;

Table 69. System PLL P-divider register (SYSPLLPDEC, address 0x4000 01BC) bit description

Bit Symbol Description Reset value

6:0 PDEC Decoded P-divider coefficient value 0 7 PREQ PDEC reload request. When a 1 is written to this bit, the PDEC value is loaded into the PLL.

31:8 - Reserved. Read value is undefined, only zero should be written. -

Must be cleared by software for any subsequent load, or the PLL can be powered down and back up via the PDEN_SYS_PLL bit in the PDRUNCFG register if the PDEC value is changed.

4.5.37.5 Spread spectrum control with PLL0

The spread spectrum functionality can be used to provide a sprea d spectrum clock, which can decrease electromagnetic interference (EMI).

The Spread Spectrum Clock Generator can be used in several ways:

• It can encode M-divider values between 1 and 255 to produce the MDEC value used

directly by the PLL, saving the need for executing encoding algorithm code, or hard-coding predetermined values into an application.

• It can provide a fractional rate feature to the PLL.

• It can be set up to automatically alter the PLL CCO frequency on an ongoing basis to

decrease electromagnetic interference (EMI).

If the spread spectrum mode is enabled, choose N to ensure 2 MHz < Fin/N < 4 MHz. Spread spectrum mode cannot be used when Fin = 32 kHz.

When the modulation (MR) is set to zero, the PLL becomes a fractional PLL.

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4.5.37.5.1 System PLL spread spectrum control register 0

Table 70. System PLL spread spectrum control register 0 (SYSPLLSSCTRL0, address 0x4000 01C0) bit description

Bit Symbol Value Description Reset

16:0 MDEC Decoded M-divider coefficient value 0 17 MREQ MDEC reload request. When a 1 is written to this bit, the MDEC value is loaded into

18 SEL_EXT Select spread spectrum mode. Selects the source of the feedback divider value. For

31:19 - Reserved. Read value is undefined, only zero should be written. -

value

0 the PLL. Must be cleared by software for any subsequent load, or the PLL can be powered down and back up via the PDEN_SYS_PLL bit in the PDRUNCFG register if the MDEC value is changed.

0 normal mode, this must be the value from the MDEC field in this register.

For spread spectrum mode: SEL_EXT = 0, BANDSEL = 0, and UPLIMOFF = 1.

0 The PLL feedback divider value comes from the spread spectrum controller. 1 The PLL feedback divider value comes from the MDEC field in this register.

PLL0 M-divider register: The PLL0 M-divider value (MDEC) can be set directly if the

PLL0 is not used with the spread spectrum clock generator (SSCG). If the SSCG is enabled via the SEL_EXT bit, then the SSCG sets the MDEC value.

Remark: MDEC does not use the direct binary representations of M directly. Instead, it uses an encoded version of M. The valid range for M is 1 to 2^15. This value is encoded into a 17-bit MDEC value.

The relationship between M and MDEC is expressed via the following pseudo-code.

M_max=0x00008000, x=0x00004000; switch (M) { case 0: x = 0xFFFFFFFF; case 1: x = 0x00018003; case 2: x = 0x00010003;

default: for (i = M; i <= M_max; i++) x = (((x ^ (x>>1)) & 1) << 14) | ((x>>1) & 0x3FFF); } MDEC[16:0] = x;

The values for SELP, SELI, and SELR depend on the value for M as expressed by the following pseudo-code:

if (M < 60) then SELP = (M>>1) + 1 else SELP = 31; if (M > 16384) then SELI = 1 else if (M > 8192) then SELI = 2 else if (M > 2048) then SELI = 4 else if (M >= 501) then SELI = 8

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else if (M >=60) then SELI = 4*(1024/(M+9)) else SELI = (M & 0x3C) + 4; /* & denotes bitwise AND */ SELR = 0;

Remark: If the 32 kHz RTC oscillator is used as the reference input to the PLL, then use fixed values SELI=1, SELP=6, and SELR=0, instead of applying the above rules. These values reduce the PLL loop bandwidth to combat the effect of reference oscillator jitter on the PLL output signal.

Remark: The values for SELP, SELI, and SELR are generated by the encoding block when the spread spectrum clock generator is enabled and need not be programmed explicitly.

Remark: While the PLL0 output is in use, do not change the MDEC value. Changing the MDEC value changes the FCCO frequency and can cause the system to fail.

4.5.37.5.2 System PLL spread spectrum control register 1

Table 71. System PLL spread spectrum control register 1 (SYSPLLSSCTRL1, address 0x4000 01C4) bit description

Bit Symbol Value Description Reset

18:0 MD M- divider value with fraction.

19 MDREQ MD reload request. When a 1 is written to this bit, the MD value is loaded into the PLL.

22:20 MF Programmable modulation frequency fm = Fref/Nss with Fref = Fin/N

25:23 MR Programmable frequency modulation depth

value

MD[18:11]: integer portion of the feedback divider value. MD[10:0]: fractional portion of the feedback divider value.

This bit is cleared when the load is complete.

0b000 => Nss = 512 (fm ≈ 3.9 - 7.8 kHz) 0b001 => Nss ≈ 384 (fm ≈ 5.2 - 10.4 kHz) 0b010 => Nss = 256 (fm ≈ 7.8 - 15.6 kHz) 0b011 => Nss = 128 (fm ≈ 15.6 - 31.3 kHz) 0b100 => Nss = 64 (fm ≈ 32.3 - 64.5 kHz) 0b101 => Nss = 32 (fm ≈ 62.5- 125 kHz) 0b110 => Nss ≈ 24 (fm ≈ 83.3- 166.6 kHz) 0b111 => Nss = 16 (fm ≈ 125- 250 kHz)

δfmodpk-pk = Fref x k/Fcco = k/MDdec 0 = no spread 0b000 => k = 0 (no spread spectrum) 0b001 => k ≈ 1 0b010 => k ≈ 1.5 0b011 => k ≈ 2 0b100 => k ≈ 3 0b101 => k ≈ 4 0b110 => k ≈ 6 0b1 11 => k ≈ 8

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Table 71. System PLL spread spectrum control register 1 (SYSPLLSSCTRL1, address 0x4000 01C4) bit description

Bit Symbol Value Description Reset

value

27:26 MC Modulation waveform control 0 = no compensation

Compensation for low pass filtering of the PLL to get a triangular modulation at the output of the PLL, giving a flat frequency spectrum.

0b00 => no compensation 0b10 => recommended setting 0b11 => max. compensation

28 PD Power down. 1

0 Enabled. Spread spectrum controller is enabled 1 Disabled. Spread spectrum controller is disabled

29 DITHER Select modulation frequency. 0

0 Fixed. Fixed modulation frequency. 1 Dither. Randomly dither between two modulation frequencies.

31:30 - Reserved. Read value is undefined, only zero should be written. -

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4.5.38 Power Configuration register

The PDRUNCFG register controls the power to the various analog blocks. Remark: for safety, this register should not be written. Changing the contents of

PDRUNCFG should be accomplished by writing to PDRUNCFGSET and/or PDRUNCFGCLR. This prevents inadvertent changes to unintended bits. Reserved bits

must not be changed by user software.

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Regarding bits 13 through 16, see Section 2.1.1

Table 72. Power Configuration register (PDRUNCFG, address 0x4000 021 0) bit description

Bit Symbol Description Reset

2:0 - . 3 PDEN_IRC_OSC IRC oscilla tor output. 0 = Powered; 1 = Powered down. 0 4 PDEN_IRC IRC oscillator. 0 = Powered; 1 = Powered down. 0 5 PDEN_FLASH Flash memory. 0 = Powered; 1 = Powered down. 0 6 - Reserved. 7 PDEN_BOD_RST Brown-out Dete ct reset. 0 = Powered; 1 = Powered down. 0 8 PDEN_BOD_INTR Brown-out Detect interrupt. 0 = Powered; 1 = Powered down. 1 9 - Reserved. 10 PDEN_ADC0 ADC0. 0 = Powered; 1 = Powered down. 1 12:11 - Reserved. 13 PDEN_SRAM0A First 8 KB of SRAM0. 0 = Powered; 1 = Powered down. 0 14 PDEN_SRAM0B Remaining portion of SRAM0. 0 = Powered; 1 = Powered down. 0 15 PDEN_SRAM1 SRAM1. 0 = Powered; 1 = Powere d down. 0 16 PDEN_SRAM2 SRAM2 (undedicated 8 KB RAM). 0 = Powered; 1 = Powered down. 0 17 PDEN_ROM ROM. 0 = Powered; 1 = Powered dow n. 0 18 - Reserved. 19 PDEN_VDDA Vdda to the ADC, must be enabled for the ADC to work. Also see bit 23. 0 = Powered;

20 PDEN_WDT_OSC Watchdog oscillator. 0 = Powered; 1 = Powered down. 1 21 - Reserved. 22 PDEN_SYS_PLL PLL0. 0 = Powered; 1 = Powered down. 1 23 PDEN_VREFP Vrefp to the ADC, must be enabled for the ADC to work. Also see bit 19. 0 = Powered;

24 PDEN_32K_OSC 32 kHz RTC oscillator. 0 = Powered; 1 = Powered down. 0 31:25 - Reserved. -

1 = Powered down.

for details of SRAM configuration.

value

4.5.39 Power configuration set register

Writing a 1 to a bit position in PDRUNCFGSET sets the corresponding position in PDRUNCFG. This is a write-only register. For bit assignments, see Table 72

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Table 73. Power configuration set register (PDRUNCFGSET, address 0x4000 0214) bit description

Bit Symbol Description Reset value

31:0 PD_SET Writing ones to this register sets the corresponding bit or bits in the PDRUNCFG register, if

they are implemented. Bits that do not correspond to defined bits in PDRUNCFG are reserved and only zeroes

should be written to them.

4.5.40 Power configuration clear register

Writing a 1 to a bit position in PDRUNCFGCLR clears the corresponding position in PDRUNCFG. This is a write-only register. For bit assignments, see Table 72

Table 74. Power configuration clear register (PDRUNCFGCLR, address 0x4000 0218) bit description

Bit Symbol Description Reset value

31:0 PD_CLR Writing ones to this register clears the corresponding bit or bits in the PDRUNCFG register,

if they are implemented. Bits that do not correspond to defined bits in PDRUNCFG are reserved and only zeroes

should be written to them.

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4.5.41 Start enable register 0

The STARTER0 and STARTER1 registers enable an interrupt for wake-up from deep-sleep and power-down modes.

Some interrupts are typically used in sleep mode only and will not occur during deep-sleep or power-down modes because relevant clocks are stopped. However, it is possible to enable those clocks (significantly increasing power consumption in the reduced power mode), making these wake-ups possible.

The pattern match feature of the pin interrupt requires a clock in order to operate, and will not wake up the device from reduced power modes beyond Sleep mode.

Whether peripheral interrupts can occur during deep-sleep or power-down modes depends on the peripheral, its configuration, and system setup.

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Remark: Also enable the corresponding interrupts in the NVIC. See Table 4 “

Interrupt

Set-Enable Register 0 register”.

Table 75. Start enable register 0 (STARTER0, address 0x4000 0240) bit description

Bit Symbol Description Reset

0 W WDT WW DT interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. 0 1 BOD BOD interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. 0 2 - Reserved. Read value is undefined, only zero should be written. 3 DMA DMA wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Typically used in sleep mode

4 G INT0 Group interrupt 0 wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. 0 5 PINT0 GPIO pin interrupt 0 wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Not for pattern

6 PINT1 GPIO pin interrupt 1 wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Not for pattern

7 PINT2 GPIO pin interrupt 2 wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Not for pattern

8 PINT3 GPIO pin interrupt 3 wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Not for pattern

9 UT ICK Micro-tick Timer wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. 0 10 MRT Multi-Rate Timer wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Typically used in

11 CT32B0 Standard counter/timer CT32B0 wake-up. 0 = Wake-up disabled. 1 = Wake-up

12 CT32B1 Standard counter/timer CT32B1 wake-up. 0 = Wake-up disabled. 1 = Wake-up

13 CT32B2 Standard counter/timer CT32B2 wake-up. 0 = Wake-up disabled. 1 = Wake-up

14 CT32B3 Standard counter/timer CT32B3 wake-up. 0 = Wake-up disabled. 1 = Wake-up

value

only since the peripheral clock must be running for it to function.

match.

sleep mode only since the peripheral clock must be running for it to function.

enabled.Typically used in sleep mode only.

enabled.Typically used in sleep mode only since the peripheral clock must be running for it to function.

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Table 75. Start enable register 0 (STARTER0, address 0x4000 0240) bit description

Bit Symbol Description Reset

15 CT32B4 Standard counter/timer CT32B4 wake-up. 0 = Wake-up disabled. 1 = Wake-up

enabled.Typically used in sleep mode only since the peripheral clock must be running for it to function.

16 SCT0 SCT0 wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled.Typically used in sleep mode

only since the peripheral clock must be running for it to function.

17 USART0 USART0 interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Peripheral

interrupt.

18 USART1 USART1 interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Peripheral

interrupt.

19 USART2 USART2 interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Peripheral

interrupt.

20 USART3 USART2 interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Peripheral

interrupt. 21 I2C0 I2C0 interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Peripheral interrupt. 0 22 I2C1 I2C1 interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Peripheral interrupt. 0 23 I2C2 I2C2 interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Peripheral interrupt. 0 24 SPI0 SPI0 interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Peripheral interrupt. 0 25 SPI1 SPI1 interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Peripheral interrupt. 0 26 ADC0_SEQA A DC0 sequence A interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up

enabled.Typically used in sleep mode only since the peripheral clock must be running for it

to function. 27 ADC0_SEQB A DC0 sequence B interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up

enabled.Typically used in sleep mode only since the peripheral clock must be running for it

to function. 28 ADC0_THCMP ADC0 threshold and error interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up

enabled.Typically used in sleep mode only since the peripheral clock must be running for it

to function. 29 RTC RTC interrupt alarm and wake-up timer. 0 = Wake-up disabled. 1 = Wake-up enabled. 0 30 - Reserved. Read value is undefined, only zero should be written. 31 MAILBOX Mailb ox interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled.At least one CPU

must be running in order for a mailbox interrupt to occur. Present on LPC54102 devices.

…continued

value

4.5.42 Start enable register 1

The STARTER1 register selects additional interrupts that may wake up the part from

deep-sleep and power-down modes.

Some interrupts are typically used in sleep mode only and will not occur during

deep-sleep or power-down modes because relevant clocks are stopped. However, it is

possible to enable those clocks (significantly increasing power consumption in the

reduced power mode), making these wake-ups possible.

The pattern match feature of the pin interrupt requires a clock in order to operate, and will

not wake up the device from reduced power modes beyond Sleep mode.

Remark: Also enable the corresponding interrupts in the NVIC. See Table 5 “

Set-Enable Register 1 register”.

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Table 76. Start enable register 1 (STARTER1, address 0x4000 0244) bit description

Bit Symbol Description Reset

0 G INT1 Group interrupt 0 wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. 0 1 PINT4 GPIO pin interrupt 4 wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Not for pattern

2 PINT5 GPIO pin interrupt 5 wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Not for pattern

3 PINT6 GPIO pin interrupt 6 wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Not for pattern

4 PINT7 GPIO pin interrupt 7 wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Not for pattern

7:5 - Reserved. Read value is undefined, only zero should be written. 0 8 RIT Repetitive Interrupt Timer interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled.

31:15 - Reserved. Read value is undefined, only zero should be written. -

value

match.

Typically used in sleep mode only since the peripheral clock must be running for it to function.

4.5.43 Start enable set register 0

Writing a 1 to a bit position in STARTERSET0 sets the corresponding position in

STARTER0. This is a write-only register. For bit assignments, see Table 75

Table 77. Start enable set register 0 (STARTERSET0, address 0x4000 0248) bit des cription

Bit Symbol Description Reset value

31:0 START_SET0 Writing ones to this register sets the corresponding bit or bits in the STARTER0

zeroes should be written to them.

4.5.44 Start enable set register 1

Writing a 1 to a bit position in STARTERSET1 sets the corresponding position in

STARTER1. This is a write-only register. For bit assignments, see Table 76

Table 78. Start enable set register 1 (STARTERSET1, address 0x4000 024C) bit description

Bit Symbol Description Reset value

31:0 START_SET1 Writing ones to this register sets the corresponding bit or bits in the STARTER1

zeroes should be written to them.

4.5.45 Start enable clear register 0

Writing a 1 to a bit position in STARTERCLR0 clears the corresponding position in

STARTER0. This is a write-only register. For bit assignments, see Table 75

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Table 79. Start enable clear register 0 (STARTERCLR0, address 0x4000 0250) bit description

Bit Symbol Description Reset value

31:0 START_CLR0 Writing ones to this register clears the corresponding bit or bits in the STARTER0

zeroes should be written to them.

4.5.46 Start enable clear register 1

Writing a 1 to a bit position in STARTERCLR1 clears the corresponding position in

STARTER1. This is a write-only register. For bit assignments, see Table 76

Table 80. Start enable clear register 1 (STARTERCLR1, address 0x4000 0254) bit description

Bit Symbol Description Reset value

31:0 START_CLR1 Writing ones to this register clears the corresponding bit or bits in the STARTER1

zeroes should be written to them.

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4.5.47 Dual-CPU related registers

These registers control usage aspects of the two CPUs in an LPC54102 device. They are

not used in an LPC54101 device that only provide a single CPU.

4.5.47.1 CPU Control register

The CPUCTRL register provides control for the 2 CPUs. Note that the Cortex-M4 is

factory set to be the master. The user can assign Cortex-M0+ to be the master CPU via

this register if needed after it is brought out of reset by Cortex-M4. The master CPU

cannot be reset or have its clock disabled via this register. Only the master CPU can use

the Power APIs to cause the device to enter reduced power modes.

If the clock to the slave CPU is to be disabled at some point in the application for power

savings, that CPU should have entered its own sleep mode prior to that point. This avoids

incomplete operations in the slave CPU.

Table 81. CPU Control register (CPUCTRL, address 0x4000 0300) bit description

Bit Symbol Value Description Reset

0 MASTERCPU Indicates which CPU is considered the master. This is factory set assign the

1 - - Reserved. Read value is undefined, only zero should be written. 2 CM4CLKEN Cortex-M4 clock enable. 1

3 CM0CLKEN Cortex-M0+ clock enable. 1

4 CM4RSTEN Cortex-M4 reset. 0

5 CM0RSTEN Cortex-M0+ reset. 0

6 POWERCPU Identifies the own er of reduced power mode control: which CPU can cause the

14:7 - - Reserved. Read value is undefined, only zero should be written. 15 - - Must be written as a 1. 31:16 - - Must be written as 0xC0C4 for the write to have an effect. -

value

Cortex-M4 as the master. The master CPU cannot have its clock turned off via the related CMnCLKEN bit or

be reset via the related CMxRSTEN in this register. The slave CPU wakes up briefly following device reset, then goes back to sleep

until activated by the master CPU. 0 M0+. Cortex-M0+ is the master CPU. 1 M4. Cortex-M4 is the master CPU.

0 Disabled. The Cortex-M4 clock is not enabled. 1 Enabled. The Cortex-M4 clock is enabled.

0 Disabled. The Cortex-M0+ clock is not enabled. 1 Enabled. The Cortex-M0+ clock is enabled.

0 Disabled. The Cortex-M4 is not being reset. 1 Enabled. The Cortex-M4 is being reset.

0 Disabled. The Cortex-M0+ is not being reset. 1 Enabled. The Cortex-M0+ is being reset.

device to enter Deep Sleep, Power-down, and Deep Power-down modes. 0 M0+. Cortex-M0+ is the owner of reduced power mode control. 1 M4. Cortex-M4 is the owner of reduced power mode control.

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4.5.47.2 Coprocessor Boot register

CPBOOT can be used in an application that uses both CPUs in order to send the slave processor (the CPU not selected as the master by the MASTERCPU bit in the CPUCTRL register) to an appropriate boot address that is different than the master CPU.

T able 82. Coprocessor Boot register (CPBOOT, address 0x4000 0304) bit description

Bit Symbol Description Reset value

31:0 BOOTADDR Slave processor boot address. 0

4.5.47.3 Coprocessor Stack register

CPST ACK can be used in an application that uses both CPUs in order to set up the stack for the slave processor (the CPU not selected as the master by the MASTERCPU bit in the CPUCTRL register) to an appropriat e ad dr e ss that is different than the master CPU.

T able 83. Coprocessor Stack register (CPSTACK, address 0x4000 0308) bit description

Bit Symbol Description Reset value

31:0 STACKADDR Slave processor stack address. 0

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4.5.47.4 Coprocessor Status register

CPU_STA T provid es some status for dual CPUs. This register can be read by software at run time, or with a debugger.

Table 84. Coprocessor Status register (CPSTAT, address 0x4000 030C) bit description

Bit Symbol Description Reset value

0 CM4SLEEPING When 1, the Cortex-M4 CPU is sleeping. 0 1 CM0SLEEPING When 1, the Cortex-M0+ CPU is sleeping. 0 2 CM4LOCKUP When 1, the Cortex-M4 CPU is in lockup. 0 3 CM4LOCKUP When 1, the Cortex-M0+ CPU is in lockup. 0 31:4 - Reserved. Read value is undefined, only zero should be written. -

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4.5.48 JTAG ID code register

This register contains the JTAG ID code.

Table 85. JTAG ID code register (JTAGIDCODE, address 0x4000 03F4) bit description

Bit Symbol Description Value

31:0 JTAGID JTAG ID code. 0x1FEC E02B

4.5.49 Device ID0 register

This register contains the part ID. The part ID can also be obtained using the ISP or IAP ReadPartID commands. See Table 488

T able 86. Device ID0 register (DEVICE_ID0, address 0x4000 03F8) bit description

Bit Symbol Description Reset value

31:0 PARTID Part ID part dependent

T able 87. Device ID0 register values

Part number Part ID

LPC54101J256 0x8845 4101 LPC54101J512 0x8885 4101 LPC54102J256 0x8845 4102 LPC54102J512 0x8885 4102

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and Table 501.

4.5.50 Device ID1 register

This register contains an ID that reflects the boot ROM and device revisions.

T able 88. Device ID1 register (DEVICE_ID1, address 0x4000 03FC) bit description

Bit Symbol Description Value

31:0 REVID Revision. part dependent

T able 89. Device ID1 register values

Part number Part ID

LPC54101J256 0x0881FECE (device revision ‘B’ and boot code version 17.1) LPC54101J512 0x0881FECE (device revision ‘B’ and boot code version 17.1) LPC54102J256 0x0881FECE (device revision ‘B’ and boot code version 17.1) LPC54102J512 0x0881FECE (device revision ‘B’ and boot code version 17.1) LPC54101J256 0x08C1FECE (device revision ‘C’ and boot code version 17.1) LPC54101J512 0x08C1FECE (device revision ‘C’ and boot code version 17.1) LPC54102J256 0x08C1FECE (device revision ‘C’ and boot code version 17.1) LPC54102J512 0x08C1FECE (device revision ‘C’ and boot code version 17.1)

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4.5.51 Asynchronous peripheral reset control register

The ASYNCPRESETCTRL register allows software to reset specific peripherals attached to the async APB bridge. Writing a zero to any assigned bit in this register clears the reset and allows the specified peripheral to operate. Writing a one asserts the reset.

Table 90. Asynchronous peripheral reset control register (ASYNCPRESETCTRL, address 0x4008 0000) bit

description

Bit Symbol Description Reset value

0- Reserved 1 USART0 USART0 reset control.

2 USART1 USART1 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function. 0 3 USART2 USART2 reset control.0 = Clear reset to this function. 1 = Assert reset to this function. 0 4 USART3 USART3 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function. 0 5 I2C0 I2C0 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function. 6 I2C1 I2C1 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function. 0 7 I2C2 I2C2 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function. 0 8- Reserved 9 SPI0 SPI0 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function. 0 10 SPI1 SPI1 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function. 0 12:11 - Reserved 13 CT32B0 Standard counter/timer CT32B0 reset control. 0 = Clea r reset t o this functi on. 1 = Assert

14 CT32B1 Standard counter/timer CT32B1 reset control. 0 = Clea r reset t o this functi on. 1 = Assert

15 FRG0 FRG reset control. 0 = Clear reset to this function. 1 = Assert reset to this function. 0 31:16 - Reserved -

0 = Clear reset to this function. 1 = Assert reset to this function.

reset to this function.

4.5.52 Asynchronous peripheral reset control set register

Writing a 1 to a bit position in ASYNCPRESETCTRLSET sets the corresponding position in ASYNCPRESETCTRL. This is a write-only register. For bit assignments, see Table 90

Table 91. Asynchronous peripheral rese t control set register (ASYNCPRESETCTRLSET, address 0x4008 0004) bit

description

Bit Symbol Description Reset value

31:0 ARST_SET Writing ones to this register sets the corresponding bit or bits in the

ASYNCPRESETCTRL register, if they are implemented. Bits that do not correspond to defined bits in ASYNCPRESETCTRL are reserved and

only zeroes should be written to them.

4.5.53 Asynchronous peripheral reset control clear register

Writing a 1 to a bit position in ASYNCPRESETCTRLCLR clears the corresponding position in PRESETCTRL0. This is a write-only register. For bit assig nments, see

Table 90

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Table 92. Asynchronous peripheral rese t control clear register (ASYNCPRESETCTRLCLR, address 0x4008 0008)

bit description

Bit Symbol Description Reset value

31:0 ARST_CLR Writing ones to this register clears the corresponding bit or bits in the

ASYNCPRESETCTRL register, if they are implemented. Bits that do not correspond to defined bits in ASYNCPRESETCTRL are reserved and

only zeroes should be written to them.

4.5.54 Asynchronous APB clock control register

This register controls how the clock selected for the asynchronous APB peripherals is divided to provide the clock to the asynchronous peripherals. The clock will be stopped if the DIV field is set to zero.

Table 93. Asynchronous APB clock control register (ASYNCAPBCLKCTRL, address 0x4008 0010) bit description

Bit Symbol Description Reset value

0 - Reserved. Read value is undefined, only zero should be written. 1 USART0 Controls the clock for USART0. 0 = Disable; 1 = Enable. 0 2 USART1 Controls the clock for USART1. 0 = Disable; 1 = Enable. 0 3 USART2 Controls the clock for USART2. 0 = Disable; 1 = Enable. 0 4 USART3 Controls the clock for USART3. 0 = Disable; 1 = Enable. 0 5 I2C0 Controls the clock for I2C0. 0 = Disable; 1 = Enable. 6 I2C1 Controls the clock for I2C1. 0 = Disable; 1 = Enable. 0 7 I2C2 Controls the clock for I2C2. 0 = Disable; 1 = Enable. 0 8 - Reserved. Read value is undefined, only zero should be written. 9 SPI0 Controls the clock for SPI0. 0 = Disable; 1 = Enable. 0 10 SPI1 Controls the clock for SPI1. 0 = Disable; 1 = Enable. 0 12:11 - Reserved. Read value is undefined, only zero should be written. 13 CT32B0 Controls the clock for CT32B0. 0 = Disable; 1 = Enable. 0 14 CT32B1 Controls the clock for CT32B1. 0 = Disable; 1 = Enable. 0 15 FRG0 Controls the clock for the Fractional Rate Generator used with the USARTs. 0 = Disable;

31:16 - Reserved. Read value is undefined, only zero should be written. -

1 = Enable.

4.5.55 Asynchronous APB clock control set register

Writing a 1 to a bit position in ASYNCAPBCLKCTRLSET sets the corresponding position in ASYNCAPBCLKCTRL. This is a write-only register. For bit assignments, see Table 90

Table 94. Asynchronous APB clock control set register (ASYNCAPBCLKCTRLSET, address 0x4008 0014) bit

description

Bit Symbol Description Reset value

31:0 ACLK_SET Writing ones to this register sets the correspon ding bit or bits in the

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ASYNCAPBCLKCTRL register, if they are implemented. Bits that do not correspond to defined bits in ASYNCPRESETCTRL are reserved and

only zeroes should be written to them.

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4.5.56 Asynchronous APB clock control clear register

Writing a 1 to a bit position in ASYNCAPBCLKCTRLCLR clears the corresponding position in ASYNCAPBCLKCTRL. This is a write-only register. For bit assignments, see

Table 90

Table 95. Asynchronous APB clock control clear register (ASYNCAPBCLKCTRLCLR, address 0x4008 0018) bit

description

Bit Symbol Description Reset value

31:0 ACLK_CLR Writing ones to this register clears the corresponding bit or bits in the

ASYNCAPBCLKCTRL register, if they are implemented. Bits that do not correspond to defined bits in ASYNCAPBCLKCTRL are reserved and

only zeroes should be written to them.

4.5.57 Asynchronous clock source select register A

This register selects a potential clock for the asynchronous APB peripherals from among several clock sources. The clock selected becomes one of the inputs to the asynchronous clock source select register B (see Table 97 asynchronous APB clock.

), which selects the final clock source for the

Table 96. Asynchronous clock source select register A (ASYNCAPBCLKSELA, address

0x4008 0020) bit description

Bit Symbol Value Description Reset value

1:0 SEL Clock source for asynchronous clock source selector A 0

0x0 IRC Oscillator 0x1 Watchdog oscillator 0x2 Reserved 0x3 Reserved

31:2 - - Reserved -

4.5.58 Asynchronous clock source select register B

This register selects the clock source for the asynchronous APB clock. Remark: Note that this selection is internally synchronized: the clock being switched from

and the clock being switched to must both be running and have occurred in specific states before the selection actually changes.

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Table 97. Asynchronous clock source select register B (ASYNCAPBCLKSELB, address

Bit Symbol Value Description Reset value

1:0 SEL Clock source for asynchronous clock source selector B. 0

31:2 - - Reserved -

4.5.59 Asynchronous APB clock divider register

This register controls how the asynchronous APB clock is divided before use by peripherals. The clock can be shut down completely by setting the DIV field to zero.

Table 98. Asynchronous APB clock divider register (ASYNCCLKDIV, address 0x4008 0028)

Bit Symbol Description Reset value

7:0 DIV Asynchronous APB clock divider value.

31:8 - Reserved -

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Chapter 4: LPC5410x System configuration (SYSCON)

0x4008 0024) bit description

0x0 Main clock 0x1 CLKIN 0x2 System PLL output. 0x3 ASYNCAPBCLKSELA. Clock selected by the

ASYNCAPBCLKSELA register.

bit description

0x01 0: Clock disabled. 1: Divide by 1. to 255: Divide by 255.

4.5.60 USART fractional baud rate generator register

All USART peripherals share a common clock (see Figure 3), which can be adjusted by a fractional divider. This register sets the MULT and DIV values for the fractional rate generator. The output rate is:

USART clock = async bridge clock rate / (1 + MULT / DIV The async bridge clock rate is the USART clock configured as selected via

ASYNCAPBCLKSELA (Section 4.5.57 divided as defined by the ASYNCCLKDIV register (Section 4.5.59

Remark: In order to use the fractional baud rate generator, 0xFF must first be written to the DIV value to yield a denominator value of 256. All other values are not supported.

4.5.61 BOD control register

The BOD control register selects four separate threshold values for sending a BOD interrupt to the NVIC and for forced reset. Reset and interrupt threshold values listed in

Table 100

Both the BOD interrupt and the BOD reset can wake-up the chip from Sleep , Deep- sleep, and Power-down modes if enabled. See Chapter 30 “

control API”.

Table 100. BOD control register (BODCTRL, address 0x4002 C044) bit description

Bit Symbol Value Description Reset value

1:0 BODRSTLEV BOD reset level 0

2 BODRSTENA BOD reset enable 0

4:3 BODINTLEV BOD interrupt level 0

5 BODINTENA BOD interrupt enable 0

6 BODRSTSTAT BOD reset status. When 1, a BOD reset has occurred. Cleared by writing 1

7 BODINTSTAT BOD in terrupt status. When 1, a BOD interrupt has occurred. Cleared by

31:8 - - Reserved -

0x0 Level 0: 1.5 V 0x1 Level 1: 1.85 V 0x2 Level 2: 2.0 V 0x3 Level 3: 2.3 V

0 Disable reset function. 1 Enable reset function.

0x0 Level 0: 2.05 V 0x1 Level 1: 2.45 V 0x2 Level 2: 2.75 V 0x3 Level 3: 3.05 V

0 Disable interrupt function. 1 Enable interrupt function.

are typical values. More details can be found in specific device data sheets.

LPC5410x Power profiles/Power

to this bit.

writing 1 to this bit.

4.6 Functional description

4.6.1 Reset

Reset has the following sources:

• The RESET pin.

• Watchdog reset.

• Power-On Reset (POR).

• Brown Out Detect (BOD).

• ARM software reset.

• ISP-AP debug reset.

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Assertion of the POR or the BOD reset, once the operating voltage attains a usable level, starts the IRC. After the IRC-start-up time (maximum of 6 s on power-up), the IRC provides a stable clock output. The reset remains asserted until the external Reset is released, the oscillator is running, and the flash controller has completed its initialization.

On the assertion of any reset source (ARM software reset, POR, BOD reset, External reset, and Watchdog reset), the following processes are initiated:

1. The IRC is enabled or starts up if not running.

2. The flash wake-up timer starts. This takes approximately 250 ms or less.

3. The boot code in the ROM starts. The boot code performs the boot tasks and may

When the internal Reset is removed, the processor begins executing at address 0, which is initially the Reset vector mapped from the boot block. At that point, all of the processor and peripheral registers have been initialized to predetermined values.

4.6.2 Start-up behavior

See Figure 4 for the start-up timing after reset. The IRC is the default clock at Reset and provides a clean system clock shortly after the supply pins reach operating voltage.

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Chapter 4: LPC5410x System configuration (SYSCON)

jump to the flash.

Fig 4. Start-up timing

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4.6.3 Brown-out detection

The part includes up to four levels for monitoring the voltage on the VDD pin. If this voltage falls below one of the selected levels, the BOD asserts an interrupt signal to the NVIC or issues a reset, depending on the value of the BODRSTENA bit in the BOD control register (Table 100

The interrupt signal can be enabled for interrupt in the Interrupt Enable Register in the NVIC (see Table 4 signal by reading a dedicated status register.

If the BOD interrupt is enabled in the STARTER0 register and in the NVIC, the BOD interrupt can wake up the chip from reduced power modes, not including deep power-down.

If the BOD reset is enabled, the forced BOD reset can wake-up the chip from reduced power modes, not including deep power-down.

On the LPC5410x, the BOD is enabled by default after power-up. At this time the BOD is set to the lowest value (1.5v) with no factory trimming applied. In the BOD block the interrupt portion is turned off and only the reset portion is on. After POR/BOD resets, the BootROM takes over and applies the factory BOD trim value so that the trip points become accurate. See the LPC5410x data sheet for BOD interrupt/reset voltage levels in the BOD static characteristics.

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Chapter 4: LPC5410x System configuration (SYSCON)

) in order to cause a CPU interrupt; if not, software can monitor the

4.6.4 PLL functional description

The PLL is typically used to create a frequency that is higher than other on-chip clock sources, and used to operate the CPU and/or other on-chip functions. It may also be used to obtain a specific clock that is otherwise not available. For example, a clock with a frequency of any integer MHz (e.g. the 12 MHz IRC) can be divided down to 1 MHz, then multiplied up to any other integer MHz (e.g. 13, 14, 15, etc.).

Fig 5. PLL block diagram showing typical operation

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4.6.4.1 PLL Features

• Input frequency: Limited to on-chip sources, including the 32 kHz RTC clock and 12

• CCO frequency: 75 MHz to 150 MHz.

• Output clock range: 1.2 MHz to 150 MHz. Note that the upper frequency limit of the

• Programmable dividers:

• Lock detector.

• Power-down mode.

• Fractional divider mode.

• Spread Spectrum mode.

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Chapter 4: LPC5410x System configuration (SYSCON)

MHz IRC, or up to 24 MHz from the CLKIN pin.

PLL exceeds the upper frequency limit of this device.

– Pre-divider. Divide by N, where N = 1 to 256 – Feedback-divider. Divide by M or 2 x M (where M = 1 to 32768) – Post-divid er. Divide by 1 or 2 x P, where P = 1 to 32

4.6.4.2 PLL description

A number of sources may be used as an input to the PLL, see Figure 3. The PLL input, in the range of 32 kHz to 24 MHz, may initially be divided down by a valu e "N", which may be in the range of 1 to 256. This input division provides a greater number of possibilities in providing a wide range of output frequencies from the same input frequency.

Following the PLL input divider is the PLL multiplier. The multiplier can multiply the input divider output through the use of a Current Controlled Oscillator (CCO) by a value "M", in the range of 1 through 32,768. The resulting freque ncy must be in the range of 75 MHz to 150 MHz. The multiplier works by dividing the CCO output by the value of M, then using a phase-frequency detector to compare the divided CCO output to the multiplier input. The error value is filtered and used to adjust the CCO frequency.

There are additional dividers at the PLL output to bring the frequency down to what is needed for the CPU, USB, and other peripherals. The PLL output dividers are described in the Clock Dividers section following the PLL description. A block diagram of the PLL is shown in Figure 5

All of the dividers use an encoded value, not th e bina ry di vide va lue. T he set_ pll API ( see

Section 30.4.1

not accept pre- and post-divider values. See s ec tion Section 4.6.4.3 for information on how to obtain divider values.

4.6.4.2.1 Lock detector

The lock detector measures the phase difference between the rising edges of the input and feedback clocks. Only when this difference is smaller than the so called “lock criterion” for more than eight consecutive input clock periods, the lock output switches from low to high. A single too large phase difference immediately resets the counter and causes the lock signal to drop (if it was high). Requiring eig h t phase me asurements in a row to be below a certain figure ensures that the lock detector will not indicate lock until both the phase and frequency of the input and feedback clocks are very well aligned. This effectively prevents false lock indications, and thus ensures a glitch free lock signal.

) adjusts the value for the main feedback divider (the M divider), but does

and Section 4.6.4.5

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Chapter 4: LPC5410x System configuration (SYSCON)

The PLL lock indicator is not dependable when Fref is below 100 kHz or above 20 MHz. In fractional mode and spread spectrum mode, the PLL will generally not lock, software

should use a time interval to insure the PLL will be stable. See Section 4.6.4.5.1

4.6.4.2.2 Power-down

To reduce the power consumption when the PLL clock is not needed, a PLL Power-down mode has been incorporated. This mode is enabled b y settin g th e SYSPLL_PD bit to on e in the power configuration register PDRUNCFG (Section 4.5.38 internal current reference will be turned off, the oscillator and the phase-frequency detector will be stopped and the dividers will enter a reset state. While in PLL Power-down mode, the lock output will be low to indicate that the PLL is not in lock. When the PLL Power-down mode is terminated by setting the SYSPLL_PD bit to zero, the PLL will resume its normal operation and will make the lock signal high once it has regained lock on the input clock.

4.6.4.3 Operating modes

The PLL includes several main operating modes, and a power-down mode. These are summarized in Table 101

Table 101. PLL operating mode summary

Mode PDEN_SYS_PLL

Normal 0 0 0 1 1 1 Fractional divider 0 0 1 0 0 0 Spread spectrum 0 0 1 0 0 0 Power-down 1 x

bit in PDRUNCFG

Bits in SYSPLLCTRL: SEL_EXT bit in BYPA SS UPLIMOFF BANDSEL

[1]

and detailed in the following sections.

SYSYPLLSSCTRL0

xxx 1

). In this mode, the

UM10850

PD bit in SYSYPLLSSCTRL1

[1] Use 1 if the PLL output is used even though the PLL is not altering the frequency.

4.6.4.3.1 Normal modes

Typica l operation of the PLL includ es an optional pre-divide of the PLL input, followe d by a frequency multiplication, and finally an optional post-divide to produce the PLL output.

Notations used in the frequency equations:

• Fin = the input to the PLL.

• Fout = the output of the PLL.

• Fref = the PLL reference frequency, the input to the phase frequency detector.

• N = optional pre-divider value.

• M = feedback divider value, which represen ts the multiplier for th e PLL . Not e th at an

additional divide-by-2 may optionally be included in the divider path.

• P = optional post-divider value. An additional divide-by-2 is included in the

post-divider path. A block diagram of the PLL as used in normal modes is shown in Figure 3 In all variations of normal mode, the following requirements must be met:

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• 75 MHz ≤ Fcco ≤ 150 MHz

• 4 kHz ≤ Fin / N ≤ 24 MHz

Normal mode with optional pre-divide

In the equations, use N = 1 when the pre-divider is not used: When the extra divide by 2 is in the feedback divider path (BYPASSCCODIV2 = 0): Fout = Fcco = 2 x M x Fin / N When the extra divide by 2 is not in the feedback divider path (BYPASSCCODIV2 = 1): Fout = Fcco = M x Fin / N

Normal mode with post-divide and optional pre-divide

In the equations, use N = 1 when the pre-divider is not used: When the extra divide by 2 is in the feedback divider path (BYPASSCCODIV2 = 0). Use N

= 1 when the pre-divider is not used:

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Chapter 4: LPC5410x System configuration (SYSCON)

Fout = Fcco / (2 x P) = M x Fin / (N x P) When the extra divide by 2 is not in the feedback divider path (BYPASSCCODIV2 = 1): Fout = Fcco / (2 x P) = M x Fin / (N x 2 x P)

4.6.4.3.2 Fractional divider mode

The PLL includes an fractional divide mode. The fractional mode uses an integer divide value and that value plus 1 in a ratio determined by the fr actional part of the divide value in order to obtain an average rate th at is a fractional multiple of the PLL reference freque ncy. The SEL_EXT bit in the SYSPLLSSCTRL0 register determines whether the fractional divider is used (SEL_EXT = 0) or bypassed (SEL_EXT = 1) . In the first case, the MD value from the SYSPLLSSCTRL1 register is used to generate the feedback divider values. In the latter case, the MDEC value from the SYSPLLSSCTRL0 register is used directly to control the feedback divider.

When the fractional divider is active, the spread spectrum controller block generates divider values M and M+1 in the correct proportion so that the average CCO frequency is represented by the specified fraction. the average CCO frequency is:

Fcco = 2 * (MD[18:11] + MD[10:0] * 2 The overall effect of the PLL otherwise the same as normal modes. A block diagram of the

PLL as used in fractional mode is shown in Figure 6

-11

) * Fref

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Chapter 4: LPC5410x System configuration (SYSCON)

Fig 6. PLL block diagram showing spread spectrum and fractional divide ope ration

4.6.4.3.3 Spread Spectrum mode

The spread spectrum mode allows the PLL to change frequency automatically in a programmable manner.

A block diagram of the PLL as used in fractional mode is shown in Figure 6

4.6.4.3.4 Power-down mode

If the PLL is not used, or if it there are cases where it is turned off in a running application , power can be saved by putting the PLL in power-down mode. Before this is done, the CPU and any peripherals that are not meant to stopped as well must be running from some other clock source.

4.6.4.4 PLL Related registers

The PLL is controlled by registers described elsewhere in this chapter, summarized below.

Table 102. System PLL status register (SYSPLLSTAT, address 0x4000 01B4) bit description

SYSPLLCTRL PLL control Section 4.5.37.1 SYSPLLSTAT PLL status Section 4.5.37.2 SYSPLLNDEC PLL N divider Section4.5.37.3

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Table 102. System PLL status register (SYSPLLSTAT, address 0x4000 01B4) bit description

SYSPLLPDEC PLL P divider Section 4.5.37.4 SYSPLLSSCTRL0 PLL spread spectrum control 0 Section 4.5.37.5.1 SYSPLLSSCTRL1 PLL spread spectrum control 1 Section 4.5.37.5.2

4.6.4.5 PLL usage

As previously noted, the PLL divider settings used in the PLL registers are not simple binary values, they are encoded as shown in the PLL register descriptions. The divider values and their encoding can be found by calculation using the information in this document. For simple PLL usage with no pre- or post-divide, the set_pll API can be used (see Section 30.4.1 latter two possibilities are recommended in order to avoid PLL setup issues.

4.6.4.5.1 Procedure for determining PLL settings

In general, PLL configuration values may be found as follows:

1. Identify a desired PLL output frequency. This may depend on a specific interface

2. Determine which clock source to use as the PLL input. This can be influenced by

3. Identify PLL settings to obtain the desired output form the selected input. The Fcco

4. There may be several ways to obtain the same PLL output frequency. PLL power

5. Check that the selected settings meet all of the PLL requirements:

UM10850

Chapter 4: LPC5410x System configuration (SYSCON)

). Also, a PLL setting calculator can be found on the NXP website. The

frequency needed or be based on expected CPU performance requirements, and

may be limited by system power availability.

power or accuracy required, or by the potential to obtain the desired PLL output

frequency.

frequency must be either the actual desired output frequency, or the desired output

frequency times 2 x P, where P is from 2 to 32. The Fcco frequency must also be a

multiple of the PLL reference frequency, which is either the PLL input, or the PLL input

divided by N, where N is from 2 to 256.

depends on Fcco (a lower frequency uses less power) and the divider used.

Bypassing the input and/or output divider saves power.

– Fin is in the range of 32 kHz to 24 MHz.

– Fcco is in the range of 75 MHz to 150 MHz.

– Fout is in the range of 1.2 MHz to 150 MHz.

– The pre-divider is either bypassed, or N is in the range of 2 to 256.

– The post-divider is either bypassed, or P is in the range of 2 to 32.

– M is in the range of 3 to 32,768.

Also note that PLL startup time becomes longer as Fref drops below 500 kHz. At 500

kHz and above, startup time is up to 500 microseconds. Below 500 kHz, startup time

can be estimated as 200 / Fref, or up to 6.1 milliseconds for Fref = 32 kHz. PLL

accuracy and jitter is better with higher values of Fref.

4.6.4.5.2 PLL setup sequence

The following sequence should be followed to initialize and connect the PLL:

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1. Make sure that the PLL output is disconnected from any downstream functions. If the

2. Select a PLL input clock source. See Section 4.5.21 “

3. Set up the PLL dividers and mode settings. See Section 4.5.37 “

4. Wait for the PLL output to stabilize. The value of the PLl lock may not be stable when

5. If the PLL will be used to clock the CPU, change the CPU Clock Divider setting for

6. Connect the PLL to whichever downstream function is will be used with. The structure

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Chapter 4: LPC5410x System configuration (SYSCON)

PLL was previously being used to clock the CPU, and the CPU Clock Divider is being

used, it may be set to speed up operation while the PLL is disconnected.

System PLL clock source select

PLL registers”.

the PLL reference frequency (FREF, the frequency of REFCLK, which is equal to the

PLL input frequency divided by the pre-divider value) is less than 100 kHz or greater

than 20 MHz. In these cases, the PLL may be assumed to be stable after a start-up

time has passed. This time is 500 μs when Fref is 500 kHz or greater and 200 / Fref

seconds when FREF is less than 500 kHz.

operation with the PLL, if needed. This must be done before connecting the PLL.

of the clock dividers may be seen on the right of Figure 3 “

Clock generation”.

4.6.5 Frequency measure function

The Frequency Measure circuit is based on two 14-bit counters, one clocked by the reference clock and one by the target clock. Synchronization between the clocks is performed at the start and end of each count sequence.

A measurement cycle is initiated by software setting a control/status bit in the FREQMECTRL register (Table 61 measurement-in-progress bit which will be cleared by hardware when the measurement operation is completed.

The measurement cycle terminates when the reference counter rolls-over. At that point the state of the target counter is loaded into a capture field in the FREQMEAS register, and the measure-in-progress bit is cleared. Software can read this capture value and apply to it a specific calculation which will return the precise frequency of the target clock in MHz.

See Section 4.2.3 “

measure function control register”, Section 8.6.4 “Frequency measure function reference clock select register”, and Section 8.6.5 “Frequency measure function target clock select register” for more on this function.

4.6.5.1 Accuracy

The frequency measurement function can measure the frequency of any on-chip (or off-chip) clock (referred to as the target clock) to a high degree of accuracy using another on-chip clock of known frequency as a reference.

Measure the frequency of a clock signal”, Section 4.5.32 “Frequency

). The software can then poll this same

The following constraints apply:

• The frequency of the reference clock must be (somewhat) greater that the frequency

of the target clock.

• The system clock used to access the frequency measure function register must also

be greater than the frequency of the target clock.

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The frequency measurement function circuit is able to measure the ta rget frequency with an error of less than 0.1%, provided the reference frequency is precisely known.

Uncertainty in the reference clock (for example the +/- 1% accuracy of the IRC) will add to the measurement error of the target clock. In general, though, this additional error is less than the uncertainty of the reference clock.

There can also be a modest loss of accuracy if the reference frequency exceeds the target frequency by a very large margin (25x or more). Accuracy is not a simple function o f the magnitude of the frequency difference, however. Nearly identical frequency combinations, still with a spread of about 43x, result in errors of less than 0.05%.

If the target and reference clocks are different by more than a factor of approximately 500, then the accuracy decreases to +/- 4%.

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Chapter 4: LPC5410x System configuration (SYSCON)

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5.1 Introduction

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Chapter 5: LPC5410x Power Management

Rev. 2.4 — 13 September 2016 User manual

This chapter provides an overview of power related information about LPC5 410x device s. These devices include a variety of adjustable regulators, power switches, an d clock switches to allow fine tuning power usage to match requirements at dif ferent perfor mance levels and reduced power modes. All devices include an on-chip API in the boot ROM to adjust power consumption in reduced power modes, and provide entry to those modes. See Chapter 30

To turn analog components on or off in active and sleep modes, use the PDRUNCFG register (see Table 72 controls which analog peripherals remain powered up (see Section 30.4.3

“Chip_POWER_EnterPowerMode”). There is no register implemented to turn analog

peripherals on or off for deep-sleep mode or power-down mode.

). In deep-sleep and power-down modes, the power profile API

5.2 General description

Power to the part is supplied via two power domains. The main power doma in is powered by VDD and supplies power to the core, peripheral, memories, inputs and outputs via an on-chip regulator.

A second, always-on power domain is also powered by Vdd, and includes the RTC and wakeup timer. This domain always has power as long as sufficient voltage is supplied to Vdd.

Power use is controlled by settings in register within the SYSCON block, regulator settings controlled via a Power API, and the operating mode of a CPU. The ROM based power configuration API configures the part for each reduced power mode. The following modes are supported in order from highest to lowest power consumption:

1. Active mode: The part is in active mode after a Power-On Reset (POR) and wh en it is fully powered and operational after booting.

2. Sleep mode: The sleep mode affects the relevant CPU only. The clock to the core is shut off.

Peripherals and memories are active and operational.

3. Deep-sleep and power-down modes: The Deep-sleep and power-down modes affect the entire system. In both modes, the

clock to all CPUs is shut down and the peripherals receive no internal clocks. All SRAM and registers maintain their internal states. Entry to these modes can only be accomplished by the master CPU in an LPC54102 device.

Through the power profiles API, selected peripherals can be left running for safe operation of the part (WWDT and BOD).

The differences between Deep-sleep mode and Power-down modes are the following:

a. In Deep-sleep mode, the flash is in st and-by mode to minimize wake-up time, and

the IRC is turned off to save power.

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Chapter 5: LPC5410x Power Management

b. In Power-down mode, the flash is also powered down to conserve power at the

expense of a somewhat longer wake-up time.

4. Deep power-down mode: For maximal power savings, the entire system (CPUs and all peripherals) is shut

down except for the PMU and the RTC. On wake-up, the part reboots. Entry to Deep power-down mode can only be accomplished by the master CPU in an LPC54102 device.

Table 103. Peripheral configuration in reduced power modes

Peripheral Sleep mode Deep-sleep mode Power-down mode Deep power-

IRC Software

configurable

Flash Software

configurable

BOD Software

configurable

PLL Software

configurable

Watchdog osc and WWDT

USART Software

SPI Software

I2C Software

Other digital peripherals

Analog peripherals

RTC oscillator Software

Software configurable

configurable

configurable Software

configurable

down mode

Off Off Off

On Off Off

Software configurable Software configurable Off

Off Off Off

Software configurable Software configurable Off

Off; but can create a wake-up interrupt in synchronous slave mode or 32 kHz clock mode

Off; but can create a wake-up interrupt in slave mode

Off Off Off

Software configurable Software configurable Off

Software configurable Software configurable Software

Off; but can create a wake-up interrupt in synchronous slave mode or 32 kHz clock mode

Off; but can create a wake-up interrupt in slave mode

Off

configurable

5.2.1 Wake-up process

The part always wakes up to the active mode. To wake up from the reduced power modes, you must configure the wake-up source. Each reduced power mode supports its own wake-up sources and needs to be configured accordingly as shown in Table 104

Table 104. Wake-up sources for reduced power modes

Power mode Wake-up source Conditions

Sleep Any interrupt Enable interrupt in NVIC.

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Table 104. Wake-up sources for reduced power modes

Power mode Wake-up source Conditions

Deep-sleep and Power-down

Pin interrupts Enab le pin interrupts in NVIC and STARTER0 and/or STARTER1 registers. BOD interrupt

• Enable interrupt in NVIC and STARTER0 registers.

• Enable interrupt in BODCTRL register.

• Configure the BOD to keep running in this mode with the power API.

BOD reset Enable reset in BODCTRL register. Watchdog interrupt

• Enable the watchdog oscillator in the PDRUNCFG register.

• Enable the watchdog interrupt in NVIC and STARTER0 registers.

• Enable the watchdog in the WWDT MOD register and feed.

• Enable interrupt in WWDT MOD register.

• Configure the WDOSC to keep running in this mode with the power API.

Watchdog reset

• Enable the watchdog oscillator in the PDRUNCFG register.

• Enable the watchdog and watchdog reset in the WWDT MOD register and

feed. Reset pin Always available. RTC 1 Hz alarm timer

• Enable the RTC 1 Hz oscillator in the RTCOSCCTRL register.

• Enable the RTC bus clock in the AHBCLKCTRL0 register.

• Start RTC alarm timer by writing a time-out value to the RTC COUNT

• Enable the RTCALARM interrupt in the STARTER0 register.

RTC 1 kHz timer time-out and alarm

• Enable the RTC 1 Hz oscillator and the RTC 1 kHz oscillator in the RTC

CTRL register.

• Start RTC 1 kHz timer by writing a time-out value to the RTC WAKE register.

• Enable the RTCWAKE interrupt in the STARTER0 register.

Micro-tick timer (specifically intended ultra-low power wake-up from Power-down mode

• Enable the watchdog oscillator in the PDRUNCFG register.

• Enable the Micro-tick timer clock by writing to the AHBCLKCTRL1 register.

• Start the Micro-tick timer by writing UTICK CTRL register.

• Enable the Micro-tick timer interrupt in the STARTER0 register.

I2C interrupt Interrupt from I2C in slave mode. See Chapter 23 “

(I2C0/1/2)”.

SPI interrupt Interrupt from SPI in slave mode. See Chapter 22 “

Interfaces (SPI0/1)”.

USART interrupt Interrupt from USART in slave or 32 kHz mode. See Chapter 21 “

USARTs (USART0/1/2/3)”.

Deep power-down

RTC 1 Hz alarm timer

RTC 1 kHz timer time-out and alarm

• Enable the RTC 1 Hz oscillator in the RTC CTRL register.

• Start RTC alarm timer by writing a time-out value to the RTC COUNT

• Enable the RTC 1 Hz oscillator and the RTC 1 kHz oscillator in the

RTCOSCCTRL register.

• Enable the RTC bus clock in the AHBCLKCTRL0 register.

• Start RTC 1 kHz timer by writing a time-out value to the RTC WAKE register.

Reset pin Always available.

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Chapter 5: LPC5410x Power Management

LPC5410x I2C-bus interfaces

LPC5410x Serial Peripheral

LPC5410x

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5.3 Functional description

5.3.1 Power management

The LPC5410x support a variety of power control features. In Active mode, when the chip is running, power and clocks to selected peripherals can be optimized for power consumption. In addition, there are four special modes of processor power reduction with different peripherals running: Sleep mode, Deep-sleep mode, Power-down mode, and Deep power-down mode, activated by the power mode config ure API (see Section 30.4.3

“Chip_POWER_EnterPowerMode”).

Remark: The Debug mode is not supported in Sleep, Deep-sleep, Power-down, or Deep power-down modes.

5.3.2 Active mode

In Active mode, the CPU, memories, and peripherals are clocked by the AHB/CPU clock. The chip is in Active mode after reset and the default power configuration is determined

by the reset values of the PDRUNCFG, AHBCLKCTRL0, and AHBCLKCTRL1 registers. The power configuration can be changed during run time.

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Chapter 5: LPC5410x Power Management

5.3.2.1 Power configuration in Active mode

Power consumption in Active mode is determined by the following configuration choices:

• The AHBCLKCTRL registers control which memories and peripherals are running

(Section 4.5.22 “

Control register 1”). Generally speaking, in order to save power , functio ns that are not

needed by the application should be turned off. If specific times are known when certain functions will not be needed, they can be turned off temporarily and turned back on when they will be needed.

AHB Clock Control register 0” and Section 4.5.23 “AHB Clock

• The power to various analog blocks (RAMs, PLL, oscillators, the BOD circuit, and the

flash block) can be controlled individually through the PDRUNCFG register (Table 72 needed by the application. If turned off, time will be needed before these blocks can be used again after being turned on.

). As with clock controls, these blocks should generally be tuned off if not

• The clock source for the system clock can be selected from the IRC (default), the

system oscillator, the 32 kHz oscillator, or the watchdog oscillator (see Figure 3 related registers).

• The system clock frequency can be selected (see Section 4.6.4 “PLL functional

description” and other clocking related sections). You can find optimal settings for

setting the system PLL by using the set_pll routine in the power API (Section 30.4.1

“Chip_POWER_SetPLL”). Generally speaking, everything uses less power at lower

frequencies, so running the CPU and other device features at a frequency sufficient for the application (plus some margin) will save power. If the PLL is not needed, it should be turned off to save power. Also, running the PLL at a lower CCO frequency saves power.

• Several peripherals use individual peripheral clocks with their own clock dividers. The

peripheral clocks can be shut down through the corresponding clock divider registers if the root clock is still needed for another function.

and

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• The power API provides an easy way to optimize power consumption depending on

5.3.3 Sleep mode

In Sleep mode, the system clock to the CPU is stopped and execution of instructions is suspended until either a reset or an interrupt occurs.

Peripheral functions, if selected to be clocked in the AHBCLKCTRL registers, continue operation during Sleep mode and may generate interrupts to cause the processor to resume execution. Sleep mode eliminates dynamic power used by the processor itself, memory systems and related controllers, and internal buses. The proce ssor state and registers, peripheral registers, and internal SRAM values are maintained, and the logic levels of the pins remain static.

As in active mode, the power API provides an easy way to optimize power consumption depending on CPU load and performance requirements in sleep mode. See

Section 30.4.3 “

Chapter 5: LPC5410x Power Management

CPU load and performance requirements. See Chapter30 “

profiles/Power control API”.

Chip_POWER_EnterPowerMode”.

UM10850

LPC5410x Power

5.3.3.1 Power configuration in Sleep mode

Power consumption in Sleep mode is configured by the same settings as in Active mode:

• The clock remains running.

• The system clock frequency remains the same as in Active mode, but the processor is

not clocked.

• Analog and digital peripherals are powered and selected as in Active mode through

the PDRUNCFG, AHBCLKCTRL0, AHBCLKCTRL1 registers.

5.3.3.2 Programming Sleep mode

The following steps must be performed to enter Sleep mode:

1. In the NVIC, enable all interrupts that are needed to wake up the part.

2. Call power API: Remark: The

3. Execute the Wait-For-Interrupt (WFI) instruction.

5.3.3.3 Wake-up from Sleep mode

Sleep mode is exited automatically when an interrupt enabled by the NVIC arrives at the processor or a reset occurs. After wake-up caused by an interrupt, the device returns to its original power configuration defined by the contents of the PDRUNCFG and the AHBCLKCTRL registers. If a reset occurs, the microcontroller enters the default configuration in Active mode.

pPWRD->power_mode_configure(SLEEP, peripheral);

peripheral

parameter is don’t care.

5.3.4 Deep-sleep mode

In Deep-sleep mode, the system clock to the processor is disabled as in Sleep mode. All analog blocks are powered down by default but can be selected to keep running through the power API if needed as wake-up sources. The main clock, and theref ore all periphera l clocks, are disabled. The IRC is disabled. The flash is in stand-by mode.

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Deep-sleep mode eliminates all power used by analog p eriphera ls an d all dy namic powe r used by the processor itself, memory systems and related controllers, and internal buses. The processor state and registers, peripheral registers, and internal SRAM values are maintained, and the logic levels of the pins remain static.

5.3.4.1 Power configuration in Deep-sleep mode

Power consumption in Deep-sleep mode is determined primarily by which analog wake-up sources remain enabled. Serial peripherals and p in interrupts configured to wake up the contribute to the power consumption only to the extent that they are clocked by external sources. All wake-up events (other than reset) must be enab led in the STARTER registers and in the NVIC. In addition, any related analog block (e.g. the RTC oscillator or the watchdog oscillator) must be explicitly enabled through the power API function power_mode_configure() for wake-up. See Table 104

5.3.4.2 Programming Deep-sleep mode

The following steps must be performed to enter Deep-sleep mode:

1. Select wake-up sources and enable all selected wake-up events in the STARTER

2. Select the IRC as the main clock and set the AHBCLKDIV register to 1. See Table 45

3. Call the power API with the p arameter

4. Execute the WFI instruction.

Chapter 5: LPC5410x Power Management

registers (Table 75

Table 46

the serve as wake-up sources (see Table 471 “

routine”):

, and Table 58.

pPWRD->power_mode_configure(DEEP_SLEEP, peripheral);

and Table 76) and in the NVIC.

peripheral

UM10850

set to enable the analog peripherals

Chip_POWER_EnterPowerMode

5.3.4.3 Wake-up from Deep-sleep mode

The part can wake up from Deep-sleep mode in the following ways:

• Using a signal on one of the eight pin interrupts selected in Section 8.6.1 “Pin interrupt

select registers”. Each pin interrupt must also be enabled in the STARTER0 register

(Table 75

) and in the NVIC.

• Using an interrupt from a block such as the watchdog interrupt or R TC interrupt, when

enabled during the reduced power mode via the power API. Also enable the wake-up sources in the STARTER registers (Table 75

• Using a reset from the RESET pin, or the BOD or WWDT (if enabled in the power

API).

• Using a wake-up signal from any of the serial peripherals that are operating in

Deep-sleep mode. Also enable the wake-up sources in the STARTER registers (Table 75

and Table 76) and the NVIC.

• GPIO group interrupt signal. The interrupt must also be enabled in the STARTER1

) and in the NVIC.

• RTC alarm signal or wake-up signal. See Chapter 16. Interrupts must also be enabled

in the STARTER1 register (Table 76

and Table 76) and the NVIC.

) and in the NVIC.

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5.3.5 Power-down mode

In Power-down mode, the system clock to the processor is disabled as in Sleep mod e. All analog blocks are powered down by default but can be selected to ke ep running if needed for waking up the part. The main clock and all peripheral clocks are disabled exce pt for the clock to the watchdog timer if the watchdog oscillator is selected. The flash is powered down, decreasing power consumption compared to Deep-sleep mode.

Power-down mode can eliminate all power used by analog peripherals and all dynamic power used by the processor itself, memory systems and related controllers, and internal buses. The processor state and registers, peripheral registers, and internal SRAM values are maintained, and the logic levels of the pins remain static. Wake-up times are longer compared to the Deep-sleep mode.

5.3.5.1 Power configuration in Power-down mode

Power consumption in power-down mode is determined by which analog wake-up sources are enabled. Serial peripherals and pin interrupts configured to wake up the part do not contribute significantly to the power consumption. All wake-up events (other than reset) must be enabled in the ST AR TER registers and in the NVIC. In addition, any related analog block (e.g. the RTC oscillator or the watchdog oscillator) must be explicitly enabled through the power API function power_mode_configure() for wake-up. See Table 104

UM10850

Chapter 5: LPC5410x Power Management

5.3.5.2 Programming Power-down mode

The following steps must be performed to enter Power-down mode:

1. Select wake-up sources and enable all related wake-up events in the STARTER registers (Table 75

2. Select the IRC as the main clock and set the AHBCLKDIV register to 1. See Table 45

Table 46

3. Call the power API with the peripheral parameter set to enable the analog wake-up sources:

4. Execute the WFI instruction.

, and Table 58.

pPWRD->power_mode_configure(POWER_DOWN, peripheral);

and Table 76) and in the NVIC.

5.3.5.3 Wake-up from Power-down mode

The part can wake up from Power-down mode in the following ways:

• Using a signal on one of the eight pin interrupts selected in Section 8.6.1 “Pin interrupt

select registers”. Each pin interrupt must also be enabled in the STARTER0 register

(Table 75

) and in the NVIC.

• Using an interrupt from a block such as the watchdog timer, RTC, or Micro-tick timer,

when enabled during the reduced power mode via the power API. Also enable the wake-up sources in the STARTER registers (Table 75

• Using a reset from the RESET pin, or the BOD or WWDT (if enabled in the power

API).

• Using a wake-up signal from any of the serial peripherals. Also enable the wake-up

sources in the STARTER registers (Table 75

• GPIO group interrupt signal. Interrupt must also be enable d in the STARTER1 register

(Table 76

) and in the NVIC.

and Table 76) and the NVIC.

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• RTC alarm signal or wake-up signal. See Chapter 16. Interrupts must also be enabled

5.3.6 Deep power-down mode

In Deep power-down mode, power and clocks are shut off to the entire chip with the exception of the RTC.

During Deep power-down mode, the contents of the SRAM and registers are not ret ained. All functional pins are tri-stated in Deep power-down mode.

5.3.6.1 Power configuration in Deep power-down mode

Deep power-down mode has no configuration options. All clocks, the core, and all peripherals are powered down. Only the RTC is powered, as long as power is supplied to the device.

5.3.6.2 Wakeup from Deep power-down mode:

Wakeup from Deep power-down can be accomplished via the reset pin or the RTC.

in the STARTER1 register (Table 76

UM10850

Chapter 5: LPC5410x Power Management

) and in the NVIC.

5.3.6.3 Programming Deep power-down mode using the RTC for wake-up:

The following steps must be performed to enter Deep power-down mode when using the RTC for waking up:

1. Set up the RTC high resolution timer. Write to the RTC VAL register. This starts the high res timer if enabled. Another option is to use the 1 Hz alarm timer.

2. Call the power API: Remark: The

3. Execute the WFI instruction.

pPWRD->power_mode_configure(DEEP_POWER_DOWN, peripheral);

peripheral

parameter is don’t care.

5.3.6.4 Wake-up from Deep power-down mode using the RTC:

The part goes through the entire reset process when the RTC times out:

• The PMU will turn on the on-chip voltage regulator. When the core voltage reaches

the power-on-reset (POR) trip point, a system reset will be triggered and the chip boots.

• All registers will be in their reset state.

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Chapter 6: LPC5410x Boot process

Rev. 2.4 — 13 September 2016 User manual

6.1 Features

• 64 KB on-chip boot ROM

• Contains the boot loader with In-System Programming (ISP) facility and the following

APIs:

– In-Application Programming (IAP) of flash memory – Power profiles for optimizing power consumption and system performance and for

6.2 Pin description

The parts support ISP via USART0. The ISP mode is determined by the state of the P0_31 pin at boot time:

Table 105. ISP modes

Boot mode P0_31 Description

No ISP HIGH ISP bypassed. Part attempts to boot from flash. USART0 LOW Part enters ISP via USART0.

controlling low power modes

6.3 General description

The boot loader controls initial operation after reset and also provides the means to program the flash memory. This could be initial programming of a blank device, erasure and re-programming of a previously programmed device, or programming of the flash memory by the application program in a running system.

The boot loader code is executed every time the part is powered on or reset (see

Figure 7

The boot loader version can be read by ISP/IAP calls (see Table 490 Assuming that power supply pins are at their nominal levels when the rising edge on

RESET decision whether to continue with user code or ISP handler is made. If the boot pins are sampled LOW and the watchdog overflow flag is set, the external hardware request to start the ISP command handler is ignored. If there is no request for the ISP command handler execution, a search is made for a valid user program. If a valid user program is found then the execution control is transferred to it. If a valid user program is not found, the auto-baud routine is invoked.

See Chapter 31 “

). The loader can execute the ISP command handler or the user application code .

pin is generated, it may take up to 3 ms before the boot pins are sampled and th e

or Table 502).

LPC5410x Flash API” for ISP and IAP commands.

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UM10850

Chapter 6: LPC5410x Boot process

6.3.1 Boot process flowchart

Fig 7. Boot process flowchart

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UM10850

Chapter 7: LPC5410x I/O pin configuration (IOCON)

Rev. 2.4 — 13 September 2016 User manual

7.1 How to read this chapter

The IOCON block is included on all LPC5410x parts. Registers for pins that are not available on a specific package are reserved.

Table 106. Available pins and configuration registers

Package Total GPIOs GPIO Port 0 GPIO Port 1

64-pin device with RTC oscillator 50 PIO0_0 to PIO0_31 PIO1_0 to PIO1_17 49-pin device with RTC oscillator 39 PIO0_0 to PIO0_1, PIO0_4 to POI0_31 PIO1_0 to PIO1_8

7.2 Features

The following electrical properties are configurable for standard port pins:

• Pull-up/pull-down resistor

• Open-drain mode

• Inverted function

Pins PIO0_23 through PIO0_28 are true open-drain pins that can be configured fo r different I

C-bus speeds.

7.3 Basic configuration

Enable the clock to the IOCON in the AHBCLKCTRL0 register ( Table 51). Once the pins are configured, the IOCON clock can be disabled in order to conserve power.

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NXP Semiconductors

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7.4 General description

7.4.1 Pin configuration

UM10850

Chapter 7: LPC5410x I/O pin configuration (IOCON)

Fig 8. Pin configuration

7.4.2 IOCON registers

The IOCON registers control the functions of device pins. Ea ch GPIO pin has a ded icated control register to select its function and characteristics. Each pin has a unique set of functional capabilities. Not all pin characteristics are selectable on all pins. For instance, pins that have an I that have an analog alternate function have an analog mode can be selected.Details of the IOCON registers are in Section 7.4.2 characteristics of pins.

Multiple connections

Since a particular peripheral function may be allowed on more than one pin, it is possible to configure more than one pin to perform the same function. If a peripheral output function is configured to appear on more than one pin, it will in fact be routed to those

C function can be configured for different I2C-bus modes, while pins

. The following sections describe specific

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pins. If a peripheral input function is defined as coming from more than one source, the values will be logically combined, possibly resulting in incorrect peripheral operation. Therefore care should be taken to avoid this situation.

7.4.2.1 Pin function

The FUNC bits in the IOCON registers can be set to GPIO (typically value 000) or to a special function. For pins set to GPIO, the DIR registers determine whether the pin is configured as an input or output (see Section 9.5.3 direction is controlled automatically dependi ng on th e fu nc tion . Th e FIO nD IR registers have no effect for special functions.

7.4.2.2 Pin mode

The MODE bits in the IOCON register allow the selection of on-chip pull-up or pull-down resistors for each pin or select the repeater mode.

The possible on-chip resistor configurations are pull-up ena bled, pull-down enabled, or no pull-up/pull-down. The default value is pull-up enabled.

The repeater mode enables the pull-up resistor if the pin is high and enables the pull-down resistor if the pin is low. This causes the pin to retain its last known state if it is configured as an input and is not driven externally . Such st ate retention is not applicable to the Deep Power-down mode. Repeater mo de ma y typ ica lly be use d to preve nt a pin fro m floating (and potentially using significant power if it floats to an indeterminate state) if it is temporarily not driven.

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Chapter 7: LPC5410x I/O pin configuration (IOCON)

). For any special function, the pin

7.4.2.3 Hysteresis

The input buffer for digital functions has built-in hysteresis. See the appropriate specific device data sheet for quantitative details.

7.4.2.4 Invert pin

This option is included to avoid having to include an external inverter on an input that is meant to be the opposite polarity of the external signal.

7.4.2.5 Analog/digital mode

When not in digital mode (DIGIMODE = 0) a pin is in analog mode, some digital pin functions are disabled and any analog pin functions are enabled. In digital mode (DIGIMODE = 1), any analog pin functions are disabled and digital pin functions are enabled. This protects the analog input from voltages outside the range of the analog power supply and reference that may sometimes be present on digit al pins, since they are typically 5V tolerant. All pin types include this control, even if they do not support any analog functions.

In order to use a pin that has an ADC input option for that purpose, select GPIO (FUNC field = 0) and disable the digital pin function (DIGIMODE = 0).

In analog mode, the MODE field should be “Inactive” (00); the INVERT, FILTEROFF, and OD settings have no effect. For an unconnected pi n that h as an analo g fu nction, keep th e DIGIMODE bit set to 1 (digital mode), and pull-up or pull-down mode selected in the MODE field.

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7.4.2.6 Input filter

Some pins include a filter that can be selectively disabled by setting the FILTEROFF bit. The filter suppresses input pulses smaller than about 10 ns.

7.4.2.7 Output slew rate

The SLEW bits of digital outputs that do not need to switch state very quickly should be set to “standard”. This setting allows multiple outputs to switch simultaneously without noticeably degrading the power/ground distribu tion of the device, and has only a small effect on signal transition time. This is particularly important if analog accuracy is significant to the application. See the relevant specific device data sheet for more details.

7.4.2.8 I2C modes

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Chapter 7: LPC5410x I/O pin configuration (IOCON)

Pins that support I2C with specialized pad electronics (P0[23] through P0[28]) have additional configuration bits. These have multiple configurations to support I These are not hard-wired so that the pins can be more easily used for non-I See Table 113

For non-I

for recommended mode settings.

C operation, these pins remain open-drain and can only drive low, regardless of how I2CSLEW and I2CDRIVE are set. They would typically be used with an external pull-up resistor if they are used as outputs unless they are used only to sink current. Leave I2CSLEW = 1, I2CDRIVE = 0, and I2CFILTER = 0 to maximize compatibility with other GPIO pins.

7.4.2.9 Open-Drain Mode

When output is selected, either by selecting a special function in the FUNC field, or by selecting the GPIO function for a pin having a 1 in the related bit of that port’s DIR register , a 1 in the OD bit selects open-drain operation, that is, a 1 disables the high-drive transistor. This option has no effect on the primary I pin in this simulated open-drain mode are somewhat different than those of a true open drain output.

C variants.

C functions.

C pins. Note that the properties of a

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Chapter 7: LPC5410x I/O pin configuration (IOCON)

7.5 Register description

Each port pin PIOm_n has one IOCON register assigned to control the pin’s electrical characteristics.

Table 107. Register overview: I/O configuration (base address 0x4001 C000)

Name Access Offset Description Reset value

PIO0_[0:1] R/W [0x000:

PIO0_[4:22] R/W [0x010:

PIO0_[23:28] R/W [0x05C:

PIO0_[29:31] R/W [0x074:

PIO1_[0:8] R/W [0x080:

PIO1_[9:17] R/W [0x0A4:

0x004]

0x058]

0x070]

0x07C]

0x0A0]

0x0C4]

Digital I/O control for port 0 pins PIO0_0 to PIO0_1

Digital I/O control for port 0 pins PIO4 to PIO0_22.

Digital I/O control for port 0 pins PIO0_23 to PIO0_28. These pins support I2C with true open-drain, drive and filtering for modes up to Fast-mode Plus.

Digital I/O control for port 0 pins PIO0_29 to PIO0_31. These pins include an ADC input.

Digital I/O control for port 1 pins PIO0_0 to PIO0_8. These pins include an ADC input.

Digital I/O control for port 1 pins PIO1_9 to PIO1_17.

0x0190 D 7.5.1

PIO0_16/17: 0x0195, others: 0x0190

0x01A0

0x0190 A 7.5.3

0x0190 D 7.5.4

[2]

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[1]

Pin type

D 7.5.1

I 7.5.2

Section

[1] Reset Value reflects the data stored in defined bits only. Reserved bits assumed to be 0. [2] The pins require an external pull-up to provide output functionality.

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7.5.1 Type D IOCON registers (PIO0)

This IOCON table applies to port pins P0[0 to 2] and P0[4 to 22]. Other pins include ADC or I

Remark: The FUNC field for P0[16] and P0[17] resets to 0b101 (0x5), selecting the Serial Wire Debug function by default.

Table 108. Address map PIO0_[0:22] registers

Peripheral Base address Offset Increment Dimension

IOCON 0x4001 C000 [0 x000:0x058] 0x4 23

Chapter 7: LPC5410x I/O pin configuration (IOCON)

C functions that alter the contents of the related IOCON registers.

UM10850

Table 109. Type D IOCON registers (PIO0_[0:22], address offsets [0x000:0x058]) bit description

Bit Symbol Value Description Reset value

2:0 FUNC Selects pin function. PIO0_16/17: 5

others: 0

4:3 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 10

0x0 Inactive. Inactive (no pull-down/pull-up resistor enabled). 0x1 Pull-down. Pull-down resistor enabled. 0x2 Pull-up. Pull-up resistor enabled.

0x3 Repeater. Repeater mode. 5 - Reserved. Read value is undefined, only zero should be written. NA 6 INVERT Input polarity. 0

0 Disabled. Input function is not inverted.

1 Enabled. Input is function inverted. 7 DIGIMODE Select Anal og/Digital mode. 1

0 Analog mode.

1 Digital mode. 8 FILTEROFF Controls input glitch filter. 1

0 Filter enabled. Noise pulses below approximately 10 ns are filtered out.

1 Filter disabled. No input filtering is done 9 SLEW Driver slew rate. 0

0 Standard mode, output slew rate control is enabled. More outputs can be

switched simultaneously.

1 Fast mode, slew rate control is disabled. Refer to the appropriate

specific device data sheet for details.

10 OD Controls open-drain mode. 0

0 Normal. Normal push-pull output

1 Open-drain. Simulated open-drain output (high drive disabled) 31:11 - Reserved. Read value is undefined, only zero should be written. NA

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Chapter 7: LPC5410x I/O pin configuration (IOCON)

Table 110. Type D I/O Control registers: FUNC values and pin functions

000 001 010 011 100 101 110 111

PIO0_0 PIO0_0 U0_RXD SPI0_SSELN0 CT32B0_CAP0 PIO0_1 PIO0_1 U0_TXD SPI0_SSELN1 CT32B0_CAP1 SCT0_OUT1 PIO0_2 PIO0_2 U0_CTS CT32B2_CAP1 PIO0_3 PIO0_3 U0_RTS CT32B1_MAT3 PIO0_4 PIO0_4 U0_SCLK SPI0_SSELN2 CT32B0_CAP2 PIO0_5 PIO0_5 U1_RXD SCT0_OUT6 CT32B0_MAT0 PIO0_6 PIO0_6 U1_TXD CT32B0_MAT1 PIO0_7 PIO0_7 U1_SCLK SCT0_OUT0 CT32B0_MAT2 CT32B0_CAP2 PIO0_8 PIO0_8 U2_RXD SCT0_OUT1 CT32B0_MAT3 PIO0_9 PIO0_9 U2_TXD SCT0_OUT2 CT32B3_CAP0 SPI0_SSELN0 PIO0_10 PIO0_10 U2_SCLK SCT0_OUT3 CT32B3_MAT0 PIO0_1 1 PIO0_11 SPI0_SCK U1_RXD CT32B2_MAT1 PIO0_12 PIO0_12 SPI0_MOSI U1_TXD CT32B2_MAT3 PIO0_13 PIO0_13 SPI0_MISO SCT0_OUT4 CT32B2_MAT0 PIO0_14 PIO0_14 SPI0_SSELN0 SCT0_OUT5 CT32B2_MAT1 PIO0_15 PIO0_15 SPI0_SSELN1 SWO CT32B2_MAT2 PIO0_16 PIO0_16 SPI0_SSELN2 U1_CTS CT32B3_MAT1 SWCLK PIO0_17 PIO0_17 SPI0_SSELN3 U1_RTS CT32B3_MAT2 SWDIO PIO0_18 PIO0_18 U3_TXD SCT0_OUT0 CT32B0_MAT0 PIO0_19 PIO0_19 U3_SCLK SCT0_OUT1 CT32B0_MAT1 PIO0_20 PIO0_20 U3_RXD U0_SCLK CT32B3_CAP0 PIO0_21 PIO0_21 CLKOUT U0_TXD CT32B3_MAT0 PIO0_22 PIO0_22 CLKIN U0_RXD CT32B3_MAT3

SCT0_OUT3

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7.5.2 Type I IOCON registers (PIO0)

This IOCON table applies to pins P0[23 to 28]. See Table 113 for recommended setting for I2C operation.

Table 111. Address map PIO0_[23:28] registers

Peripheral Base address Offset Increment Dimension

IOCON 0x4001 C000 [0x05C:0x070] 0x4 6

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Chapter 7: LPC5410x I/O pin configuration (IOCON)

Table 112. Type I IOCON registers (PIO0_[23:28], address offsets [0x05C:0x070]) bit description

Bit Symbol Value Description Reset

value

2:0 FUNC Selects pin function. 0 4:3 - Reserved. Read value is undefined, only zero should be written. NA

5 I2CSLEW Controls slew rate of I

C mode.

C pad. 1

1 GPIO mode.

6 INVERT 1 Input polarity. 0

0 Disabled. Input function is not inverted. 1 Enabled. Input is function inverted.

7 DIGIMODE Select Analog/Digital mode. 1

0 Analog mode. 1 Digital mode.

8 FILTEROFF Controls input glitch filter. 1

0 Filter enabled. Noise pulses below approximately 10 ns are filtered out 1 Filter disabled. No input filtering is done

9 I2CDRIVE Controls the current sink capability of the pin. 0

0 Low drive. Output drive sink is 4 mA. This is sufficient for standard and fast mode

1 High drive. Output drive sink is 20 mA. This is needed for Fast Mode Plus I

C. Refer

to the appropriate specific device data sheet for details.

10 I2CFILTER Configures I

C features for standard mode, fast mode, and Fast Mode Plus

operation. 0 Enabled. I 1 Disabled. I

C 50 ns glitch filter enabled.

C 50 ns glitch filter disabled.

31:11 - Reserved. Read value is undefined, only zero should be written. NA

Table 113. Suggested IOCON settings for I2C functions

IOCON register bit

Mode 10: I2CFILTER 9: I2CDRIVE 8: FILTEROFF 7: DIGIMODE 6: INVERT 5: I2CSLEW

GPIO 4 mA drive 0 0 0 GPIO 20 mA drive 0 1 0

Fast / Standard mode I Fast Mode Plus I High Speed slave I

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C0 0 1 1 0 0

C111100

C1 1 1 100

[1] The input filter may be turned by setting FILTEROFF off if it is not needed.

[1] [1]

[2]

01 01

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NXP Semiconductors

[2] The input may be turned off by clearing DIGIMODE if it is not needed.

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Chapter 7: LPC5410x I/O pin configuration (IOCON)

Table 114. Type I I/O Control registers: FUNC values and pin functions

Value of FUNC field in IOCON register

PIO0_23 PIO0_23 I2C0_SCL

CT32B0_CAP0 PIO0_24 PIO0_24 I2C0_SDA CT32B0_CAP1 CT32B0_MAT0 PIO0_25 PIO0_25 I2C1_SCL U1_CTS CT32B0_CAP2 CT32B1_CAP1 PIO0_26 PIO0_26 I2C1_SDA CT32B0_CAP3 PIO0_27 PIO0_27 I2C2_SCL CT32B2_CAP0 PIO0_28 PIO0_28 I2C2_SDA CT32B2_MAT0

7.5.3 Type A IOCON registers (PIO0, PIO1)

This IOCON table applies to pins P0[29 to 31], P1[0 to 8].

Table 115. Address map PIO0_[29:31] registers

Peripheral Base address Offset Increment Dimension

IOCON 0x4001 C000 [0 x074:0x07C] 0x4 3

Table 116. Type A IOCON registers(PIO0_[29:31], address offsets [0x074:0x07C]) bit description

Bit Symbol Value Description Reset

2:0 FUNC Selects pin function. 0 4:3 MODE Selects function mode (on-chip pull-up/pull-down resisto r contro l). 10

5 - Reserved. Read value is undefined, only zero should be written. NA 6 INVERT Input polarity. 0

7 DIGIMODE Select Analog/Digital mode. 1

8 FILTEROFF Controls input glitch filter. 1

9 - Reserved. Read value is undefined, only zero should be written. NA

value

0x0 Inactive. Inactive (no pull-down/pull-up resistor enabled). 0x1 Pull-down. Pull-down resistor enabled. 0x2 Pull-up. Pull-up resistor enabled. 0x3 Repeater. Repeater mode.

0 Disabled. Input function is not inverted. 1 Enabled. Input is function inverted.

0 Analog mode. 1 Digital mode.

0 Filter enabled. Noise pulses below approximately 10 ns are filtered out 1 Filter disabled. No input filtering is done

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UM10850

Chapter 7: LPC5410x I/O pin configuration (IOCON)

Table 116. Type A IOCON registers(PIO0_[29:31], address offsets [0x074:0x07C]) bit description

Bit Symbol Value Description Reset

value

10 OD Controls open-drain mode. 0

0 Normal. Normal push-pull output 1 Open-drain. Simulated open-drain output (high drive disabled)

31:11 - Reserved. Read value is undefined, only zero should be written. NA

Table 117. Address map PIO1_[0:8] registers

Peripheral Base address Offset Increment Dimension

IOCON 0x4001 C000 [0 x080:0x0A0] 0x4 9

Table 118. Type A IOCON registers(PIO1_[0:8], address offsets [0x080:0x0A0]) bit description

Bit Symbol Value Description Reset

value

2:0 FUNC Selects pin function. 0 4:3 MODE Selects function mode (on-chip pull-up/pull-down resisto r contro l). 10

0x0 Inactive. Inactive (no pull-down/pull-up resistor enabled). 0x1 Pull-down. Pull-down resistor enabled. 0x2 Pull-up. Pull-up resistor enabled.

0x3 Repeater. Repeater mode. 5 - Reserved. Read value is undefined, only zero should be written. NA 6 INVERT Input polarity. 0

0 Disabled. Input function is not inverted.

1 Enabled. Input is function inverted. 7 DIGIMODE Select Analog/Digital mode. 1

0 Analog mode.

1 Digital mode. 8 FILTEROFF Controls input glitch filter. 1

0 Filter enabled. Noise pulses below approximately 10 ns are filtered out

1 Filter disabled. No input filtering is done 9 - Reserved. Read value is undefined, only zero should be written. NA 10 OD Controls open-drain mode. 0

0 Normal. Normal push-pull output

1 Open-drain. Simulated open-drain output (high drive disabled) 31:11 - Reserved. Read value is undefined, only zero should be written. NA

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UM10850

Chapter 7: LPC5410x I/O pin configuration (IOCON)

Table 119. Type A I/O Control registers: FUNC values and pin functions

PIO0_29 PIO0_29/ADC_0 SCT0_OUT2 CT32B0_MAT3 PIO0_30 PIO0_30/ADC_1 SCT0_OUT3 CT32B0_MAT2 CT32B0_CAP2 PIO0_31 PIO0_31/ADC_2 U2_CTS CT32B2_CAP2 CT32B0_CAP3 CT32B0_MAT3 PIO1_0 PIO1_0/ADC_3 U2_RTS CT32B3_MAT1 CT32B0_CAP0 PIO1_1 PIO1_1/ADC_4 SWO SCT0_OUT4 PIO1_2 PIO1_2/ADC_5 SPI1_SSELN3 SCT0_OUT5 PIO1_3 PIO1_3/ADC_6 SPI1_SSELN2 SCT0_OUT6 SPI0_SCK CT32B0_CAP1 PIO1_4 PIO1_4/ADC_7 SPI1_SSELN1 SCT0_OUT7 SPI0_MISO CT32B0_MAT1 PIO1_5 PIO1_5/ADC_8 SPI1_SSELN0 CT32B1_CAP0 CT32B1_MAT3 PIO1_6 PIO1_6/ADC_9 SPI1_SCK CT32B1_CAP2 CT32B1_MAT2 PIO1_7 PIO1_7/ADC_10 SPI1_MOSI CT32B1_MAT2 CT32B1_CAP2 PIO1_8 PIO1_8/ADC_11 SPI1_MISO CT32B1_MAT3 CT32B1_CAP3

Value of FUNC field in IOCON register

CT32B0_CAP1 CT32B0_MAT1

[1] To enable an ADC input, select the GPIO function and disable the digital functions of the pin by clearing the

DIGIMODE bit in the related IOCON register.

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7.5.4 Type D IOCON registers (PIO1)

This IOCON table applies to port pins P1[9 to 17]. Other pins include ADC or I2C functions that alter the contents of the related IOCON registers.

Table 120. Address map PIO1_[9:17] registers

Peripheral Base address Offset Increment Dimension

IOCON 0x4001 C000 [0x0A4:0x0C4] 0x4 9

UM10850

Chapter 7: LPC5410x I/O pin configuration (IOCON)

Table 121. Type D IOCON registers (PIO1_[9:17], address offsets [0x0A4:0x0C4]) bit description

Bit Symbol Value Description Reset

2:0 FUNC Selects pin function. 0 4:3 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 10

5 - Reserved. Read value is undefined, only zero should be written. NA 6 INVERT Input polarity. 0

7 DIGIMODE Select Analog/Digital mode. 1

8 FILTEROFF Controls input glitch fil te r. 1

9 SLEW Driver slew rate. 0

10 OD Controls open-drain mode. 0

31:11 - Reserved. Read value is undefined, only zero should be written. NA

value

0x0 Inactive. Inactive (no pull-down/pull-up resistor enabled). 0x1 Pull-down. Pull-down resistor enabled. 0x2 Pull-up. Pull-up resistor enabled. 0x3 Repeater. Repeater mode.

0 Disabled. Input function is not inverted. 1 Enabled. Input is function inverted.

0 Analog mode. 1 Digital mode.

0 Filter enabled. Noise pulses below approximately 10 ns are filtered out 1 Filter disabled. No input filtering is done

0 Standard mode, output slew rate control is enabled. More outputs can be switched

simultaneously.

1 Fast mode, slew rate control is disabled. Refer to the appropriate specific device data

sheet for details.

0 Normal. Normal push-pull output 1 Open-drain. Simulated ope n-drain output (high drive disabled)

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UM10850

Chapter 7: LPC5410x I/O pin configuration (IOCON)

Table 122. Type D I/O Control registers: FUNC values and pin functions

PIO1_9 PIO1_9 PIO1_10 PIO1_10 U1_TXD SCT0_OUT4 PIO1_11 PIO1_11 U1_RTS CT32B1_CAP0 PIO1_12 PIO1_12 U3_RXD CT32B1_MAT0 SPI1_SCK PIO1_13 PIO1_13 U3_TXD CT32B1_MAT1 SPI1_MOSI PIO1_14 PIO1_14 U2_RXD SCT0_OUT7 SPI1_MISO PIO1_15 PIO1_15 SCT0_OUT5 CT32B1_CAP3 SPI1_SSELN0 PIO1_16 PIO1_16 CT32B0_MAT0 CT32B0_CAP0 SPI1_SSELN1 PIO1_17 PIO1_17

Value of FUNC field in IOCON register

SPI0_MOSI CT32B0_CAP2

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UM10850

Chapter 8: LPC5410x Input multiplexing (INPUT MUX)

Rev. 2.4 — 13 September 2016 User manual

8.1 How to read this chapter

Input multiplexing is available for all parts. Depending on the package, not all inputs from external pins may be available.

8.2 Features

• Configures the inputs to the pin interrupt block and pattern match engine.

• Configures the inputs to the DMA triggers.

• Configures the inputs to the frequency measu re function. This function is controlled by

the FREQMECTRL register in the SYSCON block.

8.3 Basic configuration

Once set up, no clocks are needed for the input multiplexer to function. The system clock is needed only to write to or read from the INPUT MUX registers. Once the input multiplexer is configured, disable the clock to the INPUT MUX block in the AHBCLKCTRL register.

8.4 Pin description

The input multiplexer has no dedicated pins. However, all digital pins of ports 0 and 1 can be selected as inputs to the pin interrupts. Multiplexer inputs from external pins work independently of any other function assigned to the pin as long as no analog function is enabled.

Table 123. INPUT MUX pin description

Pins Peripheral Reference

Any existing pin on port 0 or 1 Pin interrupts 0 to 7 Table 126 PIO0_4, PIO0_20, PIO0_24, PIO1_4 F r equency measure block Table 131

8.5 General description

The inputs to the DMA triggers, to the eight pin interrupts, and to the frequency measure block are multiplexed to multiple input sources. The sources can be external pins, interrupts, or output signals of other peripherals.

The input multiplexing makes it possible to design event-driven processes without CPU intervention by connecting peripherals like the ADC.

The DMA can use trigger input multiplexing to sequence DMA transactions without the use of interrupt service routines.

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The input mux for the pin interrupts and pattern match engine multiplexes all existing pins from ports 0 and 1.

Fig 9. Pin interrupt multiplexing

UM10850

Chapter 8: LPC5410x Input multiplexing (INPUT MUX)

8.5.2 DMA trigger input multiplexing

Fig 10. DMA trigger multiplexing

User manual Rev. 2.4 — 13 September 2016 101 of 464

NXP Semiconductors LPC5410x User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

1.1 Introduction

Chapter 1: LPC5410x Introductory information

1.2 Features

1.3 Block diagram

1.4 Architectural overview

1.5 ARM Cortex-M4 processor

1.6 ARM Cortex-M0+ processor (present on LPC54102 devices)

Chapter 2: LPC5410x Memory mapping

2.1 General description

2.1.1 Main SRAM

2.1.1.1 SRAM2

2.1.1.2 SRAM usage notes

2.1.2 Memory mapping

2.1.3 AHB multilayer matrix

2.1.4 Memory Protection Unit (MPU)

Chapter 3: LPC5410x Nested Vectored Interrupt Controller (NVIC)

3.1 How to read this chapter

3.2 Features

3.3 General description

3.3.1 Interrupt sources

3.4 Register description

3.4.1 Interrupt Set-Enable Register 0 register

3.4.2 Interrupt Set-Enable Register 1 register

3.4.3 Interrupt Clear-Enable Register 0

3.4.4 Interrupt Clear-Enable Register 1 register

3.4.5 Interrupt Set-Pending Register 0 register

3.4.6 Interrupt Set-Pending Register 1 register

3.4.7 Interrupt Clear-Pending Register 0 register

3.4.8 Interrupt Clear-Pending Register 1 register

3.4.9 Interrupt Active Bit Register 0

3.4.10 Interrupt Active Bit Register 1

3.4.11 Interrupt Priority Register 0

3.4.12 Interrupt Priority Register 1

3.4.13 Interrupt Priority Register 2

3.4.14 Interrupt Priority Register 3

3.4.15 Interrupt Priority Register 4

3.4.16 Interrupt Priority Register 5

3.4.17 Interrupt Priority Register 6

3.4.18 Interrupt Priority Register 7

3.4.19 Interrupt Priority Register 8

3.4.20 Interrupt Priority Register 9

3.4.21 Interrupt Priority Register 10

3.4.22 Software Trigger Interrupt Register

4.1 Features

Chapter 4: LPC5410x System configuration (SYSCON)

4.2 Basic configuration

4.2.1 Set up the PLL

4.2.2 Configure the main clock and system clock

4.2.3 Measure the frequency of a clock signal

4.3 Pin description

4.4 General description

4.4.1 Clock generation

4.5 Register description

4.5.1 AHB matrix priority register

4.5.2 System tick counter calibration register

4.5.3 NMI source selection register

4.5.4 Asynchronous APB Control register

4.5.5 System reset status register

4.5.6 Peripheral reset control register 0

4.5.7 Peripheral reset control register 1

4.5.8 Peripheral reset control set register 0

4.5.9 Peripheral reset control set register 1

4.5.10 Peripheral reset control clear register 0

4.5.1 1 Peripheral reset control clear register 1

4.5.12 POR captured value of port 0

4.5.13 POR captured value of port 1

4.5.14 Reset captured value of port 0

4.5.15 Reset captured value of port 1

4.5.16 Main clock source select register A

4.5.17 Main clock source select register B

4.5.18 ADC clock source select register

4.5.19 CLKOUT clock source select register A

4.5.20 CLKOUT clock source select register B

4.5.21 System PLL clock source select register

4.5.22 AHB Clock Control register 0

4.5.23 AHB Clock Control register 1