NXP Semiconductors LPC5410x User Manual

UM10850

LPC5410x User manual

Rev. 2.4 — 13 September 2016 User manual

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Info Content Keywords LPC5410x, ARM Cortex-M4, ARM Cortex-M0+, microcontroller, sensor

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Abstract LPC5410x User Manual

NXP Semiconductors

UM10850

LPC5410x User manual

Revision history

Rev Date Description

2.4 20160913

2.3 20160906

• Updated Table 62 “Flash configuration register (FLASHCFG, main syscon: address 0x4000 0124)

bit description”: Changed the system clock rates of the following:

– 2 system clocks flash access time (for system clock rates up to 24 MHz). – 3 system clocks flash access time (for system clock rates up to 48 MHz). – 4 system clocks flash access time (for system clock rates up to 72 MHz). – 5 system clocks flash access time (for system clock rates up to 84 MHz). – Added 0x5, 6 system clocks flash access time (for system clock rates up to 100 MHz).

• Added text and a remark to Section 30.1 “How to read this chapter”.

• Added a remark to Section 30.3 “General description”.

• Added text and a remark to Section 30.4 “API description”.

• Added Table 466 “Power API calls in LPCOpen power library”.

• Renamed section 30.4.1 to Section 30.4.1 “Chip_POWER_SetPLL”.

• Renamed section 30.4.2 to Section 30.4.2 “Chip_POWER_SetVoltage”.

• Deleted Param0: mode and Low power mode; was secti on 30.4.2.1.

• Added Section 30.4.3 “Chip_POWER_EnterPowerMode”.

• Updated Section 30.5 “Functional description”.

2.2 20160331

• Removed Section 4.5.51: Device ID1 regist er va lu e s and mo ved Table 89 “Device ID1 register

values” to section Section 4.5.50 “Device ID1 register”.

• Removed IrDA mode from Section 21.5 “General description” in Chapter 21 “LPC5410x USARTs

(USART0/1/2/3)”.

• Updated Table 307 “USART Configuration register (CFG, offset 0x00) bit description”. Removed

IOMODE from the table.

• Removed the section: IrDA communication in Chapter 21 “LPC5410x USARTs (USART0/1/2/3)”.

• Added the sentence to Section 22.5 “General description”: Set the RXIGNORE bit to only transmit

data and not read the incoming data. Otherwise, the transmit halts when the receiver buffer is full.

• Added the sentence to Table 328 “SPI Transmitter Data and Control register (TXDATCTL, offset

0x18) bit description”, bit 22, RXIGNORE: The SPI collects receive data, according to SPI clocking,

unless RXIGNORE is set; 0: The SPI transmit halts when the receive data FIFO is full.

• Added the sentence to Section 22.7.7 “Data stalls”: The transmitter will be stalled until data is read

from the receive FIFO. Use the RXIGNORE control bit setting, to avoid the need to read the received data.

User manual Rev. 2.4 — 13 September 2016 2 of 464

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UM10850

LPC5410x User manual

Revision history

Rev Date Description

2.1 20151218 • Added Table 89 “Device ID1 register values”.

…continued

• Added text to Section 4.5.47.1 “CPU Control register”: The user can assign Cortex-M0+ to be the

master CPU via this register if needed after it is brought out of reset by Cortex-M4.

• Added text to Section 4.6.3 “Brown-out detection”: On the LPC5410x, the BOD is enabled by

default after power-up. At this time the BOD is set to the lowest value (1.5v) with no factory trimming applied. In the BOD block the interrupt portion is turned off and only the reset portion is on. After POR/BOD resets, the BootROM takes over and applies the factory BOD trim value so that the trip points become accurate. See the LPC5410x data sheet for BOD interrupt/reset voltage levels in the BOD static characteristics.

• Added section Section 12.5.7 “Channel chaining”.

• Updated Figure 53 “System FIFO conceptual block diagram”.

• Updated description of 15:12,TIMEOUT VALUE; Specifies the maximum time value for timeout at

the timer position identified by TimeoutBase. Minimum time TimeoutValue - 1 (clocks of wdt_clk). See Table 383 “Configuration register for USARTn (CFGUSART[0:3], address offset [0x1000:0x1300]) bit description”.

• Updated the values in the sentence: TimeoutValue can be any value from 2 to 15. This gives a

maximum timeout range of 2 counts (too small to be useful) at the bottom end, up to 15 * 32,768 (491,520) counts at the upper end. See Section 24.5.7.1 “Receiver Timeout”

• Updated text in Table 468 “set_voltage routine”: Param1: desired frequency (in Hz); was: Param1:

desired frequency (in MHz).

• Removed text from Section 5.2 “General description”, list 3:

...or for monitoring analog inputs (comparators and internal voltage reference and temperature sensor via one of the comparators).

• Removed comparator from Section 13.5 “General description”: This provides an extremely powerful

control tool - particularly when the SCT inputs and outputs are connected to other on-chip resources (ADC triggers, other timers etc.) in addition to general-purpose I/O.

• Added AHBCLKDIV register should be set to 1 in: List item 2 “Select the IRC as the main clock and

set the AHBCLKDIV register to 1. See Table 45, Table 46, and Table 58.”, Section 5.3.4.2 “Programming Deep-sleep mode”.

• Added AHBCLKDIV register should be set to 1 in: List item 2 “Select the IRC as the main clock and

set the AHBCLKDIV register to 1. See Table 45, Table 46, and Table 58.”, Section 5.3.5.2 “Programming Power-down mode”.

• Added registers, DIRSET0, DIRCLR0, DIRNOT0. See Table 134 “Register overview: GPIO port

(base address 0x1C00 0000)” and Section 9.5.10 “GPIO port direction set registers”, Section 9.5.11 “GPIO port direction clear registers”, and Section 9.5.12 “GPIO port direction toggle registers”.

• Added note to Table 223 “SCT DMA 0 request register (DMAREQ0, address 0x5000 405C) bit

description” and Table 224 “SCT DMA 1 request register (DMAREQ1, address 0x5000 4060) bit description”.

• Added remark to Section 4.5.37.5.1 “System PLL spread spectrum control register 0”: If the 32 kHz

RTC oscillator is used as the reference input to the PLL, then use fixed values SELI=1, SELP=6 and SELR=0, instead of applying the above rules. These values reduce the PLL loop bandwidth to combat the effect of reference oscillator jitter on the PLL output signal.

• In Table 62 “Flash configuration register (FLASHCFG, main syscon: address 0x4000 0124) bit

description” replaced offset in table title to address 0x4000 0124.

User manual Rev. 2.4 — 13 September 2016 3 of 464

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LPC5410x User manual

Revision history

Rev Date Description

2.1 • Added text to Section 17.2 “Features”: 24-bit interrupt timer clocked from CPU clock.

…continued

• Added address to Section 31.3.7.3 “RAM used by IAP command handler”’: Flash programming

commands use the top 32 bytes of on-chip SRAM0, 0x0200 FFE0 - 0x0200 FFFF (see Section

2.1.1 for details of the SRAM configuration). The maximum stack usage in the user allocated stack space is 128 bytes and grows downwards.

• Removed Receiver Idle from Section 21.2 “Features” and replaced with Transmitter Idle.

• Added the text receiver to List item • “A receiver timeout feature (for USART and SPI) provides a

means to get data left for a time in a FIFO that has not reached its threshold to be transferred.” in Section 24.3 “Features”.

• Added List item • “Timeouts: The watchdog oscillator must run for the UART and SPI timeout

counter to work. Enable the watchdog oscillator via the PDRUNCFG register (Table 72).” to the Section 24.2 “Basic configuration”.

• Added text, The source of the timeout clock is the watchdog oscillator with a nominal frequency of

500 kHz to Section 24.5.7.1 “Receiver Timeout”, and Section 24.5.15.1 “Receiver Timeout”.

• Added text to Section 21.5 “General description”: The USART receiver timeout fea ture can also be

used to identify the USART receiver idle state. Set the bit TIMEOUTCONTONEMPTY in the respective CFGUSART register to 1 to allow the timeout to flag idle state of the USART peripheral.

• Fixed the reset value of MSTTIME (Master timing configuration); was 0x77, now 0x56. See

T able 340 “Register overview: I2C0/1/2 (register base addresses 0x4009 4000 (I2C0), 0x4009 8000 (I2C1), 0x4009 C000 (I2C2))”.

• Added the Flash Management Registers FMSSTART and FMSSTOPUpdated to Chapter 28

“LPC5410x Flash signature generator”.

• Typographic errors have been corrected and minor pieces of information added or clarified

throughout the document.

2.0 20150410

• Registers supporting use of dual processors on LPC54102 devices has been added to the Syscon

chapter.

• A Power Management chapter has been added.

• Some pins in the Pin description chapter have the type changed to Z for open drain pins.

• A section has been added to the ADC chapter describing how to configure sample times for

different conversion configurations.

• The ADC operating speed is increased to 5 Ms/s.

• Updated Section 4.5.33 “Flash configuration register” text and Table 62.

• Typographic errors have been corrected and minor pieces of information added or clarified

throughout the document.

1.1 20141121

• In the NVIC chapter, the bit numbers for the priority register fields have been corrected.

• In the Syscon chapter, a functional description section has been added following the register

descriptions to provide additional information about some functions.

• The SCTimer/PWM chapter has been revised to better explain the function.

• Description of the ISP-AP interface and commands is added to the Debug chapter.

• References to Timer 0, 1, 2, 3, and 4 have been updated to use the terminology of the Standard

counter/timers chapter (CT32B0, 1, 2, 3, 4).

• Typographic errors have been corrected and minor pieces of information added or clarified

throughout the document.

User manual Rev. 2.4 — 13 September 2016 4 of 464

NXP Semiconductors

UM10850

LPC5410x User manual

Revision history

Rev Date Description

1.0 20141104 Initial release of the LPC5410x User Manual

…continued

Contact information

For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com

User manual Rev. 2.4 — 13 September 2016 5 of 464

1.1 Introduction

UM10850

Chapter 1: LPC5410x Introductory information

Rev. 2.4 — 13 September 2016 User manual

The LPC5410x are ARM Cortex-M4 based microcontrollers for embedded applications. these devices include an optional ARM Cortex-M0+ coprocessor, 104 KB of on-chip SRAM, 512 KB on-chip flash, five general-purpose timers, one State-Configurable Timer with PWM capabilities (SCTimer/PWM), one R TC/alarm timer , one 24-bit Multi-Rate T imer (MRT), a Windowed Watchdog Timer (WWDT), four USARTs, two SPIs, three Fast-mode

plus I

C-bus interfaces with high-speed slave mode, and one 12-bit 5 Msamples/sec

ADC. The ARM Cortex-M4 is a 32-bit core that of fers system enha ncement s such as low power

consumption, enhanced debug features, and a high level of support block integ ration. The ARM Cortex-M4 CPU incorporates a 3-stage pipeline, uses a Harvard architecture with separate local instruction and data buses as well as a third bus for periphe rals, and includes an internal prefetch unit that supports sp eculative branching. The ARM Cortex-M4 supports single-cycle digital signal processing and SIMD instructions. The Cortex-M4 is the Cortex-M4 with the inclusion of the 32-bit Floating Point Unit.

1.2 Features

The ARM Cortex-M0+ coprocessor available on some devices is an energy-efficient and easy-to-use 32-bit core which is code- and tool-compatible with the Cortex-M4 core. The Cortex-M0+ coprocessor offers up to 100 MHz performance with a simple instruction set and reduced code size.

Refer to LPC5410x data sheets for complete details on specific products and configurations.

• Dual processor core: ARM Cortex-M4 and ARM Cortex-M0+ included fo r LPC54102

devices. Cortex-M4 only is present on LPC54101 devices.

• ARM Cortex-M4 CPU:

– ARM Cortex-M4 processor, running at a frequency of up to 100 MHz. – Floating Point Unit (FPU) and Memory Protection Unit (MPU). – The CPU can operate at frequencies of up to 100 MHz. – ARM Cortex -M 4 bu ilt- in Ne ste d Vectored Interrupt Controller (NVIC). – Non-maskable Interrupt (NMI) with a selection of sources. – Serial Wire Debug (SWD) with 8 breakpoints and 4 watchpoints. Includes Serial

Wire Output for enhanced debug capabilities.

– System tick timer.

• ARM Cortex-M0+ CPU (present on LPC54102 devices):

– ARM Cortex-M0+ processor, running at a frequency of up to 100 MHz (using the

same clock as the Cortex-M4).

– The CPU can operate at frequencies of up to 100 MHz. – ARM Cortex-M0+ built-in Nested Vectored Interrupt Controller (NVIC).

User manual Rev. 2.4 — 13 September 2016 6 of 464

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Chapter 1: LPC5410x Introductory information

– Non-maskable Interrupt (NMI) with a selection of sources. – Serial Wire Deb ug (SWD) with 4 br ea kp oin ts and 2 watchp oints. – System tick timer.

UM10850

• On-Chip memory:

– Up to 512 KB on-chi p flash programming memory with flash accelerator and 256

Byte page write and erase.

– Up to 104 KB total SRAM composed of: – Up to 96 KB contiguous main SRAM. – An additional 8 KB SRAM.

• ROM API support:

– Flash In-A pp licatio n Pro gr a mm in g (IAP ) an d In- Sys te m Pro gr a mmin g (ISP). – Power Control API.

• Serial interfaces:

– Four USART interfaces with synchronous mode and 32 kHz mode for wake-up

from Deep-sleep and Power-down modes. The USAR Ts includ e a FIFO buffer, and share a fractional baud-rate generator.

– Two SPI interfaces, each with 4 slave selects and flexible data configuration. The

SPIs include a FIFO buffer. Able to wake up the device from Deep-sleep and Power-down modes when used in slave mode.

– Three I

of up to 1Mbit/s and with multiple address recognitio n an d mo n ito r mo de . Eac h

I able to wake up the device from Deep-sleep and Power-down modes.

C-bus interfaces supporting fast mode and Fast-mode Plus with data rates

C-bus interface also supports High Speed Mode as a slave. The slave function is

• Digital peripherals:

– DMA controller with 22 channels and 20 programmable triggers, able to access all

memories and DMA-capable peripherals.

– Up to 50 General-Purpose I/O (GPIO) pins. Most GPIOs have configurable

pull-up/pull-down resistors, open-drain mode, and input inverter.

– GPIO registers are located on AHB for fast access. – Up to eight GPIOs can be selected as pin interrupts (PINT), triggered by rising,

falling or both input edges.

– Two GPIO grouped interrupts (GINT) enable an interrupt based on a logical

(AND/OR) combination of input states.

– CRC engine.

• Timers

– Five 32-bit standard general purpose timers/counters, four of which support up to 4

capture inputs and 4 compare outputs, PWM mode, and external count input. Specific timer events can be selected to generate DMA requests. The fifth timer does not have external pin connections and may be used for internal timing operations.

– One State Configurable Timer/PWM (SCTimer/PWM) 6 input and 8 output

functions (including capture and match). Inputs and outputs can be routed to/from external pins and internally to/from selected peripherals. Internally, the SCT supports 13 captures/matches, 13 events and 13 states.

User manual Rev. 2.4 — 13 September 2016 7 of 464

NXP Semiconductors

• Analog peripheral: 12-bit ADC with 12 input channels and with multiple interna l and

• Clock generation:

• Power control:

• JTAG boundary scan supported.

• Unique device serial number (128-bit) for identification.

• Single power supply 1.62 V to 3.6 V.

• Operating temperature range of -40°C to +105°C.

• Available in a 3.288 x 3.288 mm WLCSP49 package and LQFP64 package.

UM10850

Chapter 1: LPC5410x Introductory information

– 32-bit Real-time clock (RTC) with 1 s resolution running in the always-on power

domain. A timer in the RTC can be used for wake-up from all low power modes including Deep power-down, with 1 ms resolution.

– Multiple-channel multi-rate 24-bit timer (MRT) for repetitive interrupt generation at

up to four programmable, fixed rates.

– Windowed Watchdog timer (WWDT). – Ultra-low power Micro-tick Timer, running from the Watchdog oscillator, that can be

used to wake up the device from low power modes.

– Repetitive interrupt timer for general purpose use and use with debug

time-stamping.

external trigger inputs and sample rates of up to 5 MS/s. The ADC suppo rts two independent conversion sequences.

– 12 MHz internal RC oscillator, factory trimmed for accuracy, that can optionally be

used as a system clock.

– External clock input for up 24 MHz. – Internal, low-power, watchdog oscillator (WDOSC) with a nominal frequency of 500

kHz.

– 32 kHz low-power RTC oscillator. – System PLL allows CPU operation up to the maximum CPU rate without the need

for a high-frequency external clock. May be run from the internal RC oscillator, the external clock input CLKIN, or the RTC oscillator.

– Clock output function with divider that can reflect many internal clocks. – Frequency measurement unit for measuring the frequency of any on-chip or

off-chip clock signal.

– Integrated PMU (Power Management Unit) to minimize power consumption. – Reduced power modes: Sleep mode, Deep-sleep mode, Power-down mode, and

Deep power-down mode.

– Wake-up from Deep-sleep and Power-down modes on activity on USART, SPI,

– Wake-up from Sleep, Deep-sleep, Power-down, and Deep power-down modes

– Power-On Reset (POR). – Brownout detect.

C peripherals.

and I

from the RTC alarm.

User manual Rev. 2.4 — 13 September 2016 8 of 464

NXP Semiconductors

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1.3 Block diagram

UM10850

Chapter 1: LPC5410x Introductory information

Fig 1. Block diagram

Grey-shaded blocks show peripherals provide DMA request lines or that can provide hardware triggers for DMA transfers.

User manual Rev. 2.4 — 13 September 2016 9 of 464

NXP Semiconductors

1.4 Architectural overview

The ARM Cortex-M4 includes three AHB-Lite buses, one system bus and the I-code and D-code buses. One bus is dedicated for instruction fetch (I-code), and one bus is dedicated for data access (D-code). The use of two core buses allows for simultaneous operations if concurrent operations target different devices.

A multi-layer AHB matrix connects the CPU buses and other bus masters to peripherals in a flexible manner that optimizes performance by allowing peripherals on different slaves ports of the matrix to be accessed simultaneously by different bus masters. More information on the multilayer matrix can be found in Section 2.1.3 multilayer matrix are shown in Figure 1

APB peripherals are connected to the AHB matrix via two APB buses using separate slave ports from the multilayer AHB matrix. This allows for better performance by reducing collisions between the CPU and the DMA controller, and also for peripherals on the asynchronous bridge to have a fixed clock that does not track the system clock.

1.5 ARM Cortex-M4 processor

UM10850

Chapter 1: LPC5410x Introductory information

. Connections in the

The Cortex-M4 is a general purpose 32-bit microprocessor, which offers high performance and very low power consumption. The Cortex-M4 offers a Thumb-2 instruction set, low interrupt latency, interruptible/continuable multiple load and store instructions, automatic state save and restore for interrupts, tightly integrated interrupt controller, and multiple core buses capable of simultaneou s accesses.

A 3-stage pipeline is employed so that all parts of the processing and memory systems can operate continuously. Typically , while on e in struction is b eing e xecuted, its successor is being decoded, and a third instruction is being fetched from memory.

Information about Cortex-M4 configuration options can be found in Chapter 32

1.6 ARM Cortex-M0+ processor (present on LPC54102 devices)

The Cortex-M0+ is a general purpose 32-bit microprocessor with extremely low power consumption. The Cortex-M0+ includes the bulk of the Thumb instruction set and a small subset of Thumb-2 Instructions. The Cortex-M0+ has a 2-stage pipeline in order to decrease power consumption, and includes a 32-cycle multiplier.

Information about Cortex-M0+ configuration options can be found in Chapter 32

User manual Rev. 2.4 — 13 September 2016 10 of 464

UM10850

Chapter 2: LPC5410x Memory mapping

Rev. 2.4 — 13 September 2016 User manual

2.1 General description

The LPC5410x incorporates several distinct memory regions. Figure 2 shows the overall map of the entire address space from the user program viewpoint following reset.

The APB peripheral area is 512 KB in size and is divided to allow for up to 32 peripherals. Each peripheral is allocated 16 KB of space, simplifying the address decoding.

The registers incorporated into the CPU, such as NVIC, SysTick, and sleep mode control, are located on the private peripheral bus.

2.1.1 Main SRAM

The parts contain up to a tot al 96 KB of contigu ous, on-chip st atic RAM memory (this is in addition to SRAM2 as noted in the next section below, so the total device SRAM can be up to 104 KB). For each SRAM configuration, the SRAM is divi ded into two blocks: SRAM0 (up to 64 KB) and SRAM1 (up to 32 KB). The bottom 8 KB of SRAM can be enabled separately in order to allow saving dat a with minimal power usage during Power-down mode. The remaining portion of SRAM0 and the entire SRAM1 can also be disabled or enabled individually in the SYSCON block to save power. See Section 4.5.22

“AHB Clock Control register 0” and Section 4.5.38 “Power Configuration register”.

Table 1. Main SRAM configuration

SRAM0 SRAM1

(total main SRAM = up to 96 KB)

Size Up to 64 KB Up to 32 KB Address range

Power Control (via Power API)

• Always begins at 0x0200 0000.

• Continues to 0x0200 FFFF (for full 64

KB).

• First 8 KB is has a separate power switch.

• Remaining SRAM0 has a single power

switch.

• Begins at end of SRAM0, 0x0201 0000 when SRAM0

is a full 64 KB.

• Ends at 0x0201 7FFF for 32 KB SRAM1 with 64 KB

SRAM0.

• All of SRAM1 has a single power switch.

2.1.1.1 SRAM2

An additional on-chip static RAM memory, SRAM2, is available that is not contiguous to SRAM0 and SRAM1. This can be used, for example, as the location for the program stack, or any other use. SRAM2 can be disabled or enabled in the SYSCON block to save power. See Section 4.5.22 “

Configuration register”.

AHB Clock Control register 0” and Section 4.5.38 “Power

2.1.1.2 SRAM usage notes

Although always contiguous on all LPC5410x devices, SRAM0 and SRAM1 are placed on different AHB matrix ports. This allows user programs to potentially obtain better performance by dividing RAM usage among the 2 ports. For example, simultaneous access to SRAM0 by the CPU and SRAM1 by the system DMA controller does not result in any bus stalls for either master.

User manual Rev. 2.4 — 13 September 2016 11 of 464

NXP Semiconductors

Generally speaking, the CPU will read or write all peripheral data at some point, even when all such data is read from or sent to a peripheral by DMA. So, minimizing stalls is likely to involve putting data to/from different peripherals in RAM on each port.

Alternatively, sequences of data from the same peripheral could be alternated between RAM on each port. this could be helpful if DMA fills or empties a RAM buffer, then signals the CPU before proceeding on to a second buffer. the CPU would then tend to access the data while the DMA is using the other RAM.

UM10850

Chapter 2: LPC5410x Memory mapping

User manual Rev. 2.4 — 13 September 2016 12 of 464

NXP Semiconductors

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2.1.2 Memory mapping

UM10850

Chapter 2: LPC5410x Memory mapping

Fig 2. Memory mapping

User manual Rev. 2.4 — 13 September 2016 13 of 464

The private peripheral bus includes CPU peripherals such as the NVIC, SysTick, and the core control registers.

NXP Semiconductors

2.1.3 AHB multilayer matrix

The LPC5410x uses a multi-layer AHB matrix to connect the CPU buses and other bus masters to peripherals in a flexible manner that optimizes performance by allowing peripherals that are on different slave po rts of the matrix to be accessed simultaneously by different bus masters. Figure 1

2.1.4 Memory Protection Unit (MPU)

The Cortex-M4 processor has a memory protection unit (MPU) that provides fine grain memory control, enabling applications to implement security privilege levels, separating code, data and stack on a task-by-task basis. Such requirements are critical in many embedded applications.

The MPU register interface is located on the private peripheral bus and is described in detail in Ref. 1 “

UM10850

Chapter 2: LPC5410x Memory mapping

shows details of the potential matrix connections.

Cortex-M4 TRM”.

User manual Rev. 2.4 — 13 September 2016 14 of 464

UM10850

Chapter 3: LPC5410x Nested Vectored Interrupt Controller (NVIC)

Rev. 2.4 — 13 September 2016 User manual

3.1 How to read this chapter

Available interrupt sources may vary with specific LPC5410x device type.

3.2 Features

• Nested Vectored Interrupt Controller that is an integral part of each CPU.

• Tightly coupled interrupt controller provides low interrupt latency.

• Controls system exceptions and peripheral interrupts.

• The NVIC of the Cortex-M4 supports:.

– 37 vectored interrupts. – 8 programmable interrupt priority levels with hardware priority level masking. – Vector table offset register VTOR. – Software interrupt generation.

• The Cortex- M0+ (present on LPC54102 devices) supports: the first 32 interrupts.

– 32 vectored interrupts. – 4 programmable interrupt priority levels with hardware priority level masking. – Vector table offset register VTOR.

• Support for NMI from any interrupt (see Section 4.5.3).

3.3 General description

The tight coupling to the NVIC to the CPU allows for low interrupt latency and efficient processing of late arriving interrupts.

3.3.1 Interrupt sources

Table 2 lists the interrupt sources for each peripheral function. Each peripheral device

may have one or more interrupt lines to the Vectored Interrupt Controller. Each line may represent more than one interrupt source. The interrupt number does not imply any interrupt priority.

See Ref. 1 “ the NVIC and the NVIC registers.

Table 2. Connection of interrupt sources to the NVIC

Interrupt Name Description Flags

0 WDT Windowed watchdog timer interrupt WARNINT - watchdog warning interrupt 1 BOD BOD interrupt BODINTVAL - BOD interrupt level 2 (reserved) -

3 DMA DMA interrupts Interrupt A and interrupt B, error interrupt

User manual Rev. 2.4 — 13 September 2016 15 of 464

Cortex-M4 TRM” and Ref. 2 “Cortex-M0+ TRM” for detailed descriptions of

NXP Semiconductors

UM10850

Chapter 3: LPC5410x Nested Vectored Interrupt Controller (NVIC)

Table 2. Connection of interrupt sources to the NVIC

Interrupt Name Description Flags

4 GINT0 GPIO group 0 interrupt Enabled pin interrupts 5 PIN_INT0 Pin interrupt 0 or pattern match engine slice 0 int PSTAT - pin interrupt status 6 PIN_INT1 Pin interrupt 1o r pattern match engine slice 1 int PSTAT - pin interrupt status 7 PIN_INT2 Pin interrupt 2 or pattern match engine slice 2 int PSTAT - pin interrupt status 8 PIN_INT3 Pin interrupt 3 or pattern match engine slice 3 int PSTAT - pin interrupt status 9 UTICK Micro-tick Timer interrupt INTR 10 MRT Multi-rate timer interrupt Global MRT interrupts: GFLAG0, 1, 2, 3 11 CT32B0 Standard counter/timer CT32B0 interrupt Match and Capture interrupts 12 CT32B1 Standard counter/timer CT32B1 interrupt Match and Capture interrupts 13 CT32B2 Standard counter/timer CT32B2 interrupt Match and Capture interrupts 14 CT32B3 Standard counter/timer CT32B3 interrupt Match and Capture interrupts 15 CT32B4 Standard counter/timer CT32B4 interrupt Match and Capture interrupts 16 SCT0 State configurable timer interrupt EVFLAG SCT event 17 UART0 USART0 interrupt See Table 310 18 UART1 USART1 interrupt Same as USART0 19 UART2 USART2 interrupt Same as USART0 20 UART3 USART3 interrupt Same as USART0 21 I2C0 I2C0 interrupt See Table 348 22 I2C1 I2C1 interrupt Same as I2C0 23 I2C2 I2C2 interrupt Same as I2C0 24 SPI0 SPI0 interrupt See Table 325 25 SPI1 SPI1 interrupt Same as SPI0 26 ADC0_SEQA ADC0 sequence A completion. See Table 428 27 ADC0_SEQB ADC0 sequence B completion. See Table 428 28 ADC0_THCMP ADC0 threshold compare and error. See Table 428 29 RTC RTC alarm and wake-up interrupts See Table 276 30 (reserved) -

31 MAILBOX Mailbox interrupt (present on LPC54102 devices) Mailbo x Interrupt

The following interrupts are supported only on the Cortex-M4

32 GINT1 GPIO group 1 interrupt Enabled pin interrupts 33 PIN_INT4 Pin interrupt 4 or pattern match engine slice 4 int PSTAT - pin interrupt status 34 PIN_INT5 Pin interrupt 5 or pattern match engine slice 5 int PSTAT - pin interrupt status 35 PIN_INT6 Pin interrupt 6 or pattern match engine slice 6 int PSTAT - pin interrupt status 36 PIN_INT7 Pin interrupt 7 or pattern match engine slice 7 int PSTAT - pin interrupt status 39:37 (reserved) - 40 RIT Repetitive Interrupt Timer RITINT; masked compare interrupt

. . . .

User manual Rev. 2.4 — 13 September 2016 16 of 464

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UM10850

Chapter 3: LPC5410x Nested Vectored Interrupt Controller (NVIC)

3.4 Register description

The NVIC registers are located on the ARM private peripheral bus.

Table 3. Register overview: NVIC (base address 0xE000 E000)

Name Access Address

ISER0 R/W 0x100 Interrupt Set Enable Register 0. This register allows enabling interrupts

ISER1 R/W 0x104 Interrupt Set Enable Register 1. See ISER0 description. 0 Table 5 ICER0 R/W 0x180 Interrupt Clear Enable Register 0. This register allows disabling

ICER1 R/W 0x184 Interrupt Clear Enable Register 1. See ISER0 description. 0 Table 7 ISPR0 R/W 0x200 Interrupt Set Pending Register 0. This register allows changing the

ISPR1 R/W 0x204 Interrupt Set Pending Register 1. See ISPR0 description. 0 Table 9 ICPR0 R/W 0x280 Interrupt Clear Pending Register 0. This register allows changing the

ICPR1 R/W 0x284 Interrupt Clear Pending Register 1. See ICPR0 description. 0 Table 11

[1]

IABR0

IABR1 IPR0 R/W 0x400 Interrupt Priority Register 0. This register contains the 3-bit priority fields

IPR1 R/W 0x404 Interrupt Priority Register 1. This register contains the 3-bit priority fields

IPR2 R/W 0x408 Interrupt Priority Register 2. This register contains the 3-bit priority fields

IPR3 R/W 0x40C Interrupt Priority Register 3. This register contains the 3-bit priority fields

IPR4 R/W 0x410 Interrupt Priority Register 4. This register contains the 3-bit priority fields

IPR5 R/W 0x414 Interrupt Priority Register 5. This register contains the 3-bit priority fields

IPR6 R/W 0x418 Interrupt Priority Register 6. This register contains the 3-bit priority fields

IPR7 R/W 0x41C Interrupt Priority Register 7. This register contains the 3-bit priority fields

IPR8 R/W 0x420 Interrupt Priority Register 8. This register contains the 3-bit priority fields

IPR9 R/W 0x424 Interrupt Priority Register 9. This register contains the 3-bit priority fields

IPR10 R/W 0x428 Interrupt Priority Register 10. Th is register contains the 3-bit priority field

STIR

RO 0x300 Interrupt Active Bit Register 0. This register allows reading the current

[1]

RO 0x304 Interrupt Active Bit Register 1. See IABR0 description. 0 Table 13

[1]

WO 0xF00 Software Trigger Interrupt Register, allows software to generate

offset

Description Reset

value

0 Table 4

and reading back the interrupt enables for peripheral functions.

0 Table 6

interrupts and reading back the interrupt enables for peripheral functions.

0 Table 8 interrupt state to pending and reading back the interrupt pending state for peripheral functions.

0 Table 10 interrupt state to not pending and reading back the interrupt pending state for peripheral functions.

0 Table 12 interrupt active state for specific peripheral functions.

0 Table 14 for interrupts 0 to 3.

0 Table 15 for interrupts 4 to 7.

0 Table 16 for interrupts 8 to 11.

0 Table 17 for interrupts 12 to 15.

0 Table 18 for interrupts 16 to 19.

0 Table 19 for interrupts 20 to 23.

0 Table 20 for interrupts 24 to 27.

0 Table 21 for interrupts 28 to 31.

0 Table 22 for interrupts 32 to 35.

0 Table 23 for interrupts 36 to 39.

0 Table 24 for interrupt 40.

- Table 25

interrupts.

Reference

[1] This register is not available for the Cortex-M0+.

User manual Rev. 2.4 — 13 September 2016 17 of 464

NXP Semiconductors

Chapter 3: LPC5410x Nested Vectored Interrupt Controller (NVIC)

3.4.1 Interrupt Set-Enable Register 0 register

The ISER0 register allows enabling the first 32 peripheral interrupts, or for reading the enabled state of those interrupts. The rema ining interrupts are enabled via the ISER1 register (Section 3.4.2 registers (Section 3.4.3

Table 4. Interrupt Set-Enable Register 0 register

Bit Name Value Function

0 ISE_WDT 1 ISE_BOD 2 - - Reserved. Read value is undefined, only zero should be written. 3 ISE_DMA 4 ISE_GINT0 5 ISE_PINT0 6 ISE_PINT1 7 ISE_PINT2 8 ISE_PINT3 9 ISE_UTICK 10 ISE_MRT 11 ISE_CT32B0 12 ISE_CT32B1 13 ISE_CT32B2 14 ISE_CT32B3 15 ISE_CT32B4 16 ISE_SCT0 17 ISE_USART0 18 ISE_USART1 19 ISE_USART2 20 ISE_USART3 21 ISE_I2C0 22 ISE_I2C1 23 ISE_I2C2 24 ISE_SPI0 25 ISE_SPI1 26 ISE_ADC0SEQA 27 ISE_ADC0SEQB 28 ISE_ADC0THOV 29 ISE_RTC 30 - - Reserved. Read value is undefined, only zero should be written. 31 ISE_MAILBOX

[1] [1]

[1] [1] [1] [1] [1] [1] [1] [1] [1] [1] [1] [1] [1] [1] [1] [1] [1] [1] [1] [1] [1] [1] [1] [1] [1] [1] [1]

[1]

Watchdog Timer interrupt enable. BOD interrupt enable.

DMA interrupt enable. GPIO group 0 interrupt enable. Pin interrupt / pattern match engine slice 0 interrupt. Pin interrupt / pattern match engine slice 1 interrupt. Pin interrupt / pattern match engine slice 2 interrupt. Pin interrupt / pattern match engine slice 3 interrupt. Micro-Tick Timer interrupt enable. Multi-Rate Timer interrupt enable. Standard counter/timer CT32B0 interrupt enable. Standard counter/timer CT32B1 interrupt enable. Standard counter/timer CT32B2 interrupt enable. Standard counter/timer CT32B3 interrupt enable. Standard counter/timer CT32B4 interrupt enable. SCT0 interrupt enable. USART0 interrupt enable. USART1 interrupt enable. USART2 interrupt enable. USART3 interrupt enable. I2C0 interrupt enable. I2C1 interrupt enable. I2C2 interrupt enable. SPI0 interrupt enable. SPI1 interrupt enable. ADC0 sequence A interrupt enable. ADC0 sequence B interrupt enable. ADC0 threshold and error interrupt enable. Real Time Clock (RTC) interrupt enable.

Mailbox interrupt enable (present on LPC54102 devices).

). Disabling interrupts is done through the ICER0 and ICER1

and Section 3.4.4).

UM10850

[1] Write: writing 0 has no effect, writing 1 enables the interrupt.

Read: 0 indicates that the interrupt is disabled, 1 indicates that the interrupt is enabled.

User manual Rev. 2.4 — 13 September 2016 18 of 464

NXP Semiconductors

Chapter 3: LPC5410x Nested Vectored Interrupt Controller (NVIC)

3.4.2 Interrupt Set-Enable Register 1 register

The ISER1 register allows enabling the second group of peripheral interrupts, or for reading the enabled state of those interrupts. Disabling int er ru pts is done throu g h the ICER0 and ICER1 registers (Section 3.4.3

Table 5. Interrupt Set-Enable Register 1 register

Bit Name Value Function

0 ISE_GINT1 1 ISE_PINT4 2 ISE_PINT5 3 ISE_PINT6 4 ISE_PINT7 7:5 - - Reserved. Read value is undefined, only zero should be written. 8 ISE_RIT 31:9 - - Reserved. Read value is undefined, only zero should be written.

[1] [1] [1] [1] [1]

[1]

GPIO group 1 interrupt enable. Pin interrupt / pattern match engine slice 4 interrupt. Pin interrupt / pattern match engine slice 5 interrupt. Pin interrupt / pattern match engine slice 6 interrupt. Pin interrupt / pattern match engine slice 7 interrupt.

Repetitive Interrupt Timer interrupt enable.

[1] Write: writing 0 has no effect, writing 1 enables the interrupt.

Read: 0 indicates that the interrupt is disabled, 1 indicates that the interrupt is enabled.

and Section 3.4.4).

UM10850

3.4.3 Interrupt Clear-Enable Register 0

The ICER0 register allows disabling the first 32 peripheral interrupts, or for reading the enabled state of those interrupts. The remaining interrupts are disabled via the ICER1 register (Section 3.4.4 registers (Section 3.4.1

Table 6. Interrupt Clear-Enable Register 0

Bit Name Function

31:0 ICE_... Peripheral interrupt disables. Bit numbers match ISER0 registers (Table 4

Write: writing 0 has no effect, writing 1 disables the interrupt. Read: 0 indicates that the interrupt is disabled, 1 indicates that the interrupt is enabled.

). Enabling interrupts is done through the ISER0 and ISER1

and Section 3.4.2).

3.4.4 Interrupt Clear-Enable Register 1 register

The ICER1 register allows disabling the second group of peripheral interrupts, or for reading the enabled state of those interrupts. Enabling inter ru p ts is done throug h th e ISER0 and ISER1 registers (Section 3.4.1

Table 7. Interrupt Clear-Enable Register 1 register

Bit Name Function

31:0 ICE_... Peripheral interrupt disables. Bit numbers match ISER1 registers (Table 5

Write: writing 0 has no effect, writing 1 disables the interrupt. Read: 0 indicates that the interrupt is disabled, 1 indicates that the interrupt is enabled.

and Section 3.4.2).

). Unused bits are reserved.

3.4.5 Interrupt Set-Pending Register 0 register

The ISPR0 register allows setting the pending state of th e first 32 pe ripher al inter rupts, or for reading the pending state of those interrupts. The remaining interrupts can have their pending state set via the ISPR1 register (Section 3.4.6 interrupts is done through the ICPR0 and ICPR1 registers (Section 3.4.7

User manual Rev. 2.4 — 13 September 2016 19 of 464

). Clearing the pending state of

and

NXP Semiconductors

Chapter 3: LPC5410x Nested Vectored Interrupt Controller (NVIC)

Section 3.4.8).

Table 8. Interrupt Set-Pending Register 0 register

Bit Name Function

31:0 ISP_... Peripheral interrupt pending set. Bit numbers match ISER0 registers (Table 4

Write: writing 0 has no effect, writing 1 changes the interrupt state to pending. Read: 0 indicates that the interrupt is not pending, 1 indicates that the interrupt is pending.

3.4.6 Interrupt Set-Pending Register 1 register

The ISPR1 register allows setting the pending state of the second group of peripheral interrupts, or for reading the pending state of those interrupts. Clearing the pending state of interrupts is done through the ICPR0 and ICPR1 registers (Section 3.4.7

Section 3.4.8

Table 9. Interrupt Set-Pending Register 1 register

Bit Name Function

31:0 ISP_... Peripheral interrupt pending set. Bit numbers match ISER1 registers (Table 5

Write: writing 0 has no effect, writing 1 changes the interrupt state to pending. Read: 0 indicates that the interrupt is not pending, 1 indicates that the interrupt is pending.

UM10850

). Unused bits are reserved.

and

). Unused bits are reserved.

3.4.7 Interrupt Clear-Pending Register 0 register

The ICPR0 register allows clearing the pending state of the first 32 peripheral interrupts, or for reading the pending state of those interrupts. The remaining interrupts can have their pending state cleared via the ICPR1 register (Section 3.4.8 state of interrupts is done through the ISPR0 and ISPR1 registers (Section 3.4.5

Section 3.4.6

Table 10. Interrupt Clear-Pending Register 0 register

Bit Name Function

31:0 ICP_... Peripheral interrupt pendin g clear. Bit numbers match ISER0 registers (Table 4

Write: writing 0 has no effect, writing 1 changes the interrupt state to not pending. Read: 0 indicates that the interrupt is not pending, 1 indicates that the interrupt is pending.

3.4.8 Interrupt Clear-Pending Register 1 register

The ICPR1 register allows clearing the pending state of the second group of peripheral interrupts, or for reading the p ending st ate of those interrupt s. Setting the pe nding st ate of interrupts is done through the ISPR0 and ISPR1 registers (Section 3.4.5

Section 3.4.6

Table 11. Interrupt Clear-Pending Register 1 register

Bit Name Function

31:0 ICP_... Peripheral interrupt pendin g clear. Bit numbers match ISER1 registers (Table 5

Write: writing 0 has no effect, writing 1 changes the interrupt state to not pending. Read: 0 indicates that the interrupt is not pending, 1 indicates that the interrupt is pending.

). Setting the pending

and

). Unused bits are reserved.

and

). Unused bits are reserved.

User manual Rev. 2.4 — 13 September 2016 20 of 464

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Chapter 3: LPC5410x Nested Vectored Interrupt Controller (NVIC)

3.4.9 Interrupt Active Bit Register 0

The IABR0 register is a read-only register that allows reading the active state of the first 32 peripheral interrupts. Bits in IABR are set while the corresponding interrupt service routines are in progress. Additional interrupts can have their active state read via the IABR1 register (Section 3.4.10

Table 12. Interrupt Active Bit Register 0

Bit Name Function

31:0 IAB_... Peripheral interrupt active. Bit numbers match ISER0 registers (Table 4

Read: 0 indicates that the interrupt is not active, 1 indicates that the interrupt is active.

). IABR registers are not available for the Cortex-M0+.

3.4.10 Interrupt Active Bit Register 1

The IABR1 register is a read-only register that allows reading the active state of the second group of peripheral interrupts. Bits in IABR are set while the corresponding interrupt service routines are in progress. IABR registers are not available for the Cortex-M0+.

Table 13. Interrupt Active Bit Register 1

Bit Name Function

31:0 IAB_... Peripheral interrupt active. Bit numbers match ISER1 registers (Table 5

Read: 0 indicates that the interrupt is not active, 1 indicates that the interrupt is active.

UM10850

). Unused bits are reserved.

3.4.11 Interrupt Priority Register 0

The IPR0 register controls the priority of the first 4 periphera l interrupts. Each interr upt can have one of 32 priorities, where 0 is the highest priority.

Table 14. Interrupt Priority Reg is ter 0

Bit Name Function

4:0 - Unused 7:5 IP_WDT Watchdog Timer interrupt priority. 0 = highest priority. 31 (0x1F) = lowest priority. 12:8 - Unused 15:13 IP_BOD BOD interrupt priority. 0 = highest priority. 31 (0x1F) = lowest priority. 20:16 - Unused 23:21 - Reserved. 28:24 - Unused 31:29 IP_DMA DMA interrupt priority. 0 = highest priority. 31 (0x1F) = lowest priority.

3.4.12 Interrupt Priority Register 1

The IPR1 register controls the priority of the second group of 4 peripheral interru pts. Each interrupt can have one of 32 priorities, where 0 is the highest prior ity.

Table 15. Interrupt Priority Reg is ter 1

Bit Name Function

4:0 - Unused 7:5 IP_GINT0 GPIO Group 0 interrupt priority. 0 = highest priority. 31 (0x1F) = lowest priority. 12:8 - Unused

User manual Rev. 2.4 — 13 September 2016 21 of 464

NXP Semiconductors

UM10850

Chapter 3: LPC5410x Nested Vectored Interrupt Controller (NVIC)

Table 15. Interrupt Priority Reg is ter 1

Bit Name Function

15:13 IP_PINT0 Pin interrupt / pattern match engine slice 0 priority. 0 = highest priority. 31 (0x1F) = lowest priority. 20:16 - Unused 23:21 IP_PINT1 Pin interrupt / pattern match engine slice 1 priority. 0 = highest priority. 31 (0x1F) = lowest priority. 28:24 - Unused 31:29 IP_PINT2 Pin interrupt / pattern match engine slice 2 priority. 0 = highest priority. 31 (0x1F) = lowest priority.

…continued

3.4.13 Interrupt Priority Register 2

The IPR2 register controls the priority of the third group of 4 peripheral interrupts. Each interrupt can have one of 32 priorities, where 0 is the highest prior ity.

Table 16. Interrupt Priority Reg is ter 2

Bit Name Function

4:0 - Unused 7:5 IP_PINT3 Pin interrupt / pattern match engine slice 3 priority. 0 = highest priority. 31 (0x1F) = lowest priority. 12:8 - Unused 15:13 IP_UTICK Micro-Tick Timer interrupt priority. 0 = highest priority. 31 (0x1F) = lowest priority. 20:16 - Unused 23:21 IP_MRT Multi-Rate Timer interrupt priority. 0 = highest priority. 31 (0x1F) = lowest priority. 28:24 - Unused 31:29 IP_CT32B0 Standard counter/timer CT32B0 interrupt priority. 0 = highest priority. 31 (0x1F) = lowest priority.

3.4.14 Interrupt Priority Register 3

The IPR3 register controls the priority of the fourth group of 4 peripheral interrupts. Each interrupt can have one of 32 priorities, where 0 is the highest prior ity.

Table 17. Interrupt Priority Reg is ter 3

Bit Name Function

4:0 - Unused 7:5 IP_CT32B1 Standard counter/timer CT32B1 interrupt priority. 0 = highest priority. 31 (0x1F) = lowest priority. 12:8 - Unused 15:13 IP_CT32B2 Standard counter/timer CT32B2 interrupt priority. 0 = highest priority. 31 (0x1F) = lowest priority. 20:16 - Unused 23:21 IP_CT32B3 Standard counter/timer CT32B3 interrupt priority. 0 = highest priority. 31 (0x1F) = lowest priority. 28:24 - Unused 31:29 IP_CT32B4 Standard counter/timer CT32B4 interrupt priority. 0 = highest priority. 31 (0x1F) = lowest priority.

3.4.15 Interrupt Priority Register 4

The IPR4 register controls the priority of the fifth group of 4 peripheral interrupts. Each interrupt can have one of 32 priorities, where 0 is the highest prior ity.

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Chapter 3: LPC5410x Nested Vectored Interrupt Controller (NVIC)

Table 18. Interrupt Priority Reg is ter 4

Bit Name Function

4:0 - Unused 7:5 IP_SCT0 SCT0 interrupt priority. 0 = highest priority. 31 (0x1F) = lowest priority. 12:8 - Unused 15:13 IP_USART0 USAR T 0 interrupt priority. 0 = highest priority. 31 (0x1F) = lowest priority. 20:16 - Unused 23:21 IP_USART1 USAR T 1 interrupt priority. 0 = highest priority. 31 (0x1F) = lowest priority. 28:24 - Unused 31:29 IP_USART2 USAR T 2 interrupt priority. 0 = highest priority. 31 (0x1F) = lowest priority.

3.4.16 Interrupt Priority Register 5

The IPR5 register controls the priority of the sixth group of 4 peripheral interrupts. Each interrupt can have one of 32 priorities, where 0 is the highest prior ity.

Table 19. Interrupt Priority Reg is ter 5

Bit Name Function

4:0 - Unused 7:5 IP_USART3 USART 3 interrupt priority. 0 = highest priority. 31 (0x1F) = lowest priority. 12:8 - Unused 15:13 IP_I2C0 I2C 0 interrupt priority. 0 = highest priority. 31 (0x1F) = lowest priority. 20:16 - Unused 23:21 IP_I2C1 I2C 1 interrupt priority. 0 = highest priority. 31 (0x1F) = lowest priority. 28:24 - Unused 31:29 IP_I2C2 I2C 2 interrupt priority. 0 = highest priority. 31 (0x1F) = lowest priority.

3.4.17 Interrupt Priority Register 6

The IPR6 register controls the priority of the seventh group of 4 peripheral interrupts. Each interrupt can have one of 32 priorities, where 0 is the highest prior ity.

Table 20. Interrupt Priority Reg is ter 6

Bit Name Function

4:0 - Unused 7:5 IP_SPI0 SPI 0 interrupt priority. 0 = highest priority. 31 (0x1F) = lowest priority. 12:8 - Unused 15:13 IP_SPI1 SPI 1 interrup t prio rity. 0 = highest priority. 31 (0x1F) = lowest priority. 20:16 - Unused 23:21 IP_ADC0SEQA ADC 0 sequence A interrupt priority. 0 = highest priority. 31 (0x1F) = lowest priority. 28:24 - Unused 31:29 IP_ADC0SEQB ADC 0 sequence B interrupt priority. 0 = highest priority. 31 (0x1F) = lowest priority.

3.4.18 Interrupt Priority Register 7

The IPR7 register controls the priority of the eighth group of 4 peripheral interrupts. Each interrupt can have one of 32 priorities, where 0 is the highest prior ity.

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Chapter 3: LPC5410x Nested Vectored Interrupt Controller (NVIC)

Table 21. Interrupt Priority Reg is ter 7

Bit Name Function

4:0 - Unused 7:5 IP_ADC0THOV ADC 0 threshold and error interrupt priority. 0 = highest priority. 31 (0x1F) = lowest priority. 12:8 - Unused 15:13 IP_RTC Real Time clock (RTC) interrupt priority. 0 = highest priority. 31 (0x1F) = lowest priority. 20:16 - Unused 23:21 - Reserved 28:24 - Unused 31:29 IP_MAILBOX Mailbox interrupt priority. 0 = highest priority. 31 (0x1F) = lowest priority (present on LPC54102

devices).

3.4.19 Interrupt Priority Register 8

The IPR8 register controls the priority of the ninth and last group of 4 peripheral interrupts. Each interrupt can have one of 32 priorities, where 0 is the highest priority.

Table 22. Interrupt Priority Reg is ter 8

Bit Name Function

4:0 - Unused 7:5 IP_GINT1 GPIO Group 1 interrupt priority. 0 = highest priority. 31 (0x1F) = lowest priority. 12:8 - Unused 15:13 IP_PINT4 Pin interrupt / pattern match engine slice 4 priority. 0 = highest priority. 31 (0x1F) = lowest priority. 20:16 - Unused 23:21 IP_PINT5 Pin interrupt / pattern match engine slice 5 priority 0 = highest priority. 31 (0x1F) = lowest priority. 28:24 - Unused 31:29 IP_PINT6 Pin interrupt / pattern match engine slice 6 priority. 0 = highest priority. 31 (0x1F) = lowest priority.

3.4.20 Interrupt Priority Register 9

The IPR9 register controls the priority of the tenth group of 4 peripheral interrupts. Each interrupt can have one of 32 priorities, where 0 is the highest prior ity.

Table 23. Interrupt Priority Reg is ter 9

Bit Name Function

4:0 - Unused 7:5 IP_PINT7 Pin interrupt / pattern match engine slice 7 priority. 0 = highest priority. 31 (0x1F) = lowest priority. 31:8 - Reserved

3.4.21 Interrupt Priority Register 10

The IPR10 register controls the priority of the eleventh group of 4 peripheral interrupts. Each interrupt can have one of 32 priorities, where 0 is the highest priority.

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Table 24. Interrupt Priority Reg is ter 10

Bit Name Function

4:0 - Unused 7:5 IP_RIT Repetitive interrupt Timer interrupt priority. 0 = highest priority. 31 (0x1F) = lowest priority. 31:8 - Reserved

3.4.22 Software Trigger Interrupt Register

The STIR register provides an alternate way for software to generate an interrupt, in addition to using the ISPR registers. This mechanism can only be used to generate peripheral interrupts, not system exceptions. the STIR register is not available for the Cortex-M0+.

By default, only privileged software can write to the STIR register. Unprivileged software can be given this ability if privileged software sets the USERSETMPEND bit in the CCR register.

The interrupt number to be programmed in this register is listed in Table 2

Table 25. Software Trigger Interrupt Register (STIR)

Bit Symbol Description

8:0 INTID Writing a value to this field generates an interrupt for the specified the interrupt number. 31:9 - Reserved. Read value is undefined, only zero should be written.

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4.1 Features

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Chapter 4: LPC5410x System configuration (SYSCON)

Rev. 2.4 — 13 September 2016 User manual

• System and bus configuration.

• Clock select and control.

• PLL configuration

• Reset control.

• Wake-up control.

• BOD configuration.

• High-accuracy frequency measurement function for on-chip and off-chip clocks.

• Uses a selection of on-chip clocks as reference clock.

• Device ID register.

4.2 Basic configuration

Configure the SYSCON block as follows:

• The SYSCON uses the CLKIN, and CLKOUT pins which can be configured through

IOCON. See Section 4.3

• No clock configuration is needed. The clock to the SYSCON block is always enabled.

By default, the SYSCON block is clocked by the IRC.

• Target and reference clocks for the frequency measurement function are selected in

the input mux block. See Table 131

4.2.1 Set up the PLL

The PLL creates a stable output clock at a higher frequen cy than the input clock. If a mai n clock is needed with a frequency higher than the 12 MHz IRC clock, use the PLL to boost the input frequency. The PLL can be set up by calling an API supplied by NXP Semiconductors. Also see Section 4.6.4 “

“PLL registers”.

4.2.2 Configure the main clock and system clock

The clock source for the registers and memories is derived from main clock. The main clock can be selected from the sources listed in step 1 below.

. RESET is a dedicated pin.

PLL functional description” and Section 4.5.37

The divided main clock is called the system clock and clocks the core, the memories, and the peripherals (register interfaces and peripheral clocks).

1. Select the main clock. The following options are available:

– IRC: 12 MHz internal oscillator (default) – CLKIN – Watchdog oscillator – The output of the system PLL

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2. Select the divider value for the system clock. A divider value of 0 disables the system

3. Select the memories and peripherals that are operating in the application and

4.2.3 Measure the frequency of a clock signal

The frequency of any on-chip or off-chip clock signal can be measured accurately with a selectable reference clock. For example, the frequency measurement function can be used to accurately determine the frequency of the watchdog oscillator which varies over a wide range depending on process and temperature.

Chapter 4: LPC5410x System configuration (SYSCON)

– The RTC 32 kHz oscillator

Section 4.5.16 “ source select register B”.

clock.

Section 4.5.29 “

therefore must have an active clock. The core is always clocked.

Section 4.5.22 “ register 1”.

Main clock source select register A” and Section 4.5.17 “Main clock

System clock divider register”

AHB Clock Control register 0” and Section 4.5.23 “AHB Clock Control

UM10850

The clock frequency to be measured and the refe rence clock are selected in the input mux block. See Section 8.6.4 “ and Section 8.6.5 “

Details on the accuracy and measurement process are described in Section 4.6.5

“Frequency measure function”.

To start a frequency measurement cycle and read the result, see Table 61

4.3 Pin description

Table 26. SYSCON pin description

Function Direction Pin Description Reference

CLKOUT O PIO0_21 CLKOUT clock output. Chapter 7 CLKIN I PIO0_22 External clock input. Chapter 7

4.4 General description

4.4.1 Clock generation

The system control block facilitates the clock generation. Many clocking variations are possible. Figure 3 frequency is 100 MHz.

Frequency measure function reference clock select register”

Frequency measure function target clock select register”.

gives an overview of potential clock options. The maximum clock

Remark: In order for any of the clock multiplexers shown in Figure 3 currently selected clock must be running, and the clock to be switched to must also be running. This is so that the multiplexer can gracefully switch between the two clocks without glitches.

User manual Rev. 2.4 — 13 September 2016 28 of 464

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NXP Semiconductors

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The low-power watchdog oscillator provides a fixed clock of approximately 500 kHz. The accuracy of this clock is limited to +/- 40% over temperature, voltage, and silicon processing variations. To determine the actual watchdog oscillator output, use the frequency measure block. See Section 4.2.3

The part contains one system PL L that can be con figur ed to use a nu mbe r of clock in puts and produce an output clock in the range of 1.2 MHz up to the maximum chip frequency, and can be used to run most on-chip functions. The output of the PLL can be monitored through the CLKOUT pin.

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Chapter 4: LPC5410x System configuration (SYSCON)

Fig 3. Clock generation

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Chapter 4: LPC5410x System configuration (SYSCON)

4.5 Register description

All system control block registers reside on word address boundaries. Details of the registers appear in the description of each function. System configuration functions are divided into 3 groups: Main system configuration at base address 0x4000 0000 (see

Table 27 Table 28

All address offsets not shown in the tables are reserved and should not be written to. Remark: The reset value column shows the reset value seen when the boot loader

executes and the flash contains valid user code. During code development, a different value may be seen if a debugger is used to halt execution prior to boot completion.

Table 27. Register overvie w: Main system configuration (base address 0x4000 0000)

Name Access Offset Description Reset value

AHBMATPRIO R/W 0x004 AHB multilayer matrix priority control 0x0 Table 30 SYSTCKCAL R/W 0x014 System tick counter calibration 0x0 Table 31 NMISRC R/W 0x01C NMI Source Select 0x0 Table 32 ASYNCAPBCTRL R/W 0x020 Asynchronous APB Control 0x1 Table 33 SYSRSTSTAT R/W 0x040 System reset status register Note [2] Table 34 PRESETCTRL0 R/W 0x044 Peripheral reset control 0 0x0 Table 35 PRESETCTRL1 R/W 0x048 Peripheral reset control 1 0x0 Table 36 PRESETCTRLSET0 WO 0x04C Set bits in PRESETCTRL0 - Table 37 PRESETCTRLSET1 WO 0x050 Set bits in PRESETCTRL1 - Table 38 PRESETCTRLCLR0 WO 0x054 Clear bits in PRESETCTRL0 - Table 39 PRESETCTRLCLR1 WO 0x058 Clear bits in PRESETCTRL1 - Table 40 PIOPORCAP0 RO 0x05C POR captured value of port 0 Note [3] Table 41 PIOPORCAP1 RO 0x060 POR captured value of port 1 Note [3] Table 42 PIORESCAP0 RO 0x068 Reset captured value of port 0 Note [4] Table 43 PIORESCAP1 RO 0x06C Reset captured value of port 1 Note [4] Table 44 MAINCLKSELA R/W 0x080 Main clock source select A 0x0 Table 45 MAINCLKSELB R/W 0x084 Main clock source select B 0x0 Table 46 ADCCLKSEL R/W 0x08C ADC clock source select 0x0 Table 47 CLKOUTSELA R/W 0x094 CLKOUT clock source select A 0x0 Table 48 CLKOUTSELB R/W 0x098 CLKOUT clock source select B 0x0 Table 49 SYSPLLCLKSEL R/W 0x0A0 PLL clock source select 0x0 Table 50 AHBCLKCTRL0 R/W 0x0C0 A HB Clock control 0 0x18B Table 51 AHBCLKCTRL1 R/W 0x0C4 A HB Clock control 1 0x0 Table 52 AHBCLKCTRLSET0 WO 0x0C8 Set bits in AHBCLKCTRL0 - Table 53 AHBCLKCTRLSET1 WO 0x0CC Set bits in AHBCLKCTRL1 - Table 54 AHBCLKCTRLCLR0 WO 0x0D0 Clear bits in AHBCLKCTRL0 - Table 55 AHBCLKCTRLCLR1 WO 0x0D4 Clear bits in AHBCLKCTRL1 - Table 56 SYSTICKCLKDIV R/W 0x0E0 SYSTICK clock divider 0x0 Table 57 AHBCLKDIV R/W 0x100 System clock divider 0x1 Table 58 ADCCLKDIV R/W 0x108 ADC clock divider 0x0 Table 59

User manual Rev. 2.4 — 13 September 2016 30 of 464

), Asynchronous system configuration at base address 0x4008 0000 (see ), and Other system registers at base addres s 0x4 00 2 C000 (see Table 29).

[1]

Reference

NXP Semiconductors

UM10850

Chapter 4: LPC5410x System configuration (SYSCON)

Table 27. Register overvie w: Main system configuration (base address 0x4000 0000) …continued

Name Access Offset Description Reset value

CLKOUTDIV R/W 0x10C CLKOUT clock divider 0x0 Table 60 FREQMECTRL R/W 0x120 Frequency measure register 0x0 Table 61 FLASHCFG R/W 0x124 Flash wait states configuration 0x001A Table 62 FIFOCTRL R/W 0x148 Serial interface FIFO enables 0 Table 63 IRCCTRL R/W 0x184 IRC oscillator control Note [5] Table 64 RTCOSCCTRL R/W 0x190 RTC oscillator 32 kHz output control 0x1 Table 65 SYSPLLCTRL R/W 0x1B0 PLL control 0x8000 Table 66 SYSPLLSTAT RO 0x1B4 PLL status 0x0 Table 67 SYSPLLNDEC R/W 0x1B8 PLL N decoder 0x0 Table 68 SYSPLLPDEC R/W 0x1BC PLL P decoder 0x0 Table 69 SYSPLLSSCTRL0 R/W 0x1C0 PLL spread spectrum control 0 0x0 Table 70 SYSPLLSSCTRL1 R/W 0x1C4 PLL spread spectrum control 1 0x1000 0000 Table 71 PDRUNCFG R/W 0x210 Power configuration register 0xD80500 Table 72 PDRUNCFGSET WO 0x214 Set bits in PDRUNCFG - Table 73 PDRUNCFGCLR WO 0x218 Clear bits in PDRUNCFG - Table 74 STARTER0 R/W 0x240 Start logic 0 wake-up enable register 0x0 Table 75 STARTER1 R/W 0x244 Start logic 1 wake-up enable register 0x0 Table 76 STARTERSET0 WO 0x248 Set bits in STARTER0 - Table 77 STARTERSET1 WO 0x24C Set bits in STAR TER1 - Table 78 STARTERCLR0 WO 0x250 Clear bits in STARTER0 - Table 79 STARTERCLR1 WO 0x254 Clear bits in STARTER1 - Table 80 CPUCTRL R/W 0x300 CPU Control for multiple processors 0x4D Table 81 CPBOOT R/W 0x304 Coprocessor Boot Address 0 Table 82 CPSTACK R/W 0x308 Coprocessor Stack Address 0 Table 83 CPSTAT RO 0x30C Coprocessor Status 0 Table 84 JTAGIDCODE RO 0x3F4 JTAG ID code register see table Table 85 DEVICE_ID0 RO 0x3F8 Part ID register Note [5] Table 86 DEVICE_ID1 RO 0x3FC Boot ROM and device revision register Note [5] Table 88

[1]

Reference

[1] Reset Value reflects the data stored in defined bits only. Reserved bits assumed to be 0. [2] Depends on the source of the most recent reset. [3] Determined by the voltage levels on device pins upon power-on reset. [4] Determined by the voltage levels on device pins when a reset other than power-on reset occurs. [5] Part dependent.

Table 28. Register overview: Asynchronous system configuration (base address 0x4008 0000)

Name Access Offset Description Reset value

[1]

Reference

ASYNCPRESETCTRL R/W 0x000 Async peripheral reset control 0x0 Table 90 ASYNCPRESETCTRLSET WO 0x004 Set bits in ASYNCPRESETCTRL - Table 91 ASYNCPRESETCTRLCLR WO 0x008 Clear bits in ASYNCPRESETCTRL - Table 92 ASYNCAPBCLKCTRL R/W 0x010 Async peripheral clock control 0x0 Table 93 ASYNCAPBCLKCTRLSET WO 0x014 Set bits in ASYNCAPBCLKCTRL - Table 94

User manual Rev. 2.4 — 13 September 2016 31 of 464

+ 433 hidden pages

NXP Semiconductors LPC5410x User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

1.1 Introduction

Chapter 1: LPC5410x Introductory information

1.2 Features

1.3 Block diagram

1.4 Architectural overview

1.5 ARM Cortex-M4 processor

1.6 ARM Cortex-M0+ processor (present on LPC54102 devices)

Chapter 2: LPC5410x Memory mapping

2.1 General description

2.1.1 Main SRAM

2.1.1.1 SRAM2

2.1.1.2 SRAM usage notes

2.1.2 Memory mapping

2.1.3 AHB multilayer matrix

2.1.4 Memory Protection Unit (MPU)

Chapter 3: LPC5410x Nested Vectored Interrupt Controller (NVIC)

3.1 How to read this chapter

3.2 Features

3.3 General description

3.3.1 Interrupt sources

3.4 Register description

3.4.1 Interrupt Set-Enable Register 0 register

3.4.2 Interrupt Set-Enable Register 1 register

3.4.3 Interrupt Clear-Enable Register 0

3.4.4 Interrupt Clear-Enable Register 1 register

3.4.5 Interrupt Set-Pending Register 0 register

3.4.6 Interrupt Set-Pending Register 1 register

3.4.7 Interrupt Clear-Pending Register 0 register

3.4.8 Interrupt Clear-Pending Register 1 register

3.4.9 Interrupt Active Bit Register 0

3.4.10 Interrupt Active Bit Register 1

3.4.11 Interrupt Priority Register 0

3.4.12 Interrupt Priority Register 1

3.4.13 Interrupt Priority Register 2

3.4.14 Interrupt Priority Register 3

3.4.15 Interrupt Priority Register 4

3.4.16 Interrupt Priority Register 5

3.4.17 Interrupt Priority Register 6

3.4.18 Interrupt Priority Register 7

3.4.19 Interrupt Priority Register 8

3.4.20 Interrupt Priority Register 9

3.4.21 Interrupt Priority Register 10

3.4.22 Software Trigger Interrupt Register

4.1 Features

Chapter 4: LPC5410x System configuration (SYSCON)

4.2 Basic configuration

4.2.1 Set up the PLL

4.2.2 Configure the main clock and system clock

4.2.3 Measure the frequency of a clock signal

4.3 Pin description

4.4 General description

4.4.1 Clock generation

4.5 Register description