NXP Semiconductors LPC2917, LPC2919 User Manual
1. Introduction
1.1 About this document
1.2 Intended audience
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LPC2917/19
ARM9 microcontroller with CAN and LIN
Rev. 1.01 — 15 November 2007 Preliminary data sheet
This document lists detailed information about the LPC2917/19 device. It focuses on
factual information like pinning, characteristics etc. Short descriptions are used to outline
the concept of the features and functions. More details and background on developing
applications for this device are given in the LPC2917/19 User Manual (see Ref. 1
explicit references are made to the User Manual.
This document is written for engineers evaluating and/or developing systems, hardand/or software for the LPC2917/19. Some basic knowledge of ARM processors and
architecture and ARM968E-S in particular is assumed (see Ref. 2
).
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2. General description
2.1 Architectural overview
The LPC2917/19 consists of:
• An ARM968E-S processor with real-time emulation support
• An AMBA multi-layer Advanced High-performance Bus (AHB) for interfacing to the
on-chip memory controllers
• Two DTL buses (a universal NXP interface) for interfacing to the interrupt controller
and the Power, Clock and Reset Control cluster (also called subsystem)
• Three VLSI Peripheral Buses (VPB - a compatible superset of ARM's AMBA
advanced peripheral bus) for connection to on-chip peripherals clu stered in
subsystems.
The LPC2917/19 configures the ARM968E-S processor in little-endian byte order. All
peripherals run at their own clock frequency to optimize the total system power
consumption. The AHB2VPB bridge used in the subsystems contains a write-ahead buffer
one transaction deep. This implies that when the ARM968E-S issues a buffered write
action to a register located on the VPB side of the bridge, it continues even though the
actual write may not yet have taken place. Completion of a second write to the same
subsystem will not be executed until the first write is finished.
NXP Semiconductors
2.2 ARM968E-S processor
The ARM968E-S is a general purpose 32-bit RISC processor, which offers high
performance and very low power consumption. The ARM architecture is based on
Reduced Instruction Set Computer (RISC) principles, and the instruction set and related
decode mechanism are much simpler than those of micro-programmed Complex
Instruction Set Computers (CISC). This simplicity results in a high instruction throughput
and impressive real-time interrupt respon se from a sm all an d co st- effective contr olle r
core.
Amongst the most compelling features of the ARM968E-S are:
• Separate directly connected instruction and data Tightly Coupled Memory (TCM)
• Write buffers for the AHB and TCM buses
• Enhanced 16 x 32 multiplier capable of single-cycle MAC operations and 16-bit fixed-
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ARM9 microcontroller with CAN and LIN
interfaces
point DSP instructions to accelerate signal-processing algorithms and applications.
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Pipeline techniques are employed so that all part s of the pro cessing and memory systems
can operate continuously. The ARM968E-S is based on the ARMv5TE five-stage pipeline
architecture. Typically, in a three-stage pipeline architecture, while one instruction is being
executed its successor is being decoded and a third instruction is being fetched from
memory. In the five-stage pipeline additional stages are added for memory access and
write-back cycles.
The ARM968E-S processor also employs a unique architectural strategy known as
THUMB, which makes it ideally suited to high-volume applications with memory
restrictions or to applications where code density is an issue.
The key idea behind THUMB is that of a super-reduced instruction set. Essentially, the
ARM968E-S processor has two instruction sets:
• Standard 32-bit ARMv5TE set
• 16-bit THUMB set
The THUMB set's 16-bit instruction length allows it to approach twice the density of
standard ARM code while retaining most of the ARM's performance advantage over a
traditional 16-bit controller using 16-bit registers. This is possible because THUMB code
operates on the same 32-bit register set as ARM code.
THUMB code can provide up to 65 % of the code size of ARM, and 160 % of the
performance of an equivalent ARM controller connected to a 16-bit memory system.
The ARM968E-S processor is described in detail in the ARM968E-S data sheet Ref. 2
.
2.3 On-chip flash memory system
The LPC2917/19 includes a 512 kB or 768 kB flash memory system. This memory can be
used for both code and data storage. Programming of the flash memory can be
accomplished in several ways. It may be programmed in-system via a serial port; e.g.
CAN.
LPC2917_19_1 © NXP B.V. 2007. All rights reserved.
Preliminary data sheet Rev. 1.01 — 15 November 2007 2 of 68
NXP Semiconductors
2.4 On-chip static RAM
In addition to the two 16 kB TCMs the LPC2917/19 includes two static RAM memories:
one of 32 kB and one of 16 kB. Both may be used for code and/or data storage. Each
internal SRAM has its own controller, so both me mo r ies ca n be acce ssed simultaneously
from different AHB system bus layers.
3. Features
3.1 General
ARM968E-S processor at 80 MHz maximum
Multi-layer AHB system bus at 80 MHz with three separate layers
On-chip memory:
Two-channel CAN controller supporting Full-CAN and extensive message filtering
Two LIN master controllers with full hardware support for LIN communication
Two 550 UARTs with 16-byte Tx and Rx FIFO depths
Three full-duplex Q-SPIs with four slave-select lines; 16 bits wide; 8 locations deep; Tx
Four 32-bit timers each containing four capture-and-compare registers linked to I/Os
32 - bit wa tch d og with tim er cha nge pr ot ection, running on safe clock.
Up to 108 general-purpose I/O pins with programmable pull-up, pull-down or bus
Vectored Interrupt Controller (VIC) with 16 priority levels
Two 8-channel 10-bit ADCs provide a total of up to 16 analog inputs, with conversion
Up to 24 level-sensitive external interrupt pins, including CAN and LIN wake- up
External Static Memory Controller (SMC) with eight memory banks; up to 32-bit data
Processor wake-up from power-down via external interrupt pins; CAN or LIN activity
Flexible Reset Generator Unit (RGU) able to control resets of individual modules
Flexible Clock-Generation Unit (CGU) able to control clock frequency of individual
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ARM9 microcontroller with CAN and LIN
Two Tightly Coupled Memories (TCM), 16 kB Instruction (ITCM), 16 kB Data TCM
(DTCM)
Two separate internal Static RAM (SRAM) instances; 32 kB SRAM and 16 kB
SRAM
Up to 768 kB flash-program memory
FIFO and Rx FIFO
keeper
times as low as 2.44 μs per channel. Each channel provides a compare function to
minimize interrupts
features
bus; up to 24-bit address bus
modules
On-chip very low-power ring oscillator; fixed frequency of 0.4 MHz; always on to
provide a Safe_Clock source for system monitoring
On-chip crystal oscillator with operating range from 10 MHz to 50 MHz - max. PLL
input 15 MHz
On-chip PLL allows CPU operation up to a maximum CPU rate of 80 MHz
Generation of up to 10 base clocks
Seven fractional dividers
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Preliminary data sheet Rev. 1.01 — 15 November 2007 3 of 68
NXP Semiconductors
Highly configurable system Power Management Unit (PMU),
clock control of individual modules
allows minimization of system operating power consumption in any configuration
Standard ARM test and debug interface with real-time in-circuit emulator
Boundary-scan test supported
Du al po we r sup p ly:
CPU operating voltage: 1.8 V ± 5%
I/O operating voltage: 2.7 V to 3.6 V; inputs tolerant up to 5.5 V
14 4 -p i n LQ F P package
−40 °C to 85 °C ambient operating temperature range
4. Ordering information
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Table 1. Ordering information
Type number Package
LPC2917FBD144 LQFP144 plastic low profile quad flat package; 144 leads; body 20 × 20 × 1.4 mm, pin
LPC2919FBD144 LQFP144 plastic low profile quad flat package; 144 leads; body 20 × 20 × 1.4 mm, pin
Name Description Version
pitch 0.5 mm
pitch 0.5 mm
4.1 Ordering options
Table 2. Part options
Type number Flash memory
LPC2917FBD144 512 80 (incl TCMs) 32-bit 2 LQFP144
LPC2919FBD144 768 80 (incl TCMs) 32-bit 2 LQFP144
RAM (kB) SMC LIN 2.0 Package
(kB)
SOT486-1
SOT486-1
LPC2917_19_1 © NXP B.V. 2007. All rights reserved.
Preliminary data sheet Rev. 1.01 — 15 November 2007 4 of 68
NXP Semiconductors
IEEE 1149.1 JTAG TEST and
DEBUG INTERFACE
LPC2917/19
DTCM
16 Kb
ITCM
16 Kb
ARM968E-S
m
s
s
s
s
s
s
s
s
s
Multi-layer AHB
system bus
m = master port
s = slave port
External Static Memory
Controller (SMC)
Embedded
SRAM Memory 32 Kb
SRAM Controller #0
Embedded
FLASH Memory
512/768 Kb
FLASH Memory Controller (FMC)
Embedded
SRAM Memory 16 Kb
SRAM Controller #1
GLOBAL ACCEPTANCE
FILTER
2 Kbyte Static RAM
LIN MASTER 0/1
CAN Controller
0, 1
Vectored Interrupt
Controller (VIC)
AHB2VPB
Bridge
AHB2DTL
Bridge
Modulation and Sampling
Control Subsystem
PWM 0, 1, 2, 3
ADC 1, 2
Timer 0, 1 (MTMR)
AHB2VPB
Bridge
Power Clock Reset
Control Subsystem
Power Management Unit (PMU)
Reset Generation Unit (RGU)
Clock Generation Unit (CGU)
AHB2DTL
Bridge
s
General Subsystem
Event Router (ER)
System Control Unit (SCU)
Chip Feature ID (CFID)
AHB2VPB
Bridge
Peripheral Subsystem
General Purpose IO (GPIO)
0, 1, 2, 3
Timer (TMR)
0, 1, 2, 3
Watchdog Timer (WDT)
UART 0, 1
AHB2VPB
Bridge
SPI 0, 1, 2
s
5. Block diagram
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Fig 1. LPC2917/19 block diagram
LPC2917_19_1 © NXP B.V. 2007. All rights reserved.
Preliminary data sheet Rev. 1.01 — 15 November 2007 5 of 68
NXP Semiconductors
LPC2917FBD144
LPC2919FBD144
108
37
72
144
109
73
1
36
144PINS
6. Pinning information
6.1 Pinning
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Fig 2. Pin configuration for SOT486-1 (LQFP144)
6.2 Pin description
6.2.1 General description
The LPC2917/19 has up to four ports: two of 32 pins each, one of 28 pins and one of 16
pins. The pin to which each function is assigned is controlled by the SFSP registers in the
SCU. The functions combined on each port pin are shown in the pin description tables in
this section.
6.2.2 LQFP144 pin assignment
Table 3. LQFP144 pin assignment
Symbol Pin Description
TDO 1 IEEE 11 49.1 test data out
P2.21 2 GPIO 2, pin 21 - PWM2 CAP1 EXTBUS D19
P0.24 3 GPIO 0, pin 24 UART1 TxD CAN1 TxD SPI2 SCS0
P0.25 4 GPIO 0, pin 25 UART1 RxD CAN1 RxD SPI2 SDO
P0.26 5 GPIO 0, pin 26 - - SPI2 SDI
P0.27 6 GPIO 0, pin 27 - - SPI2 SCK
P0.28 7 GPIO 0, pin 28 - TIMER0 CAP0 TIMER0 MAT0
P0.29 8 GPIO 0, pin 29 - TIMER0 CAP1 TIMER0 MAT1
V
DD(IO)
P2.22 10 GPIO 2, pin 22 - PWM2 CAP2 EXTBUS D20
P2.23 11 GPIO 2, pin 23 - PWM3 CAP0 EXTBUS D21
P3.6 12 GPIO 3, pin 6 SPI0 SCS3 PWM1 MAT0 LIN1 TxD
P3.7 13 GPIO 3, pin 7 SPI2 SCS1 PWM1 MAT1 LIN1 RxD
P0.30 14 GPIO 0, pin 30 - TIMER0 CAP2 TIMER0 MAT2
P0.31 15 GPIO 0, pin 31 - TIMER0 CAP3 TIMER0 MAT3
LPC2917_19_1 © NXP B.V. 2007. All rights reserved.
Preliminary data sheet Rev. 1.01 — 15 November 2007 6 of 68
Function 0 (default) Function 1 Function 2 Function 3
9 3.3 V power supply for I/O
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Table 3. LQFP144 pin assignment
Symbol Pin Description
Function 0 (default) Function 1 Function 2 Function 3
P2.24 16 GPIO 2, pin 24 - PWM3 CAP1 EXTBUS D22
P2.25 17 GPIO 2, pin 25 - PWM3 CAP2 EXTBUS D23
V
DD(CORE)
V
SS(CORE)
P1.31 20 GPIO 1, pin 31 TIMER0 CAP1 TIMER0 MAT1 EXTINT5
V
SS(IO)
P1.30 22 GPIO 1, pin 30 TIMER0 CAP0 TIMER0 MAT0 EXTINT4
P3.8 23 GPIO 3, pin 8 SPI2 SCS0 PWM1 MAT2 P3.9 24 GPIO 3, pin 9 SPI2 SDO PWM1 MAT3 P1.29 25 GPIO 1, pin 29 TIMER1 CAP0, EXT
P1.28 26 GPIO 1, pin 28 TIMER1 CAP1, ADC1
P2.26 27 GPIO 2, pin 26 TIMER0 CAP2 TIMER0 MAT2 EXTINT6
P2.27 28 GPIO 2, pin 27 TIMER0 CAP3 TIMER0 MAT3 EXTINT7
P1.27 29 GPIO 1, pin 27 TIMER1 CAP2, ADC2
P1.26 30 GPIO 1, pin 26 PWM2 MAT0 PWM TRAP3 PWM3 MAT2
V
DD(IO)
P1.25 32 GPIO 1, pin 25 PWM1 MAT0 - PWM3 MAT1
P1.24 33 GPIO 1, pin 24 PWM0 MAT0 - PWM3 MAT0
P1.23 34 GPIO 1, pin 23 UART0 RxD - EXTBUS CS5
P1.22 35 GPIO 1, pin 22 UART0 TxD - EXTBUS CS4
TMS 36 IEEE 1149.1 test mode select, pulled up internally.
TCK 37 IEEE 1149.1 test clock
P1.21 38 GPIO 1, pin 21 TIMER3 CAP3 TIMER1 CAP3,
P1.20 39 GPIO 1, pin 20 TIMER3 CAP2 SPI0 SCS1 EXTBUS D6
P1.19 40 GPIO 1, pin 19 TIMER3 CAP1 SPI0 SCS2 EXTBUS D5
P1.18 41 GPIO 1, pin 18 TIMER3 CAP0 SPI0 SDO EXTBUS D4
P1.17 42 GPIO 1, pin 17 TIMER2 CAP3 SPI0 SDI EXTBUS D3
V
SS(IO)
P1.16 44 GPIO 1, pin 16 TIMER2 CAP2 SPI0 SCK EXTBUS D2
P2.0 45 GPIO 2, pin 0 TIMER2 MAT0 PWM TRAP3 EXTBUS D8
P2.1 46 GPIO 2, pin 1 TIMER2 MAT1 PWM TRAP2 EXTBUS D9
P3.10 47 GPIO 3, pin 10 SPI2 SDI PWM1 MAT4 P3.11 48 GPIO 3, pin 11 SPI2 SCK PWM1 MAT5 P1.15 49 GPIO 1, pin 15 TIMER2 CAP1 SPI0 SCS0 EXTBUS D1
P1.14 50 GPIO 1, pin 14 TIMER2 CAP0 SPI0 SCS3 EXTBUS D0
P1.13 51 GPIO 1, pin 13 EXTINT3 - EXTBUS WEN
P1.12 52 GPIO 1, pin 12 EXTINT2 - EXTBUS OEN
18 1.8 V power supply for digital core
19 ground for digital core
21 ground for I/O
31 3.3 V power supply for I/O
43 ground for I/O
…continued
PWM TRAP0 PWM3 MAT5
START
PWM TRAP1 PWM3 MAT4
EXT START
PWM TRAP2 PWM3 MAT3
EXT START
EXTBUS D7
MSCSS PAUSE
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LPC2917_19_1 © NXP B.V. 2007. All rights reserved.
Preliminary data sheet Rev. 1.01 — 15 November 2007 7 of 68
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Table 3. LQFP144 pin assignment
Symbol Pin Description
Function 0 (default) Function 1 Function 2 Function 3
V
DD(IO)
P2.2 54 GPIO 2, pin 2 TIMER2 MAT2 PWM TRAP1 EXTBUS D10
P2.3 55 GPIO 2, pin 3 TIMER2 MAT3 PWM TRAP0 EXTBUS D11
P1.11 56 GPIO 1, pin 11 SPI1 SCK - EXTBUS CS3
P1.10 57 GPIO 1, pin 10 SPI1 SDI - EXTBUS CS2
P3.12 58 GPIO 3, pin 12 SPI1 SCS0 EXTINT4 V
SS(CORE)
V
DD(CORE)
P3.13 61 GPIO 3, pin 13 SPI1 SDO EXTINT5 P2.4 62 GPIO 2, pin 4 TIMER1 MAT0 EXTINT0 EXTBUS D12
P2.5 63 GPIO 2, pin 5 TIMER1 MAT1 EXTINT1 EXTBUS D13
P1.9 64 GPIO 1, pin 9 SPI1 SDO LIN1 RxD EXTBUS CS1
V
SS(IO)
P1.8 66 GPIO 1, pin 8 SPI1 SCS0 LIN1 TxD EXTBUS CS0
P1.7 67 GPIO 1, pin 7 SPI1 SCS3 UART1 RxD EXTBUS A7
P1.6 68 GPIO 1, pin 6 SPI1 SCS2 UART1 TxD EXTBUS A6
P2.6 69 GPIO 2, pin 6 TIMER1 MAT2 EXTINT2 EXTBUS D14
P1.5 70 GPIO 1, pin 5 SPI1 SCS1 PWM3 MAT5 EXTBUS A5
P1.4 71 GPIO 1, pin 4 SPI2 SCS2 PWM3 MAT4 EXTBUS A4
TRSTN 72 I EEE 1149.1 test reset NOT; active LOW; pulled up internally
RSTN 73 asynchronous device reset; active LOW; pulled up internally
V
SS(OSC)
XOUT_OSC 75 crystal out for oscillator
XIN_OSC 76 crystal in for oscillator
V
DD(OSC)
V
SS(PLL)
P2.7 79 GPIO 2, pin 7 TIMER1 MAT3 EXTINT3 EXTBUS D15
P3.14 80 GPIO 3, pin 14 SPI1 SDI EXTINT6 CAN0 TxD
P3.15 81 GPIO 3, pin 15 SPI1 SCK EXTINT7 CAN0 RxD
V
DD(IO)
P2.8 83 GPIO 2, pin 8 - PWM0 MAT0 SPI0 SCS2
P2.9 84 GPIO 2, pin 9 - PWM0 MAT1 SPI0 SCS1
P1.3 85 GPIO 1, pin 3 SPI2 SCS1 PWM3 MAT3 EXTBUS A3
P1.2 86 GPIO 1, pin 2 SPI2 SCS3 PWM3 MAT2 EXTBUS A2
P1.1 87 GPIO 1, pin 1 EXTINT1 PWM3 MAT1 EXTBUS A1
V
SS(CORE)
V
DD(CORE)
P1.0 90 GPIO 1, pin 0 EXTINT0 PWM3 MAT0 EXTBUS A0
P2.10 91 GPIO 2, pin 10 - PWM0 MAT2 SPI0 SCS0
P2.11 92 GPIO 2, pin 11 - PWM0 MAT3 SPI0 SCK
53 3.3 V power supply for I/O
59 ground for digital core
60 1.8 V power supply for digital core
65 ground for I/O
74 ground for oscillator
77 1.8 V supply for oscillator
78 ground for PLL
82 3.3 V power supply for I/O
88 ground for digital core
89 1.8 V power supply for digital core
…continued
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LPC2917_19_1 © NXP B.V. 2007. All rights reserved.
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Table 3. LQFP144 pin assignment
Symbol Pin Description
Function 0 (default) Function 1 Function 2 Function 3
P0.0 93 GPIO 0, pin 0 - CAN0 TxD EXTBUS D24
V
SS(IO)
P0.1 95 GPIO 0, pin 1 - CAN0 RxD EXTBUS D25
P0.2 96 GPIO 0, pin 2 - PWM0 MAT0 EXTBUS D26
P0.3 97 GPIO 0, pin 3 - PWM0 MAT1 EXTBUS D27
P3.0 98 GPIO 3, pin 0 - PWM2 MAT0 EXTBUS CS6
P3.1 99 GPIO 3, pin 1 - PWM2 MAT1 EXTBUS CS7
P2.12 100 GPIO 2, pin 12 - PWM0 MAT4 SPI0 SDI
P2.13 101 GPIO 2, pin 13 - PWM0 MAT5 SPI0 SDO
P0.4 102 GPIO 0, pin 4 - PWM0 MAT2 EXTBUS D28
P0.5 103 GPIO 0, pin 5 - PWM0 MAT3 EXTBUS D29
V
DD(IO)
P0.6 105 GPIO 0, pin 6 - PWM0 MAT4 EXTBUS D30
P0.7 106 GPIO 0, pin 7 - PWM0 MAT5 EXTBUS D31
V
DD(A3V3)
JTAGSEL 108 TAP controller select input; LOW-level selects the ARM debug mode; HIGH-level selects
NC 109 VREFP 1 10 HIGH reference for AD Converters
VREFN 111 LOW reference for AD Converters
P0.8 112 GPIO 0, pin 8 ADC1 IN0 LIN0 TxD EXTBUS A20
P0.9 113 GPIO 0, pin 9 ADC1 IN1 LIN0 RxD EXTBUS A21
P0.10 114 GPIO 0, pin 10 ADC1 IN2 PWM1 MAT0 EXTBUS A8
P0.11 115 GPIO 0, pin 11 ADC1 IN3 PWM1 MAT1 EXTBUS A9
P2.14 1 16 GPIO 2, pin 14 - PWM0 CAP0 EXTBUS BLS0
P2.15 1 17 GPIO 2, pin 15 - PWM0 CAP1 EXTBUS BLS1
P3.2 118 GPIO 3, pin 2 TIMER3 MAT0 PWM2 MAT2 V
SS(IO)
P3.3 120 GPIO 3, pin 3 TIMER3 MAT1 PWM2 MAT3 P0.12 121 GPIO 0, pin 12 ADC1 IN4 PWM1 MAT2 EXTBUS A10
P0.13 122 GPIO 0, pin 13 ADC1 IN5 PWM1 MAT3 EXTBUS A11
P0.14 123 GPIO 0, pin 14 ADC1 IN6 PWM1 MAT4 EXTBUS A12
P0.15 124 GPIO 0, pin 15 ADC1 IN7 PWM1 MAT5 EXTBUS A13
P0.16 125 GPIO 0, pin 16 ADC2 IN0 UART0 TXD EXTBUS A22
P0.17 126 GPIO 0, pin 17 ADC2 IN1 UART0 RXD EXTBUS A23
V
DD(CORE)
V
SS(CORE)
P2.16 129 GPIO 2, pin 16 UART1 TxD PWM0 CAP2 EXTBUS BLS2
P2.17 130 GPIO 2, pin 17 UART1 RxD PWM1 CAP0 EXTBUS BLS3
V
DD(IO)
94 ground for I/O
104 3.3 V power supply for I/O
107 3.3 V power supply for AD Converters
boundary scan and flash programming; pulled up internally
1 19 ground for I/O
127 1.8 V power supply for digital core
128 ground for digital core
131 3.3 V power supply for I/O
…continued
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Table 3. LQFP144 pin assignment
Symbol Pin Description
Function 0 (default) Function 1 Function 2 Function 3
P0.18 132 GPIO 0, pin 18 ADC2 IN2 PWM2 MAT0 EXTBUS A14
P0.19 133 GPIO 0, pin 19 ADC2 IN3 PWM2 MAT1 EXTBUS A15
P3.4 134 GPIO 3, pin 4 TIMER3 MAT2 PWM2 MAT4 CAN1 TxD
P3.5 135 GPIO 3, pin 5 TIMER3 MAT3 PWM2 MAT5 CAN1 RxD
P2.18 136 GPIO 2, pin 18 - PWM1 CAP1 EXTBUS D16
P2.19 137 GPIO 2, pin 19 - PWM1 CAP2 EXTBUS D17
P0.20 138 GPIO 0, pin 20 ADC2 IN4 PWM2 MAT2 EXTBUS A16
P0.21 139 GPIO 0, pin 21 ADC2 IN5 PWM2 MAT3 EXTBUS A17
P0.22 140 GPIO 0, pin 22 ADC2 IN6 PWM2 MAT4 EXTBUS A18
V
SS(IO)
P0.23 142 GPIO 0, pin 23 ADC2 IN7 PWM2 MAT5 EXTBUS A19
P2.20 143 GPIO 2, pin 20 - PWM2 CAP0 EXTBUS D18
TDI 144 IEEE 1149.1 data in, pulled up internally.
141 ground for I/O
…continued
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7. Functional description
7.1 Reset, debug, test and power description
7.1.1 Reset and power-up behavior
The LPC2917/19 contains external reset input and internal power-up reset circuits. This
ensures that a reset is extended internally until the oscillators and flash have reached a
stable state. See Section 11
Section 12
the reset pin.
Table 4. Reset pin
Symbol Direction Description
RSTN in external reset input, active LOW; pulled up internally
At activation of the RSTN pin the JTAGSEL pin is sensed as logic LOW. If this is the case
the LPC2917/19 is assumed to be connected to debug hardware, and internal circuits
re-program the source for the BASE_SYS_CLK to be the crystal oscillator instead of the
Low-Power Ring Oscillator (LP_OSC). This is required because the clock rate when
running at LP_OSC speed is too low for the external debugging environment.
7.1.2 Reset strategy
The LPC2917/19 contains a central module, the Reset Generator Unit (RGU) in the
Power, Clock and Reset Control Subsystem (PCRSS), which controls all internal reset
signals towards the peripheral modules. The RGU provides individua l reset control as well
as the monitoring functions needed for tracing a reset back to source.
for characteristics of the several start-up and initialization times. Table 4 shows
for trip levels of the internal power-up reset circuit1. See
1. Only for 1.8 V power sources
LPC2917_19_1 © NXP B.V. 2007. All rights reserved.
Preliminary data sheet Rev. 1.01 — 15 November 2007 10 of 68
NXP Semiconductors
7.1.3 IEEE 1149.1 interface pins (JTAG boundary-scan test)
The LPC2917/19 contains boundary-scan test logic according to IEEE 1149.1, also
referred to in this document as Joint Test Action Group (JTAG). The boundary-scan test
pins can be used to connect a debugger probe for the embedded ARM processor. Pin
JTAGSEL selects between boundary-scan mode and debug mode. Table 5
boundary- scan test pins.
Table 5. IEEE 1149.1 boundary-scan test and debug interfa ce
Symbol Description
JTAGSEL TAP controller select input. LOW level selects ARM debug mode and HIGH level
TRSTN test reset input; pulled up internally (active LOW)
TMS test-mode select input; pulled up internally
TDI test data input, pulled up internally
TDO test data output
TCK test clock input
DRAFT
D
RAFT DRAFT DRAFT DRAFT DRAFT D
D
LPC2917/19
RAFT DRA
ARM9 microcontroller with CAN and LIN
F
selects boundary scan and flash programming; pulled up internally
D
RAFT
DR
DRAFT
T DRAFT DRAFT DRAFT DRA
AFT
DRA
DR
AFT
DRAFT
DR
F
T DRAF
shows the
7.1.4 Power supply pins description
Table 6 shows the power supply pins.
Table 6. Power supplies
Symbol Description
V
DD(CORE)
V
SS(CORE)
V
DD(IO)
V
SS(IO)
V
DD(OSC)
V
SS(OSC)
V
DD(A3V3)
V
SS(PLL)
digital core supply 1.8 V
digital core ground (digital core, ADC 1)
I/O pins supply 3.3 V
I/O pins ground
oscillator and PLL supply
oscillator ground
ADC 3.3 V supply
PLL ground
7.2 Clocking strategy
7.2.1 Clock architecture
The LPC2917/19 contains several different internal clock areas. Peripherals like Timers,
SPI, UART, CAN and LIN have their own individual clock sources called Base Clocks. All
base clocks are generated by the Clock Generator Unit (CGU). They may b e unre lated in
frequency and phase and can have different clock sources within the CGU.
The system clock for the CPU and AHB Multilayer Bus infrastructure has its own base
clock. This means most peripherals are clocked independently from the system clock. See
Figure 3
for an overview of the clock areas within the device.
Within each clock area there may be multiple branch clocks, which offers very flexible
control for power-management purposes. All branch clocks are outputs of the Power
Management Unit (PMU) and can be controlled independently. Branch clocks derived
from the same base clock are synchronous in frequency and phase. See Section 8.8
for
more details of clock and power control within the device.
LPC2917_19_1 © NXP B.V. 2007. All rights reserved.
Preliminary data sheet Rev. 1.01 — 15 November 2007 11 of 68
NXP Semiconductors
General Subsystem
Event Router (ER)
System Control Unit (SCU)
Chip Feature ID (CFID)
AHB2VPB
Bridge
s
IEEE 1149.1 JTAG TEST and
DEBUG INTERFACE
LPC2917/19
DTCM
16 Kb
ITCM
16 Kb
ARM968E-S
m
s
s
s
s
s
s
s
s
s
External Static Memory
Controller (SMC)
Embedded
SRAM Memory 32 Kb
SRAM Controller #0
Embedded
FLASH Memory
512 - 768 Kb
FLASH Memory Controller (FMC)
Embedded
SRAM Memory 16 Kb
SRAM Controller #1
GLOBAL ACCEPTANCE
FILTER
2 Kbyte Static RAM
LIN MASTER 0/1
CAN Controller
0, 1
Vectored Interrupt
Controller (VIC)
AHB2VPB
Bridge
AHB2DTL
Bridge
Modulation and Sampling
Control Subsystem
PWM 0, 1, 2, 3
ADC 1, 2
Timer 0, 1 (MTMR)
AHB2VPB
Bridge
Power Clock Reset
Control Subsystem
Power Management Unit (PMU)
Reset Generation Unit (RGU)
Clock Generation Unit (CGU)
AHB2DTL
Bridge
Peripheral Subsystem
General Purpose IO (GPIO)
0, 1, 2, 3
Timer (TMR)
0, 1, 2, 3
Watchdog Timer (WDT)
UART 0, 1
AHB2VPB
Bridge
TMR_CLK
SAFE_CLK
UART_CLK
SPI_CLK
PCR_CLK
IVNSS_CLK
ADC_CLK
MSCSS_CLK
SYS_CLK
SPI 0, 1, 2
s
DRAFT
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LPC2917/19
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T DRAFT DRAFT DRAFT DRA
DR
AFT
DRAFT
DR
F
T DRAF
Fig 3. LPC2917/19 block diagram, overview of clock areas
LPC2917_19_1 © NXP B.V. 2007. All rights reserved.
Preliminary data sheet Rev. 1.01 — 15 November 2007 12 of 68
NXP Semiconductors
7.2.2 Base clock and branch clock relationship
The next table contains an overview of all the base blocks in the LPC2917/19 and their
derived branch clocks. A short description is given of the hardware parts that are clocked
with the individual branch clocks. In relevant cases more detailed information can be
found in the specific subsystem description. Some branch clocks have special protection
since they clock vital system parts of the device and shou ld (for example) not be switched
off. See Section 8.8.6
T able 7. Base clock and branch clock overview
Base clock Branch clock name Parts of the device clocked by
BASE_SAFE_CLK CLK_SAFE Watchdog Timer
BASE_SYS_CLK CLK_SYS_CPU ARM968E-S and TCMs
BASE_PCR_CLK CLK_PCR_SLOW PCRSS, CGU, RGU and PMU
BASE_IVNSS_CLK CLK_IVNSS_VPB VPB side of the IVNSS
DRAFT
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RAFT DRA
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DRAFT
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F
T DRAFT DRAFT DRAFT DRA
for more details of how to control the individual branch clocks.
Remark
this branch clock
[1]
CLK_SYS_SYS AHB Bus infrastructure
CLK_SYS_PCRSS AHB side of bridge in PCRSS
CLK_SYS_FMC Flash-Memory Controller
CLK_SYS_RAM0 Embedded SRAM Controller 0
(32 KByte)
CLK_SYS_RAM1 Embedded SRAM Controller 1
(16 KByte)
CLK_SYS_SMC External Static-Memory
Controller
CLK_SYS_GESS General Subsystem
CLK_SYS_VIC Vectored Interrupt Controller
CLK_SYS_PESS Peripheral Subsystem
CLK_SYS_GPIO0 GPIO bank 0
CLK_SYS_GPIO1 GPIO bank 1
CLK_SYS_GPIO2 GPIO bank 2
CLK_SYS_GPIO3 GPIO bank 3
CLK_SYS_IVNSS_A AHB side of bridge of IVNSS
logic clock
CLK_IVNSS_CANCA CAN controller Acceptance Filter
CLK_IVNSS_CANC0 CAN channel 0
CLK_IVNSS_CANC1 CAN channel 1
CLK_IVNSS_LIN0 LIN channel 0
CLK_IVNSS_LIN1 LIN channel 1
[2] [4]
[1], [3]
AFT
DRA
DR
AFT
DRAFT
DR
F
T DRAF
LPC2917_19_1 © NXP B.V. 2007. All rights reserved.
Preliminary data sheet Rev. 1.01 — 15 November 2007 13 of 68
NXP Semiconductors
T able 7. Base clock and branch clock overview
Base clock Branch clock name Parts of the device clocked by
BASE_MSCSS_CLK CLK_MSCSS_VPB VPB side of the MSCSS
BASE_UART_CLK CLK_UART0 UART 0 interface clock
BASE_SPI_CLK CLK_SPI0 SPI 0 interface clock
BASE_TMR_CLK CLK_TMR0 Timer 0 clock for counter part
BASE_ADC_CLK CLK_ADC1 Control of ADC 1, capture sample
BASE_CLK_TESTSHELL CLK_TESTSHELL_IP
DRAFT
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…continued
this branch clock
CLK_MSCSS_MTMR0 Timer 0 in the MSCSS
CLK_MSCSS_MTMR1 Timer 1 in the MSCSS
CLK_MSCSS_PWM0 PWM 0
CLK_MSCSS_PWM1 PWM 0
CLK_MSCSS_PWM2 PWM 0
CLK_MSCSS_PWM3 PWM 0
CLK_MSCSS_ADC1_VPBVPB side of ADC 1
CLK_MSCSS_ADC2_VPBVPB side of ADC 2
CLK_UART1 UART 1 interface clock
CLK_SPI1 SPI 1 interface clock
CLK_SPI2 SPI 2 interface clock
CLK_TMR1 Timer 1 clock for counter part
CLK_TMR2 Timer 2 clock for counter part
CLK_TMR3 Timer 3 clock for counter part
result
CLK_ADC2 Control of ADC 2, capture sample
result
DR
AFT
DRAFT
DRA
Remark
DR
AFT
DRAFT
DR
F
T DRAF
[1] This clock is always on (cannot be switched off for system safety reasons)
[2] In the peripheral subsystem parts of the Timers, Watchdog Timer, SPI and UART have their own clock
source. See Section 8.4
[3] In the Power Clock and Reset Control subsystem parts of the CGU, RGU PMU have their own clock
source. See Section 8.8
[4] The clock should remain activated w hen system wake-up on timer or UART is required.
for details.
for details.
8. Block description
8.1 Flash memory controller
8.1.1 Overview
The Flash Memory Controller (FMC) interfaces to the embedded flash memory for two
tasks:
• Providing memory data transfer
• Memory configuration via triggering, programming and erasing
LPC2917_19_1 © NXP B.V. 2007. All rights reserved.
Preliminary data sheet Rev. 1.01 — 15 November 2007 14 of 68
NXP Semiconductors
The flash memory has a 128-bit wide data interface and the flash controller offers two
128-bit buffer lines to improve system performance. The flash has to be programmed
initially via JTAG. In-system programming must be supported by the boot loader.
In-application programming is possible. Flash memory contents can be protected by
disabling JTAG access. Suspension of burning or erasing is not supported.
The key features are:
• Programming by CPU via AHB
• Programming by external programmer via JTAG
• JTAG access protection
• Burn-finished and erase-finished interr up t
8.1.2 Description
DRAFT
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LPC2917/19
RAFT DRA
D
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DR
AFT
DRAFT
DRA
DR
AFT
DRAFT
DR
F
T DRAF
After reset flash initialization is started, which takes t
initialization flash access is not possible and AHB transfers to flash are stalled, blocking
the AHB bus.
During flash initialization the index sector is read to identify the status of the JTAG access
protection and sector security. If JTAG access protection is active the flash is not
accessible via JTAG. ARM debug facilities are disabled to protect the flash-memory
contents against unwanted reading out externally. If sector security is active only the
concerned sections are read.
Flash can be read synchronously or asynchronously to the system clock. In synchronous
operation the flash goes into standby after returning the read data. Started reads cannot
be stopped, and speculative reading and dual buff ering are therefore not supported.
With asynchronous reading, transfer of the address to the flash and of read da ta from the
flash is done asynchronously , giving the fastest possib le response time. S t arted reads can
be stopped, so speculative reading and dual buffering are supported.
Buffering is offered because the flash has a 128-bit wide data interface while the AHB
interface has only 32 bits. With buffering a buffer line holds the complete 128-bit flash
word, from which four words can be read. Without buffering every AHB data port read
starts a flash read. A flash read is a slow process compare d to the minimum AHB cycle
time, so with buffering the average read time is reduced. This can improve system
performance.
time, see Section 12. During this
init
With single buffering the most recently read flash word remains availabl e until the next
flash read. When an AHB data-port read transfer requires data from the same flash word
as the previous read transfer , no ne w flash read is done and the read dat a is given without
wait cycles.
When an AHB data-port read transfer requires data from a different flash word to that
involved in the previous read transfer, a new flash read is done and wait states are given
until the new read data is available.
With dual buffering a secondary buffer line is used, the output of the flash being
considered as the primary buffer. On a primary buffer hit data can be copied to the
secondary buffer line, which allows the flash to start a speculative read of the next flash
word.
LPC2917_19_1 © NXP B.V. 2007. All rights reserved.
Preliminary data sheet Rev. 1.01 — 15 November 2007 15 of 68
NXP Semiconductors
Both buffer lines are invalidated after:
• Initialization
• Configuration-register access
• Data-latch reading
• Index-sector reading
DRAFT
ARM9 microcontroller with CAN and LIN
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LPC2917/19
RAFT DRA
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DRAFT
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DRAFT
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The modes of operation are listed in Table 8
Table 8. Flash read modes
Synchronous timing
No buffer line for single (non-linear) reads; one flash-word read per word read
Single buffer line default mo de of operation; most recently read flash word is kept until
another flash word is required
Asynchronous timing
No buffer line one flash-word read per word read
Single buffer line most recently read flash word is kept until another flash word is
required
Dual buffer line, single
speculative
Dual buffer line, always
speculative
on a buffer miss a flash read is done, followed by at most one
speculative read; optimized for execution of code with small loops
(less than eight words) from flash
most recently used flash word is copied into second buffer line; next
flash-word read is started; highest performance for linear reads
.
8.1.3 Flash memory controller pin description
The flash memory controller has no extern al pins. However, the flash can be programmed
via the JTAG pins, see Section 7.1.3
.
8.1.4 Flash memory controller clock description
The flash memory controller is clocked by CLK_SYS_FMC, see Section 7.2.2.
8.1.5 Flash layout
The ARM processor can program the flash for ISP (In-System Programming) a nd IAP (InApplication Programming). Note that the flash always has to be programmed by ‘flash
words’ of 128 bits (four 32-bit AHB bus words, hence 16 bytes).
The flash memory is organized into eight ‘small’ sectors of 8 kB each and up to 11 ‘large’
sectors of 64 kB each. The number of large sectors depends on the device type. A sector
must be erased before data can be written to it. The flash memory also has sector-wise
protection. Writing occurs per page which consists of 4096 bits (32 flash words). A small
sector contains 16 pages; a large sector contains 128 pages.
Table 9
Table 9. Flas h sector overview
Sector number Sector size (kB) Sector base address
0 8 0000 0000h
1 8 0000 2000h
2 8 0000 4000h
LPC2917_19_1 © NXP B.V. 2007. All rights reserved.
Preliminary data sheet Rev. 1.01 — 15 November 2007 16 of 68
gives an overview of the flash-sector base addresses.
NXP Semiconductors
WST
t
acc clk()
t
t
tclk sys()
------------------
> 1–
WST
t
acc addr()
t
tclk sys()
--------------------- -
> 1–
Table 9. Flas h sector overview
Sector number Sector size (kB) Sector base address
3 8 0000 6000h
4 8 0000 8000h
5 8 0000 A000h
6 8 0000 C000h
7 8 0000 E000h
8 64 0001 0000h
9 64 0002 0000h
10 64 0003 0000h
11 64 0004 0000h
12 64 0005 0000h
13 64 0006 0000h
14 64 0007 0000h
[1]
15
[1]
16
[1]
17
[1]
18
ARM9 microcontroller with CAN and LIN
…continued
64 0008 0000h
64 0009 0000h
64 000A 0000h
64 000B 0000h
DRAFT
D
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LPC2917/19
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DRAFT
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DRAFT
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[1] Availability of sector 15 to sector 18 depends on device type, see Section 4 “Ordering information”.
The index sector is a special sector in which the JTAG access protection and sector
security are located. The address space becomes visible by setting the FS_ISS bit and
overlaps the regular flash sector’s address space.
Note that the index sector cannot be erased, and that acce ss to it ha s to be pe rformed via
code outside the flash.
8.1.6 Flash bridge wait-states
To eliminate the delay associated with synchronizing flash-read data, a predefined
number of wait-states must be programmed. These depend on flash-memory response
time and system clock period. The minimum wait-states value can be calculated with the
following formulas:
Synchronous reading:
Asynchronous reading:
LPC2917_19_1 © NXP B.V. 2007. All rights reserved.
Preliminary data sheet Rev. 1.01 — 15 November 2007 17 of 68
NXP Semiconductors
Remark: If the programmed number of wait-states is more than three, flash-data reading
cannot be performed at full speed (i.e. with zero wait-states at the AHB bus) if speculative
reading is active.
8.2 External static memory controller
8.2.1 Overview
The LPC2917/19 contains an external Static Memory Controller (SMC) which provides an
interface for external (off-chip) memory devices.
Key features are:
• Supports static memory-mapped devices including RAM, ROM, flash, burst ROM and
• Asynchronous page-mode read operation in non-clocked memory subsystems
• Asynchronous burst-mode read access to burst-mode ROM devices
• Independent configuration for up to eight banks, each up to 16 MB
• Programmable bus-turnaround (idle) cycles (one to 16)
• Programmable read and write wait states (up to 32), for static RAM devices
• Programmable initial and subsequent burst-read wait state for burst-ROM devices
• Programmable write protection
• Programmable burst-mode operation
• Programmable external data width: 8-bit, 16-bit or 32-bit
• Programmable read-byte lane enable control
external I/O devices
DRAFT
ARM9 microcontroller with CAN and LIN
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LPC2917/19
RAFT DRA
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T DRAFT DRAFT DRAFT DRA
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AFT
DRAFT
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DR
AFT
DRAFT
DR
F
T DRAF
8.2.2 Description
The SMC simultaneously supports up to eigh t independently configurable memory banks.
Each memory bank can be 8, 16 or 32 bits wide and is capable of supporting SRAM,
ROM, burst-ROM memory or external I/O devices.
A separate chip-select output is available for each bank. The chip-select lines are
configurable to be active HIGH or LOW. Memory-bank selection is controlled by memory
addressing. Table 10
memory base addresses, chip selects and bank internal addresses.
Table 10. External memory-bank address bit description
32 bit
System
Address Bit
field
31 to 29 BA[2:0] external static-memory base address (three most significant bits);
28 to 26 CS[2:0] chip-select address space for eight memory banks; see
25 and 24 - always ’00’; other values are ’mirrors’ of the 16 MByte bank address
23 to 0 A[23:0] 16-MByte memory banks address space
shows how the 32-bit system address is mapped to the external bus
Symbol Description
the base address can be found in the memory map; see Ref. 1
field contains ’010’ when addressing an external memory bank.
. This
[1]
LPC2917_19_1 © NXP B.V. 2007. All rights reserved.
Preliminary data sheet Rev. 1.01 — 15 November 2007 18 of 68
NXP Semiconductors
Table 11. External static-memory controller banks
CS[2:0] Bank
000 bank 0
001 bank 1
010 bank 2
011 bank 3
100 bank 4
101 bank 5
110 bank 6
111 bank 7
8.2.3 External static-memory controller pin description
The external static-memory controller module in the LPC2917/19 has the following pins,
which are combined with other functions on the port pins of the LPC2917/19. Table 12
shows the external memory controller pins.
Table 12. External memory controller pins
Symbol Direction Description
EXTBUS CSx out memory-bank x select, x runs from 0 to 7
EXTBUS BLSy out byte-lane select input y, y runs from 0 to 3
EXTBUS WE_N out write enable (active LOW)
EXTBUS OE_N out output enable (active LOW)
EXTBUS A[23:0] out address bus
EXTBUS D[31:0] in/out data bus
DRAFT
ARM9 microcontroller with CAN and LIN
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LPC2917/19
RAFT DRA
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DRAFT
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DRAFT
DR
F
T DRAF
8.2.4 External static-memory controller clock description
The External Static-Memory Controller is clocked by CLK_SYS_SMC, see Section 7.2.2.
8.2.5 External memory timing diagrams
A timing diagram for reading from external memory is shown in Figure 4. The relationship
between the wait-state settings is indicated with arrows.
LPC2917_19_1 © NXP B.V. 2007. All rights reserved.
Preliminary data sheet Rev. 1.01 — 15 November 2007 19 of 68
NXP Semiconductors
OE_N
CLK(SYS)
CS
ADDR
DATA
WSTOEN
WST1
CLK(SYS)
CS
ADDR
DATA
WSTWEN
WST2
WE_N / BLS
DRAFT
ARM9 microcontroller with CAN and LIN
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RAFT DRAFT DRAFT DRAFT DRAFT D
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LPC2917/19
RAFT DRA
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AFT
DRAFT
DRA
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DRAFT
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WSTOEN=3, WST1=7
Fig 4. Reading from external memory
A timing diagram for writing to external memory is shown In Figure 5. The relationship
between wait-state settings is indicated with arrows.
WSTWEN=3, WST2=7
Fig 5. Writing to external memory
LPC2917_19_1 © NXP B.V. 2007. All rights reserved.
Preliminary data sheet Rev. 1.01 — 15 November 2007 20 of 68
NXP Semiconductors
OE_N
CLK(SYS)
CS
ADDR
DATA
WSTOEN
WST1
WSTWEN
WST2
WE_N / BLS
IDCY
Usage of the idle/turn-around time (IDCY) is de mon str ated In Figure 6. Extra wait states
are added between a read and a write cycle in the same external memory device.
DRAFT
ARM9 microcontroller with CAN and LIN
D
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LPC2917/19
RAFT DRA
D
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AFT
DRAFT
DRA
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DR
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DRAFT
DR
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WSTOEN=5, WSTWEN=5, WST1=7, WST2=6, IDCY=5
Fig 6. Reading/writing external memory
Address pins on the device are shared with other functions. When connecting external
memories, check that the I/O pin is programmed for the correct function. Control of these
settings is handled by the SCU.
LPC2917_19_1 © NXP B.V. 2007. All rights reserved.
Preliminary data sheet Rev. 1.01 — 15 November 2007 21 of 68
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