NXP Semiconductors LPC2210, LPC2220 User guide

UM10114

LPC2210/2220 User manual

Rev. 02 — 27 April 2007 User manual

Document information

Info Content Keywords LPC2210, LPC2220, LPC2210/01, ARM, ARM7, 32-bit, Microcontroller Abstract LPC2210/2220 User manual release

NXP Semiconductors

UM10114

LPC2210/2220 User manual

Revision history

Rev Date Description

2.1 20070425

• details on master mode

• SPI SSEL line conditioning added (see Table 12–159 “SPI pin description”).

2.0 20070123

• Details on LPC2210/01 device added into the document.

• The format of this data sheet has been redesigned to comply with the new identity

guidelines of NXP Semiconductors.

• Legal texts have been adapted to the new company name where appropriate.

1.0 20051012 Moved the UM document into the new structured FameMaker template. Many changes were made to the format throughout the document. Here are the most important:

• UART0 and UART1 description updated (fractional baudrate generator and hardware

handshake features added - auto-CTS/RTS)

• ADC chapter updated with the dedicated result registers

• GPIO chapter updated with the descri ption of the Fast IOs

Contact information

For additional information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com

User manual Rev. 02 — 27 April 2007 2 of 290

1. Introduction

UM10114

Chapter 1: Introductory information

Rev. 02 — 27 April 2007 User manual

The LPC2210/2220 and LPC2210/01 microcontrollers are based on a 16/32 bit ARM7TDMI-S CPU with real-time emulation and embedded trace support. For critical code size applications, the alternative 16-bit Thumb Mode reduces code by more than 30 % with minimal performance penalty.

With a 144 pin package, low power consumption, various 32 bit timers, 8 Channel 10 bit ADC, PWM channels and up to nine external interrupt pins this microcontroller is particularly suitable for industrial control, medical systems, access control and point-of-sale. LPC2210/2220 and LPC2210/01 can provide up to 76 GPIO depending on bus configuration. With a wide range of serial communications interfaces, it is also very well suited for communication gateways, protocol converters a nd embedded sof t modems as well as many other general-purpose applications.

2. Features introduced with LPC2210/01 and LPC2220 over LPC2210

• CPU clock up to 75 MHz.

• Fast IO registers are located on the ARM local bus for the fastest possible I/O timing.

• All GPIO registers are byte addressable.

• Entire port value can be written in one instruction.

• Mask registers allow single instruction to set or clear any number of bits in one port.

• TIMER0/1 can be driven by an external clock/can count external events

• Powerful Fractional baud rate generator with autobauding capabilities provides

standard baud rates such as 115200 with any crystal frequency above 2 MHz.

• UART1 is equipped with auto-CTS/RTS flow-control fully implemented in hardware.

• SSP serial controller supporting SPI/4-wire SSI and Microwire buses

• Every analog input has a dedicated result regis te r to re du ce inte rr up t ov er he ad .

• Every analog input can generate an interrupt once the conversion is completed.

3. Features

• 16/32-bit ARM7TDMI-S microcontroller in a LQFP144 and TFBGA144 package

• 16 kB (LPC2210 and LPC2210/01) or 64 kB (LPC2220) of on-chip static RAM.

• Serial boot-loader using UART0 provides in-system download and programming

capabilities.

• EmbeddedICE-RT and Embedded T race interface s offer real-tim e debugging with the

on-chip RealMonitor software and high speed tracing of instruction execution.

• Eight channel 10-bit A/D converter with a dedicated result register for every channel

and conversion time as low as 2.44 μs.

• Two 32-bit timers/external event counters with four capture and four compare

channels each, PWM unit (six outputs), Real-Time Clock (RTC) and watchdog.

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UM10114

Chapter 1: LPC2210/20 Introductory information

4. Applications

• Serial interfaces include two UARTs (16C550), Fast I

C (400 kbit/s), and two SPIs.

• Vectored Interrupt Controller (VIC) with configurable priorities and vector addresses.

• Configurable external memory interface with up to four banks, each up to 16 MB and

8/16/32 bit data width.

• Up to 76 general purpose Fast I/O pins (5 V tolerant) capable of toggling a GPIO pin

at 15 MHz. Up to nine edge or level sensitive external interrupt pins available.

• Up to 60 MHz (LPC2210) and 75 MHz (LPC2210/01 and LPC2220) maximum CPU

clock available from programmable on-chip Phase-Locked Loop (PLL) with settling time of 100 μs.

• On-chip integrated oscillator operates with an external crystal in range of 1 MHz to

30 MHz and with external oscillator up to 50 MHz.

• Power saving modes include Idle and Power-down.

• Processor wake-up from Power-down mode via external interrupt.

• Individual enable/disable of peripheral functions for power optimization.

• Dual power supply:

– CPU operating voltage range of 1.65 V to 1.95 V (1.8 V ±0.15 V). – I/O power supply range of 3.0 V to 3.6 V (3.3 V ±10 %) with 5 V tolerant I/O pads.

16/32 bit ARM7TDMI-S processor.

• Industrial control

• Medical systems

• Access control

• Point-of-sale

• Communication gateway

• Embedded soft modem

• General purpose applications

5. Device information

Table 1. LPC2210/2220 device information

Device Number

of pins

LPC2210 144 16 kB - 8 With external

LPC2210/01 144 16 kB - 8 + With external

LPC2220 144 64 kB - 8 + With external

On-chip SRAM

On-chip FLASH

Number of 10-bit AD Channels

Faster CPU, Fast IOs, TIMER0/1 external counter input, improved ADC, enhanced UARTs, SSP

Note

memory interface

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6. Architectural overview

LPC2210/20 and LPC2210/01 consist of an ARM7TDMI-S CPU with emulation support, the ARM7 Local Bus for interface to on-chip memory controllers and Fast GPIO, the AMBA Advanced High-performance Bus (AHB) for interface to the interrupt controller, and the VLSI Peripheral Bus (APB, a compatible superset of ARM’s AMBA Advanced Peripheral Bus) for connection to on-chip peripheral functions. The LPC2210/2220 and LPC2210/01 microcontroller configure the ARM7TDMI-S processor in little-endian byte order and this can not be altered by user.

AHB peripherals are allocated a 2 megabyte range of addresses at the very top of the 4 gigabyte ARM memory space. Each AHB peripheral is allocated a 16 kB address space within the AHB address space. LPC2210/2220 and LPC2210/01 peripheral functions (other than the interrupt controller) are connected to the APB bus. The AHB to APB bridge interfaces the APB bus to the AHB bus. APB peripherals are also allocated a 2 megabyte range of addresses, beginning at the 3.5 gigabyte address point. Each APB peripheral is allocated a 16 kB address space within the APB address space.

The connection of on-chip peripherals to device pins is controlled by a Pin Connect Block, see Section 7–4 requirements for the use of peripheral functions and pins.

UM10114

Chapter 1: LPC2210/20 Introductory information

. This must be configured by software to fit specific application

7. ARM7TDMI-S Processor

The ARM7TDMI-S is a general purpose 32-bit microprocessor, which offers high performance and very low power consumption. The ARM architecture is based on Reduced Instruction Set Computer (RISC) principles, and the instruction set and related decode mechanism are much simpler than those of microprogrammed Complex Instruction Set Computers. This simplicity results in a high instruction throughput and impressive real-time interrupt response from a small and cost-effective processor core.

Pipeline techniques are employed so that all part s of the pro cessing and memory systems can operate continuously. Typically, while one instruction is being executed, its successor is being decoded, and a third instruction is being fetched from memory.

The ARM7TDMI-S processor also employs a unique architectural strategy known as THUMB, which makes it ideally suited to high-volume applications with memory restrictions, or applications where code density is an issue.

The key idea behind THUMB is that of a super-reduced instruction set. Essentially, the ARM7TDMI-S processor has two instruction sets:

• The standard 32-bit ARM instruction set.

• A 16-bit THUMB instruction set.

The THUMB set’s 16-bit instruction length allows it to approach twice the density of standard ARM code while retaining most of the ARM’s performance advantage over a traditional 16-bit processor using 16-bit registers. This is possible because THUMB code operates on the same 32-bit register set as ARM code.

THUMB code is able to provide up to 65% of the code size of ARM, and 160% of the performance of an equivalent ARM processor connected to a 16-bit memory system.

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The ARM7TDMI-S processor is described in detail in the ARM7TDMI-S Datasheet that can be found on official ARM website.

8. On-Chip bootloader

The microcontroller incorporates an on-chip serial boot-loader located in a 8 kB ROM. Using UART0, this utility enables the loading an application into the microcontroller’s RAM for execution. Typically, an application loaded and executed from RAM would take care of programming of off-chip Flash memory with user’s code.

9. On-Chip Static RAM

On-Chip Static RAM (SRAM) may be used for code and/or data storage. The on-chip SRAM may be accessed as 8-bits, 16-bits, and 32-bits. The LPC2210 and LPC2210/01 provide 16 kB of static RAM while LPC2220 provides 64 kB of static RAM.

The microcontroller’s SRAM is designed to be accessed as a byte-addressed memory. Word and halfword accesses to the memory ignore the alignment of the address and access the naturally-aligned value that is addressed (so a memory access ignores address bits 0 and 1 for word accesses, and ignores bit 0 for halfword accesses). Therefore valid reads and writes require data accessed as halfwords to originate from addresses with address line 0 being 0 (addresses ending with 0, 2, 4, 6, 8, A, C, and E in hexadecimal notation) and data accessed as words to originate from addresses with address lines 0 and 1 being 0 (addresses ending with 0, 4, 8, and C in hexadecimal notation). This rule applies to both off and on-chip memory usage.

UM10114

Chapter 1: LPC2210/20 Introductory information

The SRAM controller incorporates a write-back buffer in order to prevent CPU stalls during back-to-back writes. The write-back buffer always holds the last data sent by software to the SRAM. This data is only written to the SRAM when another write is requested by software (the data is only written to the SRAM when software does another write). If a chip reset occurs, actual SRAM contents will not reflect the most recent write request (i.e. after a "warm" chip reset, the SRAM does not reflect the last wr ite operation). Any software that checks SRAM contents after reset must take this into account. Two identical writes to a location guarantee that the data will be present after a Reset. Alternatively, a dummy write operation before entering idle or power-down mode will similarly guarantee that the last data written will be present in SRAM after a subsequent Reset.

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002aaa793

system

clock

SCL

P0[30:27], P0[25:0]

P2[31:0]

P1[31:16], P1[1:0]

P3[31:0]

SDA

CS3 to CS0

(2)

A23 to A0

(2)

BLS3 to BLS0

(2)

OE, WE

(2)

D31 to D0

(2)

TRST

(1)

TMS

(1)

TCK

(1)

TDI

(1)

TDO

(1)

XTAL2

XTAL1

SCK0, SCK1

MOSI0, MOSI1

MISO0, MISO1

EINT3 to EINT0

4 × CAP0 4 × CAP1

4 × MAT1

4 × MAT0

AIN7 to AIN0

PWM6 to PWM1

SSEL0, SSEL1

TXD0, TXD1

RXD0, RXD1

DSR1, CTS1, RTS, DTR DCD1, RI1

AMBA AHB

(Advanced High-performance Bus)

AHB BRIDGE

EMULATION

TRACE MODULE

TEST/DEBUG

INTERFACE

AHB

DECODER

AHB TO APB

BRIDGE

APB

DIVIDER

VECTORED INTERRUPT

CONTROLLER

SYSTEM

FUNCTIONS

PLL

SPI AND SSP

SERIAL INTERFACES

0 AND 1

C SERIAL

INTERFACE

UART0/UART1

REAL TIME CLOCK

WATCHDOG

TIMER

SYSTEM

CONTROL

EXTERNAL

INTERRUPTS

GENERAL

PURPOSE I/O

PWM0

CAPTURE/ COMPARE

TIMER 0/TIMER 1

A/D CONVERTER

ARM7TDMI-S

LPC2210/2220

LPC2210/01

INTERNAL

SRAM

CONTROLLER

16/64 kB

SRAM

APB (ARM

Peripheral Bus)

RST

EXTERNAL MEMORY

CONTROLLER

ARM7 local bus

P0[30:27], P0[25:0]

P1[31:16], P1[1:0]

FAST GENERAL

PURPOSE I/O

10. Block diagram

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Chapter 1: LPC2210/20 Introductory information

User manual Rev. 02 — 27 April 2007 7 of 290

(1) When debug interface is used, GPIO/other functions sharing these pins are not available. (2) Shared with GPIO.

Fig 1. LPC2210/2220 and LPC2210/01 block diagram

AHB PERIPHERALS

APB PERIPHERALS

RESERVED ADDRESS SPACE

BOOT BLOCK (RE-MAPPED FROM

ON-CHIP ROM MEMORY

RESERVED ADDRESS SPACE

64 KBYTE ON-CHIP STATIC RAM (LPC2220)

16 KBYTE ON-CHIP STATIC RAM

(LPC2210, LPC2210/01)

RESERVED ADDRESS SPACE

0xFFFF FFFF

0xF000 0000 0xEFFF FFFF

0xE000 0000 0xDFFF FFFF

0x8400 0000

0x7FFF FFFF

0x7FFF E000

EXTERNAL MEMORY BANK 3

0x83FF FFFF

0x8300 0000

EXTERNAL MEMORY BANK 2

0x82FF FFFF

0x8200 0000

EXTERNAL MEMORY BANK 1

0x81FF FFFF

0x8100 0000

EXTERNAL MEMORY BANK 0

0x80FF FFFF

0x8000 0000

0x7FFF DFFF

0x4000 4000 0x4000 3FFF

0x4001 0000 0x4000 FFFF

0x4000 0000 0x3FFF FFFF

4.0 GB

3.75 GB

3.5 GB

3.0 GB

2.0 GB

1.0 GB

0x0000 0000

0.0 GB

002aaa795

1. Memory maps

The LPC2210/2220 and LPC2210/01 incorporate several d istinct memory r egions, shown in the following figures. Figure 2–2 from the user program viewpoint following reset. The interrupt vector area supports address remapping, which is described later in this section.

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Chapter 2: LPC2210/20 memory mapping

Rev. 02 — 27 April 2007 User manual

shows the overall map of the entire address space

Fig 2. System memory map

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RESERVED

0xF000 0000 0xEFFF FFFF

APB PERIPHERALS

0xE020 0000 0xE01F FFFF

0xE000 0000

AHB PERIPHERALS

0xFFFF FFFF

0xFFE0 0000 0xFFDF FFFF

3.75 GB

3.5 GB

3.5 GB + 2 MB

4.0 GB - 2 MB

4.0 GB

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Chapter 2: LPC2210/20 Memory map

Fig 3. Peripheral memory map

Figures 3 through 4 and Table 2–2 show different views of the peripheral address space. Both the AHB and APB peripheral areas are 2 megabyte sp aces which are divided up into 128 peripherals. Each peripheral space is 16 kilobytes in size. This allows simplifying the address decoding for each peripheral. All peripheral register addresses are word aligned (to 32-bit boundaries) regardless of their size. This eliminates the need for byte lane mapping hardware that would be required to allow byte (8-bit) or half-wor d (16-bit)

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VECTORED INTERRUPT CONTROLLER

(AHB PERIPHERAL #0)

0xFFFF F000 (4G - 4K)

0xFFFF C000

0xFFFF 8000

(AHB PERIPHERAL #125)

(AHB PERIPHERAL #124)

(AHB PERIPHERAL #3)

(AHB PERIPHERAL #2)

(AHB PERIPHERAL #1)

(AHB PERIPHERAL #126)

0xFFFF 4000

0xFFFF 0000

0xFFE1 0000

0xFFE0 C000

0xFFE0 8000

0xFFE0 4000

0xFFE0 0000

accesses to occur at smaller boundaries. An implication of this is that word and half-word registers must be accessed all at once. For example, it is not possible to read or write the upper byte of a word register separately.

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Chapter 2: LPC2210/20 Memory map

AHB section is 128 x 16 kB blocks (totaling 2 MB). APB section is 128 x 16 kB blocks (totaling 2MB).

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Fig 4. AHB peripheral map

NXP Semiconductors

Table 2. APB peripheries and base addresses

APB peripheral Base address Peripheral name

0 0xE000 0000 Watchdog timer 1 0xE000 4000 Timer 0 2 0xE000 8000 Timer 1 3 0xE000 C000 UART0 4 0xE001 0000 UART1 5 0xE001 4000 PWM 6 0xE001 8000 Not used 7 0xE001 C000 I 8 0xE002 0000 SPI0 9 0xE002 4000 RTC 10 0xE002 8000 GPIO 11 0xE002 C000 Pin connect block 12 0xE003 0000 SPI1 13 0xE003 4000 10 bit ADC 14 - 22 0xE003 8000

23 0xE005 C000 SSP (LPC2210/01 and LPC2220 only) 24 - 126 0xE006 0000

127 0xE01F C000 System Control Block

0xE005 8000

0xE01F 8000

Not used

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Chapter 2: LPC2210/20 Memory map

2. LPC2210/2220 Memory re-mapping and boot block

2.1 Memory map concepts and operating modes

The basic concept on the LPC2210/2220 and L PC2210 /0 1 is that ea ch memor y a rea ha s a "natural" location in the memory map. This is the address range for which code residing in that area is written. The bulk of each memory space remains permanently fixed in the same location, eliminating the need to have portions of the code designed to run in different address ranges.

Because of the location of the interrupt vectors on the ARM7 processor (at addresses 0x0000 0000 through 0x0000 001C, as shown in Table 2–3 Boot Block and SRAM spaces need to be re-mapped in order to allow alternative uses of interrupts in the different operating modes described in Table 2–4 interrupts is accomplished via the Memory Mapping Control features.

Table 3. ARM Exceptio n Vector Locations

Address Exception

0x0000 0000 Reset 0x0000 0004 Undefined Instruction 0x0000 0008 Software Interrupt 0x0000 000C Prefetch Abort (instruction fetch memory fault) 0x0000 0010 Data Abort (data access memory fault)

below), a small portion of the

. Re-mapping of the

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Table 3. ARM Exceptio n Vector Locations

Address Exception

0x0000 0014 Reserved

0x0000 0018 IRQ 0x0000 001C FIQ

Table 4. LPC2210/2220 and LPC2210/01 Memory Mapp ing Modes

Mode Activation Usage

Boot Loader mode

User RAM mode

User External mode

Hardware activation by any Reset

Software activation by User program

Activated by BOOT1:0 pins

UM10114

Chapter 2: LPC2210/20 Memory map

Note: Identified as reserved in ARM documentation.

The Boot Loader always executes after any reset. The Boot Block interrupt vectors are mapped to the bottom of memory to allow handling exceptions and using interrupts during the Boot Loading process.

Activated by a User Program as desired. Interrupt vectors are re-mapped to the bottom of the Static RAM.

Activated by Boot Loader when P0.14 is not LOW at the end of RESET LOW. Interrupt vectors are re-mapped from the bottom of the external memory map.

2.2 Memory re-mapping

In order to allow for compatibility with future derivatives, the entire Boot Block is mapped to the top of the on-chip memory space. Memory spaces other than the interrupt vectors remain in fixed locations. Figure 2–5 defined above.

The portion of memory that is re-mapped to allow interrupt processing in different modes includes the interrupt vector area (32 bytes) and an additional 32 bytes, for a total of 64 bytes. The re-mapped code locations overlay addresses 0x0000 0000 through 0x0000 003F. The vector contained in the SRAM, external memory, and Boot Block must contain branches to the actual interrupt handlers, or to other instructions that accomplish the branch to the interrupt handlers.

There are two reasons this configuration was chosen:

1. Minimize the need for the SRAM and Boot Block vectors to deal with arbitrary boundaries in the middle of code space.

2. To provide space to store constants for jumping beyond the range of single word branch instructions.

Re-mapped memory areas, including the Boot Block and interrupt vectors, continue to appear in their original location in addition to the re-mapped address.

Details on re-mapping and examples can be found in Section 4–7 “

control” on page 34.

shows the on-chip memory mapping in the modes

Memory mapping

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8 kB BOOT BLOCK

(RE-MAPPED FROM TOP OF FLASH MEMORY)

RESERVED ADDRESSING SPACE

16 kB ON-CHIP SRAM (LPC2210, LPC2210/01)

0.0 GB

ACTIVE INTERRUPT VECTORS (FROM FLASH, SRAM, OR BOOT

BLOCK)

0x8000 0000

0x4000 4000 0x4000 3FFF

0x4000 0000 0x3FFF FFFF

0x0000 0000

0x7FFF FFFF

1.0 GB

2.0 GB - 8 kB

2.0 GB

(BOOT BLOCK INTERRUPT VECTORS)

(SRAM INTERRUPT VECTORS)

RESERVED MEMORY SPACE

(8 kB BOOT BLOCK RE-MAPPED TO HIGHER ADDRESS RANGE)

0x0004 0000 0x0003 FFFF

RESERVED ADDRESSING SPACE

0x7FFF E000 0x7FFF DFFF

0x4001 0000 0x4000 FFFF

64 kB ON-CHIP SRAM (LPC2220)

0x0003 E000 0x0003 DFFF

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UM10114

Chapter 2: LPC2210/20 Memory map

Fig 5. Map of lower memory is showing re-mapped and re-ma p pable areas

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3. Prefetch abort and data abort exceptions

The LPC2210/2220 and LPC2210/01 generate the appropriate bus cycle abort exception if an access is attempted for an address that is in a reserved or unassigned address region. The regions are:

• Areas of the memory map that are not implemented for a specific ARM derivative. Fo r

the LPC2210/2220 and LPC2210/01, this is: – Address space between the re-mapped interrupt vector area and an On-Chip

SRAM, labelled "Reserved Address Space" in Figure 2–2 an address range from 0x0000 0040 to 0x3FFF FFFF.

– Address space between On-Chip Static RAM and Boot Block. Labelled "Reserved

Address Space" in Figure 2–2 range from 0x4000 4000 to 0x7FFF DFFF and for LPC2220 this is an address range from 0x4001 0000 to 0x7FFF DFFF.

– Address space between 0x8400 0000 to 0xDFFF FFFF, labelled "Reserved

Address Space".

– Reserved regions of the AHB and APB spaces. See Figure 2–3

• Unassigned AHB peripheral spaces. See Figure 2–4.

• Unassigned APB peripheral spaces. See Table 2–2.

. For LPC2210 and LPC2210/01 this is an address

UM10114

Chapter 2: LPC2210/20 Memory map

and Figure 2–5. This is

and Table 2–2.

For these areas, both attempted data acce ss and in struction fetch genera te an exception. In addition, a Prefetch Abort exception is generated for any instruction fetch that maps to an AHB or APB peripheral address.

Within the address space of an existing APB peripheral, a data abort exception is not generated in response to an access to an undefined address. Address decoding within each peripheral is limited to that needed to distinguish defined registers within the peripheral itself. For example, an access to address 0xE000 D000 (an undefined address within the UART0 space) may result in an access to the register defined at address 0xE000 C000. Details of such address aliasing within a peripheral space are not defined in the LPC2210/2220 and LPC2210/01 documentation and are not a supported feature.

Note: The ARM core stores the Prefetch Abort flag along with the associated instruction (which will be meaningless) in the pipeline and processes the abort only if an attempt is made to execute the instruction fetched from the illegal address. This prevents accidental aborts that could be caused by prefetches that occur when code is executed very near a memory boundary.

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1. Features

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Chapter 3: External Memory Controller (EMC)

Rev. 02 — 27 April 2007 User manual

• Support for various static memory-mapped devices including RAM, ROM, flash, burst

ROM, and some external I/O devices

• Asynchronous page mode read operation in non-clocked memory subsystems

• Asynchronous burst mode read access to burst mode ROM devices

• Independent configuration for up to four banks, each up to 16 M Bytes

• Programmable bus turnaround (idle) cycles (1 to 16)

• Programmable read and write WAIT states (up to 32) for static RAM devices

• Programmable initial and subsequent burst read WAIT state, for burst ROM devices

• Programmable write protection

• Programmable burst mode operation

• Programmable read byte lane enable control

2. Description

The external Static Memory Controller is an AMBA AHB slave module which provides an interface between an AMBA AHB system bus and external (off-chip) memory devices. It provides support for up to four independently configurable memory banks simult aneously. Each memory bank is capable of supporting SRAM, ROM, Flash EPROM, Burst ROM memory, or some external I/O devices .

Each memory bank may be 8, 16, or 32 bits wide. Since the LPC2210/20 144 pin package pins out addre ss line s A[23:0] only, the decoding

among the four banks uses address bits A[25:24]. The native lo catio n of th e four ban ks is at the start of the External Memory area identified in Figure 2–2 on page 8 be used for initial booting under control of the state of the BOOT[1:0] pins.

Table 5. Address ranges of the external memory banks

Bank Address range Configuration register

0 0x8000 0000 - 0x80FF FFFF BCFG0 1 0x8100 0000 - 0x81FF FFFF BCFG1 2 0x8200 0000 - 0x82FF FFFF BCFG2 3 0x8300 0000 - 0x83FF FFFF BCFG3

, but Bank 0 can

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3. Pin description

Table 6. Exter nal Me mory Controller pin description

Pin name Type Pin description

D[31:0] Input/Output External memory Data lines A[23:0] Output External memory Address lines OE Output Low-active Output Enable signal BLS[3:0] Output Low-active Byte Lane Select signals WE Output Low-active Write Enable signal CS[3:0] Output Low-active Chip-Select signals

4. Register description

The external memory controller contains 4 registers as shown in Table 3–7.

Table 7. Exter nal Me mory Controller register map

Name Description Access Reset value,

BCFG0 Configuration register for memory bank 0 R/W 0x0000 FBEF 0xFFE0 0000 BCFG1 Configuration register for memory bank 1 R/W 0x2000 FBEF 0xFFE0 0004 BCFG2 Configuration register for memory bank 2 R/W 0x1000 FBEF 0xFFE0 0008 BCFG3 Configuration register for memory bank 3 R/W 0x0000 FBEF 0xFFE0 000C

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Chapter 3: LPC2210/20 EMC

Address

see Table 9.

Each register selects the following options for its memory bank:

• The number of idle clock cycles inserted between read and write accesses in this

bank, and between an access in another bank and an access in this bank, to avoid bus contention between devices (1 to 17 clocks)

• The length of read accesses, except for subsequent reads from a burst ROM (3 to 35

clocks)

• The length of write accesses (3 to 19 clocks)

• Whether the bank is write-protected or not

• Whether the bank is 8, 16, or 32 bits wide

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4.1 Bank Configuration Registers 0-3 (BCFG0-3 - 0xFFE0 0000 to 0xFFE0 000C)

Table 8. Bank Con f iguration Registers 0-3 (BCFG0-3 - 0xFFE0 0000 to 0xFFE0 000C)

BCFG0-3 Name Function Reset

3:0 IDCY This field controls the minimum number of “idle” CCLK cycles

4 - Reserved, user software should not write ones to reserved bits.

9:5 WST1 This field controls the length of read accesses (except for

10 RBLE This bit should be 0 for banks composed of byte-wide or

15:11 WST2 For SRAM banks, this field controls the length of write accesses,

23:16 - Reserved, user software should not write ones to reserved bits.

24 BUSERR The only known case in which this bit is set is if the EMC detects

25 WPERR This bit is set if software attempts to write to a bank that has the

26 WP A 1 in this bit write-protects the bank. 0 27 BM A 1 in this bit identifies a burst-ROM bank. 0 29:28 MW This field controls the width of the data bus for this bank:

31:30 AT Always write 00 to this field. 00

address description

that the EMC maintains between read and write accesses in this bank, and between an access in another bank and an access in this bank, to avoid bus contention between devices. The number of idle CCLK cycles between such accesses is the value in this field plus 1.

The value read from a reserved bit is not defined.

subsequent reads from a burst ROM). The length of read accesses, in CCLK cycles, is this field value plus 3.

non-byte-partitioned devices, so that the EMC drives the BLS3:0 lines High during read accesses. This bit should be 1 for banks composed of 16-bit and 32-bit wide devices that include byte select inputs, so that the EMC drives the BLS3:0 lines Low during read accesses.

which consist of: One CCLK cycle of address setup with CS, BLS, and WE high This value plus 1, CCLK cycles with address valid and CS, BLS,

and WE low AND One CCLK cycle with address valid, CS low, BLS and WE high. For burst ROM banks, this field controls the length of subsequent

accesses, which are (this value plus 1) CCLK cycles long.

The value read from a reserved bit is not defined.

an AMBA request for more than 32 bits of data. The ARM7TDMI-S will not make such a request.

WP bit 1. Write a 1 to this bit to clear it.

00=8 bit, 01=16 bit, 10=32 bit, 11=reserved

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Chapter 3: LPC2210/20 EMC

value

1111

11111

See

Table 3– 9

The table below shows the state of BCFG0[29:28] after the Boot Loader has run. The hardware reset state of these bits is 10.

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T able 9. Default memory widths at reset

Bank BOOT[1:0] during Reset BCFG[29:28] Reset value Memory width

0LL 00 8bits 0LH 01 16bits 0HL 10 32bits 0HH 01 16bits 1XX 10 32bits 2XX 01 16bits 3XX 00 8bits

4.2 Read Byte Lane Control (RBLE)

The External Memory Controller (EMC) generates byte lane control signals BLS[3:0] according to:

• External memory bank data bus wid th , de fined within each configuration register (see

• External memory bank type, being either byte (8 bits), halfword (16 bits) or word (32

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Chapter 3: LPC2210/20 EMC

MW field in BCFG register)

bits) (see RBLE field in BCFG register)

Each memory bank can either be 8, 16 or 32 bits wide. The type of memory used to configure a particular memory bank determines how the WE and BLS signals are connected to provide byte, halfword and word access. For read accesses, it is necessary to control the BLS signals by driving them either all HIGH, or all LOW.

This control is achieved by programming the Read Byte Lane Enable (RBLE) bit within each configuration register. The following two sections explain why different connections in respect of WE and BLS[3:0] are needed for different memory configurations.

4.3 Accesses to memory banks constructed from 8-bit or non byte-partitioned memory devices

For memory banks constructed from 8-bit or non byte-partitioned memory devices, it is important that the RBLE bit is cleared to zero within the respective memory bank configuration register. This forces all BLS[3:0] lines HIGH during a read access to that particular bank.

Figure 3–6

memory banks that are 8, 16 and 32 bits wide. In each of these configurations, the BLS[3:0] signals are connected to write enable (WE) inputs of each 8-bit memory.

Note: The WE signal from the EMC is not used. For write transfers, the relevant BLS[3:0] byte lane signals are asserted LOW and steer the data to the addressed bytes.

For read transfers, all of the BLS[3:0] lines are deasserted HIGH, which allows the external bus to be defined for at least the width of the accessed memory.

(a), Figure 3–7 (a) and Figure 3–8 show 8-bit memory being used to configure

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4.4 Accesses to memory banks constructed from 16 or 32 bit memory devices

For memory banks constructed from 16 bit or 32-bit memory devices, it is important that the RBLE bit is set to one within the respective memory bank configuraton register. This asserts all BLS[3:0] lines LOW during a read access to that particular bank. For 16 and 32-bit wide memory devices, byte select signals exist and must be appropriately controlled as shown in Figure 3–6

5. External memory interface

External memory interfacing depends on the bank width (32, 16 or 8 bit selected via MW bits in corresponding BCFG register). Furthermore, the memory chip(s) require an adequate setup of RBLE bit in BCFG register. Memory accessed with an 8-bit wide data bus require RBLE = 0, while memory banks capable of accepting 16 or 32 bit wide data require RBLE = 1.

If a memory bank is configured to be 32 bits wide, address lines A0 and A1 can be used as non-address lines. If a memory bank is configured to 16 bits wide, A0 is not required. However, 8 bit wide memory banks do require all address lines down to A0. Configuring A1 and/or A0 line(s) to provide address or non-address function is accomplished using bits 23 and 24 in Pin Function Select Register 2 (PINSEL2 register, see Section 7–4.3

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Chapter 3: LPC2210/20 EMC

and Figure 3–7.

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A[a_b:2]

BLS[1]

D[15:8]

CE OE WE

IO[7:0] A[a_m:0]

BLS[0]

D[7:0]

CE OE WE

IO[7:0] A[a_m:0]

BLS[3]

D[31:24]

CE OE WE

IO[7:0] A[a_m:0]

BLS[2]

D[23:16]

CE OE WE

IO[7:0] A[a_m:0]

CE OE WE UB LB

IO[15:0] A[a_m:0]

D[31:16]

BLS[2]

CE OE WE UB LB

IO[15:0] A[a_m:0]

D[15:0]

BLS[0]

A[a_b:2]

BLS[3] BLS[1]

CE OE WE B3 B2 B1 B0

IO[31:0] A[a_m:0]

D[31:0]

BLS[2]

A[a_b:2]

BLS[3]

BLS[0]

BLS[1]

Symbol "a_b" in the following figures refers to the highest order address line in the data bus. Symbol "a_m" refers to the highest order address line of the me mory chip used in the external memory interface.

a. 32 bit wide memory bank interfaced to 8 bit memory chips (RBLE = 0)

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Chapter 3: LPC2210/20 EMC

b. 32 bit wide memory bank interfaced to 16 bit memory chips (RBLE = 1)

c. 32 bit wide memory bank interfaced to 8 bit memort chips (RBLE = 1)

Fig 6. 32 bit bank external memory interfaces (BGFGx Bits MW = 10)

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BLS[1]

D[15:8]

CE OE WE

IO[7:0] A[a_m:0]

BLS[0]

D[7:0]

CE OE WE

IO[7:0] A[a_m:0]

A[a_b:1]

CE OE WE UB LB

IO[15:0] A[a_m:0]

D[15:0]

BLS[0]

A[a_b:1]

BLS[1]

BLS[0]

D[7:0]

CE OE WE

IO[7:0] A[a_m:0]

A[a_b:0]

a. 16 bit wide memory bank interfaced to 8 bit memory chips (RBLE = 0)

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Chapter 3: LPC2210/20 EMC

b. 16 bit wide memory bank interfaced to 16 bit memory chips (RBLE = 1)

Fig 7. 16 bit bank external memory interfaces (BCFGx bits MW = 01)

Fig 8. 8 bit bank external memory interface (BCFGx bits MW = 00 and RBLE = 0)

6. Typical bus sequences

The following figures show typical external read and write access cycles. XCLK is the clock signal available on P3.23. While not necessarily used by external memory, in these examples it is used to provide time reference (XCLK and CCLK are set to have the same

User manual Rev. 02 — 27 April 2007 21 of 290

frequency).

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WE/BLS

XCLK

addr data

WE/BLS

change valid data

valid address

1 wait state

(WST1=0)

XCLK

addr

data

change valid data

valid address

2 wait states

(WST1=1)

XCLK

addr

data

WE/BLS

valid address

valid data

XCLK

addr

data

WE/BLS

valid address

valid data

WST2 = 0

WST2 = 1

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Chapter 3: LPC2210/20 EMC

Fig 9. External memory read access (WST1 = 0 and WST1 = 1 examples)

User manual Rev. 02 — 27 April 2007 22 of 290

Fig 10. E xternal memory write access (WST2 = 0 and WST2 = 1 examples)

Figure 3–9 and Figure 3–10 show typical read and write accesses to external memory.

Dashed lines on Figure 3–9 having BLS lines connected to UB/LB or B[3:0] (see Section 3–4.4

Figure 3–7

correspond to memory banks using 16/32 bit memory chips

and Figure 3–6 ,

NXP Semiconductors

Address A Ad.A+1 Ad.A+2 Address A+3

D(A) D(A+1) D(A+2) Data(A+3)

2 wait states

XCLK

addr

data

0 wait states

MAX

2WST1+

RAM

20ns+

------------------------------

≤

WST1

RAM

20ns+

CYC

------------------------------

≥ 2–

RAMtCYC

2WST1+()× 20ns–≤

It is important to notice that some variations from Figure 3–9 and Figure 3–10 do exist in some particular cases.

For example, when the first read access to the memory bank that has just been selected is performed, CS and OE lines may become low one XCLK cycle earl ier than it is shown in

Figure 3–10

Likewise, in a sequence of several consecutive write accesses to SRAM, the last write access will look like those shown in Figure 3–10 in that case will have data valid one cycle longer. Also, isolated write access will be identical to the one in Figure 3–10

The EMC supports sequential access burst reads of up to four consecutive lo ca tions in 8 , 16 or 32-bit memories. This feature supports burst mode ROM devices and increases the bandwidth by using reduced (configurable) ac cess time for three sequential reads following a quad-location boundary read. Figure 3–11 read transfer. The first burst read access has two wait states and subsequent accesses have zero wait states.

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Chapter 3: LPC2210/20 EMC

. On the other hand, leading write cycles

shows an external memory burst

Fig 11. External burst memory read access (WST1 = 0 and WST1 = 1 examp les)

7. External memory selection

Based on the description of the EMC operation and external memory in general (appropriate read and write access times t can be constructed and used for extern a l mem o ry se lect ion . t CCLK cycle (see Figure 3–9 cycle). f

is the maximum CCLK frequency achievable in the system with selected

max

and Figure 3–10 where one XCLK cycle equals one CCLK

external memory.

Table 10. External memory and system requirements

Access

Maximum frequency WST setting

cycle

Standard Read

User manual Rev. 02 — 27 April 2007 23 of 290

(WST>=0; round up to integer)

and t

respectively), the following table

WRITE

is the period of a single

CYC

Required memory access time

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MAX

1WST2+

WRITE

5ns+

------------------------------- -

≤

WST2

WRITEtCYC

5+–

CYC

-------------------------------------------

≥

WRITEtCYC

1WST2+()× 5ns–≤

MAX

2WST1+

INIT

20ns+

----------------------------- -

≤

WST1

INIT

20ns+

CYC

----------------------------- -

≥ 2–

INITtCYC

2WST1+()× 20ns–≤

MAX

ROM

20ns+

------------------------------ -

≤

ROMtCYC

20ns–≤

Table 10. External memory and system requirements

Access cycle

Standard Write

Burst read (initial)

Maximum frequency WST setting

(WST>=0; round up to integer)

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Required memory access time

Burst read subsequent 3x

N/A

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Chapter 4: System control

Rev. 02 — 27 April 2007 User manual

1. Summary of system control block functions

The System Control Block includes several system features and control registers for a number of functions that are not related to specific peripheral devices. These include:

• Crystal Oscillator

• External Interrupt Inputs

• Miscellaneous System Controls and Status

• Memory Mapping Control

• PLL

• Power Control

• Reset

• APB Divider

• Wakeup Timer

Each type of function has its own register(s) if any are required and unneeded bits are defined as reserved in order to allow future expansion. Unrelated functions never share the same register addresses

2. Pin description

Table 4–11 shows pins that are associated with System Control block functions.

Table 11. Pin summary

Pin name Pin

XTAL1 Input Crystal Oscillator Input - Input to the oscillator and internal clock

XTAL2 Output Crystal Oscillator Output - Output from the oscillator amplifier EINT0 Input External Interrupt Input 0 - An active low/high level or

EINT1 Input External Interrupt Input 1 - See the EINT0 description above.

Pin description

direction

generator circuits

falling/rising edge general purpose interrupt input. This pin may be used to wake up the processor from Idle or Power-down modes.

Pins P0.1 and P0.16 can be selected to perform EINT0 function.

Pins P0.3 and P0.14 can be selected to perform EINT1 function. Important: LOW level on pin P0.14 immediately after reset is

considered as an external hardware request to start the ISP command handler. More details on ISP and Serial Boot Loader can be found in "On-chip Serial Bootloader" chapter on page 242.

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Table 11. Pin summary

Pin name Pin

EINT2 Input External Interrupt Input 2 - See the EINT0 description above.

EINT3 Input External Interrupt Input 3 - See the EINT0 description above.

RESET

3. Register description

All registers, regardless of size, are on word address boundaries. Details of the registers appear in the description of each function.

T able 12. Summary of system control registers

Name Description Access Reset

External Interrupts

EXTINT External Interrupt Flag Register R/W 0 0xE01F C140 EXTWAKE External Interrupt Wakeup Register R/W 0 0xE01F C144 EXTMODE External Interrupt Mode Register R/W 0 0xE01FC148 EXTPOLAR External Interrupt Polarity Register R/W 0 0xE01F C14C

Memory Mapping Control

MEMMAP Memory Mapping Control R/W 0 0xE01F C040

Phase Locked Loop

PLLCON PLL Control Register R/W 0 0xE01F C080 PLLCFG PLL Configuration Register R/W 0 0xE01F C084 PLLSTAT PLL Status Register RO 0 0xE01F C088 PLLFEED PLL Fee d Register WO NA 0xE01F C08C

Power Control

PCON Power Control Register R/W 0 0xE01F C0C0 PCONP Power Control for Peripherals R/W 0x1FBE 0xE01F C0C4

APB Divider

APBDIV APB Divider Control R/W 0 0xE01F C100

Syscon Miscellaneous Registers

SCS System Controls and Status R/W 0 0xE01F C1A0

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Chapter 4: LPC2210/20 System control

Pin description

direction

Pins P0.7 and P0.15 can be selected to perform EINT2 function.

Pins P0.9, P0.20 and P0.30 can be selected to perform EINT3 function.

Input External Reset input - A LOW on this pin resets the chip, causing

I/O ports and peripherals to take on their default states, and the processor to begin execution at address 0x0000 0000.

Address

value

[1]

[1] Reset value reflects the data stored in used bits only. It does not include reserved bits content.

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LPC2xxx LPC2xxx

Clock

< = >

a) b) c)

Xtal

XTAL1 XTAL2

4. Crystal oscillator

While an input signal of 50-50 duty cycle within a frequency range from 1 MHz to 50 MHz can be used by the LPC2210/2220 and LPC2210/01 if supplied to its input XTAL1 pin, this microcontroller’s onboard oscillator circuit supports external crystals in the range of 1 MHz to 30 MHz only. If the on-chip PLL system or the boot-loader is used, the input clock frequency is limited to an exclusive range of 10 MHz to 25 MHz.

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Chapter 4: LPC2210/20 System control

The oscillator output frequency is called F referred to as CCLK for purposes of rate equations, etc. elsewhere in this document. F

and the ARM processor clock frequency is

OSC

and CCLK are the same value unless the PLL is running and connected. Refer to the

Section 4–8 “

Phase Locked Loop (PLL)” on page 35 for details and frequency limitations.

The onboard oscillator in the LPC2210/2220 and LPC2210/01 can operate in one of two modes: slave mode and oscillation mode.

In slave mode the input clock signal should be coupled by means of a capacitor of 100 pF (C

in Figure 4–12, drawing a), with an amplitude of at least 200 mVrms. The X2 pin in

this configuration can be left not connected. If slave mode is selected, the F

signal of

OSC

50-50 duty cycle can range from 1 MHz to 50 MHz. External components and models used in oscillation mode are shown in Figure 4–12

drawings b and c, and in Table 4–13 only a crystal and the capacitances C

. Since the feedback resistance is integrated on chip,

and CX2 need to be connected externally in case

of fundamental mode oscillation (the fundamental frequency is represented by L, C R

). Capacitance CP in Figure 4–12, drawing c, repr e sen ts the parallel package

capacitance and should not be larger than 7 pF. Parameters F

, CL, RS and CP are

and

supplied by the crystal manufacturer. Choosing an oscillation mode as an on-board oscillator mode of operation limits F

OSC

clock selection to 1 MHz to 30 MHz.

Fig 12. Oscillator modes and models: a) slave mode of operation, b) oscillation mode of operation, c) external

User manual Rev. 02 — 27 April 2007 27 of 290

crystal model used for C

evaluation

X1/X2

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true

MIN f

OSC

= 10 MHz

MAX f

OSC

= 25 MHz

true

MIN f

OSC

= 1 MHz

MAX f

OSC

= 50 MHz

MIN f

OSC

= 1 MHz

MAX f

OSC

= 30 MHz

mode a and/or b mode a mode b

on-chip PLL used

in application?

ISP used for initial

code download?

external crystal

oscillator used?

true

false

OSC

selection

T able 13. Recommended values for C

Fundamental oscillation frequency F

OSC

1 MHz - 5 MHz 10 pF NA NA

5 MHz - 10 MHz 10 pF < 300 Ω 18 pF, 18 pF

10 MHz - 15 MHz 10 pF < 300 Ω 18 pF, 18 pF

15 MHz - 20 MHz 10 pF < 220 Ω 18 pF, 18 pF

20 MHz - 25 MHz 10 pF < 160 Ω 18 pF, 18 pF

25 MHz - 30 MHz 10 pF < 130 Ω 18 pF, 18 pF

components parameters)

Crystal load capacitance C

20 pF NA NA 30 pF < 300 Ω 58pF, 58 pF

20 pF < 300 Ω 38 pF, 38 pF 30 pF < 300 Ω 58 pF, 58 pF

20 pF < 220 Ω 38 pF, 38 pF 30 pF < 140 Ω 58 pF, 58 pF

20 pF < 140 Ω 38 pF, 38 pF 30 pF < 80 Ω 58 pF, 58 pF

20 pF < 90 Ω 38 pF, 38 pF 30 pF < 50 Ω 58 pF, 58 pF

20 pF < 50 Ω 38 pF, 38 pF 30 pF NA NA

Chapter 4: LPC2210/20 System control

in oscillation mode (crystal and external

X1/X2

Maximum crystal

series resistance R

External load capacitors C

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X1, CX2

Fig 13. F

selection algorithm

OSC

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5. External interrupt inputs

The LPC2210/2220 and LPC2210/01 include four External Interrupt Inputs as select able pin functions. The External Interrupt Inputs can optionally be used to wake up the processor from Power-down mode.

5.1 Register description

The external interrupt function has four registers associated with it. The EXTINT register contains the interrupt flags, and the EXTWAKE register cont ains bits that enable individual external interrupts to wake up the microcontroller from Power-down mode. The EXTMODE and EXTPOLAR registers specify the level and edge sensitivity parameters.

Table 14. External interrupt registers

Name Description Access Reset

EXTINT The External Interrupt Flag Register contains

interrupt flags for EINT0, EINT1, EINT2 and EINT3. See Table 4–15

EXTWAKE The External Interrupt Wakeup Register

contains four enable bits that control whether each external interrupt will cause the processor to wake up from Power-down mode. See

Table 4–16

EXTMODE The External Interrupt Mode Register controls

whether each pin is edge- or level sensitive.

EXTPOLAR The External Interrupt Polarity Register controls

which level or edge on each pin will cause an interrupt.

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Chapter 4: LPC2210/20 System control

Address

[1]

value

R/W 0 0xE01F C140

R/W 0 0xE01F C144

R/W 0 0xE01F C148

R/W 0 0xE01F C14C

[1] Reset value reflects the data stored in used bits only. It does not include reserved bits content.

5.2 External Interrupt Flag register (EXTINT - 0xE01F C140)

When a pin is selected for its external interrupt function, the level or edge on that pin (selected by its bits in the EXTPOLAR a nd EXTMODE registers) will set its interrupt fla g in this register. This asserts the corresponding interrupt request to the VIC, which will cause an interrupt if interrupts from the pin are enabled.

Writing ones to bits EINT0 through EINT3 in EXTINT register clears the corre sp onding bits. In level-sensitive mode this action is efficacious only when the pin is in its inactive state.

Once a bit from EINT0 to EINT3 is set and an appropriate code star ts to execute (hand ling wakeup and/or external interrupt), this bit in EXTINT register must be cleared. Otherwise the event that was just triggered by activity on the EINT pin will not be recognized in the future.

Important: whenever a change of externa l interrupt operating mode (i.e. active level/edge) is performed (including the initialization of an external interrupt), the corresponding bit in the EXTINT register must be cleared! For details see Section

4–5.4 “External Interrupt Mode register (EXTMODE - 0xE01F C148)” and Section 4–5.5 “External Interrupt Polarity register (EXTPOLAR - 0xE01F C14C)”.

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Chapter 4: LPC2210/20 System control

For example, if a system wakes up from power-down using a low level on external interrupt 0 pin, its post-wakeup code must reset the EINT0 bit in order to a llow future entry into the power-down mode. If the EINT0 bit is left set to 1, subsequent attempt(s) to invoke power-down mode will fail. The same goes for external interrupt handling.

More details on power-down mode will be discussed in the following chapters.

Table 15. External Interrupt Flag register (EXTINT - address 0xE01F C140) bit description

Bit Symbol Description Reset

0 EINT0 In level-sensitive mode, this bit is set if the EINT0 function is selected for its pin, and the pin is in

1 EINT1 In level-sensitive mode, this bit is set if the EINT1 function is selected for its pin, and the pin is in

2 EINT2 In level-sensitive mode, this bit is set if the EINT2 function is selected for its pin, and the pin is in

3 EINT3 In level-sensitive mode, this bit is set if the EINT3 function is selected for its pin, and the pin is in

7:4 - Reserved, user software should not write ones to reserved bits. The value read from a reserved

value

0 its active state. In edge-sensitive mode, this bit is set if the EINT0 function is selected for its pin, and the selected edge occurs on the pin.

Up to two pins can be selected to perform the EINT0 function (see P0.1 and P0.16 description in "Pin Configuration" chapter page 63.)

This bit is cleared by writing a one to it, except in level sensitive mode when the pin is in its active state (e.g. if EINT0 is selected to be low level sensitive and a low level is present on the corresponding pin, this bit can not be cleared; this bit can be cleared only when the signal on the pin becomes high).

0 its active state. In edge-sensitive mode, this bit is set if the EINT1 function is selected for its pin, and the selected edge occurs on the pin.

Up to two pins can be selected to perform the EINT1 function (see P0.3 and P0.14 description in "Pin Configuration" chapter on page 63.)

This bit is cleared by writing a one to it, except in level sensitive mode when the pin is in its active state (e.g. if EINT1 is selected to be low level sensitive and a low level is present on the corresponding pin, this bit can not be cleared; this bit can be cleared only when the signal on the pin becomes high).

0 its active state. In edge-sensitive mode, this bit is set if the EINT2 function is selected for its pin, and the selected edge occurs on the pin.

Up to two pins can be selected to perform the EINT2 function (see P0.7 and P0.15 description in "Pin Configuration" chapter on page 63.)

This bit is cleared by writing a one to it, except in level sensitive mode when the pin is in its active state (e.g. if EINT2 is selected to be low level sensitive and a low level is present on the corresponding pin, this bit can not be cleared; this bit can be cleared only when the signal on the pin becomes high).

0 its active state. In edge-sensitive mode, this bit is set if the EINT3 function is selected for its pin, and the selected edge occurs on the pin.

Up to three pins can be selected to perform the EINT3 function (see P0.9, P0.20 and P0.30 description in "Pin Configuration" chapter on page 63.)

This bit is cleared by writing a one to it, except in level sensitive mode when the pin is in its active state (e.g. if EINT3 is selected to be low level sensitive and a low level is present on the corresponding pin, this bit can not be cleared; this bit can be cleared only when the signal on the pin becomes high).

NA bit is not defined.

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5.3 External interrupt Wakeup register (EXTWAKE - 0xE01F C144)

Enable bits in the EXTWAKE register allow the external interrupts and other sources to wake up the processor if it is in Power-down mode. The related EINTn function must be mapped to the pin in order for the wakeup process to take place. It is not nece ssary for the interrupt to be enabled in the Vectored Interrupt Controller for a wakeup to take place. This arrangement allows additional capabilities, such as having an external interrupt input wake up the processor from Power-down mode without causing an interrupt (simply resuming operation), or allowing an interrupt to be enabled during Power-down without waking the processor up if it is asserted (eliminating the need to disable the interrupt if the wakeup feature is not desirable in the application).

For an external interrupt pin to be a source that would wake up the microco ntroller from Power-down mode, it is also necessary to clear the corresponding bit in the External Interrupt Flag register (Section 4–5.2 on page 29

Table 16. Interrupt Wakeup register (INTWAKE - address 0xE01F C144) bit description

Bit Symbol Description Reset

0 EXTWAKE0 When one, assertion of EINT0 will wake up the processor from

1 EXTWAKE1 When one, assertion of EINT1 will wake up the processor from

2 EXTWAKE2 When one, assertion of EINT2 will wake up the processor from

3 EXTWAKE3 When one, assertion of EINT3 will wake up the processor from

7:4 - Reserved, user software should not write ones to reserved bits.

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Chapter 4: LPC2210/20 System control

value

Power-down mode.

The value read from a reserved bit is not defined.

5.4 External Interrupt Mode register (EXTMODE - 0xE01F C148)

The bits in this register select whether each EI NT pin is le vel- or edge- sensitive. Only pins that are selected for the EINT function (see chapter Pin Connect Block on page 75) and enabled via the VICIntEnable register (Section 5–4.4 “

(VICIntEnable - 0xFFFF F010)” on page 53) can cause interrupts from the External

Interrupt function (though of course pins selected for other functions may cause i nterrupt s from those functions).

Note: Software should only change a bit in this register when its interrupt is disabled in the VICIntEnable register, and should write the corresponding 1 to the EXTINT register before enabling (initializing) or re-enabling the interrupt, to clear the EXTINT bit that could be set by changing the mode.

Table 17. External Interrupt Mode register (EXTMODE - address 0xE01F C148) bit

description

Bit Symbol Value Description Reset

0 EXTMODE0 0 Level-sensitivity is selected for EINT0. 0

1 EINT0 is edge sensitive.

1 EXTMODE1 0 Level-sensitivity is selected for EINT1. 0

1 EINT1 is edge sensitive.

User manual Rev. 02 — 27 April 2007 31 of 290

Interrupt Enable Register

value

NXP Semiconductors

Table 17. External Interrupt Mode register (EXTMODE - address 0xE01F C148) bit

Bit Symbol Value Description Reset

2 EXTMODE2 0 Level-sensitivity is selected for EINT2. 0

3 EXTMODE3 0 Level-sensitivity is selected for EINT3. 0

7:4 - - Reserved, user software should not write ones to reserved

5.5 External Interrupt Polarity register (EXTPOLAR - 0xE01F C14C)

In level-sensitive mode, the bits in this register select whether the corresponding pin is high- or low-active. In edge-sensitive mode, they select whether the pin is rising- or falling-edge sensitive. Only pins that are selected for the EINT function (see "Pin Connect Block" chapter on page 76) and enabled in the VICIntEnable register (Section 5–4.4

“Interrupt Enable Register (VICIntEnable - 0xFFFF F010)” on page 53) can cause

interrupts from the External Interrupt function (though of course pins selected for other functions may cause interrupts from those functions).

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description

value

1 EINT2 is edge sensitive.

1 EINT3 is edge sensitive.

bits. The value read from a reserved bit is not defined.

Table 18. External Interrupt Polarity register (EXTPOLAR - address 0xE01F C14C) bit

description

Bit Symbol Value Description Reset

value

0 EXTPOLAR0 0 EINT0 is low-active or falling-edge sensitive (depending on

EXTMODE0).

1 EINT0 is high-active or rising-edge sensitive (depending on

EXTMODE0).

1 EXTPOLAR1 0 EINT1 is low-active or falling-edge sensitive (depending on

EXTMODE1).

1 EINT1 is high-active or rising-edge sensitive (depending on

EXTMODE1).

2 EXTPOLAR2 0 EINT2 is low-active or falling-edge sensitive (depending on

EXTMODE2).

1 EINT2 is high-active or rising-edge sensitive (depending on

EXTMODE2).

3 EXTPOLAR3 0 EINT3 is low-active or falling-edge sensitive (depending on

EXTMODE3).

1 EINT3 is high-active or rising-edge sensitive (depending on

EXTMODE3).

7:4 - - Reserved, user software should not write ones to reserved

bits. The value read from a reserved bit is not defined.

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GLITCH

FILTER

wakeup enable

(one bit of EXTWAKE)

APB Read of EXTWAKE

EINTi to wakeup timer

PCLK

interrupt flag

(one bit of EXTINT)

APB read of EXTINT

to VIC

EINTi

APB Bus Data

EXTMODEi

reset

write 1 to EXTINTi

EXTPOLARi

PCLK

D Q

PCLK

5.6 Multiple external interrupt pins

Software can select multiple pins for each of EINT3:0 in the Pin Select registers, which are described in chapter Pin Connect Block on page 75. The external interrupt logic for each of EINT3:0 receives the state of all of its associated pins from the pins’ receivers, along with signals that indicate whether each pin is selected for the EINT function. The external interrupt logic handles the case when m ore than one pin is so selected, dif ferently according to the state of its Mode and Polarity bits:

• In Low-Active Level Sensitive mode, the states of all pins selected for the same EINTx

• In High-Active Level Sensitive mode, the states of all pins selected for the same

• In Edge Sensitive mode, regardless of polarity, the pin with the lowest GPIO port

The signal derived by this logic processing multiple external interrupt pins is the EINTi signal in the following logic schematic Figure 4–14

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Chapter 4: LPC2210/20 System control

functionality are digitally combined using a positive logic AND gate.

EINTx functionality are digitally combined using a positive logic OR gate.

number is used. (Selecting multiple pins for an EINTx in edge-sensitive mode could be considered a programming error.)

For example, if the EINT3 function is selected in the PINSEL0 and PINSEL1 registers for pins P0.9, P0.20 and P0.30, and EINT3 is configured to be low level sensitive, the inputs from all three pins will be logically ANDed. When more than one EINT pin is logically ORed, the interrupt service routine can read the states of the pins from the GPIO port using the IO0PIN and IO1PIN registers, to determine which pin(s) caused the interrupt.

Fig 14. External interrupt logic

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6. Other system controls

Some aspects of controlling LPC2210/2220 and LPC2210/01 operat ion that do not fit into peripheral or other registers are grouped here.

6.1 System Control and Status flags register (SCS - 0xE01F C1A0)

Remark: This feature is available in LPC2210/01 and LPC2220 only.

Table 19. System Control and Status flags register (SCS - address 0xE01F C1A0) bit description

Bit Symbol Value Description Reset

0 GPIO0M GPIO port 0 mode selection. 0

1 GPIO1M GPIO port 1 mode selection. 0

31:2 - Reserved, user software should not write ones to reserved bits. The value read from

value

0 GPIO port 0 is accessed via APB addresses in a fashion compatible with previous

LCP2000 devices.

1 High speed GPIO is enabled on GPIO port 0, accessed via addresses in the on-chip

memory range. This mode includes the port masking feature described in the GPIO chapter on page page 83.

0 GPIO port 1 is accessed via APB addresses in a fashion compatible with previous

LCP2000 devices.

1 High speed GPIO is enabled on GPIO port 1, accessed via addresses in the on-chip

memory range. This mode includes the port masking feature described in the GPIO chapter on page page 83.

a reserved bit is not defined.

7. Memory mapping control

The Memory Mapping Control alters the mapping of the interrupt vectors that appear beginning at address 0x0000 0000. This allows code running in different memory spaces to have control of the interrupts.

7.1 Memory Mapping control register (MEMMAP - 0xE01F C040)

Whenever an exception handling is necessary , the microcontroller will fetch an instruction residing on the exception corresponding address as described in Table 2–3 “

Exception Ve ctor Locations ” on page 11. The MEMMAP register determines the source of

data that will fill this table.

ARM

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Table 20. Memory Mapping control register (MEMMAP - address 0xE01F C040) bit

Bit Symbol Value Description Reset

1:0 MAP 00 Boot Loader Mode. Interrupt vectors are re-mapped to Boot

7:2 - - Reserved, user software should not write ones to reserved

[1] The hardware reset value of the MAP1:0 bits is 00 for LPC2210/2220 and LPC2210/01 parts. The apparent

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description

value

[1]

Block. 01 Reserved. Do not use this option. 10 User RAM Mode. Interrupt vectors are re-mapped to Static

RAM. 1 1 User External memory Mode. Interrupt vectors are re-mapped

to external memory. Warning: Improper setting of this value may result in incorrect

operation of the device.

bits. The value read from a reserved bit is not defined.

reset value that the user will see will be altered by the Boot Loader code, which always runs initially at reset.

7.2 Memory mapping control usage notes

The Memory Mapping Control simply selects one out of three available sources of data (sets of 64 bytes each) necessary fo r handling ARM exceptions (interrupts).

For example, whenever a Software Interrupt request is generated, the ARM core will always fetch 32-bit data "residing" on 0x0000 0008 see Table 2–3 “

Locations” on page 11. This means that when MEMMAP[1:0]=10 (User RAM Mode), a

read/fetch from 0x0000 0008 will provide data stored in 0x4000 0008. In case of MEMMAP[1:0]=00 (Boot Loader Mode), a read/fetch from 0x0000 0008 will provide data available also at 0x7FFF E008 (Boot Block remapped from on-chip Bootloader). MEMMAP[1:1]=11 (User External Memory Mode) will result in fetching data from off-chip memory at location 0x8000 0008.

8. Phase Locked Loop (PLL)

The PLL accepts an input clock frequency in the range of 10 MHz to 25 MHz only. The input frequency is multiplied up the range of 10 MHz to 60 MHz (LPC2210) or 75 MHz (LPC2210/01 and LPC2220) for the CCLK clock using a Current Controlled Oscillators (CCO). The multiplier can be an integer value from 1 to 32 (in practice, the multiplier value cannot be higher than 7 due to the upper frequency limit of the CPU). The CCO operates in the range of 156 MHz to 320 MHz, so there is an additional divider in the loop to keep the CCO within its frequency range while the PLL is providing the desired output frequency. The output divider may be set to divide by 2, 4, 8, or 16 to produce the output clock. Since the minimum output divider value is 2, it is insured that the PLL output has a 50% duty cycle. A block diagram of the PLL is shown in Figure 4–15

ARM Exception Vector

PLL activation is controlled via the PLLCON register. The PLL multiplier and divider values are controlled by the PLLCFG register. These two registers are protected in order to prevent accidental alteration of PLL parameters or deactivation of the PLL. Since all chip operations, including the Watchdog Timer, are dependent on the PLL when it is providing the chip clock, accidental changes to the PLL setup could result in unexpected

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behavior of the microcontroller. The protection is accomplished by a feed sequence similar to that of the Watchdog Timer. Details are provided in the description of the PLLFEED register.

The PLL is turned off and bypassed following a chip Reset and when by en tering Power-down mode. The PLL is enabled by software only. The program must configure and activate the PLL, wait for the PLL to Lock, then connect to the PLL as a clock source.

8.1 Register description

The PLL is controlled by the registers shown in Table 4–21. More detailed descriptions follow.

Warning: Improper setting of the PLL values may result in incorre ct operation of the device!

Table 21. PLL registers

Name Description Access Reset

PLLCON PLL Control Register. Holding register for updating PLL control bits.

Values written to this register do not take effect until a valid PLL feed sequence has taken place.

PLLCFG PLL Configuration Register. Holding register for updating PLL

configuration values. Values written to this register do not take effect until a valid PLL feed sequence has taken place.

PLLSTAT PLL Status Register. Read-back register for PLL control and

configuration information. If PLLCON or PLLCFG have been written to, but a PLL feed sequence has not yet occurred, they will not reflect the current PLL state. Reading this register provides the actual values controlling the PLL, as well as the status of the PLL.

PLLFEED PLL Feed Register. This register enables loading of the PLL control

and configuration information from the PLLCON and PLLCFG registers into the shadow registers that actually affect PLL operation.

value

R/W 0 0xE01F C080

R/W 0 0xE01F C084

RO 0 0xE01F C088

WO NA 0xE01F C08C

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Address

[1]

[1] Reset value reflects the data stored in used bits only. It does not include reserved bits content.

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/2P

CLOCK

SYNCHRONIZATION

CCLK

PLLC

PLOCK

OSC

PLLE

PHASE-

FREQUENCY

DETECTOR

bypass

MSEL[4:0]

MSEL<4:0>

OUT

DIV-BY-M

CCO

PSEL[1:0]

direct

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Fig 15. PLL block diagram

8.2 PLL Control register (PLLCON - 0xE01F C080)

The PLLCON register contains the bits that enable and connect the PLL. Enabling the PLL allows it to attempt to lock to the current settings of the multiplier and divider values. Connecting the PLL causes the processor and all chip functions to run from the PLL output clock. Changes to the PLLCON register do not take effect until a correct PLL feed sequence has been given (see Section 4–8.7 “

PLL Feed register (PLLFEED 0xE01F C08C)” and Section 4–8.3 “PLL Configuration register (PLLCFG - 0xE01F C084)” on page 38).

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Table 22. PLL Control register (PLLCON - address 0xE01F C080) bit description

Bit Symbol Description Reset

0 PLLE PLL Enable. When one, and after a valid PLL feed, this bit will

1 PLLC PLL Connect. When PLLC and PLLE are both set to one, and after a

7:2 - Reserved, user software should not write ones to reserved bits. The

The PLL must be set up, enabled, and Lock established before it may be used as a clock source. When switching from the oscillator clock to the PLL output or vice versa, internal circuitry synchronizes the operation in order to ensure that glitches are not generate d. Hardware does not insure that the PLL is locked before it is connected or automatically disconnect the PLL if lock is lost during operation. In the event of loss of PLL lock, it is likely that the oscillator clock has become unstable and disconnecting the PLL will not remedy the situation.

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activate the PLL and allow it to lock to the requested frequency. See PLLSTAT register, Table 4–24

valid PLL feed, connects the PLL as the clock source for the microcontroller. Otherwise, the oscillator clock is used directly by the microcontroller. See PLLSTAT register, Table 4–24

value read from a reserved bit is not defined.

value

8.3 PLL Configuration register (PLLCFG - 0xE01F C084)

The PLLCFG register contains the PLL multiplier and divider values. Changes to the PLLCFG register do not take ef fect until a correct PLL fee d sequence has been give n (see

Section 4–8.7 “

PLL Feed register (PLLFEED - 0xE01F C08C)” on page 39). Calculations

for the PLL frequency, and multiplier and divider values are found in the PLL Frequency Calculation section on page 40.

Table 23. PLL Configuration register (PLLCF G - add ress 0xE01F C084) bit descriptio n

Bit Symbol Description Reset

4:0 MSEL PLL Multiplier value. Supplies the value "M" in the PLL frequency

calculations. Note: For details on selecting the right value for MSEL see Section

4–8.9 “PLL frequency calculation” on page 40.

6:5 PSEL PLL Divider value. Supplies the value "P" in the PLL frequency

calculations. Note: For details on selecting the right value for PSEL see Section

4–8.9 “PLL frequency calculation” on page 40.

7 - Reserved, user software should not write ones to reserved bits. The

value read from a reserved bit is not defined.

8.4 PLL Status register (PLLSTAT - 0xE01F C088)

value

The read-only PLLSTAT register provides the actual PLL parameters that are in effect at the time it is read, as well as the PLL status. PLLSTAT may disa gree with values found in PLLCON and PLLCFG because changes to those registers do not take effect until a proper PLL feed has occurred (see Section 4–8.7 “

PLL Feed register (PLLFEED -

0xE01F C08C)”).

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T able 24. PLL Status register (PLLSTAT - address 0xE01F C088) bit description

Bit Symbol Description Reset

4:0 MSEL Read-back for the PLL Multiplier value. This is the value currently

6:5 PSEL Read-back for the PLL Divider value. This is the value currently

7 - Reserved, user software should not write ones to reserved bits. The

8 PLL E Read-back for the PLL Enable bit. When one, the PLL is currently

9 PLLC Read-back for the PLL Connect bit. When PLLC and PLLE are both

10 PLOCK Reflects the PLL Lock status. When zero, the PLL is not locked.

15:11 - Reserved, user software should not write ones to reserved bits. The

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Chapter 4: LPC2210/20 System control

value

used by the PLL.

value read from a reserved bit is not defined.

0 activated. When zero, the PLL is turned off. This bit is automatically cleared when Power-down mode is activated.

0 one, the PLL is connected as the clock source for the microcontroller. When either PLLC or PLLE is zero, the PLL is bypassed and the oscillator clock is used directly by the microcontroller. This bit is automatically cleared when Power-down mode is activated.

0 When one, the PLL is locked onto the requested frequency.

NA value read from a reserved bit is not defined.

8.5 PLL Interrupt

The PLOCK bit in the PLLSTAT register is connected to the interrupt controller. This allows for software to turn on the PLL and continue with other functions witho ut having to wait for the PLL to achieve lock. When the interrupt occurs (PLOCK = 1), the PLL may be connected, and the interrupt disabled. For details on how to enable and disabl e the PLL interrupt, see Section 5–4.4 “

Interrupt Enable Register (VICIntEnable - 0xFFFF F010)” on page 53 and Section 5–4.5 “Interrupt Enable Clear Register (VICIntEnClear 0xFFFF F014)” on page 53.

8.6 PLL Modes

The combinations of PLLE and PLLC are shown in Table 4–25.

Table 25. PLL Control bit combinations

PLLC PLLE PLL Function

0 0 PLL is turned off and disconnected. The CCLK equals (system runs from) the

unmodified clock input.

0 1 The PLL is active, but not yet connected. The PLL can be connected after

PLOCK is asserted.

1 0 Same as 00 combination. This prevents the possibility of the PLL being

connected without also being enabled.

1 1 The PLL is active and has been connected as the system clock source.

CCLK/system clock equals the PLL output.

8.7 PLL Feed register (PLLFEED - 0xE01F C08C)

A correct feed sequence must be written to the PLLFEED register in order for changes to the PLLCON and PLLCFG registers to take effect. The feed sequence is:

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1. Write the value 0xAA to PLLFEED.

2. Write the value 0x55 to PLLFEED.

The two writes must be in the correct sequence, and must be consecutive APB bus cycles. The latter requirement implies that interrupts must be disabled for the duration of the PLL feed operation. If either of the feed values is incorrect, or one of the previously mentioned conditions is not met, any changes to the PLLCON or PLLCFG register will not become effective.

Table 26. PLL Feed register (PLLFEED - address 0xE01F C08C) bit description

Bit Symbol Description Reset

7:0 PLLFEED The PLL feed sequence must be written to this register in order for

8.8 PLL and Power-down mode

Power-down mode automatically turns off and disconnects activated PLL. Wakeup from Power-down mode does not automatically restore the PLL settings, this must be done in software. Ty pically, a routine to activate the PLL, wait for lock, and then connect the PLL can be called at the beginning of any interrupt service routine that might be called due to the wakeup. It is important not to attempt to restart the PLL by simply feeding it when execution resumes after a wakeup from Power-down mode. This would enable and connect the PLL at the same time, before PLL lock is established.

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value

0x00

PLL configuration and control register changes to take effect.

8.9 PLL frequency calculation

The PLL equations use the following parameters:

T able 27. Elements determining PLL’s frequency

Element Description

OSC

CCO

CCLK the PLL output frequency (also the processor clock frequency) M PLL Multiplier value from the MSEL bits in the PLLCFG register P PLL Divider value from the PSEL bits in the PLLCFG register

The PLL output frequency (when the PLL is both active and connected) is given by: CCLK = M × F

The CCO frequency can be computed as:

= CCLK × 2 × P or F

CCO

The PLL inputs and settings must meet the following:

the frequency from the crystal oscillator/external oscillator the frequency of the PLL current controlled oscillator

or CCLK = F

OSC

CCO

= F

/ (2 × P)

× M × 2 × P

OSC

• F

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is in the range of 10 MHz to 25 MHz.

OSC

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• CCLK is in the range of 10 MHz to F

(the maximum allowed frequency for the

max

microcontroller - determined by the system microcontroller is embedded in).

• F

is in the range of 156 MHz to 320 MHz.

CCO

8.10 Procedure for determining PLL settings

If a particular application uses the PLL, its configuration may be determined as follows:

1. Choose the desired processor operating frequency (CCLK). This may be based on processor throughput requirements, need to support a specific set of UART baud rates, etc. Bear in mind that peripheral devices may be running from a lower clock than the processor (see Section 4–11 “

2. Choose an oscillator frequency (F multiple of F

OSC

3. Calculate the value of M to configure the MSEL bits. M = CCLK / F the range of 1 to 32. The value written to the MSEL bits in PLLCFG is M − 1 (see

Table 4–29

4. Find a value for P to configure the PSEL bits, such that F frequency limits. F

is calculated using the equation given above. P must have one

CCO

of the values 1, 2, 4, or 8. The value written to the PSEL bits in PLLCFG is 00 for P = 1; 01 for P = 2; 10 for P = 4; 11 for P = 8 (see Table 4–28

Table 28. PLL Divider values

PSEL Bits (PLLCFG bit s [6:5]) Value of P

00 1 01 2 10 4 11 8

APB divider” on page 45).

). CCLK must be the whole (non-fractional)

OSC

. M must be in

OSC

is within its defined

CCO

Table 29. PLL Multiplier values

MSEL Bits (PLLCFG bits [4:0]) Value of M

00000 1 00001 2 00010 3 00011 4

... ...

11110 31 11111 32

8.11 PLL configuring examples

Example: System design asks for F

Based on these specifications, M = CCLK / Fosc = 60 MHz / 10 MHz = 6. Consequently, M - 1 = 5 will be written as PLLCFG[4:0].

User manual Rev. 02 — 27 April 2007 41 of 290

= 10 MHz and requires CCLK = 60 MHz.

OSC

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V alue for P can be d erived from P = F in range of 156 MHz to 320 MHz. Assuming the lowest allowed frequency for F

CCO

produces P = 2.67. The only solution for P that satisfies both of these requirements and is listed in Table 4–28

9. Power control

The LPC2210/2220 and LPC2210/01 support two reduced power modes: Idle mode and Power-down mode. In Idle mode, execution of instructions is suspended until either a Reset or interrupt occurs. Peripheral functions continue operation during Idle mode and may generate interrupts to cause the processor to resume execution. Idle mode eliminates power used by the processor itself, memory systems and related controllers, and internal buses.

In Power-down mode, the oscillator is shut down and the chip receives no internal clocks. The processor state and registers, peripheral registers, and internal SRAM values are preserved throughout Power-down mode and the logic levels of chip pins remain static. The Power-down mode can be terminated and normal operation resumed by either a Reset or certain specific interrupts that are able to function without clocks. Since all dynamic operation of the chip is suspended, Power-down mode reduces chip power consumption to nearly zero.

Entry to Power-down and Idle modes must be coordinated with program execution. Wakeup from Power-down or Idle modes via an interrupt resumes program execution in such a way that no instructions are lost, incomplete, or repeated. Wake up from Power-down mode is discussed further in Section 4–12 “

/ (CCLK x 2), using condition that F

CCO

= 156 MHz, P = 156 MHz / (2 x 60 MHz) = 1.3. The highest F

is P = 2. Therefore, PLLCFG[6:5] = 1 will be used.

Wakeup timer” on page 47.

CCO

frequency criteria

CCO

must be

A Power Control for Peripherals feature allows individual peripherals to be turned off if they are not needed in the application, resulting in additional power savings.

9.1 Register description

The Power Control function contains two registers, as shown in Table 4–30. More detailed descriptions follow.

Table 30. Power control registers

Name Description Access Reset

PCON Power Control Register. This register contains

control bits that enable the two reduced power operating modes of the microcontroller. See

Table 4–31

PCONP Power Control for Peripherals Register. This

register contains control bits that enable and disable individual peripheral functions, Allowing elimination of power consumption by peripherals that are not needed.

[1] Reset value reflects the data stored in used bits only. It does not include reserved bits content.

R/W 0x00 0xE01F C0C0

R/W 0x0000 1FBE 0xE01F C0C4

value

[1]

Address

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9.2 Power Control register (PCON - 0xE01F COCO)

The PCON register contains two bits. Writing a one to the corresponding bit causes entry to either the Power-down or Idle mode. If both bits are set, Power-down mode is entered.

Table 31. Power Control register (PCON - address 0xE01F COCO) bit description

Bit Symbol Description Reset

0 IDL Idle mode - when 1, this bit causes the processor clock to be stopped,

1 PD Power-down mode - when 1, this bit causes the oscillator and all

7:2 - Reserved, user software should not write ones to reserved bits. The

9.3 Power Control for Peripherals register (PCONP - 0xE01F COC4)

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value

0 while on-chip peripherals remain active. Any enabled interrupt from a peripheral or an external interrupt source will cause the processor to resume execution.

0 on-chip clocks to be stopped. A wakeup condition from an external interrupt can cause the oscillator to restart, the PD bit to be cleared, and the processor to resume execution.

NA value read from a reserved bit is not defined.

The PCONP register allows turning off selected peripheral functions for the purpose of saving power. This is accomplished by gating off the clock source to the specified peripheral blocks. A few peripheral functions cannot be turned off (i.e. the Watchdog timer, GPIO, the Pin Connect block, and the System Control block). Some peripherals, particularly those that include analog functions, may consume power that is not clock dependent. These peripherals may contain a separate disable control that turns off additional circuitry to reduce power. Each bit in PCONP controls one of the peripherals. The bit numbers correspond to the related peripheral number as shown in the APB peripheral map Table 2–2 “

APB peripheries and base addresses” in the "Memory

Addressing" chapter. If a peripheral control bit is 1, that peripheral is enabled. If a periph er al bit is 0, that

peripheral is disabled to conserve power. For example if bit 19 is 1, the I enabled. If bit 19 is 0, the I

C1 interface is disabled.

C1 interface is

Important: valid read from a peripheral register and valid write to a peripheral register is possible only if that peripheral is enabled in the PCONP register!

Table 32. Power Control for Peripherals register (PCONP - address 0xE01F C0C4) bit

description

Bit Symbol Description Reset

value

0 - Reserved, user software should not write ones to reserved bits. The

value read from a reserved bit is not defined. 1 PCTIM0 Timer/Counter 0 power/clock control bit. 1 2 PCTIM1 Timer/Counter 1 power/clock control bit. 1 3 PCUART0 UART0 power/clock control bit. 1 4 PCUART1 UART1 power/clock control bit. 1 5 PCPWM0 PWM0 power/clock control bit. 1 6 - Reserved, user software should not write ones to reserved bits. The

value read from a reserved bit is not defined.

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Table 32. Power Control for Peripherals register (PCONP - address 0xE01F C0C4) bit

Bit Symbol Description Reset

7 PCI2C The I2C interface power/clock control bit. 1 8 PCSPI0 The SPI0 interface power/clock control bit. 1 9 PCRTC The RTC power/clock control bit. 1 10 PCSPI1 The SPI1 interface power/clock control bit. 1 11 PCEMC The External Memory Controller power/clock control bit. 1 12 PCAD A/D Converter (ADC) power/clock control bit.

20:13 - Reserved, user software should not write ones to reserved bits. The

21 PCSSP The SSP power/clock control bit. This bit is available in LPC2210/01

31:22 - Reserved, user software should not write ones to reserved bits. The

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description

value

Note: Clear the PDN bit in the ADCR before clearing this bit, and set

this bit before setting PDN.

value read from a reserved bit is not defined.

and LPC2220 only.

Note: bits PCSPI1 and PCSSP can not be 1 at the same time. Built-in

hardware mechanism makes sure that at least one of them is 0. In

case attempt is made to have both of these bits set to 1, this will result

in PCSPI1 being 1 and PCSSP becoming 0.

value read from a reserved bit is not defined.

10. Reset

9.4 Power control usage notes

After every reset, the PCONP register contains the value that en ables all interfaces and peripherals controlled by the PCONP to be enabled. Therefore, apart from proper configuring via peripheral dedicated registers, the user’s application has no need to access the PCONP in order to start using any of the on-board peripherals.

Power saving oriented systems should have 1s in the PCONP register only in positions that match peripherals really used in the application. All other bits, declared to be "Reserved" or dedicated to the peripherals not used in the current application, must be cleared to 0.

Reset has two sources on the LPC2210/2220 and LPC2210/01: the RESET pin and Watchdog Reset. The RESET filter. Assertion of chip Reset by any sour ce starts the Wakeup Timer (see description in

Section 4–12 “

Wakeup timer” in this chapter), causing reset to remain asserted until the

external Reset is de-asserted, the oscillator is running, a fixed number of clocks have passed, and the on-chip circuitry has completed its initialization. The relationship between Reset, the oscillator, and the Wakeup Timer are shown in Figure 4–16

The Reset glitch filter allows the processor to ignore exte rn al re se t puls es that are very short, and also determines the minimum duration of RESET order to guarantee a chip reset. Once asserted, RESET crystal oscillator is fully running and an adequate signal is present on the X1 pin of the microcontroller. Assuming that an external crystal is used in the crystal oscillator

pin is a Schmitt trigger input pin with an additional glitch

that must be asserted in

pin can be deasserted only when

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ABP read of PDBIT in PCON

power

down

OSC

to other blocks

WAKEUP TIMER

watchdog

reset

external

reset

START

COUNT 2

oscillator

output (F

OSC

)

Reset to the on-chip circuitry

Reset to PCON.PD

write “1”

from APB

reset

EINT0 wakeup EINT1 wakeup EINT2 wakeup EINT3 wakeup

RTC wakeup

subsystem, after power on, the RESET pin should be asserted for 10 ms. For all subsequent resets when crystal oscillator is already running and stable signal is on the X1 pin, the RESET

When the internal Reset is removed, the processor begins executing at address 0, which is initially the Reset vector mapped from the Boot Block. At that point, all of the processor and peripheral registers have been initialized to predetermined values.

External and internal Resets have some small differences. An external Reset causes the value of certain pins to be latched to configure the part. External circuitry cannot determine when an internal Reset occurs in order to allow setting up those special pins, so those latches are not reloaded during an internal Reset. Pins that are examined during an external Reset for various purposes are: P1.20/TRACESYNC, P1.26/RTCK (see chapters "Pin Configuration" on page 63 and "Pin Connect Block" on page 75). Pin P0.14 (see "On-chip Serial Bootloader" chapter on p age 242) is examined by on-chip bootloader when this code is executed after every Reset.

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Chapter 4: LPC2210/20 System control

pin needs to be asserted for 300 ns only.

Fig 16. Reset block diagram including the wakeup timer

11. APB divider

The APB Divider determines the relationship between the processor clock (CCLK) and the clock used by peripheral devices (PCLK). The APB Divider serves two purposes.

The first is to provides peripherals with desired PCLK via APB bus so that they can operate at the speed chosen for the ARM processor. In order to achieve this, the APB bus may be slowed down to one half or one fourth of the processor clock rate. Because the

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PLL0

crystal oscillator or

external clock source

OSC

)

APB DIVIDER

processor clock

(CCLK)

APB clock

(PCLK)

APB bus must work properly at power up (and its timing cannot be altered if it does not work since the APB divider control registers reside on the APB bus), the default condition at reset is for the APB bus to run at one quarter speed.

The second purpose of the APB Divider is to allow power savings when an application does not require any peripherals to run at the full processor rate.

The connection of the APB Divider relative to the oscillator and the processor clock is shown in Figure 4–17 remains active (if it was running) during Idle mode.

1 1.1 Register description

Only one register is used to control the APB Divider.

Table 33. APB divider register map

Name Description Access Reset

APBDIV Controls the rate of the APB clock in relation to

. Because the APB Divider is connected to the PLL output, the PLL

the processor clock.

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Chapter 4: LPC2210/20 System control

Address

[1]

value

R/W 0x00 0xE01F C100

[1] Reset value reflects the data stored in used bits only. It does not include reserved bits content.

11.2 APBDIV register (APBDIV - 0xE01F C100)

The APB Divider register contains two bits, allowing three divide r values, as shown in

Table 4–34

T able 34. APB Divider register (APBDIV - address 0xE01F C100) bit description

Bit Symbol Value Description Reset

1:0 APBDIV 00 APB bus clock is one fourth of the processor clock. 00

7:2 - - Reserved, user software should not write ones to reserved

01 APB bus clock is the same as the processor clock. 10 APB bus clock is one half of the processor clock. 11 Reserved. If this value is written to the APBDIV register, it

has no effect (the previous setting is retained).

bits. The value read from a reserved bit is not defined.

value

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Fig 17. APB divider connections

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12. Wakeup timer

The purpose of the wakeup timer is to ensure that the oscillator and other analog functions required for chip operation are fully functional before the processor is allowed to execute instructions. This is important at power on, all types of Rese t, an d when e ve r any of the aforementioned functions are turned off for any reason. Since the oscillator and other functions are turned off during Power-down mode, any wakeup of the processor from Power-down mode makes use of the Wakeup Timer.

The Wakeup T i mer monitors the crystal oscillator as the means of checking whether it is safe to begin code execution. When power is applied to the chip, or some event caused the chip to exit Power-down mode, some time is required for the oscillator to produce a signal of sufficient amplitude to drive the clock logic. The amount of time depends on many factors, including the rate of V and its electrical characteristics (if a quartz crystal is used), as well as any other external circuitry (e.g. capacitors), and the characteristics of the oscillator itself under the existing ambient conditions.

Once a clock is detected, the Wake up T imer counts 4096 clocks, then enables the on-chip circuitry to initialize. When the onboard modules initialization is complete, the processor is released to execute instructions if the external Reset has been deasserted. In the case where an external clock source is used in the system (as opposed to a crystal connected to the oscillator pins), the possibility that there could be little or no delay for oscillator start-up must be considered. The Wakeup Timer design then ensures that any other required chip functions will be operational prior to the beginning of program execution.

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ramp (in the case of power on), the type of crystal

Any of the various Resets can bring the microcontroller out of power-down mode, as can the external interrupts EINT3:0. When one of these interrupts is enabled for wakeup and its selected event occurs, an oscillator wakeup cycle is started. The actual interrupt (if any) occurs after the wakeup timer expires, and is handled by the Vectored Interrupt Controller.

However, th e pin multiplexing on the LPC2210/2220 and LPC2210/01 (see chapters "Pin Configuration" on page 63 and "Pin Connect Block" on page 75) was designed to allow other peripherals to, in effect, bring the device out of Power-down mode. The following pin-function pairings allow interrupt s from eve nts relating to UART0 or 1, SPI 0 or 1, or the

C: RxD0 / EINT0, SDA / EINT1, SSEL0 / EINT2, RxD1 / EINT3, DCD1 / EINT1, RI1 /

EINT2, SSEL1 / EINT3. To put the device in Power-down mode and allow activity on one or more of these buses

or lines to power it back up, software should reprogram the pin function to External Interrupt, select the appropriate mode and polarity for the Interrupt, and then select Power-down mode. Upon wakeup software should restore the pin multiplexing to the peripheral function.

All of the bus- or line-activity indications in the list above happen to be low-active. If software wants the device to come out of power -down mode in response to activity on more than one pin that share the same EINTi channel, it should progr am low-level sensitivity for that channel, because only in level mode will the channel logically OR the signals to wake the device.

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The only flaw in this scheme is that the time to restart the oscillator prevents the LPC2210/2220 and LPC2210/01 from capturing the bus or line activity that wakes it up. Idle mode is more appropriate than power-down mode for devices that must capture and respond to external activity in a timely manner.

To summarize: on the LPC2210/2220 and LPC2210/01, the Wakeup Timer enforces a minimum reset duration based on the crystal oscillator, and is activated whenever there is a wakeup from Power-down mode or any type of Reset.

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1. Features

2. Description

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Chapter 5: Vectored Interrupt Controller (VIC)

Rev. 02 — 27 April 2007 User manual

• ARM PrimeCell Vectored Interrupt Controller

• 32 interrupt request inputs

• 16 vectored IRQ interrupts

• 16 priority levels dynamically assigned to interrupt requests

• Software interrupt generation

The Vectored Interrupt Controller (VIC) takes 32 interrupt request inputs and programmably assigns them into 3 categories, FIQ, vectored IRQ, and non-vectored IRQ. The programmable assignment scheme means that priorities of interrupts from the various peripherals can be dynamically assigned and adjusted.

Fast Interrupt reQuest (FIQ) requests have the high est priority. If more than one request is assigned to FIQ, the VIC ORs the requests to produce the FIQ signal to the ARM processor. The fastest po ssible FIQ latency is achieved when only one request is classified as FIQ, because then the FIQ service routine can simply start dealing with that device. But if more than one request is assigned to the FIQ class, the FIQ service routine can read a word from the VIC that identifies which FIQ source(s) is (are) requesting an interrupt.

Vectored IRQs have th e midd le pr iority, but only 16 of the 32 requests can be assigned to this category . Any of the 32 reque sts can be as signed to any of the 16 vectored IRQ slot s, among which slot 0 has the highest priority and slot 15 has the lowest.

Non-vectored IRQs have the lowest priority. The VIC ORs the requests from all the vectored and non-vectored IRQs to produce the

IRQ signal to the ARM processor. The IRQ service routine can start by reading a register from the VIC and jumping there. If any of the vectored IRQs are requesting, the VIC provides the address of the highest-priority req ue sting IRQs service routine, otherwise it provides the address of a default routine that is shared by all the non-vectored IRQs. The default routine can read another VIC register to see what IRQs are active.

All registers in the VIC are word registers. Byte and halfword reads and write are not supported.

Additional information on the Vectored Interrupt Controller is available in the ARM PrimeCell Vectored Interrupt Controller (PL190) documentation.

3. Register description

The VIC implements the registers shown in Table 5–35. More detailed descriptions follow.

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T able 35. VIC register map

Name Description Access Reset

VICIRQStatus IRQ Status Register. This register reads out

VICFIQStatus FIQ Status Requests. This register reads out

VICRawIntr Raw Interrupt Status Register. This register

VICIntSelect Interrupt Select Register. This register

VICIntEnable Interrupt Enable Register. This register

VICIntEnClr Interrupt Enable Clear Register. This register

VICSoftInt Software Interrupt Register. The contents of

VICSoftIntClear Software Interrupt Clear Register. This

VICProtection Protection enable register. This register

VICVectAddr Vector Address Registe r. When an IRQ

VICDefVectAddr Default Vector Address Register. This

VICVectAddr0 Vector address 0 register. Vector Address

VICVectAddr1 Vector address 1 register. R/W 0 0xFFFF F104 VICVectAddr2 Vector address 2 register. R/W 0 0xFFFF F108 VICVectAddr3 Vector address 3 register. R/W 0 0xFFFF F10C VICVectAddr4 Vector address 4 register. R/W 0 0xFFFF F110 VICVectAddr5 Vector address 5 register. R/W 0 0xFFFF F114 VICVectAddr6 Vector address 6 register. R/W 0 0xFFFF F118 VICVectAddr7 Vector address 7 register. R/W 0 0xFFFF F11C VICVectAddr8 Vector address 8 register. R/W 0 0xFFFF F120

the state of those interrupt requests that are enabled and classified as IRQ.

the state of those interrupt requests that are enabled and classified as FIQ.

reads out the state of the 32 interrupt requests / software interrupts, regardless of enabling or classification.

classifies each of the 32 interrupt requests as contributing to FIQ or IRQ.

controls which of the 32 interrupt requests and software interrupts are enabled to contribute to FIQ or IRQ.

allows software to clear one or more bits in the Interrupt Enable register.

this register are ORed with the 32 interrupt requests from various peripheral functions.

allows limiting access to the VIC registers by software running in privileged mode.

interrupt occurs, the IRQ service routine can read this register and jump to the value read.

Registers 0-15 hold the addresses of the Interrupt Service routines (ISRs) for the 16 vectored IRQ slots.

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Address

[1]

value

RO 0 0xFFFF F000

RO 0 0xFFFF F004

RO 0 0xFFFF F008

R/W 0 0xFFFF F00C

R/W 0 0xFFFF F010

WO 0 0xFFFF F014

R/W 0 0xFFFF F018

WO 0 0xFFFF F01C

R/W 0 0xFFFF F020

R/W 0 0xFFFF F030

R/W 0 0xFFFF F034

R/W 0 0xFFFF F100

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T able 35. VIC register map

Name Description Access Reset

VICVectAddr9 Vector address 9 register. R/W 0 0xFFFF F124 VICVectAddr10 Vector address 10 register . R/W 0 0xFFFF F128 VICVectAddr11 Vector address 11 register. R/W 0 0xFFFF F12C VICVectAddr12 Vector address 12 register . R/W 0 0xFFFF F130 VICVectAddr13 Vector address 13 register . R/W 0 0xFFFF F134 VICVectAddr14 Vector address 14 register . R/W 0 0xFFFF F138 VICVectAddr15 Vector address 15 register . R/W 0 0xFFFF F13C VICVectCntl0 Vector control 0 register. Vector Control

VICVectCntl1 Vector control 1 register. R/W 0 0xFFFF F204 VICVectCntl2 Vector control 2 register. R/W 0 0xFFFF F208 VICVectCntl3 Vector control 3 register. R/W 0 0xFFFF F20C VICVectCntl4 Vector control 4 register. R/W 0 0xFFFF F210 VICVectCntl5 Vector control 5 register. R/W 0 0xFFFF F214 VICVectCntl6 Vector control 6 register. R/W 0 0xFFFF F218 VICVectCntl7 Vector control 7 register. R/W 0 0xFFFF F21C VICVectCntl8 Vector control 8 register. R/W 0 0xFFFF F220 VICVectCntl9 Vector control 9 register. R/W 0 0xFFFF F224 VICVectCntl10 Vector control 10 register. R/W 0 0xFFFF F228 VICVectCntl11 Vector control 11 register. R/W 0 0xFFFF F22C VICVectCntl12 Vector control 12 register. R/W 0 0xFFFF F230 VICVectCntl13 Vector control 13 register. R/W 0 0xFFFF F234 VICVectCntl14 Vector control 14 register. R/W 0 0xFFFF F238 VICVectCntl15 Vector control 15 register. R/W 0 0xFFFF F23C

Registers 0-15 each control one of the 16 vectored IRQ slots. Slot 0 has the highest priority and slot 15 the lowest.

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Chapter 5: LPC2210/20 VIC

Address

[1]

value

R/W 0 0xFFFF F200

[1] Reset Value refers to the data stored in used bits only. It does not include reserved bits content.

4. VIC registers

The following section describes the VIC registers in the order in which they are used in the VIC logic, from those closest to the interrupt request inputs to those most abstracted for use by software. For most people, this is also the best order to read about the registers when learning the VIC.

4.1 Software Interrupt Register (VICSoftInt - 0xFFFF F018)

The contents of this register are ORed with the 32 interrup t requests from the various peripherals, before any other logic is applied.

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Table 36. Software Interrupt Register (VICSoftInt - address 0xFFFF F018) bit allocation

Reset value: 0x0000 0000

Bit 31 30 29 28 27 26 25 24 Symbol -------Access R/W R/W R/W R/W R/W R/W R/W R/W Bit 23 22 21 20 19 18 17 16 Symbol -----ADCEINT3EINT2 Access R/W R/W R/W R/W R/W R/W R/W R/W Bit 15 14 13 12 11 10 9 8 Symbol EINT1 EINT0 RTC PLL SPI1/SSP SPI0 I2C PWM Access R/W R/W R/W R/W R/W R/W R/W R/W Bit 7 6 5 4 3 2 1 0 Symbol UART1 UART0 TIMER1 TIMER0 ARMCore1 ARMCore0 - WDT Access R/W R/W R/W R/W R/W R/W R/W R/W

Table 37. Software Interrupt Register (VICSoftInt - address 0xFFFF F018) bit description

Bit Symbol Reset

Value Description

value

31-0 See

VICSoftInt bit allocation table.

0 0 Do not force the interrupt request with this bit number. Writing

zeroes to bits in VICSoftInt has no effect, see VICSoftIntClear (Section 5–4.2

1 Force the interrupt request with this bit number.

4.2 Software Interrupt Clear Register (VICSoftIntClear - 0xFFFF F01C)

This register allows software to clear one or more bits in the Software Interrupt register, without having to first read it.

Table 38. Software Interrupt Clear Register (VICSoftIntClear - 0xFFFF F01C)

VICSoftIntClear Description Reset

Value

31:0 1: writing a 1 clears the corresponding bit in the Software Interrupt

register, thus releasing the forcing of this request. 0: writing a 0 leaves the corresponding bit in VICSoftInt unchanged.

Table 39. Software Interrupt Clear Register (VICSoftIntClear - address 0xFFFF F01C) bit allocation

Reset value: 0x0000 0000

Bit 31 30 29 28 27 26 25 24 Symbol -------Access WO WO WO WO WO WO WO WO Bit 23 22 21 20 19 18 17 16 Symbol -----ADCEINT3EINT2 Access WO WO WO WO WO WO WO WO Bit 15 14 13 12 11 10 9 8 Symbol EINT1 EINT0 RTC PLL SPI1/SSP SPI0 I2C PWM Access WO WO WO WO WO WO WO WO

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Bit 7 6 5 4 3 2 1 0 Symbol UART1 UART0 TIMER1 TIMER0 ARMCore1 ARMCore0 - WDT Access WO WO WO WO WO WO WO WO

Table 40. Software Interrupt Clear Register (VICSoftIntClear - address 0xFFFF F01C) bit

description

Bit Symbol Reset

value

31-0 See

VICSoftIntClear bit allocation table.

0 0 Writing a 0 leaves the corresponding bit in VICSoftInt

Value Description

unchanged.

1 Writing a 1 clears the corresponding bit in the Software

Interrupt register, thus releasing the forcing of this request.

4.3 Raw Interrupt Status Register (VICRawIntr - 0xFFFF F008)

This is a read only register. This register reads out the state of the 32 interrupt requests and software interrupts, rega rdless of enabling or classification.

Table 41. Raw Interrupt Status Register (VICRawIntr - address 0xFFFF F008) b it description

VICRawIntr Description Reset

value

31:0 1: the interrupt request or software interrupt with this bit number is

asserted. 0: the interrupt request or software interrupt with this bit number is

negated.

4.4 Interrupt Enable Register (VICIntEnable - 0xFFFF F010)

This is a read/write accessible register. This register controls which of the 32 interrupt requests and software interrupts contribute to FIQ or IRQ.

Table 42. Interrupt Enable Register (VICINtEnable - addre ss 0xFFFF F010) bit description

VICIntEnable Description Reset

31:0 Wh en this register is read, 1s indicate interrupt requests or software

interrupts that are enabled to contribute to FIQ or IRQ. When this register is written, ones enable interrupt requests or software

interrupts to contribute to FIQ or IRQ, zeroes have no effect. See

Section 5–4.5 “ 0xFFFF F014)” on page 53 and Table 5–43 below for how to disable

interrupts.

Interrupt Enable Clear Register (VICIntEnClear -

4.5 Interrupt Enable Clear Register (VICIntEnClear - 0xFFFF F014)

This is a write only register. This register allows software to clear one or more bits in the Interrupt Enable register (Section 5–4.4

), without having to first read it.

value

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Table 43. Software Interrupt Clear Register (VICIntEnClear - address 0xFFFF F014) bit

VICIntEnClear Description Reset

31:0 1: writing a 1 clears the corresponding bit in the Interrupt Enable

4.6 Interrupt Select Register (VICIntSelect - 0xFFFF F00C)

This is a read/write accessible register. This register classifies each of the 32 interrupt requests as contributing to FIQ or IRQ.

T able 44. Interrupt Select Register (VICIntSelect - address 0xFFFF F00C) bit description

VICIntSelect Description Reset

31:0 1: the interrupt request with this bit number is assigned to the FIQ

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description

value

register, thus disabling interrupts for this request. 0: writing a 0 leaves the corresponding bit in VICIntEnable unchanged.

value

category. 0: the interrupt request with this bit number is assigned to the IRQ

category.

4.7 IRQ Status Register (VICIRQStatus - 0xFFFF F000)

This is a read only register. This register reads out the state of those interrupt requests that are enabled and classified as IRQ. It does not differentiate between vectored and non-vectored IRQs.

Table 45. IRQ Status Register (VICIRQStatus - address 0xFFFF F000) bit description

VICIRQStatus Description Reset

31:0 1: the interrupt request with this bit number is enabled, classified as

IRQ, and asserted.

4.8 FIQ Status Register (VICFIQStatus - 0xFFFF F004)

This is a read only register. This register reads out the state of those interrupt requests that are enabled and classified as FIQ. If more than one request is classified as FIQ, the FIQ service routine can read this register to see which request(s) is (are) active.

Table 46. FIQ Status Register (VICFIQStatus - address 0xFFFF F004) bit description

VICFIQStatus Description Reset

31:0 1: the interrupt request with this bit number is enabled, classified as

FIQ, and asserted.

value

4.9 Vector Control Registers 0-15 (VICvectCntl0-15 - 0xFFFF F200-23C)

These are a read/write accessible registers. Each of these registers controls one of the 16 vectored IRQ slots. Slot 0 has the highest priority and slot 15 the lowest. Note that disabling a vectored IRQ slot in one of the VICVectCntl registers does not disable the interrupt itself, the interrupt is simply changed to the non-vectored form.

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Table 47. Vector Control Registers (VICVectCntl0-15 - addresses 0xFFFF F200-23C) bit

VICVectCntl0-15 Description Reset

4:0 The number of the interrupt request or software interrupt assigned to

5 1: this vectored IRQ slot is enabled, and can produce a unique ISR

31:6 Reserved, user software should not write ones to reserved bits. The

4.10 Vector Address Registers 0-15 (VICVectAddr0-15 - 0xFFFF F100-13C)

These are a read/write accessible registers. These registers hold the addresses of the Interrupt Service routines (ISRs) for the 16 vectored IRQ slots.

T able 48. Vector Address Registers (VICVectAddr0-15 - addresses 0xFFFF F100-13C) bit

VICVectAddr0-15 Description Reset

31:0 When one or more interrupt request or software interrupt is (are)

description

this vectored IRQ slot. As a matter of good programming practice, software should not assign the same interrupt number to more than one enabled vectored IRQ slot. But if this does occur, the lower numbered slot will be used when the interrupt request or software interrupt is enabled, classified as IRQ, and asserted.

address when its assigned interrupt request or software interrupt is enabled, classified as IRQ, and asserted.

value read from a reserved bit is not defined.

description

enabled, classified as IRQ, asserted, and assigned to an enabled vectored IRQ slot, the valu e from this register for the highest-priority such slot will be provided when the IRQ service routine reads the Vector Address register -VICVectAddr (Section 5–4.10

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Chapter 5: LPC2210/20 VIC

value

4.11 Default Vector Address Register (VICDefVectAddr - 0xFFFF F034)

This is a read/write accessible register. This register holds the address of the Interrupt Service routine (ISR) for non-vectored IRQs.

Table 49. Default Vector Address Register (VICDefVectAddr - address 0xFFFF F034) bit

description

VICDefVectAddr Description Reset

value

31:0 When an IRQ service rout ine reads the Vector Address register

(VICVectAddr), and no IRQ slot responds as described above, this address is returned.

4.12 Vector Address Register (VICVectAddr - 0xFFFF F030)

This is a read/write accessible register. When an IRQ interrupt occurs, the IRQ service routine can read this register and jump to the value read.

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Table 50. Vector Address Register (VICVectAddr - address 0xFFFF F030) bit description

VICVectAddr Description Reset

31:0 If any of the interrupt requests or software interrupts that are assigned

4.13 Protection Enable Register (VICProtection - 0xFFFF F020)

This is a read/write accessible register. This one-bit register controls access to the VIC registers by software running in User mode.

Table 51. Protection Enable Register (VICProtection - address 0xFFFF F020) bit description

VICProtection Description Reset

0 1: the VIC registers can only be accessed in privileged mode.

31:1 Reserved, user software should not write ones to reserved bits. The

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Chapter 5: LPC2210/20 VIC

value

0 to a vectored IRQ slot is (are) enabled, classified as IRQ, and asserted, reading from this register returns the address in the Vector Address Register for the highest-priority such slot (lowest-numbered) such slot. Otherwise it returns the address in the Default Vector Address Register.

Writing to this register does not set the value for future reads from it. Rather, this register should be written near the end of an ISR, to update the priority hardware.

value

0 0: VIC registers can be accessed in User or privileged mode.

NA value read from a reserved bit is not defined.

5. Interrupt sources

Table 5–52 lists the interrupt sources for each peripheral function. Each perip heral device

has one interrupt line connected to the V ectored In terrupt Controller , but may have several internal interrupt flags. Individual interrupt flags may also represent more than one interrupt source.

Table 52. Connection of interrupt sources to the Vectored Interrupt Controller

Block Flag(s) VIC

WDT Watchdog Interrupt (WDINT) 0 0x0000 0001

- Reserved for software interrupts only 1 0x0000 0002 ARM Core Embedded ICE, DbgCommRx 2 0x0000 0004 ARM Core Embedded ICE, DbgCommTX 3 0x0000 0008 TIMER0 Match 0 - 3 (MR0, MR1, MR2, MR3)

TIMER1 Match 0 - 3 (MR0, MR1, MR2, MR3)

Capture 0 - 3 (CR0, CR1, CR2, CR3)

VIC Channel #

Hex

and Mask

4 0x0000 0010

5 0x0000 0020

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Table 52. Connection of interrupt sources to the Vectored Interrupt Controller

Block Flag(s) VIC

UART0 Rx Line Status (RLS)

UART1 Rx Line Status (RLS)

PWM Match 0 - 6 (MR0, MR1, MR2, MR3, MR4, MR5, MR6) 8 0x0000 0100

C SI (state change) 9 0x0000 0200

SPI0 SPI Interrupt Flag (SPIF)

SPI1 (SSP) Source: SPI1

PLL PLL Lock (PLOCK) 12 0x0000 1000 RTC Counter Increment (RTCCIF)

System Control External Interrupt 0 (EINT0) 14 0x0000 4000

ADC A/D Converter end of conversion 18 0x0004 0000 Reserved Reserved 19-31NA

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VIC Channel #

Hex

and Mask

6 0x0000 0040 Transmit Holding Register Empty (THRE) Rx Data Available (RDA) Character Time-out Indicator (CTI) Auto-Baud Time-Out (ABTO) End of Auto-Baud (ABEO)

7 0x0000 0080 Transmit Holding Register Empty (THRE) Rx Data Available (RDA) Character Time-out Indicator (CTI) Modem Status Interrupt (MSI) Auto-Baud Time-Out (ABTO) End of Auto-Baud (ABEO)

10 0x0000 0400 Mode Fault (MODF)

11 0x0000 0800 SPI Interrupt Flag (SPIF) Mode Fault (MODF) Source: SSP (in LPC2210/01 and LPC2220 only) TX FIFO at least half empty (TXRIS) Rx FIFO at least half full (RXRIS) Receive Timeout condition (RTRIS) Receive overrun (RORRIS)

13 0x0000 2000 Alarm (RTCALF)

External Interrupt 1 (EINT1) 15 0x0000 8000 External Interrupt 2 (EINT2) 16 0x0001 0000 External Interrupt 3 (EINT3) 17 0x0002 0000

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FIQSTATUS

[31:0]

VECTIRQ0

HARDWARE

PRIORITY

LOGIC

IRQSTATUS

[31:0]

nVICFIQ

NonVectIRQ

non-vectored IRQ interrupt logic

priority 0

nVICIRQ

VECTADDR0[31:0]

VECTIRQ1

VECTIRQ15

VECTADDR1[31:0]

VECTADDR15[31:0]

IRQ

address select for highest priority interrupt

VECTADDR

[31:0]

VICVECT

ADDROUT

[31:0]

DEFAULT

VECTADDR

[31:0]

priority15

priority2

priority1

VECTADDR

[31:0]

SOURCE

VECTCNTL[5:0]

ENABLE

vector interrupt 0

vector interrupt 1

vector interrupt 15

RAWINTERRUPT

[31:0]

INTSELECT

[31:0]

SOFTINT

[31:0]

INTENABLE

[31:0]

SOFTINTCLEAR

[31:0]

INTENABLECLEAR

[31:0]

VICINT

SOURCE

[31:0]

IRQSTATUS[31:0]

FIQSTATUS[31:0]

nVICFIQIN

non-vectored FIQ interrupt logic

interrupt priority logic

interrupt request, masking and selection

nVICIRQIN

VICVECTADDRIN[31:0]

IRQ

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Chapter 5: LPC2210/20 VIC

Fig 18. Block diagram of the Vectored Interrupt Controller (VIC)

6. Spurious interrupts

Spurious interrupts are possible in the ARM7TDMI based microcontrollers such as the LPC2210/2220 and LPC2210/01 due to asynchronous interrupt handling. The asynchronous character of the interrupt processing has its roots in the interaction of the core and the VIC. If the VIC state is changed between the moment s when the core detect s an interrupt, and the core actually processes an interrupt, problems may be gene rated.

Real-life applications may experience the following scenarios:

1. VIC decides there is an IRQ interrupt and sends the IRQ signal to the core.

2. Core latches the IRQ state.

3. Processing continues for a few cycles due to pipelining.

4. Core loads IRQ address from VIC.

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Furthermore, It is possible that the VIC state has changed during step 3. For example, VIC was modified so that the interrupt that triggered the sequence starting with step 1) is no longer pending -interrupt got disabled in the executed code. In this case, the VIC will not be able to clearly identify the interrupt that generated the interrupt request, and as a result the VIC will return the default interrupt VicDefVectAddr (0xFFFF F034).

This potentially disastrous chain of events can be prevented in two ways:

1. Application code should be set up in a way to prevent the spurious interrupts from

2. VIC default handler should be set up and tested properly.

6.1 Details and case studies on spurious interrupts

This chapter contains details that can be obtained from the official ARM website (FAQ section under the "Technical Support" link):

What happens if an interrupt occurs as it is being disabled?

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Chapter 5: LPC2210/20 VIC

occurring. Simple guarding of changes to the VIC may not be enough since, for example, glitches on level sensitive interrupts can also cause spurious interrupts.

Applies to: ARM7TDMI If an interrupt is received by the core during execution of an instruction that disables

interrupts, the ARM7 family will still take the interrupt. This occurs for both IRQ and FIQ interrupts.

For example, consider the following instruction sequence:

MRS r0, cpsr ORR r0, r0, #I_Bit:OR:F_Bit ;disable IRQ and FIQ interrupts MSR cpsr_c, r0

If an IRQ interrupt is received during execut ion of the MSR instruction, then the behavior will be as follows:

• The IRQ interrupt is latched.

• The MSR cpsr, r0 executes to completion setting both the I bit and the F bit in the

CPSR.

• The IRQ interrupt is taken because the core was committed to taking the interrupt

exception before the I bit was set in the CPSR.

• The CPSR (with the I bit and F bit set) is moved to the SPSR_IRQ.

This means that, on entry to the IRQ interrupt service routine, you can see the unusual effect that an IRQ interrupt has just been taken while the I bit in the SPSR is set. In the example above, the F bit will also be set in both the CPSR and SPSR. This means that FIQs are disabled upon entry to the IRQ service routine, and will remain so until explicitly re-enabled. FIQs will not be reenabled automatically by the IRQ return sequence.

Although the example shows both IRQ and FIQ interrupts be ing disabled, similar behavior occurs when only one of the two interrupt types is being disabled. The fact that the core processes the IRQ after completion of the MSR instruction which disables IRQs does not normally cause a problem, since an interrupt arriving just one cycle earlier would be expected to be taken. When the interrupt routine returns with an instruction like:

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SUBS pc, lr, #4

The SPSR_IRQ is restored to the CPSR. The CPSR will now have the I bit and F bit set, and therefore execution will continue with all interrupts disabled. However, this can cause problems in the following cases:

Problem 1: A particular routine maybe called as an IRQ handler, or as a regular subroutine. In the latter case, the system guarantees that IRQs would have been disabled prior to the routine being called. The routine exploits this restriction to determine how it was called (by examining the I bit of the SPSR), and returns using the appropriate instruction. If the routine is entered due to an IRQ being received during execution of the MSR instruction which disables IRQs, then the I bit in the SPSR will be set. The routine would therefore assume that it could not have been entered via an IRQ.

Problem 2: FIQs and IRQs are both disabled by the same write to the CPSR. In this case, if an IRQ is received during the CPSR write, FIQs will be disabled for the execution time of the IRQ handler. This may not be acceptable in a system where FIQs must not be disabled for more than a few cycles.

6.2 Workaround

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There are 3 suggested workarounds. Which of these is most applicable will depend upon the requirements of the particular system.

6.3 Solution 1: Test for an IRQ received during a write to disable IRQs

Add code similar to the following at the start of the interrupt routine.

SUB lr, lr, #4 ; Adjust LR to point to return STMFD sp!, {..., lr} ; Get some free regs MRS lr, SPSR ; See if we got an interrupt while TST lr, #I_Bit ; interrupts were disabled. LDMNEFD sp!, {..., pc}^ ; If so, just return immediately. ; The interrupt will remain pending since we haven’t ; acknowledged it and will be reissued when interrupts ; are next enabled. ; Rest of interrupt routine

This code will test for the situation where the IRQ was received during a write to disable IRQs. If this is the case, the code returns immediately - resulting in the IRQ not being acknowledged (cleared), and further IRQs being disabled.

Similar code may also be applied to the FIQ handler, in order to resolve the first issue. This is the recommended workaround, as it overcomes both problems mentioned above.

However, in the case of p roblem two, it do es add several cycles to the maximu m length of time FIQs will be disabled.

6.4 Solution 2: Disable IRQs and FIQs using separate writes to the CPSR

MRS r0, cpsr ORR r0, r0, #I_Bit ;disable IRQs MSR cpsr_c, r0 ORR r0, r0, #F_Bit ;disable FIQs

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MSR cpsr_c, r0

This is the best workaround where the maximum time for which FIQs are disabled is critical (it does not increase this time at all). However, it does not solve problem one, and requires extra instructions at every point where IRQs and FIQs are disabled together.

6.5 Solution 3: Re-enable FIQs at the beginning of the IRQ handler

As the required state of all bits in the c field of the CPSR are known, this can be most efficiently be achieved by writing an immediate value to CPSR_C, for example:

MSR cpsr_c, #I_Bit:OR:irq_MODE ;IRQ should be disabled ;FIQ enabled ;ARM state, IRQ mode

This requires only the IRQ handler to be modified, and FIQs may be re-enabled more quickly than by using workaround 1. However, this should only be used if the system can guarantee that FIQs are never disabled while IRQs are enabled. It does not address problem one.

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7. VIC usage notes

If user code is running from an on-chip RAM and an application uses interrupts, interrupt vectors must be re-mapped to on-chip address 0x0. This is necessary because all th e exception vectors are located at addresse s 0x 0 an d ab o ve. Th is is easily achieved by configuring the MEMMAP register (see Section 4–7.1 “

(MEMMAP - 0xE01F C040)” on page 34) to User RAM mode. Application code should be

linked such that at 0x4000 0000 the Interrupt Vector Table (IVT) will reside. Although multiple sources can be selected (VICIntSelect) to generate FIQ request, only

one interrupt service routine should be dedicated to service all available/present FIQ request(s). Therefore, if more than one interrupt sources are classified as FIQ the FIQ interrupt service routine must read VICFIQStatus to decide based on this content what to do and how to process the interrupt request. However, it is recommended that only one interrupt source should be classified as FIQ. Classifying more than one interrupt sources as FIQ will increase the interrupt latency.

Following the completion of the desired interrupt service routine, clearing of the interrupt flag on the peripheral level will propagate to corresponding bits in VIC registers (VICRawIntr, VICFIQStatus and VICIRQStatus). Also, before the next interrupt can be serviced, it is necessary that write is performed into the VICVectAddr register before the return from interrupt is executed. This write will clear the respective interrupt flag in the internal interrupt priority hardware.

Memory Mapping control register

In order to disable the interrupt at the VIC you need to clear corresponding bit in the VICIntEnClr register, which in turn clears the related bit in the VICIntEnable register. This also applies to the VICSoftInt and VICSoftIntClear in which VICSoftIntClear will clear the respective bits in VICSoftInt. For example, if VICSoftInt = 0x0000 0005 and bit 0 has to be cleared, VICSoftIntClear = 0x0000 0001 will accomplish this. Before the new clear operation on the same bit in VICSoftInt using writing into VICSoftIntClear is performed in the future, VICSoftIntClear = 0x0000 0000 must be assigned. Therefore writing 1 to any bit in Clear register will have one-time-effect in the destination register.

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If the watchdog is enabled for interrupt on underflow or invalid feed sequence only then there is no way of clearing the interrupt. The only way you could perform return from interrupt is by disabling the interrupt at the VIC (using VICIntEnClr).

Example: Assuming that UART0 and SPI0 are generating interrupt requests that are classified as vectored IRQs (UART0 being on the higher level than SPI0), while UART1 and I setup:

VICIntSelect = 0x0000 0000 ; SPI0, I2C, UART1 and UART0 are IRQ => ; bit10, bit9, bit7 and bit6=0 VICIntEnable = 0x0000 06C0 ; SPI0, I2C, UART1 and UART0 are enabled interrupts => ; bit10, bit9, bit 7 and bit6=1 VICDefVectAddr = 0x... ; holds address at what routine for servicing ; non-vectored IRQs (i.e. UART1 and I2C) starts VICVectAddr0 = 0x... ; holds address where UART0 IRQ service routine starts VICVectAddr1 = 0x... ; holds address where SPI0 IRQ service routine starts VICVectCntl0 = 0x0000 0026 ; interrupt source with index 6 (UART0) is enabled as ; the one with priority 0 (the highest) VICVectCntl1 = 0x0000 002A ; interrupt source with index 10 (SPI0) is enabled ; as the one with priority 1

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Chapter 5: LPC2210/20 VIC

C are generating non-vectored IRQs, the following could be one possibility for VIC

After any of IRQ requests (SPI0, I2C, UART0 or UART1) is made, microcontroller will redirect code execution to the address specified at location 0x0000 0018. For vectored and non-vectored IRQ’s the following instruction could be placed at 0x0000 0018:

LDR pc, [pc,#-0xFF0]

This instruction loads PC with the address that is present in VICVectAddr register. In case UART0 request has been made, VICVectAddr will be identical to VICVectAddr0,

while in case SPI0 request has been made value from VICVectAddr1 will be found here. If neither UART0 nor SPI0 have generated IRQ request but UART1 and/or I reason, content of VICVectAddr will be identical to VICDefVectAddr.

C were the

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LPC2210FBD144 LPC2220FBD144

LPC2210/01FBD144

108

144

109

002aaa794

002aab245

LPC2220/10FET144 LPC2210/01FET144

Transparent top view

24681012135791113

ball A1 index area

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Chapter 6: Pin configuration

Rev. 02 — 27 April 2007 User manual

1. LPC2210/2220 and LPC2210/01 pinout

Fig 19. LPC2210/2220 and LPC2210/01 pin configuration for 144-pin LQFP package

Fig 20. Ball configuration diagram for 144-pin TFBGA package

User manual Rev. 02 — 27 April 2007 63 of 290

xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx

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Table 53. Ball allocation

Row Column

A P2.22/

C P0.21/

D P0.24 P1.19/

E P2.25/

F P2.27/

G P2.29/

H P0.25 n.c. P0.27/

J P0.28/

K P3.27/WE P3.26/

xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx

1 2 3 4 5 6 7 8 9 10 11 12 13

D22

DD(3V3)

PWM5/ CAP1.3

D25

D27/ BOOT1

D29

AIN1/ CAP0.2/ MAT0.2

DDA(1V8)

P1.27/ TDO

TRACEP KT3

P2.24/ D24

P1.18/ TRACEP KT2

P2.28/ D28

CS1

P1.28/ TDI

XTAL2 V

XTAL1 V

P0.23 P0.22/

P2.23 V

DDA(3V3)

P2.30/ D30/AIN4

AIN0/ CAP0.1/ MAT0.1

P3.29/ BLS2/ AIN6

DD(3V3)

P2.21/ D21

SSA(PLL)

SSA

CAP0.0/ MAT0.0

P2.26/ D26/ BOOT0

P2.31/ D31/AIN5

P1.17/ TRACEP KT1

P3.28/ BLS3/ AIN7

P3.22/ A22

P2.18/ D18

P2.19/ D19

P2.14/ D14

P2.15/ D15

RESET P2.16/

D16

P2.20/ D20

P3.20/ A20

P2.17/ D17

P0.1/ RXD0/ PWM3/ EINT0

P1.29/ TCK

P2.12/ D12

P2.13/ D13

P3.14/ A14

P2.11/ D11

P0.20/ MAT1.3/ SSEL1/ EINT3

P0.19/ MAT1.2/ MOSI1/ CAP1.2

P0.18/ CAP1.3/ MISO1/ MAT1.3

P1.25/ EXTIN0

P2.10/

P2.7/D7 V

DD(3V3)

DD(1V8)

D10 V

DD(3V3)

P2.6/D6 V

P2.3/D3 V

P2.9/D9 P2.5/D5 P2.2/D2 P2.1/D1 V

P2.8/D8 P1.30/

TMS

P1.20/ TRACES YNC

P0.16/ EINT0/ MAT0.2/

P0.15/ RI1/ EINT2

P2.0/D0 P3.30/

CAP0.2 P3.31/

BLS0

P1.21/ PIPESTA

DD(3V3)

P0.14/

P1.0/CS0 P3.0/A0 P1.1/OE DCD1/ EINT1

P3.11/ A11

P0.13/ DTR1/ MAT1.1

P3.3/A3 P1.23/

DD(3V3)

P1.22/

PIPESTA

P0.10/

RTS1/

P3.2/A2 P3.1/A1

P0.11/ CTS1/ CAP1.1

CAP1.0

P2.4/D4

DD(3V3)

P0.17/ CAP1.2/ SCK1/ MAT1.2

BLS1

P0.12/ DSR1/ MAT1.0

P3.4/A4

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Table 53. Ball allocation

Row Column

L P0.29/

M P3.25/

xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx

1 2 3 4 5 6 7 8 9 10 11 12 13

AIN2/ CAP0.3/ MAT0.3

CS2

DD(1V8)

P0.30/ AIN3/ EINT3/ CAP0.0

P3.24/ CS3

…continued

P1.16/ TRACEP KT0

DD(3V3)

P3.23/ A23/ XCLK

P0.0/ TXD0/ PWM1

P1.31/ TRST

P3.21/ A21

P3.19/ A19

P3.18/ A18

P3.17/ A17

P0.2/ SCL/ CAP0.0

DD(3V3)

P1.26/ RTCK

P3.15/ A15

P3.16/ A16

P0.4/ SCK0/ CAP0.1

P0.3/ SDA/ MAT0.0/ EINT1

DD(3V3)

P3.12/ A12

P3.13/ A13

P0.5/ MISO0/ MAT0.1

P1.24/

TRACEC

P3.9/A9 P0.7/

SSEL0/

PWM2/

EINT2 P3.10/

A10

P0.6/

MOSI0/

CAP0.2

P0.8/ TXD1/ PWM4

P0.9/ RXD1/ PWM6/ EINT3

P3.7/A7 P3.5/A5

P3.8/A8 P3.6/A6

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Chapter 6: LPC2210/20 Pin configuration

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Chapter 6: LPC2210/20 Pin configuration

2. Pin description for LPC2210/2220 and LPC2210/01

Pin description for LPC2210/2220 and LPC2210/01 and a brief explanation of corresponding functions are shown in the following table.

(LQFP)

[1]

[2]

[3]

[1]

[2]

[1]

Pin (TFBGA)

N11

M11

L12

Type Description

for each bit. The operation of port 0 pins depends upon the pin function selected via the Pin Connect Block.

Pins 26 and 31 of port 0 are not available.

[1]

I/O P0.0 — General purpose digital input/output pin. O TXD0 — Transmitter output for UART0 O PWM1 — Pulse Width Modulator output 1

[2]

I/O P0.1 — General purpose digital input/output pin. I RxD0 — Receiver input for UART0 O PWM3 — Pulse Width Modulator output 3 I EINT0 — External interrupt 0 input

[3]

I/O P0.2 — General purpose digital input/output pin.

I/O SCL — I

C clock input/output. Open drain output (for I2C compliance)

I CAP0.0 — Capture input for Timer 0, chan nel 0

[3]

I/O P0.3 — General purpose digital input/output pin.

I/O SDA — I

C data input/output. Open drain output (for I2C compliance) O MAT0.0 — Match output for Timer 0, channel 0 I EINT1 — External interrupt 1 input

[1]

I/O P0.4 — General purpose digital input/output pin. I/O SCK0 — Serial clock for SPI0. SPI clock output from master or input to slave I CAP0.1 — Capture input for Timer 0, chan nel 0

[1]

I/O P0.5 — General purpose digital input/output pin. I/O MISO0 — Master In Slave OUT for SPI0. Data input to SPI master or data

output from SPI slave

O MAT0.1 — Match output for Timer 0, channel 1

[1]

I/O P0.6 — General purpose digital input/output pin. I/O MOSI0 — Master Out Slave In for SPI0. Data output from SPI master or data

input to SPI slave

I CAP0.2 — Capture input for Timer 0, chan nel 2

[2]

I/O P0.7 — General purpose digital input/output pin. I SSEL0 — Slave Select for SPI0. Selects the SPI interface as a slave O PWM2 — Pulse Width Modulator output 2 I EINT2 — External interrupt 2 input

[1]

I/O P0.8 — General purpose digital input/output pin. O TXD1 — Transmitter output for UART1 O PWM4 — Pulse Width Modulator output 4

Table 54. Pin description

Symbol Pin

P0.0 to P0.31 I/O Port 0: Port 0 is a 32-bit bidirectional I/O port with individual direction controls

P0.0/TXD0/ PWM1

P0.1/RxD0/ PWM3/EINT0

P0.2/SCL0/ CAP0.0

P0.3/SDA0/ MAT0.0/EINT1

P0.4/SCK0/ CAP0.1

P0.5/MISO0/ MAT0.1

P0.6/MOSI0/ CAP0.2

P0.7/SSEL0/ PWM2/EINT2

P0.8/TXD1/ PWM4

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Chapter 6: LPC2210/20 Pin configuration

Table 54. Pin description

Symbol Pin

(LQFP)

P0.9/RxD1/

[2]

PWM6/EINT3

P0.10/RTS1/

[1]

CAP1.0

P0.11/CTS1/

[1]

CAP1.1

P0.12/DSR1/

[1]

MAT1.0

P0.13/DTR1/

[1]

MAT1.1

P0.14/DCD1/

[2]

EINT1

P0.15/RI1/

[2]

EINT2

P0.16/EINT0/

100

[2]

MAT0.2/CAP0.2

P0.17/CAP1.2/

101

[1]

SCK1/MAT1.2

P0.18/CAP1.3/

121

[1]

MISO1/MAT1.3

…continued

Pin (TFBGA)

[2]

L13

[1]

K11

[1]

J12

[1]

J13

[1]

H10

[2]

G10

[2]

E11

[2]

E10

[1]

D13

[1]

Type Description

I/O P0.9 — General purpose digital input/output pin. I RxD1 — Receiver input for UART1 O PWM6 — Pulse Width Modulator output 6 I EINT3 — External interrupt 3 input I/O P0.10 — General purpose digital input/output pin. O RTS1 — Request to Send output for UART1. I CAP1.0 — Capture input for Timer 1, chan nel 0 I/O P0.11 — General purpose digital input/output pin. I CTS1 — Clear to Send input for UART1. I CAP1.1 — Capture input for Timer 1, chan nel 1. I/O P0.12 — General purpose digital input/output pin. I DSR1 — Data Set Ready input for UART1. O MAT1.0 — Match output for Timer 1, channel 0. I/O P0.13 — General purpose digital input/output pin. O DTR1 — Data Terminal Ready output for UART1. O MAT1.1 — Match output for Timer 1, channel 1. I/O P0.14 — General purpose digital input/output pin. I DCD1 — Data Carrier Detect input for UART1. I EINT1 — External interrupt 1 input

Note: LOW on this pin while RESET is LOW forces on-chip boot-loader to

take over control of the part after reset. I/O P0.15 — General purpose digital input/output pin. I RI1 — Ring Indicator input for UART1. I EINT2 — External interrupt 2 input. I/O P0.16 — General purpose digital input/output pin. I EINT0 — External interrupt 0 input. O MAT0.2 — Match output for Timer 0, channel 2. I CAP0.2 — Capture input for Timer 0, chan nel 2. I/O P0.17 — General purpose digital input/output pin. I CAP1.2 — Capture input for Timer 1, chan nel 2. I/O SCK1 — Serial Clock for SSP. Clock output from master or input to slave

(available in LPC2210/01 and LPC2220 only). O MAT1.2 — Match output for Timer 1, channel 2. I/O P0.18 — General purpose digital input/output pin. I CAP1.3 — Capture input for Timer 1, chan nel 3. I/O MISO1 — Master In Slave Out for SSP. Data input to SPI master or data

output from SSP slave (available in LPC2210/01 and LPC2220 only). O MAT1.3 — Match output for Timer 1, channel 3.

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[1]

…continued

Pin (TFBGA)

[1]

Type Description

I/O P0.19 — General purpose digital input/output pin. O MAT1.2 — Match output for Timer 1, channel 2.

Table 54. Pin description

Symbol Pin

(LQFP)

P0.19/MAT1.2/

122

MOSI1/CAP1.2

I/O MOSI1 — Master Out Slave In for SSP. Dat a output from SSP master or data

input to SSP slave (available in LPC2210/01 and LPC220 only). I CAP1.2 — Capture input for Timer 1, chan nel 2.

P0.20/MAT1.3/ SSEL1/EINT3

123

[2]

I/O P0.20 — General purpose digital input/output pin. O MAT1.3 — Match output for Timer 1, channel 3. I SSEL1 — Slave Select for SSP. Selects the SSP interface as a slave

(available in LPC2210/01 and LPC220 only). I EINT3 — External interrupt 3 input.

P0.21/PWM5/ CAP1.3

[1]

I/O P0.21 — General purpose digital input/output pin. O PWM5 — Pulse Width Modulator output 5. I CAP1.3 — Capture input for Timer 1, chan nel 3.

P0.22/ CAP0.0/MAT0.0

[1]

I/O P0.22 — General purpose digital input/output pin. I CAP0.0 — Capture input for Timer 0, chan nel 0. O MAT0.0 — Match output for Timer 0, channel 0.

P0.23 6 P0.24 8 P0.25 21 P0.27/AIN0/

CAP0.1/MAT0.1

[1] [1]

[1] [4]

D3 D1 H1 H3

[1] [1] [1] [4]

I/O P0.23 — General purpose digital input/output pin. I/O P0.24 — General purpose digital input/output pin. I/O P0.25 — General purpose digital input/output pin. I/O P0.27 — General purpose digital input/output pin. I AIN0 — A/D converter input 0. I CAP0.1 — Capture input for Timer 0, chan nel 1. O MAT0.1 — Match output for Timer 0, channel 1.

P0.28/AIN1/ CAP0.2/MAT0.2

[4]

I/O P0.28 — General purpose digital input/output pin. I AIN1 — A/D converter input 1. I CAP0.2 — Capture input for Timer 0, chan nel 2. O MAT0.2 — Match output for Timer 0, channel 2.

P0.29/AIN2/ CAP0.3/MAT0.3

[4]

I/O P0.29 — General purpose digital input/output pin. I AIN2 — A/D converter input 2. I CAP0.3 — Capture input for Timer 0, Channel 3. O MAT0.3 — Match output for Timer 0, channel 3.

P0.30/AIN3/ EINT3/CAP0.0

[4]

I/O P0.30 — General purpose digital input/output pin. I AIN3 — A/D converter input 3. I EINT3 — External interrupt 3 input. I CAP0.0 — Capture input for Timer 0, chan nel 0.

P1.0 to P1.31 I/O Port 1: Port 1 is a 32-bit bidirectional I/O port with individual direction controls

for each bit. The operation of port 1 pins depends upon the pin function

selected via the Pin Connect Block.

Pins 0 through 15 of port 1 are not available.

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Chapter 6: LPC2210/20 Pin configuration

[5]

…continued

Pin (TFBGA)

[5]

G11

Type Description

I/O P1.0 — General purpose digital input/output pin.

Table 54. Pin description

Symbol Pin

(LQFP)

P1.0/CS0 91

O CS0 — LOW-active Chip Select 0 signal.

(Bank 0 addresses range 0x8000 0000 to 0x80FF FFFF)

P1.1/OE 90

[5]

G13

[5]

I/O P1.1 — General purpose digital input/output pin. O OE — LOW-active Output Enable signal.

P1.16/ TRACEPKT0

P1.17/ TRACEPKT1

P1.18/ TRACEPKT2

P1.19/ TRACEPKT3

P1.20/ TRACESYNC

[5]

102

[5]

D12

[5]

I/O P1.16 — General purpose digital input/output pin. O TRACEPKT0 — Trace Packet, bit 0. Standard I/O port with internal pull-up.

[5]

I/O P1.17 — General purpose digital input/output pin. O TRACEPKT1 — Trace Packet, bit 1. Standard I/O port with internal pull-up.

[5]

I/O P1.18 — General purpose digital input/output pin. O TRACEPKT2 — Trace Packet, bit 2. Standard I/O port with internal pull-up.

[5]

I/O P1.19 — General purpose digital input/output pin. O TRACEPKT3 — Trace Packet, bit 3. Standard I/O port with internal pull-up.

[5]

I/O P1.20 — General purpose digital input/output pin. O TRACESYNC — Trace Synchronization. Standard I/O port with internal

pull-up.

Note: LOW on this pin while RESET is LOW enables pins P1.25:16 to operate

as Trace port afte r reset

P1.21/

PIPESTAT0 P1.22/

PIPESTAT1 P1.23/

PIPESTAT2 P1.24/

TRACECLK P1.25/EXTIN0 60

[5]

F11

H11

J11

L11

[5]

I/O P1.21 — General purpose digital input/output pin. O PIPESTAT0 — Pipeline Status, bit 0. Standard I/O port with internal pull-up.

[5]

I/O P1.22 — General purpose digital input/output pin. O PIPESTAT1 — Pipeline Status, bit 1. Standard I/O port with internal pull-up.

[5]

I/O P1.23 — General purpose digital input/output pin. O PIPESTAT2 — Pipeline Status, bit 2. Standard I/O port with internal pull-up.

[5]

I/O P1.24 — General purpose digital input/output pin. O TRACECLK — Trace Clock. Standard I/O port with internal pull-up.

[5]

I/O P1.25 — General purpose digital input/output pin. I EXTIN0 — External Trigger Input. Standard I/O with internal pull-up.

P1.26/RTCK 52

[5]

I/O P1.26 — General purpose digital input/output pin. I/O RTCK — Returned Test Clock output. Extra signal added to the JTAG port.

Assists debugger synchronization when processor frequency varies.

Bi-directional pin with internal pull-up.

Note: LOW on this pin while RESET

is LOW enables pins P1.31:26 to operate

as Debug port after reset

P1.27/TDO 144

[5]

I/O P1.27 — General purpose digital input/output pin. O TDO — Test Data out for JTAG interface.

P1.28/TDI 140

[5]

I/O P1.28 — General purpose digital input/output pin. I TDI — Test Data in for JTAG interface.

P1.29/TCK 126

[5]

I/O P1.29 — General purpose digital input/output pin. I TCK — Test Clock for JTAG interface.

P1.30/TMS 113

[5]

D10

[5]

I/O P1.30 — General purpose digital input/output pin. I TMS — Test Mode Select for JTAG interface.

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Chapter 6: LPC2210/20 Pin configuration

[5]

…continued

Pin (TFBGA)

[5]

Type Description

I/O P1.31 — General purpose digital input/output pin. I TRST

— Test Reset for JTAG interface.

Table 54. Pin description

Symbol Pin

(LQFP)

P1.31/TRST 43

P2.0 to P2.31 I/O Port 2 — Port 2 is a 32-bit bidirectional I/O port with individual direction

controls for each bit. The operation of port 2 pins depends upon the pin

function selected via the Pin Connect Block.

P2.0/D0 98

[5]

E12

[5]

I/O P2.0 — General purpose digital input/output pin. I/O D0 — External memory data line 0.

P2.1/D1 105

[5]

C12

[5]

I/O P2.1 — General purpose digital input/output pin. I/O D1 — External memory data line 1.

P2.2/D2 106

[5]

C11

[5]

I/O P2.2 — General purpose digital input/output pin. I/O D2 — External memory data line 2.

P2.3/D3 108

[5]

B12

[5]

I/O P2.3 — General purpose digital input/output pin. I/O D3 — External memory data line 3.

P2.4/D4 109

[5]

A13

[5]

I/O P2.4 — General purpose digital input/output pin. I/O D4 — External memory data line 4.

P2.5/D5 114

[5]

C10

[5]

I/O P2.5 — General purpose digital input/output pin. I/O D5 — External memory data line 5.

P2.6/D6 115

[5]

B10

[5]

I/O P2.6 — General purpose digital input/output pin. I/O D6 — External memory data line 6.

P2.7/D7 116

[5]

A10

[5]

I/O P2.7 — General purpose digital input/output pin. I/O D7 — External memory data line 7.

P2.8/D8 117

[5]

I/O P2.8 — General purpose digital input/output pin. I/O D8 — External memory data line 8.

P2.9/D9 118

[5]

I/O P2.9 — General purpose digital input/output pin. I/O D9 — External memory data line 9.

P2.10/D10 120

[5]

I/O P2.10 — General purpose digital input/output pin. I/O D10 — External memory data line 10.

P2.11/D11 124

[5]

I/O P2.11 — General purpose digital input/output pin. I/O D11 — External memory data line 11.

P2.12/D12 125

[5]

I/O P2.12 — General purpose digital input/output pin. I/O D12 — External memory data line 12.

P2.13/D13 127

[5]

I/O P2.13 — General purpose digital input/output pin. I/O D13 — External memory data line 13.

P2.14/D14 129

[5]

I/O P2.14 — General purpose digital input/output pin. I/O D14 — External memory data line 14.

P2.15/D15 130

[5]

I/O P2.15 — General purpose digital input/output pin. I/O D15 — External memory data line 15.

P2.16/D16 131

[5]

I/O P2.16 — General purpose digital input/output pin. I/O D16 — External memory data line 16.

P2.17/D17 132

[5]

I/O P2.17 — General purpose digital input/output pin. I/O D17 — External memory data line 17.

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Table 54. Pin description

Symbol Pin

(LQFP)

[5]

P2.18/D18 133

P2.19/D19 134

P2.20/D20 136

P2.21/D21 137

P2.22/D22 1

P2.23/D23 10

P2.24/D24 11

P2.25/D25 12

P2.26/D26/ BOOT0

P2.27/D27/

[5]

BOOT1

[5]

[2]

P2.28/D28 17

P2.29/D29 18

P2.30/D30/ AIN4

P2.31/D31/

[2]

AIN5

…continued

Pin (TFBGA)

[5]

[2]

Type Description

I/O P2.18 — General purpose digital input/output pin. I/O D18 — External memory data line 18. I/O P2.19 — General purpose digital input/output pin. I/O D19 — External memory data line 19. I/O P2.20 — General purpose digital input/output pin. I/O D20 — External memory data line 20. I/O P2.21 — General purpose digital input/output pin. I/O D21 — External memory data line 21. I/O P2.22 — General purpose digital input/output pin. I/O D22 — External memory data line 22. I/O P2.23 — General purpose digital input/output pin. I/O D23 — External memory data line 23. I/O P2.24 — General purpose digital input/output pin. I/O D24 — External memory data line 24. I/O P2.25 — General purpose digital input/output pin. I/O D25 — External memory data line 25. I/O P2.26 — General purpose digital input/output pin. I/O D26 — External memory data line 26. I BOOT0 — While RESET

is LOW, together with BOOT1 controls booting and internal operation. Internal pull-up ensures HIGH state if pin is left unconnected.

I/O P2.27 — General purpose digital input/output pin. I/O D27 — External memory data line 27. I BOOT1 — While RESET

is LOW, together with BOOT0 controls booting and internal operation. Internal pull-up ensures HIGH state if pin is left unconnected.

BOOT1:0 selects one of the following options:

- 00 selects 8-bit memory on CS0 for boot.

- 01 selects 16-bit memory on CS0 for boot.

- 10 selects 32-bit memory on CS0 for boot.

- 11 selects 16-bit memory on CS0 for boot.

I/O P2.28 — General purpose digital input/output pin. I/O D28 — External memory data line 28. I/O P2.29 — General purpose digital input/output pin. I/O D29 — External memory data line 29. I/O P2.30 — General purpose digital input/output pin. I/O D30 — External memory data line 30. I AIN4 — A/D converter, input 4. I/O P2.31 — General purpose digital input/output pin. I/O D31 — External memory data line 31. I AIN5 — A/D converter, input 5.

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Chapter 6: LPC2210/20 Pin configuration

Table 54. Pin description

Symbol Pin

(LQFP)

…continued

Pin (TFBGA)

Type Description

P3.0 to P3.31 I/O Port 3 — Port 3 is a 32-bit bidirectional I/O port with individual direction

controls for each bit. The operation of port 3 pins depends upon the pin function selected via the Pin Connect Block.

P3.0/A0 89

[5]

G12

[5]

I/O P3.0 — General purpose digital input/output pin. O A0 — External memory address line 0.

P3.1/A1 88

[5]

H13

[5]

I/O P3.1 — General purpose digital input/output pin. O A1 — External memory address line 1.

P3.2/A2 87

[5]

H12

[5]

I/O P3.2 — General purpose digital input/output pin. O A2 — External memory address line 2.

P3.3/A3 81

[5]

J10

[5]

I/O P3.3 — General purpose digital input/output pin. O A3 — External memory address line 3.

P3.4/A4 80

[5]

K13

[5]

I/O P3.4 — General purpose digital input/output pin. O A4 — External memory address line 4.

P3.5/A5 74

[5]

M13

[5]

I/O P3.5 — General purpose digital input/output pin. O A5 — External memory address line 5.

P3.6/A6 73

[5]

N13

[5]

I/O P3.6 — General purpose digital input/output pin. O A6 — External memory address line 6.

P3.7/A7 72

[5]

M12

[5]

I/O P3.7 — General purpose digital input/output pin. O A7 — External memory address line 7.

P3.8/A8 71

[5]

N12

[5]

I/O P3.8 — General purpose digital input/output pin. O A8 — External memory address line 8.

P3.9/A9 66

[5]

M10

[5]

I/O P3.9 — General purpose digital input/output pin. O A9 — External memory address line 9.

P3.10/A10 65

[5]

N10

[5]

I/O P3.10 — General purpose digital input/output pin. O A10 — External memory address line 10.

P3.11/A11 64

[5]

I/O P3.11 — General purpose digital input/output pin. O A11 — External memory address line 11.

P3.12/A12 63

[5]

I/O P3.12 — General purpose digital input/output pin. O A12 — External memory address line 12.

P3.13/A13 62

[5]

I/O P3.13 — General purpose digital input/output pin. O A13 — External memory address line 13.

P3.14/A14 56

[5]

I/O P3.14 — General purpose digital input/output pin. O A14 — External memory address line 14.

P3.15/A15 55

[5]

I/O P3.15 — General purpose digital input/output pin. O A15 — External memory address line 15.

P3.16/A16 53

[5]

I/O P3.16 — General purpose digital input/output pin. O A16 — External memory address line 16.

P3.17/A17 48

[5]

I/O P3.17 — General purpose digital input/output pin. O A17 — External memory address line 17.

P3.18/A18 47

[5]

I/O P3.18 — General purpose digital input/output pin. O A18 — External memory address line 18.

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Table 54. Pin description

Symbol Pin

(LQFP)

[5]

P3.19/A19 46

P3.20/A20 45

P3.21/A21 44

P3.22/A22 41

P3.23/A23/ XCLK

[5]

[2]

P3.24/CS3 36

P3.25/CS2 35

P3.26/CS1 30

P3.27/WE 29

P3.28/BLS3/ AIN7

P3.29/BLS2/

[4]

AIN6

135

[4]

[5]

[6]

[7] [7]

P3.30/BLS1 97

P3.31/BLS0 96

NC 22

RESET

XTAL1 142 XTAL2 141

…continued

Pin (TFBGA)

[5]

[2]

[4]

E13

[4]

F10

[5]

[6]

[7]

Type Description

I/O P3.19 — General purpose digital input/output pin. O A19 — External memory address line 19. I/O P3.20 — General purpose digital input/output pin. O A20 — External memory address line 20. I/O P3.21 — General purpose digital input/output pin. O A21 — External memory address line 21. I/O P3.22 — General purpose digital input/output pin. O A22 — External memory address line 22. I/O P3.23 — General purpose digital input/output pin. O A23 — External memory address line 23. O XCLK — Clock output. I/O P3.24 — General purpose digital input/output pin. O CS3 — LOW-active Chip Select 3 signal.

(Bank 3 addresses range 0x8300 0000 to 0x83FF FFFF)

I/O P3.25 — General purpose digital input/output pin. O CS2 — LOW-active Chip Select 2 signal.

(Bank 2 addresses range 0x8200 0000 to 82FF FFFF)

I/O P3.26 — General purpose digital input/output pin. O CS1 — LOW-active Chip Select 1 signal.

(Bank 1 addresses range 0x8100 0000 to 0x81FF FFFF)

I/O P3.27 — General purpose digital input/output pin. O WE — LOW-active Write enable signal. I/O P3.28 — General purpose digital input/output pin. O BLS3 — LOW-active Byte Lane Select signal (External Memory Bank 3). I AIN7 — A/D converter, input 7. I/O P3.29 — General purpose digital input/output pin. O BLS2 — LOW-active Byte Lane Select signal (External Memory Bank 2). I AIN6 — A/D converter, input 6. I/O P3.30 — General purpose digital input/output pin. O BLS1 — LOW-active Byte Lane Select signal (External Memory Bank 1). I/O P3.31 — General purpose digital input/output pin. O BLS0 — LOW-active Byte Lane Select signal (External Memory Bank 0).

Not connected. This pin MUST NOT be pulled LOW or the device might not operate properly.

I External reset input: A LOW on this pin resets the device, causing I/O ports

and peripherals to take on their default states, and processor execution to begin at address 0. TTL with hysteresis, 5 V tolerant.

I Input to the oscillator circuit and internal clock genera to r circui ts. O Output from the oscillator amplifier.

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Table 54. Pin description …continued

Symbol Pin

(LQFP)

3, 9, 26, 38, 54, 67, 79, 93, 103, 107, 111, 128

SSA

SSA(PLL)

DD(V18)

DDA(V18A)

DD(V3)

139 C4 I Analog ground: 0 V reference. This should nominally be the same voltage as

138 B4 I PLL analog ground: 0 V reference. This should nominally be the same

37, 110 N1, A12 I 1.8 V core power supply: This is the power supply voltage for internal

143 A2 I Analog 1.8 V core power supply: This is the power supply voltage for

2, 31, 39, 51, 57, 77, 94, 104, 1 12, 119

DDA(V3A)

14 F3 I Analog 3.3 V pad power su ppl y: This should be nominally the same voltage

Pin (TFBGA)

C2, E4, J2, N2, N7, L10, K12, F13, D1 1, B13, B1 1, D7

B1, K3, M3, M6, N8, K10, F12, C13, A1 1, B9

UM10114

Chapter 6: LPC2210/20 Pin configuration

Type Description

I Ground: 0 V reference.

VSS, but should be isolated to minimize noise and error.

voltage as VSS, but should be isolated to minimize noise and error.

circuitry.

internal circuitry. This should be nominally the same voltage as V should be isolated to minimize noise and error.

I 3.3 V pad power supply: This is the power supply voltage for the I/O ports.

as V

but should be isolated to minimize noise and error. This voltage is

DD(V3)

used to power the ADC.

DD(V18)

but

[1] 5 V tolerant pad providing digital I/O functions with TTL levels and hysteresis and 10 ns slew rate control. [2] 5 V tolerant pad providing digital I/O functions with TTL levels and hysteresis and 10 ns slew rate control. If configured for an input

function, this pad utilizes built-in glitch filter that blocks pulses shorter than 3 ns.

[3] Open drain 5 V tolerant digital I/O I

functionality.

[4] 5 V tolerant pad providing digital I/O (with TTL levels and hysteresis and 10 ns slew rate control) and analog input function. If configured

for a digital input function, this pad utilizes built-in glitch filter that blocks pulses shorter than 3 ns. When configured as an ADC input, digital section of the pad is disabled.

[5] 5 V tolerant pad with built-in pull-up resistor providing digital I/O functions with TTL levels and hysteresis and 10 ns slew rate control.

The pull-up resistor’s value ranges from 60 kΩ to 300 kΩ. [6] 5 V tolerant pad providing digital input (with TTL levels and hysteresis) function only. [7] Pad provides special analog functionality.

User manual Rev. 02 — 27 April 2007 74 of 290

C-bus 400 kHz specification compatible pad. It requires external pull-up to provide an output

1. Features

Allows individual pin configuration.

2. Applications

The purpose of the Pin Connect Block is to configure the microcontroller pins to the desired functions.

3. Description

The pin connect block allows selected pins of the microcontroller to have more than one function. Configuration registers control the multiplexers to allow connection between the pin and the on chip peripherals.

UM10114

Chapter 7: Pin connect block

Rev. 02 — 27 April 2007 User manual

Peripherals should be connected to the appropri ate pins prior to being activated, and prior to any related interrupt(s) being enabled. Activity of any enabled peripheral function that is not mapped to a related pin should be considered undefined.

Selection of a single function on a port pin completely excludes all other functions otherwise available on the same pin.

The only partial exception from the above rule of exclusion is the case of inputs to the A/D converter. Regardless of the function that is selected for the port pin that also hosts the A/D input, this A/D input can be read at any time and var iations of the vol t age level on this pin will be reflected in the A/D readings. However, valid analog reading(s) can be obtained if and only if the function of an analog input is selected. Only in this case proper interface circuit is active in between the physical pin and the A/D module. In all other cases, a par t of digital logic necessary for the digital function to be performed will be active, and will disrupt proper behavior of the A/D.

4. Register description

The Pin Control Module contains 2 registers as shown in Table 7–55 below.

Table 55. Pin connect block register map

Name Description Access Reset value Address

PINSEL0 Pin function select

PINSEL1 Pin function select

PINSEL2 Pin function select

R/W 0x0000 0000 0xE002 C000

R/W 0x1540 0000 0xE002 C004

R/W See Table 7–58

. 0xE002 C014

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Chapter 7: LPC2210/20 Pin connect block

4.1 Pin Function Select Register 0 (PINSEL0 - 0xE002 C000)

The PINSEL0 register controls the functions of the pins as per the settings listed in

Table 7–59

GPIO function is selected for a pin. For other functions, direction is controlled automatically.

Table 56. Pin Function Select Register 0 (PINSEL0 - address 0xE002 C000) bit description

Bit Symbol Value Function Value after reset

1:0 P0.0 00 GPIO Port 0.0 0

3:2 P0.1 00 GPIO Port 0.1 0

5:4 P0.2 00 GPIO Port 0.2 0

7:6 P0.3 00 GPIO Port 0.3 0

9:8 P0.4 00 GPIO Port 0.4 0

11:10 P0.5 00 GPIO Port 0.5 0

13:12 P0.6 00 GPIO Port 0.6 0

15:14 P0.7 00 GPIO Port 0.7 0

17:16 P0.8 00 GPIO Port 0.8 0

User manual Rev. 02 — 27 April 2007 76 of 290

. The direction control bit in the IO0DIR register is effective only when the

01 TXD (UART0) 10 PWM1 11 Reserved

01 RxD (UART0) 10 PWM3 11 EINT0

01 SCL (I 10 Capture 0.0 (Timer 0) 11 Reserved

01 SDA (I 10 Match 0.0 (Timer 0) 11 EINT1

01 SCK0 (SPI0) 10 Capture 0.1 (Timer 0) 11 Reserved

01 MISO0 (SPI0) 10 Match 0.1 (Timer 0) 11 Reserved

01 MOSI0 (SPI0) 10 Capture 0.2 (Timer 0) 11 Reserved

01 SSEL0 (SPI0) 10 PWM2 11 EINT2

01 TXD UART1 10 PWM4 11 Reserved

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Chapter 7: LPC2210/20 Pin connect block

Table 56. Pin Function Select Register 0 (PINSEL0 - address 0xE002 C000) bit description

Bit Symbol Value Function Value after reset

19:18 P0.9 00 GPIO Port 0.9 0

01 RxD (UART1) 10 PWM6 11 EINT3

21:20 P0.10 00 GPIO Port 0.10 0

01 RTS (UART1) 10 Capture 1.0 (Timer 1) 11 Reserved

23:22 P0.11 00 GPIO Port 0.11 0

01 CTS (UART1) 10 Capture 1.1 (Timer 1) 11 Reserved

25:24 P0.12 00 GPIO Port 0.12 0

01 DSR (UART1) 10 Match 1.0 (Timer 1) 11 Reserved

27:26 P0.13 00 GPIO Port 0.13 0

01 DTR (UART1) 10 Match 1.1 (Timer 1) 11 Reserved

29:28 P0.14 00 GPIO Port 0.14 0

01 CD (UART1) 10 EINT1 11 Reserved

31:30 P0.15 00 GPIO Port 0.15 0

01 RI (UART1) 10 EINT2 11 Reserved

4.2 Pin Function Select Register 1 (PINSEL1 - 0xE002 C004)

The PINSEL1 register controls the functions of the pins as per the settings listed in following tables. The direction control bit in the IO0DIR register is effective only when the GPIO function is selected for a pin. For other functions direction is controlled automatically.

Table 57. Pin Function Select Register 1 (PINSEL1 - address 0xE002 C004) bit description

Bit Symbol Value Function Value after reset

1:0 P0.16 00 GPIO Port 0.16 0

01 EINT0 10 Match 0.2 (Timer 0) 11 Capture 0.2 (Timer 0)

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Table 57. Pin Function Select Register 1 (PINSEL1 - address 0xE002 C004) bit description

Bit Symbol Value Function Value after reset

3:2 P0.17 00 GPIO Port 0.17 0

01 Capture 1.2 (Timer 1) 10 SCK1 (SPI1) 11 Match 1.2 (Timer 1)

5:4 P0.18 00 GPIO Port 0.18 0

01 Capture 1.3 (Timer 1) 10 MISO1 (SPI1) 11 Match 1.3 (Timer 1)

7:6 P0.19 00 GPIO Port 0.19 0

01 Match 1.2 (Timer 1) 10 MOSI1 (SPI1) 11 Match 1.3 (Timer 1)

9:8 P0.20 00 GPIO Port 0.20 0

01 Match 1.3 (Timer 1) 10 SSEL1 (SPI1) 11 EINT3

1 1:10 P0.21 00 GPIO Port 0.21 0

01 PWM5 10 Reserved 11 Match 1.3 (Timer 1)

13:12 P0.22 00 GPIO Port 0.22 0

01 Reserved 10 Capture 0.0 (Timer 0) 11 Match 0.0 (Timer 0)

15:14 P0.23 00 GPIO Port 0.23 0

01 Reserved 10 Reserved 11 Reserved

17:16 P0.24 00 GPIO Port 0.24 0

01 Reserved 10 Reserved 11 Reserved

19:18 P0.25 00 GPIO Port 0.25 0

01 Reserved 10 Reserved 11 Reserved

21:20 P0.26 00 Reserved 0

01 Reserved 10 Reserved 11 Reserved

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Table 57. Pin Function Select Register 1 (PINSEL1 - address 0xE002 C004) bit description

Bit Symbol Value Function Value after reset

23:22 P0.27 00 GPIO Port 0.27 0

01 AIN0 (A/D Converter) 10 Capture 0.1 (Timer 0) 11 Match 0.1 (Timer 0)

25:24 P0.28 00 GPIO Port 0.28 0

01 AIN1 (A/D Converter) 10 Capture 0.2 (Timer 0) 11 Match 0.2 (Timer 0)

27:26 P0.29 00 GPIO Port 0.29 0

01 AIN2 (A/D Converter) 10 Capture 0.3 (Timer 0) 11 Match 0.3 (Timer 0)

29:28 P0.30 00 GPIO Port 0.30 0

01 AIN3 (A/D Converter) 10 EINT3 11 Capture 0.0 (Timer 0)

31:30 P0.31 00 Reserved 0

01 Reserved 10 Reserved 11 Reserved

4.3 Pin Function Select Register 2 (PINSEL2 - 0xE002 C014)

The PINSEL2 register controls the functions of the pins as per the settings listed in

Table 7–58

only when the GPIO function is selected for a pin. For other functions direction is controlled automatically.

Warning: Use read-modify-write ope ra tion when accessing PINSEL2 register. Accidental write of 0 to bit 2 and/or bit 3 results in loss of debug and/or trace functionality! Changing of either bit 4 or bit 5 from 1 to 0 may cause an incorrect code execution!

Table 58. Pin Function Select Register 2 (PINSEL2 - 0xE002 C014) bit description

Bit Symbol Value Function Value after reset

1:0 - NA Reserved, user software should not write ones to reserved bits. The

2GPIO/

DEBUG

3GPIO/

TRACE

Controls the use of P1.31-26 pin s. 0 Pins P1.31-26 are used as GPIO pins. P1.26 1 Pins P1.31-26 are used as a Debug port. Controls the use of P1.25-16 pin s . P1.20 0 Pins P1.25-16 are used as GPIO pins. 1 Pins P1.25-16 are used as a Trace port.

. The direction control bit in the IO1DIR/IO2DIR/IO3DIR register is effective

value read from a reserved bit is not defined.

/RTCK

TRACESYNC

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Table 58. Pin Function Select Register 2 (PINSEL2 - 0xE002 C014) bit description

Bit Symbol Value Function Value after reset

5:4 CTRLDBP Controls the use of the data bus and strobe pins. At a reset triggered via the

RESET pin, these bits are loaded with the content from lines BOOT1:0; if a watchdog reset occurs, these two bits are loaded with the BOOT10_SAVE register content (see Section 7–5 “

Functions available based on PINSEL2[5:4] values Pins P1.1 OE P1.1 P2.7:0 D7:0 P2.7:0 P2.15:8 D15:8 P2.15:8 P2.27:16 D27:16 P2.27:16 P2.29:28 D29:28 P2.29:28 or reser v ed (s ee bi t 20 ) P2.30 D30 P2.30 or AIN4 (see bit 21) P2.31 D31 P2.31 or AIN5 (see bit 22) P1.0 CS0 P1.0 P3.31 BLS0 P3.31 P3.30 BLS1 P3.30 P3.28 BLS2 P3.28 or AIN6 (see bit 7) P3.29 BLS3 P3.29 or AIN7 (see bit 6)

10 01 00 11

Boot control” on page 82).

…continued

BOOT1:0 or BOOT10_SAVE

6 CTRLP329 If bits 5:4 are not 10, controls the use of pin P3.29: 1

0 P3.29 is a GPIO pin. 1 P3.29 is an ADC input pin (AIN6).

7 CTRLP328 If bits 5:4 are not 10, controls the use of pin P3.28: 1

0 P3.28 is a GPIO pin. 1 P3.28 is an ADC input pin (AIN7).

8 CTRLP327 Controls the use of pin P3.27: 0

0 P3.27 is a GPIO pin. 1 P3.27 is a Write Enable pin (WE).

10:9 - Reserved 11 CTRLP326 Controls the use of pin P3.26: 0

0 P3.26 is a GPIO pin. 1 P3.26 is a chip/memory bank select pin (CS1).

12 - NA Reserved 13 CTRLP323 If bits 25:23 are not 111, controls the use of pin P3.23/A23/XCLK: 0

0 P3.23 is a GPIO/address line pin (see bits 27:25). 1 P3.23 is XCLK output pin.

15:14 CTRLP325 Controls the use of pin P3.25: 00

00 P3.25 is a GPIO pin. 01 P3.25 is a chip/memory bank select pin (CS2). 10 Reserved 11 Reserved

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Table 58. Pin Function Select Register 2 (PINSEL2 - 0xE002 C014) bit description

Bit Symbol Value Function Value after reset

17:16 CTRLP324 Controls the use of pin P3.24: 00

00 P3.24 is a GPIO pin. 01 P3.24 is a chip/memory bank select pin (CS3). 10 Reserved 11 Reserved

19:18 - NA Reserved 20 CTRLP229_28If bits PINSEL2[5:4] are not 10, controls the use of pin P2.29:28: 0

0 P2.29 and P2.28 are GPIO pins. 1 Reserved

21 CTRLP230 If bits PINSEL2[5:4] are not 10, controls the use of pin P2.30: 1

0 P2.30 is a GPIO pin. 1 P2.30 is an ADC input pin (AIN4).

22 CTRLP231 If bits PINSEL2[5:4] are not 10, controls the use of pin P2.31: 1

0 P2.31 is a GPIO pin. 1 P2.31 is an ADC input pin (AIN5).

23 CTRLP300 Controls P3.0/A0 (if it is a port pin or an address line): 1 if BOOT1:0 = 00

0 P3.0/A0 is a GPIO pin. 1 P3.0/A0 is an address line.

24 CTRLP301 Controls 3.1/A1 (if it is a port pin or an address line): BOOT1

0 3.1/A1 is a GPIO pin. 1 3.1/A1 is an address line.

27:25 CTRLAB Controls the number of pins among P3.23/A23/XCLK and P3.22:2/A2.22:2 that

are address lines: 000 None 001 A3:2 are address lines. 010 A5:2 are address lines. 011 A7:2 are address lines. 100 A11:2 are address lines. 101 A15:2 are address lines. 1 10 A19:2 are address lines. 1 11 A23:2 are address lines.

31:28 - NA Reserved, user software should not write ones to reserved bits. The

value read from a reserved bit is not defined.

…continued

at RESET = 0, 0 otherwise

during

Reset

000 if BOOT1:0 = 11 at Reset; 111 otherwise

4.4 Pin function select register values

The PINSEL registers control the functions of device pins as shown below. Pairs of bits in these registers correspond to specific device pins.

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Table 59. Pin Function Select register Bits

PINSEL0 & PINSEL1 values Function Value after reset

00 Primary (default) function, typically GPIO port 00 01 First alternate function 10 Second alternate function 11 Reserved

The direction control bit in the IO0DIR/IO1DIR register is effective only when the GPIO function is selected for a pin. For other functions, direction is controlled automatically. Each derivative typically has a different pinout and theref or e a different set of fu nct ion s possible for each pin. Details for a specific derivative may be found in the appropriate data sheet.

5. Boot control

The state of the BOOT1:0 pins, while RESET is low, controls booting and initial operation. Internal pullups in the receivers ensure high state if a pin is left unconnected. Board designers can connect weak pulldown resistors (10 kΩ) or transistors that drive low while RESET is low, to these pins to select among the following options:

Table 60. Boot control on BOOT1:0

P2.27/D27/BOOT1 P2.26/D26/BOOT0 Boot from

0 0 8 bit memory on CS0 0 1 16 bit memory on CS0 1 0 32 bit memory on CS0 1 1 16 bit memory on CS0

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When LPC2210/2220 and LPC2210/01 hardware detects a rising edge on the Reset pin, it latches content from BOOT[1:0] pins and stores it into bits 5 and 4 of the BOOT10_SAVE register (0x3FFF 8030). Once this register is written, it is accessible for reading only.

Whenever the bootloader is executed, it reads the content of the BOOT10_SAVE register, and configures the PINSEL2 (address and data bus structure) together with other resources. For the bootloader flowchart details, see Figure 19–63 “

Boot process

flowchart” on page 246.

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1. Features

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• Every physical GPIO port is accessible via either the group of registers providing an

enhanced features and accelerated port access or the legacy group of registers

• Accelerated GPIO functions (available in LPC2210/01 and LPC2220 only):

– GPIO registers are relocated to the ARM local bus so that the fastest possible I/O

timing can be achieved

– Mask registers allow treating sets of port bits as a group, leaving other bits

unchanged

– All registers are byte and half-word addressable – Entire port value can be written in one instruction

• Bit-level set and clear registers allow a single instruction set or clear of an y number of

bits in one port

• Direction control of individual bits

• All I/O default to inputs after reset

• Backward compatibility with other earlier devices is maintained with legacy registers

appearing at the original addresses on the APB bus

2. Applications

• General purpose I/O

• Driving LEDs, or other indicators

• Controlling off-chip devices

• Sensing digital inputs

3. Pin description

Table 61. GPIO pin description

Pin Type Description

P0.0-P.31 P1.16-P1.31

P2.0-P2.31 P3.0-P3.31

4. Register description

LPC2210/2220 and LPC2210/01 have two 32-bit General Purpose I/O ports. Total of 30 out of 32 pins are available on PORT0. PORT1 has up to 16 pins available for GPIO functions. PORT0 and PORT1 are controlled via two groups of 4 registers as shown in

Table 8–62

and Table 8–63. Apart from them, LPC2210/2220 and LPC2210/01 have two

Input/ Output

General purpose input/output. The number of GPIOs actually available depends on the use of alternate functions.

External bus data/address lines shared with GPIO, digital and analog functions. The number of GPIOs/digital and analog functions actually available depends on the selected bus structure.

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additional 32-bit ports, PORT2 and PORT3, and they are configured to be used either as external memory data address and data bus, or as GPIOs sharing pin s wit h a hand fu l of digital and analog functions. Details on PORT2 and PORT3 usage can be found in Pin Configuration chapter on page 63 and Pin Connect Block chapter on page 75.

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Legacy registers shown in Table 8–62 devices, using existing code. The functions an d rela tive timin g of olde r GPI O implementations is preserved.

The registers in Table 8–63 PORT0 and PORT1 only. All of thes e re gis te rs ar e located directly on the local bus of the CPU for the fastest possible read and write timing. An additional feature has been added that provides byte addressability of all GPIO registers. A mask register allows treating groups of bits in a single GPIO port separately from other bits on the same port.

When PORT0 and/or PORT1 are used, user must select whether a these ports will be accessed via registers that provide enhanced features or a legacy set of registers (see

Section 4–6.1 “

34). While both of a port’s fast and legacy GPIO registers are controlling the same

physical pins, these two port control branches are mutually exclusive and operate independently. For example, changing a pin’s output via a fast register will not be observable via the corresponding legacy register.

The following text will refer to the legacy GPIO as "the slow" GPIO, while GPIO equipped with the enhanced features will be referred as "the fast" GPIO.

While the legacy registers are available on LPC2210/2220 and LPC2210/01 devices, registers controlling the enhanced features are available on LPC2210/01 and LPC2220 devices only.

System Control and Status flags register (SCS - 0xE01F C1A0)” on page

represent the enhanced GPIO features available on the

allow backward compatibility with earlier family

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Table 62. GPIO register map (legacy APB accessible registe rs)

Generic

Description Access Reset

Name

PORT0

[1]

value

Address & Name

IOPIN GPIO Port Pin value register.

The current state of the

R/W NA 0xE002 8000

IO0PIN GPIO configured port pins can always be read from this register, regardless of pin direction.

IOSET GPIO Port Output Set

R/W 0x0000

0000

0xE002 8004

IO0SET controls the state of output pins in conjunction with the IOCLR register. Writing ones produces highs at the corresponding port pins. Writing zeroes has no effect.

IODIR GPIO Port Direction control

R/W 0x0000

0000

0xE002 8008

IO0DIR individually controls the direction of each port pin.

IOCLR GPIO Port Output Clear

WO 0x0000

0000

0xE002 800C

IO0CLR controls the state of output pins. Writing ones produces lows at the corresponding port pins and clears the corresponding bits in the IOSET register. Writing zeroes has no effect.

PORT1 Address & Name

0xE002 8010 IO1PIN

0xE002 8014 IO1SET

0xE002 8018 IO1DIR

0xE002 801C IO1CLR

PORT2 Address & name

0xE002 8020 IO2PIN

0xE002 8024 IO2SET

0xE002 8028 IO2DIR

0xE002 802C IO2CLR

PORT3 Address & name

0xE002 8030 IO3PIN

0xE002 8034 IO3SET

0xE002 8038 IO3DIR

0xE002 803C IO3CLR

[1] Reset value reflects the data stored in used bits only. It does not include reserved bits content.

Table 63. GPIO register map (local bus accessible registers - enhanced features in LPC2210/01 and LPC220 only)

Generic

Description Access Reset

Name

FIODIR Fast GPIO Port Direction control register.

This register individually controls the

[1]

value

Address & Name

R/W 0x0000 0000 0x3FFF C000

FIO0DIR

PORT0

PORT1 Address & Name

0x3FFF C020 FIO1DIR

direction of each port pin.

FIOMASK Fast Mask register for port. Writes, sets,

clears, and reads to port (done via writes to

R/W 0x0000 0000 0x3FFF C010

FIO0MASK

0x3FFF C030

FIO1MASK FIOPIN, FIOSET , and FIOCLR, and reads of FIOPIN) alter or return only the bits enabled by zeros in this register.

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Table 63. GPIO register map (local bus accessible registers - enhanced features in LPC2210/01 and LPC220 only)

Generic Name

FIOPIN Fast Port Pin value register using FIOMASK.

FIOSET Fast Port Output Set register using

FIOCLR Fast Port Output Clear register using

Description Access Reset

value

R/W 0x0000 0000 0x3FFF C014 The current state of digital port pins can be read from this register, regardless of pin direction or alternate function selection (as long as pins is not configured as an input to ADC). The value read is masked by ANDing with FIOMASK. Writing to this register places corresponding values in all bits enabled by zeroes in FIOMASK.

R/W 0x0000 0000 0x3FFF C018 FIOMASK. This register controls the state of output pins. Writing 1s produces highs at the corresponding port pins. Writing 0s has no effect. Reading this register returns the current contents of the port output register. Only bits enabled by zeroes in FIOMASK can be altered.

WO 0x0000 0000 0x3FFF C01C FIOMASK0. This register controls the state of output pins. Writing 1s produces lows at the corresponding port pins. Writing 0s has no effect. Only bits enabled by zeroes in FIOMASK0 can be altered.

[1]

PORT0 Address & Name

FIO0PIN

FIO0SET

FIO0CLR

PORT1 Address & Name

0x3FFF C034 FIO1PIN

0x3FFF C038 FIO1SET

0x3FFF C03C FIO1CLR

[1] Reset value reflects the data stored in used bits only. It does not include reserved bits content.

4.1 GPIO port Direction register IODIR (IO0DIR - 0xE002 8008, IO1DIR 0xE002 8018, IO2DIR - 0xE002 8028, IO3DIR - 0xE002 8038, FIO0DIR 0x3FFF C000, FIO1DIR - 0x3FFF C020)

This word accessible register is used to control the direction of the pins when they are configured as GPIO port pins. Direction bit for any pin must be set according to the pin functionality.

Legacy registers are the IO0DIR, IO1DIR, IO2DIR and IO3DIR while the enhanced GPIO functions are supported via the FIO0DIR and FIO1DIR registers.

Table 64. GPIO port 0 Direction register (IO0DIR - address 0xE002 8008) bit description

Bit Symbol Value Description Reset value

31:0 P0xDIR

Table 65. GPIO port 1 Direction register (IO1DIR - address 0xE002 8018) bit description

Bit Symbol Value Description Reset value

31:0 P1xDIR

Slow GPIO Direction control bits. Bit 0 controls P0.0 ... bit 30 controls P0.30.

0 1 Controlled pin is output.

Controlled pin is input.

Slow GPIO Direction control bits. Bit 0 in IO1DIR controls P1.0 ... Bit 30 in IO1DIR controls P1.30.

Controlled pin is input.

0x0000 0000

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Table 66. GPIO port 2 Direction register (IO2DIR - address 0xE002 8028) bit description

Bit Symbol Value Description Reset value

31:0 P2xDIR

Slow GPIO Direction control bits. Bit 0 in IO2DIR controls P2.0 ... Bit 30 in

0x0000 0000

IO2DIR controls P2.30.

Controlled pin is input.

1 Controlled pin is output.

Table 67. GPIO port 3 Direction register (IO3DIR - address 0xE002 8038) bit description

Bit Symbol Value Description Reset value

31:0 P3xDIR

Slow GPIO Direction control bits. Bit 0 in IO3DIR controls P3.0 ... Bit 30 in

0x0000 0000

IO3DIR controls P3.30.

Controlled pin is input.

1 Controlled pin is output.

Table 68. Fast GPIO port 0 Direction register (FIO0DIR - address 0x3FFF C000) bit description

Bit Symbol Value Description Reset value

31:0 FP0xDIR

Fast GPIO Direction control bits. Bit 0 in FIO0DIR controls P0.0 ... Bit 30 in

0x0000 0000

FIO0DIR controls P0.30.

Controlled pin is input.

1 Controlled pin is output.

Table 69. Fast GPIO port 1 Direction register (FIO1DIR - address 0x3FFF C020) bit description

Bit Symbol Value Description Reset value

31:0 FP1xDIR

Fast GPIO Direction control bits. Bit 0 in FIO1DIR controls P1.0 ... Bit 30 in

0x0000 0000

FIO1DIR controls P1.30.

Controlled pin is input.

1 Controlled pin is output.

Aside from the 32-bit long and word only accessible FIODIR register, every fast GPIO port can also be controlled via several byte and half-word accessible registers listed in

Table 8–70

and Table 8–71, too. Next to providing the same functions as the FIOD IR

Table 70. Fast GPIO port 0 Direction control byte and half-word accessible register description

FIO0DIR0 8 (byte) 0x3FFF C000 Fast GPIO Port 0 Direction control register 0. Bit 0 in FIO0DIR0

FIO0DIR1 8 (byte) 0x3FFF C001 Fast GPIO Port 0 Direction control register 1. Bit 0 in FIO0DIR1

FIO0DIR2 8 (byte) 0x3FFF C002 Fast GPIO Port 0 Direction control register 2. Bit 0 in FIO0DIR2

Address Description Reset

value

0x00

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Table 70. Fast GPIO port 0 Direction control byte and half-word accessible register description

FIO0DIR3 8 (byte) 0x3FFF C003 Fast GPIO Port 0 Direction control register 3. Bit 0 in FIO0DIR3

FIO0DIRL 16

FIO0DIRU 16

(half-word)

Address Description Reset

0x3FFF C000 Fast GPIO Port 0 Direction control Lower half-word register. Bit 0 in

FIO0DIRL register corresponds to P0.0 ... bit 15 to P0.15.

0x3FFF C002 Fast GPIO Port 0 Direction control Upper half-word register. Bit 0 in

FIO0DIRU register corresponds to P0.16 ... bit 15 to P0.31.

value

0x00

0x0000

Table 71. Fast GPIO port 1 Direction control byte and half-word accessible register description

FIO1DIR0 8 (byte) 0x3FFF C020 Fast GPIO Port 1 Direction control register 0. Bit 0 in FIO1DIR0

FIO1DIR1 8 (byte) 0x3FFF C021 Fast GPIO Port 1 Direction control register 1. Bit 0 in FIO1DIR1

FIO1DIR2 8 (byte) 0x3FFF C022 Fast GPIO Port 1 Direction control register 2. Bit 0 in FIO1DIR2

FIO1DIR3 8 (byte) 0x3FFF C023 Fast GPIO Port 1 Direction control register 3. Bit 0 in FIO1DIR3

FIO1DIRL 16

FIO1DIRU 16

(half-word)

Address Description Reset

0x3FFF C020 Fast GPIO Port 1 Direction control Lower half-word register. Bit 0 in

FIO1DIRL register corresponds to P1.0 ... bit 15 to P1.15.

0x3FFF C022 Fast GPIO Port 1 Direction control Upper half-word register. Bit 0 in

FIO1DIRU register corresponds to P1.16 ... bit 15 to P1.31.

4.2 GPIO port output Set register IOSET (IO0SET - 0xE002 8004, IO1SET 0xE002 8014, IO2SET - 0xE002 8024, IO3SET - 0xE002 8034, FIO0SET

- 0x3FFF C018, FIO1SET - 0x3FFF C038)

This register is used to produce a HIGH level output at the port pins configured as GPIO in an OUTPUT mode. Writing 1 produces a HIGH level at the corresponding port pins. Writing 0 has no effect. If any pin is configured as an input or a se condary functio n, writing 1 to the corresponding bit in the IOSET has no effect.

value

0x00

0x0000

Reading the IOSET register returns the value of this register, as determined by previous writes to IOSET and IOCLR (or IOPIN as noted above). This value does not reflect the effect of any outside world influence on the I/O pins.

Legacy registers are the IO0SET, IO1SET, IO2SET and IO3SET while the enhanced GPIOs are supported via the FIO0SET and FIO1SET registers. Access to a port pins via the FIOSET register is conditioned by the corresponding FIOMASK register (see Section

8–4.5 “Fast GPIO port Mask register FIOMASK(FIO0MASK - 0x3FFF C010, FIO1MASK 0x3FFF C030)”).

Table 72. GPIO port 0 output Set register (IO0SET - address 0xE002 8004 bit description

Bit Symbol Description Reset value

31:0 P0xSET Slow GPIO output value Set bits. Bit 0 in IO0SET corres ponds to P0.0 ... Bit 30

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0x0000 0000

in IO0SET corresponds to P0.30.

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Table 73. GPIO port 1 output Set register (IO1SET - address 0xE002 8014) bit description

Bit Symbol Description Reset value

31:0 P1xSET Slow GPIO output value Set bits. Bit 0 in IO1SET corresponds to P1.0 ... Bit 30

0x0000 0000

in IO1SET corresponds to P1.30.

Table 74. GPIO port 2 output Set register (IO2SET - address 0xE002 8024) bit description

Bit Symbol Description Reset value

31:0 P2xSET Slow GPIO output value Set bits. Bit 0 in IO2SET corresponds to P2.0 ... Bit 30

0x0000 0000

in IO2SET corresponds to P2.30.

Table 75. GPIO port 3 output Set register (IO3SET - address 0xE002 8034) bit description

Bit Symbol Description Reset value

31:0 P3xSET Slow GPIO output value Set bits. Bit 0 in IO3SET corresponds to P3.0 ... Bit 30

0x0000 0000

in IO3SET corresponds to P3.30.

Table 76. Fast GPIO port 0 output Set register (FIO0SET - address 0x3FF F C018) bit description

Bit Symbol Description Reset value

31:0 FP0xSET Fast GPIO output value Set bits. Bit 0 in FIO0SET corresponds to P0.0 ... Bit 31

0x0000 0000

in FIO0SET corresponds to P0.31.

Table 77. Fast GPIO port 1 output Set register (FIO1SET - address 0x3FF F C038) bit description

Bit Symbol Description Reset value

31:0 FP1xSET Fast GPIO output value Set bits. Bit 0 Fin IO1SET corresponds to P1.0 ... Bit

0x0000 0000

31 in FIO1SET corresponds to P1.31.

Aside from the 32-bit long and word only accessible FIOSET register, every fast GPIO port can also be controlled via several byte and half-word accessible registers listed in

Table 8–78

and Table 8–79, too. Next to providing the same functions as the FIOSE T

Table 78. Fast GPIO port 0 output Set byte and half-word accessible register description

FIO0SET0 8 (byte) 0x3FFF C018 Fast GPIO Port 0 output Set register 0. Bit 0 in FIO0SET0 register

FIO0SET1 8 (byte) 0x3FFF C019 Fast GPIO Port 0 output Set register 1. Bit 0 in FIO0SET1 register

FIO0SET2 8 (byte) 0x3FFF C01A Fast GPIO Port 0 output Set register 2. Bit 0 in FIO0SET2 register

FIO0SET3 8 (byte) 0x3FFF C01B Fast GPIO Port 0 output Set register 3. Bit 0 in FIO0SET3 register

FIO0SETL 16

(half-word)

FIO0SETU 16

(half-word)

Address Description Reset

corresponds to P0.0 ... bit 7 to P0.7.

corresponds to P0.8 ... bit 7 to P0.15.

corresponds to P0.16 ... bit 7 to P0.23.

corresponds to P0.24 ... bit 7 to P0.31.

0x3FFF C018 Fast GPIO Port 0 output Set Lower half-word register. Bit 0 in

FIO0SETL register corresponds to P0.0 ... bit 15 to P0.15.

0x3FFF C01A Fast GPIO Port 0 output Set Upper half-word register. Bit 0 in

FIO0SETU register corresponds to P0.16 ... bit 15 to P0.31.

value

0x00

0x0000

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Table 79. Fast GPIO port 1 output Set byte and half-word accessible register description

Address Description Reset

& access

FIO1SET0 8 (byte) 0x3FFF C038 Fast GPIO Port 1 output Set register 0. Bit 0 in FIO1SET0 register

corresponds to P1.0 ... bit 7 to P1.7.

FIO1SET1 8 (byte) 0x3FFF C039 Fast GPIO Port 1 output Set register 1. Bit 0 in FIO1SET1 register

corresponds to P1.8 ... bit 7 to P1.15.

FIO1SET2 8 (byte) 0x3FFF C03A Fast GPIO Port 1 output Set register 2. Bit 0 in FIO1SET2 register

corresponds to P1.16 ... bit 7 to P1.23.

FIO1SET3 8 (byte) 0x3FFF C03B Fast GPIO Port 1 output Set register 3. Bit 0 in FIO1SET3 register

corresponds to P1.24 ... bit 7 to P1.31.

FIO1SETL 16

(half-word)

FIO1SETU 16

(half-word)

0x3FFF C038 Fast GPIO Port 1 output Set Lower half-word register. Bit 0 in

FIO1SETL register corresponds to P1.0 ... bit 15 to P1.15.

0x3FFF C03A Fast GPIO Port 1 output Set Upper half-word register. Bit 0 in

FIO1SETU register corresponds to P1.16 ... bit 15 to P1.31.

4.3 GPIO port output Clear register IOCLR (IO0CLR - 0xE002 800C, IO1CLR - 0xE002 801C, IO2CLR - 0xE002 802C, IO3CLR 0xE002 803C, FIO0CLR - 0x3FFF C01C, FIO1CLR - 0x3FFF C03C)

This register is used to produce a LOW level output at port pins configured as GPIO in an OUTPUT mode. Writing 1 produces a LOW leve l at the cor respond ing po rt pin a nd cle ars the corresponding bit in the IOSET register. Wr iting 0 has no effect. If any pin is configured as an input or a secondary function, writing to IOCLR has no effect.

value

0x00

0x0000

Legacy registers are the IO0CLR, IO1CLR, IO2CLR and IO3CLR while the enhanced GPIOs are supported via the FIO0CLR and FIO1CLR registers. Access to a port pins via the FIOCLR register is conditioned by the corresponding FIOMASK register (see Section

8–4.5 “Fast GPIO port Mask register FIOMASK(FIO0MASK - 0x3FFF C010, FIO1MASK 0x3FFF C030)”).

Table 80. GPIO port 0 output Clear register 0 (IO0CLR - address 0xE002 800C) bit description

Bit Symbol Description Reset value

31:0 P0xCLR Slow GPIO output value Clear bits. Bit 0 in IO0CLR corresponds to P0.0 ... Bit

Table 81. GPIO port 1 output Clear register 1 (IO1CLR - address 0xE002 801C) bit description

Bit Symbol Description Re set value

31:0 P1xCLR Slow GPIO output value Clear bits. Bit 0 in IO1CLR corresponds to P1.0 ... Bit

Table 82. GPIO port 2 output Clear register 2 (IO2CLR - address 0xE002 802C) bit description

Bit Symbol Description Re set value

31:0 P2xCLR Slow GPIO output value Clear bits. Bit 0 in IO2CLR corresponds to P1.0 ... Bit

0x0000 0000

31 in IO0CLR corresponds to P0.31.

0x0000 0000

31 in IO1CLR corresponds to P1.31.

0x0000 0000

30 in IO2CLR corresponds to P2.30.

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Table 83. GPIO port 3 output Clear register 3 (IO3CLR - address 0xE002 803C) bit description

Bit Symbol Description Re set value

31:0 P3xCLR Slow GPIO output value Clear bits. Bit 0 in IO3CLR corresponds to P1.0 ... Bit

0x0000 0000

30 in IO3CLR corresponds to P2.30.

Table 84. Fast GPIO port 0 output Clear register 0 (FIO0CLR - address 0x3FFF C01C) bit descrip tion

Bit Symbol Description Reset value

31:0 FP0xCLR Fast GPIO output value Clear bits. Bit 0 in FIO0CLR corresponds to P0.0 ... Bit

0x0000 0000

31 in FIO0CLR corresponds to P0.31.

Table 85. Fast GPIO port 1 output Clear register 1 (FIO1CLR - address 0x3FFF C03C) bit descrip tion

Bit Symbol Description Re set value

31:0 FP1xCLR Fast GPIO output value Clear bits. Bit 0 in FIO1CLR corresponds to P1.0 ... Bit

0x0000 0000

31 in FIO1CLR corresponds to P1.31.

Aside from the 32-bit long and word only accessible FIOCLR register, every fast GPIO port can also be controlled via several byte and half-word accessible registers listed in

Table 8–86

and Table 8–87, too. Next to providing the same functions as the FIOC LR

Table 86. Fast GPIO port 0 output Clear byte and half-word accessible register description

FIO0CLR0 8 (byte) 0x3FFF C01C Fast GPIO Port 0 output Clear register 0. Bit 0 in FIO0CLR0 register

FIO0CLR1 8 (byte) 0x3FFF C01D Fast GPIO Port 0 output Clear register 1. Bit 0 in FIO0CLR1 register

FIO0CLR2 8 (byte) 0x3FFF C01E Fast GPIO Port 0 output Clear register 2. Bit 0 in FIO0CLR2 register

FIO0CLR3 8 (byte) 0x3FFF C01F Fast GPIO Port 0 output Clear register 3. Bit 0 in FIO0CLR3 register

FIO0CLRL 16

(half-word)

FIO0CLRU 16

(half-word)

Address Description Reset

corresponds to P0.0 ... bit 7 to P0.7.

corresponds to P0.8 ... bit 7 to P0.15.

corresponds to P0.16 ... bit 7 to P0.23.

corresponds to P0.24 ... bit 7 to P0.31.

0x3FFF C01C Fast GPIO Port 0 output Clear Lower half-word register. Bit 0 in

FIO0CLRL register corresponds to P0.0 ... bit 15 to P0.15.

0x3FFF C01E Fast GPIO Port 0 output Clear Upper half-word register. Bit 0 in

FIO0SETU register corresponds to P0.16 ... bit 15 to P0.31.

value

0x00

0x0000

Table 87. Fast GPIO port 1 output Clear byte and half-word accessible register description

Address Description Reset

value

& access

FIO1CLR0 8 (byte) 0x3FFF C03C Fast GPIO Port 1 output Clear register 0. Bit 0 in FIO1CLR0 register

0x00

corresponds to P1.0 ... bit 7 to P1.7.

FIO1CLR1 8 (byte) 0x3FFF C03D Fast GPIO Port 1 output Clear register 1. Bit 0 in FIO1CLR1 register

0x00

corresponds to P1.8 ... bit 7 to P1.15.

FIO1CLR2 8 (byte) 0x3FFF C03E Fast GPIO Port 1 output Clear register 2. Bit 0 in FIO1CLR2 register

0x00

corresponds to P1.16 ... bit 7 to P1.23.

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Table 87. Fast GPIO port 1 output Clear byte and half-word accessible register description

FIO1CLR3 8 (byte) 0x3FFF C03F Fast GPIO Port 1 output Clear register 3. Bit 0 in FIO1CLR3 register

FIO1CLRL 16

FIO1CLRU 16

(half-word)

Address Description Reset

corresponds to P1.24 ... bit 7 to P1.31.

0x3FFF C03C Fast GPIO Port 1 output Clear Lower half-word register. Bit 0 in

FIO1CLRL register corresponds to P1.0 ... bit 15 to P1.15.

0x3FFF C03E Fast GPIO Port 1 output Clear Upper half-word register. Bit 0 in

FIO1CLRU register corresponds to P1.16 ... bit 15 to P1.31.

4.4 GPIO port Pin value register IOPIN (IO0PIN - 0xE002 8000, IO1PIN 0xE002 8010, IO2PIN - 0xE002 8020, IO3PIN - 0xE002 8030, FIO0PIN 0x3FFF C014, FIO1PIN - 0x3FFF C034)

This register provides the value of port pins that are configured to perform only digital functions. The register will give the logic value of the pin regardless of whether the pin is configured for input or output, or as GPIO or an alternate digital function. As an example, a particular port pin may have GPIO input, GPIO output, UART receive, and PWM output as selectable functions. Any configuration of that pin will allow its current logic state to be read from the corresponding IOPIN register.

value

0x00

0x0000

If a pin has an analog function as one of its options, the pin state cannot be r ead if the analog configuration is selected. Selecting the pin as an A/D input disconnect s the digital features of the pin. In that case, the pin value read in the IOPIN register is not valid.

Writing to the IOPIN register stores the value in the port output register, bypassing the need to use both the IOSET and IOCLR registers to obtain the entire written value. This feature should be used carefully in an application since it affects the entire port.

Legacy registers are the IO0PIN, IO1PIN, IO2PIN and IO3PIN while the enhanced GPIOs are supported via the FIO0PIN and FIO1PIN registers. Access to a port pins via the FIOPIN register is conditioned by the corresponding FIOMASK register (see Section

8–4.5 “Fast GPIO port Mask register FIOMASK(FIO0MASK - 0x3FFF C010, FIO1MASK 0x3FFF C030)”).

Only pins masked with zeros in the Mask register (see Section 8–4.5 “

Fast GPIO port Mask register FIOMASK(FIO0MASK - 0x3FFF C010, FIO1MASK - 0x3FFF C030)”) will

be correlated to the current content of the Fast GPIO port pin value register.

Table 88. GPIO port 0 Pin value register (IO0PIN - address 0xE002 8000) bit description

Bit Symbol Description Reset value

31:0 P0xVAL Slow GPIO pin value bits. Bit 0 in IO0PIN corresponds to P0.0 ... Bit 30 in IO0PIN

Table 89. GPIO port 1 Pin value register (IO1PIN - address 0xE002 8010) bit description

Bit Symbol Description Reset value

31:0 P1xVAL Slow GPIO pin value bits. Bit 0 in IO1PIN corresponds to P1.0 ... Bit 30 in IO1PIN

corresponds to P0.30.

corresponds to P1.30.

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Table 90. GPIO port 2 Pin value register (IO2PIN - address 0xE002 8020) bit description

Bit Symbol Description Reset value

31:0 P2xVAL Slow GPIO pin value bits. Bit 0 in IO2PIN corresponds to P1.0 ... Bit 30 in IO2PIN

corresponds to P2.30.

Table 91. GPIO port 3 Pin value register (IO3PIN - address 0xE002 8030) bit description

Bit Symbol Description Reset value

31:0 P3xVAL Slow GPIO pin value bits. Bit 0 in IO3PIN corresponds to P3.0 ... Bit 30 in IO3PIN

corresponds to P3.30.

Table 92. Fast GPIO port 0 Pin value register (FIO0PIN - address 0x3FFF C014) bit description

Bit Symbol Description Reset value

31:0 FP0xVAL Fast GPIO pin value bits. Bit 0 in FIO0PIN corresponds to P0.0 ... Bit 30 in FIO0PIN

corresponds to P0.30.

Table 93. Fast GPIO port 1 Pin value register (FIO1PIN - address 0x3FFF C034) bit description

Bit Symbol Description Reset value

31:0 FP1xVAL Fast GPIO pin value bits. Bit 0 in FIO1PIN corresponds to P1.0 ... Bit 30 in FIO1PIN

corresponds to P1.30.

Aside from the 32-bit long and word only acce ssible FIOPIN register , every fast GPIO port can also be controlled via several byte and half-word accessible registers listed in

Table 8–94

and Table 8–95, too. Next to providing the same functions as the FIOPIN

Table 94. Fast GPIO port 0 Pin value byte and half-word accessible register description

FIO0PIN0 8 (byte) 0x3FFF C014 Fast GPIO Port 0 Pin value register 0. Bit 0 in FIO0PIN0 register

FIO0PIN1 8 (byte) 0x3FFF C015 Fast GPIO Port 0 Pin value register 1. Bit 0 in FIO0PIN1 register

FIO0PIN2 8 (byte) 0x3FFF C016 Fast GPIO Port 0 Pin value register 2. Bit 0 in FIO0PIN2 register

FIO0PIN3 8 (byte) 0x3FFF C017 Fast GPIO Port 0 Pin value register 3. Bit 0 in FIO0PIN3 register

FIO0PINL 16

(half-word)

FIO0PINU 16

(half-word)

Address Description Reset

corresponds to P0.0 ... bit 7 to P0.7.

corresponds to P0.8 ... bit 7 to P0.15.

corresponds to P0.16 ... bit 7 to P0.23.

corresponds to P0.24 ... bit 7 to P0.31.

0x3FFF C014 Fast GPIO Port 0 Pin value Lower half-word register. Bit 0 in

FIO0PINL register corresponds to P0.0 ... bit 15 to P0.15.

0x3FFF C016 Fast GPIO Port 0 Pin value Upper half-word register. Bit 0 in

FIO0PINU register corresponds to P0.16 ... bit 15 to P0.31.

value

0x00

0x0000

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Table 95. Fast GPIO port 1 Pin value byte and half-word accessible register description

FIO1PIN0 8 (byte) 0x3FFF C034 Fast GPIO Port 1 Pin value register 0. Bit 0 in FIO1PIN0 register

FIO1PIN1 8 (byte) 0x3FFF C035 Fast GPIO Port 1 Pin value register 1. Bit 0 in FIO1PIN1 register

FIO1PIN2 8 (byte) 0x3FFF C036 Fast GPIO Port 1 Pin value register 2. Bit 0 in FIO1PIN2 register

FIO1PIN3 8 (byte) 0x3FFF C037 Fast GPIO Port 1 Pin value register 3. Bit 0 in FIO1PIN3 register

FIO1PINL 16

FIO1PINU 16

(half-word)

Address Description Reset

corresponds to P1.0 ... bit 7 to P1.7.

corresponds to P1.8 ... bit 7 to P1.15.

corresponds to P1.16 ... bit 7 to P1.23.

corresponds to P1.24 ... bit 7 to P1.31.

0x3FFF C034 Fast GPIO Port 1 Pin value Lower half-word register. Bit 0 in

FIO1PINL register corresponds to P1.0 ... bit 15 to P1.15.

0x3FFF C036 Fast GPIO Port 1 Pin value Upper half-word register. Bit 0 in

FIO1PINU register corresponds to P1.16 ... bit 15 to P1.31.

4.5 Fast GPIO port Mask register FIOMASK(FIO0MASK - 0x3FFF C010, FIO1MASK - 0x3FFF C030)

This register is available in the enhanced group of registers only. It is used to select port’s pins that will and will not be affected by a write accesses to the FIOPIN, FIOSET or FIOSLR register. Mask register also filters out port’s content when the FIOPIN register is read.

value

0x00

0x0000

A zero in this register’s bit enables an access to the corresponding physical pin via a read or write access. If a bit in this register is one, corresponding pin will not be changed with write access and if read, will not be reflected in the updated FIOPIN register. For software examples, see Section 8–5 “

Table 96. Fast GPIO port 0 Mask register (FIO0MASK - address 0x3FFF C010) bit description

Bit Symbol Value Description Reset value

31:0 FP0xMASK

Table 97. Fast GPIO port 1 Mask register (FIO1MASK - address 0x3FFF C030) bit description

Bit Symbol Value Description Reset value

31:0 FP1xMASK

Fast GPIO physical pin access control.

1 Physical pin is unaffected by writes into the FIOSET, FIOCLR and FIOPIN

Pin is affected by writes to the FIOSET, FIOCLR, and FIOPIN registers. Current state of the pin will be observable in the FIOPIN register.

registers. When the FIOPIN register is read, the coresponding physical pin will be represented as 0.

Fast GPIO physical pin access control. Pin is affected by writes to the FIOSET, FIOCLR, and FIOPIN registers.

Current state of the pin will be observable in the FIOPIN register.

registers. When the FIOPIN register is read, the coresponding physical pin will be represented as 0.

GPIO usage notes” on page 95

0x0000 0000

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Aside from the 32-bit long and word only accessible FIOMASK register, every fast GPIO port can also be controlled via several byte and half-word accessible registers listed in

Table 8–98

and Table 8–99, too. Next to providing the same functions as the FIOMASK

Table 98. Fast GPIO port 0 Mask byte and half-word accessible register description

FIO0MASK0 8 (byte) 0x3FFF C010 Fast GPIO Port 0 Mask register 0. Bit 0 in FIO0MASK0 register

FIO0MASK1 8 (byte) 0x3FFF C011 Fast GPIO Port 0 Mask register 1. Bit 0 in FIO0MASK1 register

FIO0MASK2 8 (byte) 0x3FFF C012 Fast GPIO Port 0 Mask register 2. Bit 0 in FIO0MASK2 register

FIO0MASK3 8 (byte) 0x3FFF C013 Fast GPIO Port 0 Mask register 3. Bit 0 in FIO0MASK3 register

FIO0MASKL 16

FIO0MASKU 16

(half-word)

Address Description Reset

corresponds to P0.0 ... bit 7 to P0.7.

corresponds to P0.8 ... bit 7 to P0.15.

corresponds to P0.16 ... bit 7 to P0.23.

corresponds to P0.24 ... bit 7 to P0.31.

0x3FFF C010 Fast GPIO Port 0 Mask Lower half-word register. Bit 0 in

FIO0MASKL register corresponds to P0.0 ... bit 15 to P0.15.

0x3FFF C012 Fast GPIO Port 0 Mask Upper half-word register. Bit 0 in

FIO0MASKU register corresponds to P0.16 ... bit 15 to P0.31.

value

0x00

0x0000

Table 99. Fast GPIO port 1 Mask byte and half-word accessible register description

FIO1MASK0 8 (byte) 0x3FFF C010 Fast GPIO Port 1 Mask register 0. Bit 0 in FIO1MASK0 register

FIO1MASK1 8 (byte) 0x3FFF C011 Fast GPIO Port 1 Mask register 1. Bit 0 in FIO1MASK1 register

FIO1MASK2 8 (byte) 0x3FFF C012 Fast GPIO Port 1 Mask register 2. Bit 0 in FIO1MASK2 register

FIO1MASK3 8 (byte) 0x3FFF C013 Fast GPIO Port 1 Mask register 3. Bit 0 in FIO1MASK3 register

FIO1MASKL 16

FIO1MASKU 16

(half-word)

Address Description Reset

corresponds to P1.0 ... bit 7 to P1.7.

corresponds to P1.8 ... bit 7 to P1.15.

corresponds to P1.16 ... bit 7 to P1.23.

corresponds to P1.24 ... bit 7 to P1.31.

0x3FFF C010 Fast GPIO Port 1 Mask Lower half-word register. Bit 0 in

FIO1MASKL register corresponds to P1.0 ... bit 15 to P1.15.

0x3FFF C012 Fast GPIO Port 1 Mask Upper half-word register. Bit 0 in

FIO1MASKU register corresponds to P1.16 ... bit 15 to P1.31.

5. GPIO usage notes

5.1 Example 1: sequential accesses to IOSET and IOCLR affecting the same GPIO pin/bit

value

0x00

0x0000

State of the output configured GPIO pin is determined by writes into the pin’s port IOSET and IOCLR registers. Last of these accesses to the IOSET/IOCLR register will determine the final output of a pin.

In case of a code:

IO0DIR = 0x0000 0080 ;pin P0.7 configured as output

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IO0CLR = 0x0000 0080 ;P0.7 goes LOW IO0SET = 0x0000 0080 ;P0.7 goes HIGH IO0CLR = 0x0000 0080 ;P0.7 goes LOW

pin P0.7 is configured as an output (write to IO0DIR register). After this, P0.7 output is set to low (first write to IO0CLR register). Short high pulse follows on P0.7 (write access to IO0SET), and the final write to IO0CLR register sets pin P0.7 back to low level.

5.2 Example 2: an immediate output of 0s and 1s on a GPIO port

Write access to port’s IOSET followed by write to the IOCLR register results with pins outputting 0s being slightly later then pins outputting 1s. There are systems that can tolerate this delay of a valid output, but for some applications simultaneous output of a binary content (mixed 0s and 1s) within a group of pins on a single GPIO port is required. This can be accomplished by writing to the port’s IOPIN register.

Following code will preserve existing output on PORT0 pins P0.[31:16] and P0.[7:0] and at the same time set P0.[15:8] to 0xA5, regardless of the previous value of pins P0.[15:8]:

IO0PIN = (IO0PIN && 0xFFFF00FF) || 0x0000A500

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Chapter 8: LPC2210/20 GPIO

The same outcome can be obtained using the fast port access. Solution 1: using 32-bit (word) accessible fast GPIO registers

FIO0MASK = 0xFFFF00FF; FIO0PIN = 0x0000A500;

Solution 2: using 16-bit (half-word) accessible fast GPIO registers

FIO0MASKL = 0x00FF; FIO0PINL = 0xA500;

Solution 3: using 8-bit (byte) accessible fast GPIO registers

FIO0PIN1 = 0xA5;

5.3 Writing to IOSET/IOCLR .vs. IOPIN

Write to the IOSET/IOCLR register allows easy change of the port’s selected output pin(s) to high/low level at a time. Only pin/bit(s) in the IOSET/IOCLR written with 1 will be set to high/low level, while those written as 0 will remain unaffected. However, by just writing to either IOSET or IOCLR register it is not possible to instantaneously output arbitrary binary data containing mixture of 0s and 1s on a GPIO port.

Write to the IOPIN register enables instantaneous output of a desired content on the parallel GPIO. Binary data written into the IOPIN register will affect all output configured pins of that parallel port: 0s in the IOPIN will produce low level pin outputs and 1s in IOPIN will produce high level pin outputs. In order to change output of only a group of port’s pins, application must logically AND readout from the IOPIN with mask containing 0s in bits corresponding to pins that will be changed, and 1s for all others. Finally, this result has to be logically ORred with the desired content and stored back into the IOPIN register. Example 2 from above illustrates output of 0xA5 on PORT0 pins 15 to 8 while preserving all other PORT0 output pins as they were before.

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5.4 Output signal frequency considerations when using the legacy and enhanced GPIO registers

This section is related to LPC2210/01 and LPC2220 only.

The enhanced features of the fast GPIO ports available on this microcontroller make GPIO pins more responsive to the code that has task of controlling them. In particular, software access to a GPIO pin is 3.5 times faster via the fast GPIO registers than it is when the legacy set of registers is used. As a result of the access speed increase, the maximum output frequency of the digital pin is increased 3 .5 times, too. This tremendous increase of the output frequency is not always that visible when a plain C code is used, and a portion of an application handling the fast port output might have to be written in an assembly code and executed in the ARM mode.

Here is a code where the pin control section is written in assembly language for ARM. It illustrates the difference between the fast and slow GPIO port output capabilities. For the best performances, compile this code in the ARM mode and execute from the on-chip SRAM memory.

loop: b loop

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ldr r0,=0xe01fc1a0 /*register address--enable fast port*/ mov r1,#0x1 str r1,[r0] /*enable fast port0*/ ldr r1,=0xffffffff ldr r0,=0x3fffc000 /*direction of fast port0*/ str r1,[r0] ldr r0,=0xe0028018 /*direction of slow port 1*/ str r1,[r0] ldr r0,=0x3fffc018 /*FIO0SET -- fast port0 register*/ ldr r1,=0x3fffc01c /*FIO0CLR0 -- fast port0 register*/ ldr r2,=0xC0010000 /*select fast port 0.16 for toggle*/ ldr r3,=0xE0028014 /*IO1SET -- slow port1 register*/ ldr r4,=0xE002801C /*IO1CLR -- slow port1 register*/ ldr r5,=0x00100000 /*select slow port 1.20 for toggle*/ /*Generate 2 pulses on the fast port*/ str r2,[r0] str r2,[r1] str r2,[r0] str r2,[r1] /*Generate 2 pulses on the slow port*/ str r5,[r3] str r5,[r4] str r5,[r3] str r5,[r4]

Figure 8–21 illustrates the code from above executed from the LPC2210/01 or LPC2220

on-chip SRAM. The PLL generated F APBDIV = 1 (PCLK = CCLK).

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=60 MHz out of external F

CCLK

= 12 MHz and

OSC

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Fig 21. Illustration of the fast and slow GPIO access and output showing 3.5 x increase of the pin output

frequency

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1. Features

1.1 Enhancements available in LPC2210/01 and LPC2220 only

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Chapter 9: Universal Asynchronous Receiver/Transmitter (UART0)

Rev. 02 — 27 April 2007 User manual

• 16 byte Receive and Transmit FIFOs

• Register locations conform to ‘550 industry standard.

• Receiver FIFO trigger points at 1, 4, 8, and 14 bytes.

• Built-in fractional baud rate generator with autobauding capabilities.

• Mechanism that enables software and hardware flow control implementation.

Powerful Fractional baud rate generator with autobauding capabilities provides standard baud rates such as 115200 with any crystal frequency above 2 MHz.

2. Pin description

Table 100: UART0 pin description

Pin Type Description

RXD0 Input Serial Input. Serial receive data. TXD0 Output Serial Output. Serial transmit data.

3. Register description

UART0 contains register s organized as shown in Table 9–101. The Divisor Latch Access Bit (DLAB) is contained in U0LCR[7] and enables access to the Diviso r Latches.

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Table 101: UART0 register map

Name Description Bit functions and addresses Access Reset

U0RBR Receiver Buffer

U0THR Transmit Holding

U0DLL Divisor Latch LSB 8-bit Data R/W 0x01 0xE000 C000

U0DLM Divisor Latch MSB 8-bit Data R/W 0x00 0xE000 C004

U0IER Interrupt Enable

U0IIRInterrupt ID Reg.------ABTO IntABEO Int RO 0x01 0xE000 C008

U0FCR FIFO Control

U0LCR Line Control

U0LSR Line Status

U0SCR Scratch Pad Reg. 8-bit Data R/W 0x00 0xE000 C01C

U0ACR Auto-baud Control

U0FDR Fractional Divider

U0TERTX. Enable Reg.TXEN-------R/W0x800xE000C030

xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx

MSB LSB

BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0

8-bit Read Data RO NA 0xE000 C000

8-bit Write Data WO NA 0xE000 C000

------En.ABTOEn.ABEO R/W 0x00 0xE000 C004

-----En.RX

FIFOs Enabled - - IIR3 IIR2 IIR1 IIR0

RX Trigger - - - TX FIFO

DLAB Set

Break

RX FIFO

Error

- -----ABTO

- ----Aut.Rstrt. Mode Start

TEMT THRE BI FE PE OE DR RO 0x60 0xE000 C014

Stick

Parity

MulVal DivAddVal

Even

Par.Selct.

Reserved[31:8] 0x10 0xE000 C028

Parity

Enable

Lin.St.Int

Reset

No. of

Stop Bits

Address

[1]

value

(DLAB=0)

(DLAB=1)

Enable

THRE Int

RX FIFO

Reset

Word Length Select R/W 0x00 0xE000 C00C

Int.Clr

En.RX

Dat.Av.In

FIFO

Enable

ABEO

Int.Clr

WO 0x00 0xE000 C008

R/W 0x00 0xE000 C020

(DLAB=0)

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[1] Reset value reflects the data stored in used bits only. It does not include reserved bits content.

NXP Semiconductors LPC2210, LPC2220 User guide

Specifications and Main Features

Frequently Asked Questions

User Manual

1. Introduction

Chapter 1: Introductory information

2. Features introduced with LPC2210/01 and LPC2220 over LPC2210

3. Features

4. Applications

5. Device information

6. Architectural overview

7. ARM7TDMI-S Processor

8. On-Chip bootloader

9. On-Chip Static RAM

10. Block diagram

1. Memory maps

Chapter 2: LPC2210/20 memory mapping

2. LPC2210/2220 Memory re-mapping and boot block

2.1 Memory map concepts and operating modes

2.2 Memory re-mapping

3. Prefetch abort and data abort exceptions

1. Features

Chapter 3: External Memory Controller (EMC)

2. Description

3. Pin description

4. Register description

4.1 Bank Configuration Registers 0-3 (BCFG0-3 - 0xFFE0 0000 to 0xFFE0 000C)

4.2 Read Byte Lane Control (RBLE)

4.3 Accesses to memory banks constructed from 8-bit or non byte-partitioned memory devices

4.4 Accesses to memory banks constructed from 16 or 32 bit memory devices

5. External memory interface

6. Typical bus sequences

7. External memory selection

Chapter 4: System control

1. Summary of system control block functions

2. Pin description

3. Register description

4. Crystal oscillator

5. External interrupt inputs

5.1 Register description

5.2 External Interrupt Flag register (EXTINT - 0xE01F C140)

5.3 External interrupt Wakeup register (EXTWAKE - 0xE01F C144)

5.4 External Interrupt Mode register (EXTMODE - 0xE01F C148)

5.5 External Interrupt Polarity register (EXTPOLAR - 0xE01F C14C)

5.6 Multiple external interrupt pins

6. Other system controls

6.1 System Control and Status flags register (SCS - 0xE01F C1A0)

7. Memory mapping control

7.1 Memory Mapping control register (MEMMAP - 0xE01F C040)

7.2 Memory mapping control usage notes

8. Phase Locked Loop (PLL)

8.1 Register description

8.2 PLL Control register (PLLCON - 0xE01F C080)

8.3 PLL Configuration register (PLLCFG - 0xE01F C084)

8.4 PLL Status register (PLLSTAT - 0xE01F C088)

8.5 PLL Interrupt

8.6 PLL Modes

8.7 PLL Feed register (PLLFEED - 0xE01F C08C)

8.8 PLL and Power-down mode

8.9 PLL frequency calculation

8.10 Procedure for determining PLL settings

8.11 PLL configuring examples

9. Power control

9.1 Register description

9.2 Power Control register (PCON - 0xE01F COCO)

9.3 Power Control for Peripherals register (PCONP - 0xE01F COC4)

10. Reset

9.4 Power control usage notes

11. APB divider

1 1.1 Register description

11.2 APBDIV register (APBDIV - 0xE01F C100)

12. Wakeup timer

1. Features

2. Description

Chapter 5: Vectored Interrupt Controller (VIC)

3. Register description

4. VIC registers

4.1 Software Interrupt Register (VICSoftInt - 0xFFFF F018)

4.2 Software Interrupt Clear Register (VICSoftIntClear - 0xFFFF F01C)

4.3 Raw Interrupt Status Register (VICRawIntr - 0xFFFF F008)