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NXP Semiconductors LPC2210, LPC2220 User guide

UM10114
LPC2210/2220 User manual
Rev. 02 — 27 April 2007 User manual
Document information
Info Content Keywords LPC2210, LPC2220, LPC2210/01, ARM, ARM7, 32-bit, Microcontroller Abstract LPC2210/2220 User manual release
NXP Semiconductors
UM10114
LPC2210/2220 User manual
Revision history
Rev Date Description
2.1 20070425
• details on master mode
• SPI SSEL line conditioning added (see Table 12–159 “SPI pin description”).
2.0 20070123
• Details on LPC2210/01 device added into the document.
• The format of this data sheet has been redesigned to comply with the new identity
guidelines of NXP Semiconductors.
• Legal texts have been adapted to the new company name where appropriate.
1.0 20051012 Moved the UM document into the new structured FameMaker template. Many changes were made to the format throughout the document. Here are the most important:
• UART0 and UART1 description updated (fractional baudrate generator and hardware
handshake features added - auto-CTS/RTS)
• ADC chapter updated with the dedicated result registers
• GPIO chapter updated with the descri ption of the Fast IOs
Contact information
For additional information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com
User manual Rev. 02 — 27 April 2007 2 of 290

1. Introduction

UM10114

Chapter 1: Introductory information

Rev. 02 — 27 April 2007 User manual
The LPC2210/2220 and LPC2210/01 microcontrollers are based on a 16/32 bit ARM7TDMI-S CPU with real-time emulation and embedded trace support. For critical code size applications, the alternative 16-bit Thumb Mode reduces code by more than 30 % with minimal performance penalty.
With a 144 pin package, low power consumption, various 32 bit timers, 8 Channel 10 bit ADC, PWM channels and up to nine external interrupt pins this microcontroller is particularly suitable for industrial control, medical systems, access control and point-of-sale. LPC2210/2220 and LPC2210/01 can provide up to 76 GPIO depending on bus configuration. With a wide range of serial communications interfaces, it is also very well suited for communication gateways, protocol converters a nd embedded sof t modems as well as many other general-purpose applications.

2. Features introduced with LPC2210/01 and LPC2220 over LPC2210

• CPU clock up to 75 MHz.
• Fast IO registers are located on the ARM local bus for the fastest possible I/O timing.
• All GPIO registers are byte addressable.
• Entire port value can be written in one instruction.
• Mask registers allow single instruction to set or clear any number of bits in one port.
• TIMER0/1 can be driven by an external clock/can count external events
• Powerful Fractional baud rate generator with autobauding capabilities provides
standard baud rates such as 115200 with any crystal frequency above 2 MHz.
• UART1 is equipped with auto-CTS/RTS flow-control fully implemented in hardware.
• SSP serial controller supporting SPI/4-wire SSI and Microwire buses
• Every analog input has a dedicated result regis te r to re du ce inte rr up t ov er he ad .
• Every analog input can generate an interrupt once the conversion is completed.

3. Features

• 16/32-bit ARM7TDMI-S microcontroller in a LQFP144 and TFBGA144 package
• 16 kB (LPC2210 and LPC2210/01) or 64 kB (LPC2220) of on-chip static RAM.
• Serial boot-loader using UART0 provides in-system download and programming
capabilities.
• EmbeddedICE-RT and Embedded T race interface s offer real-tim e debugging with the
on-chip RealMonitor software and high speed tracing of instruction execution.
• Eight channel 10-bit A/D converter with a dedicated result register for every channel
and conversion time as low as 2.44 μs.
• Two 32-bit timers/external event counters with four capture and four compare
channels each, PWM unit (six outputs), Real-Time Clock (RTC) and watchdog.
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UM10114
Chapter 1: LPC2210/20 Introductory information

4. Applications

• Serial interfaces include two UARTs (16C550), Fast I
2
C (400 kbit/s), and two SPIs.
• Vectored Interrupt Controller (VIC) with configurable priorities and vector addresses.
• Configurable external memory interface with up to four banks, each up to 16 MB and
8/16/32 bit data width.
• Up to 76 general purpose Fast I/O pins (5 V tolerant) capable of toggling a GPIO pin
at 15 MHz. Up to nine edge or level sensitive external interrupt pins available.
• Up to 60 MHz (LPC2210) and 75 MHz (LPC2210/01 and LPC2220) maximum CPU
clock available from programmable on-chip Phase-Locked Loop (PLL) with settling time of 100 μs.
• On-chip integrated oscillator operates with an external crystal in range of 1 MHz to
30 MHz and with external oscillator up to 50 MHz.
• Power saving modes include Idle and Power-down.
• Processor wake-up from Power-down mode via external interrupt.
• Individual enable/disable of peripheral functions for power optimization.
• Dual power supply:
– CPU operating voltage range of 1.65 V to 1.95 V (1.8 V ±0.15 V). – I/O power supply range of 3.0 V to 3.6 V (3.3 V ±10 %) with 5 V tolerant I/O pads.
16/32 bit ARM7TDMI-S processor.
• Industrial control
• Medical systems
• Access control
• Point-of-sale
• Communication gateway
• Embedded soft modem
• General purpose applications

5. Device information

Table 1. LPC2210/2220 device information
Device Number
of pins
LPC2210 144 16 kB - 8 With external
LPC2210/01 144 16 kB - 8 + With external
LPC2220 144 64 kB - 8 + With external
On-chip SRAM
On-chip FLASH
Number of 10-bit AD Channels
Faster CPU, Fast IOs, TIMER0/1 external counter input, improved ADC, enhanced UARTs, SSP
Note
memory interface
memory interface
memory interface
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6. Architectural overview

LPC2210/20 and LPC2210/01 consist of an ARM7TDMI-S CPU with emulation support, the ARM7 Local Bus for interface to on-chip memory controllers and Fast GPIO, the AMBA Advanced High-performance Bus (AHB) for interface to the interrupt controller, and the VLSI Peripheral Bus (APB, a compatible superset of ARM’s AMBA Advanced Peripheral Bus) for connection to on-chip peripheral functions. The LPC2210/2220 and LPC2210/01 microcontroller configure the ARM7TDMI-S processor in little-endian byte order and this can not be altered by user.
AHB peripherals are allocated a 2 megabyte range of addresses at the very top of the 4 gigabyte ARM memory space. Each AHB peripheral is allocated a 16 kB address space within the AHB address space. LPC2210/2220 and LPC2210/01 peripheral functions (other than the interrupt controller) are connected to the APB bus. The AHB to APB bridge interfaces the APB bus to the AHB bus. APB peripherals are also allocated a 2 megabyte range of addresses, beginning at the 3.5 gigabyte address point. Each APB peripheral is allocated a 16 kB address space within the APB address space.
The connection of on-chip peripherals to device pins is controlled by a Pin Connect Block, see Section 7–4 requirements for the use of peripheral functions and pins.
UM10114
Chapter 1: LPC2210/20 Introductory information
. This must be configured by software to fit specific application

7. ARM7TDMI-S Processor

The ARM7TDMI-S is a general purpose 32-bit microprocessor, which offers high performance and very low power consumption. The ARM architecture is based on Reduced Instruction Set Computer (RISC) principles, and the instruction set and related decode mechanism are much simpler than those of microprogrammed Complex Instruction Set Computers. This simplicity results in a high instruction throughput and impressive real-time interrupt response from a small and cost-effective processor core.
Pipeline techniques are employed so that all part s of the pro cessing and memory systems can operate continuously. Typically, while one instruction is being executed, its successor is being decoded, and a third instruction is being fetched from memory.
The ARM7TDMI-S processor also employs a unique architectural strategy known as THUMB, which makes it ideally suited to high-volume applications with memory restrictions, or applications where code density is an issue.
The key idea behind THUMB is that of a super-reduced instruction set. Essentially, the ARM7TDMI-S processor has two instruction sets:
• The standard 32-bit ARM instruction set.
• A 16-bit THUMB instruction set.
The THUMB set’s 16-bit instruction length allows it to approach twice the density of standard ARM code while retaining most of the ARM’s performance advantage over a traditional 16-bit processor using 16-bit registers. This is possible because THUMB code operates on the same 32-bit register set as ARM code.
THUMB code is able to provide up to 65% of the code size of ARM, and 160% of the performance of an equivalent ARM processor connected to a 16-bit memory system.
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The ARM7TDMI-S processor is described in detail in the ARM7TDMI-S Datasheet that can be found on official ARM website.

8. On-Chip bootloader

The microcontroller incorporates an on-chip serial boot-loader located in a 8 kB ROM. Using UART0, this utility enables the loading an application into the microcontroller’s RAM for execution. Typically, an application loaded and executed from RAM would take care of programming of off-chip Flash memory with user’s code.

9. On-Chip Static RAM

On-Chip Static RAM (SRAM) may be used for code and/or data storage. The on-chip SRAM may be accessed as 8-bits, 16-bits, and 32-bits. The LPC2210 and LPC2210/01 provide 16 kB of static RAM while LPC2220 provides 64 kB of static RAM.
The microcontroller’s SRAM is designed to be accessed as a byte-addressed memory. Word and halfword accesses to the memory ignore the alignment of the address and access the naturally-aligned value that is addressed (so a memory access ignores address bits 0 and 1 for word accesses, and ignores bit 0 for halfword accesses). Therefore valid reads and writes require data accessed as halfwords to originate from addresses with address line 0 being 0 (addresses ending with 0, 2, 4, 6, 8, A, C, and E in hexadecimal notation) and data accessed as words to originate from addresses with address lines 0 and 1 being 0 (addresses ending with 0, 4, 8, and C in hexadecimal notation). This rule applies to both off and on-chip memory usage.
UM10114
Chapter 1: LPC2210/20 Introductory information
The SRAM controller incorporates a write-back buffer in order to prevent CPU stalls during back-to-back writes. The write-back buffer always holds the last data sent by software to the SRAM. This data is only written to the SRAM when another write is requested by software (the data is only written to the SRAM when software does another write). If a chip reset occurs, actual SRAM contents will not reflect the most recent write request (i.e. after a "warm" chip reset, the SRAM does not reflect the last wr ite operation). Any software that checks SRAM contents after reset must take this into account. Two identical writes to a location guarantee that the data will be present after a Reset. Alternatively, a dummy write operation before entering idle or power-down mode will similarly guarantee that the last data written will be present in SRAM after a subsequent Reset.
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002aaa793
system
clock
SCL
P0[30:27], P0[25:0]
P2[31:0]
P1[31:16], P1[1:0]
P3[31:0]
SDA
CS3 to CS0
(2)
A23 to A0
(2)
BLS3 to BLS0
(2)
OE, WE
(2)
D31 to D0
(2)
TRST
(1)
TMS
(1)
TCK
(1)
TDI
(1)
TDO
(1)
XTAL2
XTAL1
SCK0, SCK1
MOSI0, MOSI1
MISO0, MISO1
EINT3 to EINT0
4 × CAP0 4 × CAP1
4 × MAT1
4 × MAT0
AIN7 to AIN0
PWM6 to PWM1
SSEL0, SSEL1
TXD0, TXD1
RXD0, RXD1
DSR1, CTS1, RTS, DTR DCD1, RI1
AMBA AHB
(Advanced High-performance Bus)
AHB BRIDGE
EMULATION
TRACE MODULE
TEST/DEBUG
INTERFACE
AHB
DECODER
AHB TO APB
BRIDGE
APB
DIVIDER
VECTORED INTERRUPT
CONTROLLER
SYSTEM
FUNCTIONS
PLL
SPI AND SSP
SERIAL INTERFACES
0 AND 1
I
2
C SERIAL
INTERFACE
UART0/UART1
REAL TIME CLOCK
WATCHDOG
TIMER
SYSTEM
CONTROL
EXTERNAL
INTERRUPTS
GENERAL
PURPOSE I/O
PWM0
CAPTURE/ COMPARE
TIMER 0/TIMER 1
A/D CONVERTER
ARM7TDMI-S
LPC2210/2220
LPC2210/01
INTERNAL
SRAM
CONTROLLER
16/64 kB
SRAM
APB (ARM
Peripheral Bus)
RST
EXTERNAL MEMORY
CONTROLLER
ARM7 local bus
P0[30:27], P0[25:0]
P1[31:16], P1[1:0]
FAST GENERAL
PURPOSE I/O

10. Block diagram

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Chapter 1: LPC2210/20 Introductory information
User manual Rev. 02 — 27 April 2007 7 of 290
(1) When debug interface is used, GPIO/other functions sharing these pins are not available. (2) Shared with GPIO.
Fig 1. LPC2210/2220 and LPC2210/01 block diagram
AHB PERIPHERALS
APB PERIPHERALS
RESERVED ADDRESS SPACE
BOOT BLOCK (RE-MAPPED FROM
ON-CHIP ROM MEMORY
RESERVED ADDRESS SPACE
64 KBYTE ON-CHIP STATIC RAM (LPC2220)
16 KBYTE ON-CHIP STATIC RAM
(LPC2210, LPC2210/01)
RESERVED ADDRESS SPACE
0xFFFF FFFF
0xF000 0000 0xEFFF FFFF
0xE000 0000 0xDFFF FFFF
0x8400 0000
0x7FFF FFFF
0x7FFF E000
EXTERNAL MEMORY BANK 3
0x83FF FFFF
0x8300 0000
EXTERNAL MEMORY BANK 2
0x82FF FFFF
0x8200 0000
EXTERNAL MEMORY BANK 1
0x81FF FFFF
0x8100 0000
EXTERNAL MEMORY BANK 0
0x80FF FFFF
0x8000 0000
0x7FFF DFFF
0x4000 4000 0x4000 3FFF
0x4001 0000 0x4000 FFFF
0x4000 0000 0x3FFF FFFF
4.0 GB
3.75 GB
3.5 GB
3.0 GB
2.0 GB
1.0 GB
0x0000 0000
0.0 GB
002aaa795

1. Memory maps

The LPC2210/2220 and LPC2210/01 incorporate several d istinct memory r egions, shown in the following figures. Figure 2–2 from the user program viewpoint following reset. The interrupt vector area supports address remapping, which is described later in this section.
UM10114

Chapter 2: LPC2210/20 memory mapping

Rev. 02 — 27 April 2007 User manual
shows the overall map of the entire address space
Fig 2. System memory map
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RESERVED
RESERVED
0xF000 0000 0xEFFF FFFF
APB PERIPHERALS
0xE020 0000 0xE01F FFFF
0xE000 0000
AHB PERIPHERALS
0xFFFF FFFF
0xFFE0 0000 0xFFDF FFFF
3.75 GB
3.5 GB
3.5 GB + 2 MB
4.0 GB - 2 MB
4.0 GB
UM10114
Chapter 2: LPC2210/20 Memory map
Fig 3. Peripheral memory map
Figures 3 through 4 and Table 2–2 show different views of the peripheral address space. Both the AHB and APB peripheral areas are 2 megabyte sp aces which are divided up into 128 peripherals. Each peripheral space is 16 kilobytes in size. This allows simplifying the address decoding for each peripheral. All peripheral register addresses are word aligned (to 32-bit boundaries) regardless of their size. This eliminates the need for byte lane mapping hardware that would be required to allow byte (8-bit) or half-wor d (16-bit)
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VECTORED INTERRUPT CONTROLLER
(AHB PERIPHERAL #0)
0xFFFF F000 (4G - 4K)
0xFFFF C000
0xFFFF 8000
(AHB PERIPHERAL #125)
(AHB PERIPHERAL #124)
(AHB PERIPHERAL #3)
(AHB PERIPHERAL #2)
(AHB PERIPHERAL #1)
(AHB PERIPHERAL #126)
0xFFFF 4000
0xFFFF 0000
0xFFE1 0000
0xFFE0 C000
0xFFE0 8000
0xFFE0 4000
0xFFE0 0000
accesses to occur at smaller boundaries. An implication of this is that word and half-word registers must be accessed all at once. For example, it is not possible to read or write the upper byte of a word register separately.
UM10114
Chapter 2: LPC2210/20 Memory map
AHB section is 128 x 16 kB blocks (totaling 2 MB). APB section is 128 x 16 kB blocks (totaling 2MB).
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Fig 4. AHB peripheral map
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Table 2. APB peripheries and base addresses
APB peripheral Base address Peripheral name
0 0xE000 0000 Watchdog timer 1 0xE000 4000 Timer 0 2 0xE000 8000 Timer 1 3 0xE000 C000 UART0 4 0xE001 0000 UART1 5 0xE001 4000 PWM 6 0xE001 8000 Not used 7 0xE001 C000 I 8 0xE002 0000 SPI0 9 0xE002 4000 RTC 10 0xE002 8000 GPIO 11 0xE002 C000 Pin connect block 12 0xE003 0000 SPI1 13 0xE003 4000 10 bit ADC 14 - 22 0xE003 8000
23 0xE005 C000 SSP (LPC2210/01 and LPC2220 only) 24 - 126 0xE006 0000
127 0xE01F C000 System Control Block
0xE005 8000
0xE01F 8000
2
C
Not used
Not used
UM10114
Chapter 2: LPC2210/20 Memory map

2. LPC2210/2220 Memory re-mapping and boot block

2.1 Memory map concepts and operating modes

The basic concept on the LPC2210/2220 and L PC2210 /0 1 is that ea ch memor y a rea ha s a "natural" location in the memory map. This is the address range for which code residing in that area is written. The bulk of each memory space remains permanently fixed in the same location, eliminating the need to have portions of the code designed to run in different address ranges.
Because of the location of the interrupt vectors on the ARM7 processor (at addresses 0x0000 0000 through 0x0000 001C, as shown in Table 2–3 Boot Block and SRAM spaces need to be re-mapped in order to allow alternative uses of interrupts in the different operating modes described in Table 2–4 interrupts is accomplished via the Memory Mapping Control features.
Table 3. ARM Exceptio n Vector Locations
Address Exception
0x0000 0000 Reset 0x0000 0004 Undefined Instruction 0x0000 0008 Software Interrupt 0x0000 000C Prefetch Abort (instruction fetch memory fault) 0x0000 0010 Data Abort (data access memory fault)
below), a small portion of the
. Re-mapping of the
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Table 3. ARM Exceptio n Vector Locations
Address Exception
0x0000 0014 Reserved
0x0000 0018 IRQ 0x0000 001C FIQ
Table 4. LPC2210/2220 and LPC2210/01 Memory Mapp ing Modes
Mode Activation Usage
Boot Loader mode
User RAM mode
User External mode
Hardware activation by any Reset
Software activation by User program
Activated by BOOT1:0 pins
UM10114
Chapter 2: LPC2210/20 Memory map
Note: Identified as reserved in ARM documentation.
The Boot Loader always executes after any reset. The Boot Block interrupt vectors are mapped to the bottom of memory to allow handling exceptions and using interrupts during the Boot Loading process.
Activated by a User Program as desired. Interrupt vectors are re-mapped to the bottom of the Static RAM.
Activated by Boot Loader when P0.14 is not LOW at the end of RESET LOW. Interrupt vectors are re-mapped from the bottom of the external memory map.

2.2 Memory re-mapping

In order to allow for compatibility with future derivatives, the entire Boot Block is mapped to the top of the on-chip memory space. Memory spaces other than the interrupt vectors remain in fixed locations. Figure 2–5 defined above.
The portion of memory that is re-mapped to allow interrupt processing in different modes includes the interrupt vector area (32 bytes) and an additional 32 bytes, for a total of 64 bytes. The re-mapped code locations overlay addresses 0x0000 0000 through 0x0000 003F. The vector contained in the SRAM, external memory, and Boot Block must contain branches to the actual interrupt handlers, or to other instructions that accomplish the branch to the interrupt handlers.
There are two reasons this configuration was chosen:
1. Minimize the need for the SRAM and Boot Block vectors to deal with arbitrary boundaries in the middle of code space.
2. To provide space to store constants for jumping beyond the range of single word branch instructions.
Re-mapped memory areas, including the Boot Block and interrupt vectors, continue to appear in their original location in addition to the re-mapped address.
Details on re-mapping and examples can be found in Section 4–7 “
control” on page 34.
shows the on-chip memory mapping in the modes
Memory mapping
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8 kB BOOT BLOCK
(RE-MAPPED FROM TOP OF FLASH MEMORY)
RESERVED ADDRESSING SPACE
16 kB ON-CHIP SRAM (LPC2210, LPC2210/01)
0.0 GB
ACTIVE INTERRUPT VECTORS (FROM FLASH, SRAM, OR BOOT
BLOCK)
0x8000 0000
0x4000 4000 0x4000 3FFF
0x4000 0000 0x3FFF FFFF
0x0000 0000
0x7FFF FFFF
1.0 GB
2.0 GB - 8 kB
2.0 GB
(BOOT BLOCK INTERRUPT VECTORS)
(SRAM INTERRUPT VECTORS)
RESERVED MEMORY SPACE
(8 kB BOOT BLOCK RE-MAPPED TO HIGHER ADDRESS RANGE)
0x0004 0000 0x0003 FFFF
RESERVED ADDRESSING SPACE
0x7FFF E000 0x7FFF DFFF
0x4001 0000 0x4000 FFFF
64 kB ON-CHIP SRAM (LPC2220)
0x0003 E000 0x0003 DFFF
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UM10114
Chapter 2: LPC2210/20 Memory map
Fig 5. Map of lower memory is showing re-mapped and re-ma p pable areas
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3. Prefetch abort and data abort exceptions

The LPC2210/2220 and LPC2210/01 generate the appropriate bus cycle abort exception if an access is attempted for an address that is in a reserved or unassigned address region. The regions are:
• Areas of the memory map that are not implemented for a specific ARM derivative. Fo r
the LPC2210/2220 and LPC2210/01, this is: – Address space between the re-mapped interrupt vector area and an On-Chip
SRAM, labelled "Reserved Address Space" in Figure 2–2 an address range from 0x0000 0040 to 0x3FFF FFFF.
– Address space between On-Chip Static RAM and Boot Block. Labelled "Reserved
Address Space" in Figure 2–2 range from 0x4000 4000 to 0x7FFF DFFF and for LPC2220 this is an address range from 0x4001 0000 to 0x7FFF DFFF.
– Address space between 0x8400 0000 to 0xDFFF FFFF, labelled "Reserved
Address Space".
– Reserved regions of the AHB and APB spaces. See Figure 2–3
• Unassigned AHB peripheral spaces. See Figure 2–4.
• Unassigned APB peripheral spaces. See Table 2–2.
. For LPC2210 and LPC2210/01 this is an address
UM10114
Chapter 2: LPC2210/20 Memory map
and Figure 2–5. This is
and Table 2–2.
For these areas, both attempted data acce ss and in struction fetch genera te an exception. In addition, a Prefetch Abort exception is generated for any instruction fetch that maps to an AHB or APB peripheral address.
Within the address space of an existing APB peripheral, a data abort exception is not generated in response to an access to an undefined address. Address decoding within each peripheral is limited to that needed to distinguish defined registers within the peripheral itself. For example, an access to address 0xE000 D000 (an undefined address within the UART0 space) may result in an access to the register defined at address 0xE000 C000. Details of such address aliasing within a peripheral space are not defined in the LPC2210/2220 and LPC2210/01 documentation and are not a supported feature.
Note: The ARM core stores the Prefetch Abort flag along with the associated instruction (which will be meaningless) in the pipeline and processes the abort only if an attempt is made to execute the instruction fetched from the illegal address. This prevents accidental aborts that could be caused by prefetches that occur when code is executed very near a memory boundary.
User manual Rev. 02 — 27 April 2007 14 of 290

1. Features

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Chapter 3: External Memory Controller (EMC)

Rev. 02 — 27 April 2007 User manual
• Support for various static memory-mapped devices including RAM, ROM, flash, burst
ROM, and some external I/O devices
• Asynchronous page mode read operation in non-clocked memory subsystems
• Asynchronous burst mode read access to burst mode ROM devices
• Independent configuration for up to four banks, each up to 16 M Bytes
• Programmable bus turnaround (idle) cycles (1 to 16)
• Programmable read and write WAIT states (up to 32) for static RAM devices
• Programmable initial and subsequent burst read WAIT state, for burst ROM devices
• Programmable write protection
• Programmable burst mode operation
• Programmable read byte lane enable control

2. Description

The external Static Memory Controller is an AMBA AHB slave module which provides an interface between an AMBA AHB system bus and external (off-chip) memory devices. It provides support for up to four independently configurable memory banks simult aneously. Each memory bank is capable of supporting SRAM, ROM, Flash EPROM, Burst ROM memory, or some external I/O devices .
Each memory bank may be 8, 16, or 32 bits wide. Since the LPC2210/20 144 pin package pins out addre ss line s A[23:0] only, the decoding
among the four banks uses address bits A[25:24]. The native lo catio n of th e four ban ks is at the start of the External Memory area identified in Figure 2–2 on page 8 be used for initial booting under control of the state of the BOOT[1:0] pins.
Table 5. Address ranges of the external memory banks
Bank Address range Configuration register
0 0x8000 0000 - 0x80FF FFFF BCFG0 1 0x8100 0000 - 0x81FF FFFF BCFG1 2 0x8200 0000 - 0x82FF FFFF BCFG2 3 0x8300 0000 - 0x83FF FFFF BCFG3
, but Bank 0 can
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3. Pin description

Table 6. Exter nal Me mory Controller pin description
Pin name Type Pin description
D[31:0] Input/Output External memory Data lines A[23:0] Output External memory Address lines OE Output Low-active Output Enable signal BLS[3:0] Output Low-active Byte Lane Select signals WE Output Low-active Write Enable signal CS[3:0] Output Low-active Chip-Select signals

4. Register description

The external memory controller contains 4 registers as shown in Table 3–7.
Table 7. Exter nal Me mory Controller register map
Name Description Access Reset value,
BCFG0 Configuration register for memory bank 0 R/W 0x0000 FBEF 0xFFE0 0000 BCFG1 Configuration register for memory bank 1 R/W 0x2000 FBEF 0xFFE0 0004 BCFG2 Configuration register for memory bank 2 R/W 0x1000 FBEF 0xFFE0 0008 BCFG3 Configuration register for memory bank 3 R/W 0x0000 FBEF 0xFFE0 000C
UM10114
Chapter 3: LPC2210/20 EMC
Address
see Table 9.
Each register selects the following options for its memory bank:
• The number of idle clock cycles inserted between read and write accesses in this
bank, and between an access in another bank and an access in this bank, to avoid bus contention between devices (1 to 17 clocks)
• The length of read accesses, except for subsequent reads from a burst ROM (3 to 35
clocks)
• The length of write accesses (3 to 19 clocks)
• Whether the bank is write-protected or not
• Whether the bank is 8, 16, or 32 bits wide
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4.1 Bank Configuration Registers 0-3 (BCFG0-3 - 0xFFE0 0000 to 0xFFE0 000C)

Table 8. Bank Con f iguration Registers 0-3 (BCFG0-3 - 0xFFE0 0000 to 0xFFE0 000C)
BCFG0-3 Name Function Reset
3:0 IDCY This field controls the minimum number of “idle” CCLK cycles
4 - Reserved, user software should not write ones to reserved bits.
9:5 WST1 This field controls the length of read accesses (except for
10 RBLE This bit should be 0 for banks composed of byte-wide or
15:11 WST2 For SRAM banks, this field controls the length of write accesses,
23:16 - Reserved, user software should not write ones to reserved bits.
24 BUSERR The only known case in which this bit is set is if the EMC detects
25 WPERR This bit is set if software attempts to write to a bank that has the
26 WP A 1 in this bit write-protects the bank. 0 27 BM A 1 in this bit identifies a burst-ROM bank. 0 29:28 MW This field controls the width of the data bus for this bank:
31:30 AT Always write 00 to this field. 00
address description
that the EMC maintains between read and write accesses in this bank, and between an access in another bank and an access in this bank, to avoid bus contention between devices. The number of idle CCLK cycles between such accesses is the value in this field plus 1.
The value read from a reserved bit is not defined.
subsequent reads from a burst ROM). The length of read accesses, in CCLK cycles, is this field value plus 3.
non-byte-partitioned devices, so that the EMC drives the BLS3:0 lines High during read accesses. This bit should be 1 for banks composed of 16-bit and 32-bit wide devices that include byte select inputs, so that the EMC drives the BLS3:0 lines Low during read accesses.
which consist of: One CCLK cycle of address setup with CS, BLS, and WE high This value plus 1, CCLK cycles with address valid and CS, BLS,
and WE low AND One CCLK cycle with address valid, CS low, BLS and WE high. For burst ROM banks, this field controls the length of subsequent
accesses, which are (this value plus 1) CCLK cycles long.
The value read from a reserved bit is not defined.
an AMBA request for more than 32 bits of data. The ARM7TDMI-S will not make such a request.
WP bit 1. Write a 1 to this bit to clear it.
00=8 bit, 01=16 bit, 10=32 bit, 11=reserved
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Chapter 3: LPC2210/20 EMC
value
1111
NA
11111
0
11111
NA
0
0
See
Table 3– 9
The table below shows the state of BCFG0[29:28] after the Boot Loader has run. The hardware reset state of these bits is 10.
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NXP Semiconductors
T able 9. Default memory widths at reset
Bank BOOT[1:0] during Reset BCFG[29:28] Reset value Memory width
0LL 00 8bits 0LH 01 16bits 0HL 10 32bits 0HH 01 16bits 1XX 10 32bits 2XX 01 16bits 3XX 00 8bits

4.2 Read Byte Lane Control (RBLE)

The External Memory Controller (EMC) generates byte lane control signals BLS[3:0] according to:
• External memory bank data bus wid th , de fined within each configuration register (see
• External memory bank type, being either byte (8 bits), halfword (16 bits) or word (32
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Chapter 3: LPC2210/20 EMC
MW field in BCFG register)
bits) (see RBLE field in BCFG register)
Each memory bank can either be 8, 16 or 32 bits wide. The type of memory used to configure a particular memory bank determines how the WE and BLS signals are connected to provide byte, halfword and word access. For read accesses, it is necessary to control the BLS signals by driving them either all HIGH, or all LOW.
This control is achieved by programming the Read Byte Lane Enable (RBLE) bit within each configuration register. The following two sections explain why different connections in respect of WE and BLS[3:0] are needed for different memory configurations.

4.3 Accesses to memory banks constructed from 8-bit or non byte-partitioned memory devices

For memory banks constructed from 8-bit or non byte-partitioned memory devices, it is important that the RBLE bit is cleared to zero within the respective memory bank configuration register. This forces all BLS[3:0] lines HIGH during a read access to that particular bank.
Figure 3–6
memory banks that are 8, 16 and 32 bits wide. In each of these configurations, the BLS[3:0] signals are connected to write enable (WE) inputs of each 8-bit memory.
Note: The WE signal from the EMC is not used. For write transfers, the relevant BLS[3:0] byte lane signals are asserted LOW and steer the data to the addressed bytes.
For read transfers, all of the BLS[3:0] lines are deasserted HIGH, which allows the external bus to be defined for at least the width of the accessed memory.
(a), Figure 3–7 (a) and Figure 3–8 show 8-bit memory being used to configure
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4.4 Accesses to memory banks constructed from 16 or 32 bit memory devices

For memory banks constructed from 16 bit or 32-bit memory devices, it is important that the RBLE bit is set to one within the respective memory bank configuraton register. This asserts all BLS[3:0] lines LOW during a read access to that particular bank. For 16 and 32-bit wide memory devices, byte select signals exist and must be appropriately controlled as shown in Figure 3–6

5. External memory interface

External memory interfacing depends on the bank width (32, 16 or 8 bit selected via MW bits in corresponding BCFG register). Furthermore, the memory chip(s) require an adequate setup of RBLE bit in BCFG register. Memory accessed with an 8-bit wide data bus require RBLE = 0, while memory banks capable of accepting 16 or 32 bit wide data require RBLE = 1.
If a memory bank is configured to be 32 bits wide, address lines A0 and A1 can be used as non-address lines. If a memory bank is configured to 16 bits wide, A0 is not required. However, 8 bit wide memory banks do require all address lines down to A0. Configuring A1 and/or A0 line(s) to provide address or non-address function is accomplished using bits 23 and 24 in Pin Function Select Register 2 (PINSEL2 register, see Section 7–4.3
UM10114
Chapter 3: LPC2210/20 EMC
and Figure 3–7.
).
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A[a_b:2]
BLS[1]
D[15:8]
CE OE WE
IO[7:0] A[a_m:0]
BLS[0]
D[7:0]
CE OE WE
IO[7:0] A[a_m:0]
OE
CS
BLS[3]
D[31:24]
CE OE WE
IO[7:0] A[a_m:0]
BLS[2]
D[23:16]
CE OE WE
IO[7:0] A[a_m:0]
OE
CS
WE
CE OE WE UB LB
IO[15:0] A[a_m:0]
D[31:16]
BLS[2]
CE OE WE UB LB
IO[15:0] A[a_m:0]
D[15:0]
BLS[0]
A[a_b:2]
BLS[3] BLS[1]
OE
CS
WE
CE OE WE B3 B2 B1 B0
IO[31:0] A[a_m:0]
D[31:0]
BLS[2]
A[a_b:2]
BLS[3]
BLS[0]
BLS[1]
Symbol "a_b" in the following figures refers to the highest order address line in the data bus. Symbol "a_m" refers to the highest order address line of the me mory chip used in the external memory interface.
a. 32 bit wide memory bank interfaced to 8 bit memory chips (RBLE = 0)
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Chapter 3: LPC2210/20 EMC
b. 32 bit wide memory bank interfaced to 16 bit memory chips (RBLE = 1)
c. 32 bit wide memory bank interfaced to 8 bit memort chips (RBLE = 1)
Fig 6. 32 bit bank external memory interfaces (BGFGx Bits MW = 10)
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OE
CS
BLS[1]
D[15:8]
CE OE WE
IO[7:0] A[a_m:0]
BLS[0]
D[7:0]
CE OE WE
IO[7:0] A[a_m:0]
A[a_b:1]
OE
CS
WE
CE OE WE UB LB
IO[15:0] A[a_m:0]
D[15:0]
BLS[0]
A[a_b:1]
BLS[1]
OE
CS
BLS[0]
D[7:0]
CE OE WE
IO[7:0] A[a_m:0]
A[a_b:0]
a. 16 bit wide memory bank interfaced to 8 bit memory chips (RBLE = 0)
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Chapter 3: LPC2210/20 EMC
b. 16 bit wide memory bank interfaced to 16 bit memory chips (RBLE = 1)
Fig 7. 16 bit bank external memory interfaces (BCFGx bits MW = 01)
Fig 8. 8 bit bank external memory interface (BCFGx bits MW = 00 and RBLE = 0)

6. Typical bus sequences

The following figures show typical external read and write access cycles. XCLK is the clock signal available on P3.23. While not necessarily used by external memory, in these examples it is used to provide time reference (XCLK and CCLK are set to have the same
User manual Rev. 02 — 27 April 2007 21 of 290
frequency).
NXP Semiconductors
WE/BLS
XCLK
CS
addr data
OE
WE/BLS
change valid data
valid address
1 wait state
(WST1=0)
XCLK
CS
addr
data
OE
change valid data
valid address
2 wait states
(WST1=1)
XCLK
CS
addr
data
OE
WE/BLS
valid address
valid data
XCLK
CS
addr
data
OE
WE/BLS
valid address
valid data
WST2 = 0
WST2 = 1
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Chapter 3: LPC2210/20 EMC
Fig 9. External memory read access (WST1 = 0 and WST1 = 1 examples)
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Fig 10. E xternal memory write access (WST2 = 0 and WST2 = 1 examples)
Figure 3–9 and Figure 3–10 show typical read and write accesses to external memory.
Dashed lines on Figure 3–9 having BLS lines connected to UB/LB or B[3:0] (see Section 3–4.4
Figure 3–7
correspond to memory banks using 16/32 bit memory chips
and Figure 3–6 ,
).
NXP Semiconductors
Address A Ad.A+1 Ad.A+2 Address A+3
D(A) D(A+1) D(A+2) Data(A+3)
2 wait states
XCLK
addr
data
CS
OE
0 wait states
f
MAX
2WST1+
t
RAM
20ns+
------------------------------
≤
WST1
t
RAM
20ns+
t
CYC
------------------------------
≥ 2–
t
RAMtCYC
2WST1+()× 20ns–≤
It is important to notice that some variations from Figure 3–9 and Figure 3–10 do exist in some particular cases.
For example, when the first read access to the memory bank that has just been selected is performed, CS and OE lines may become low one XCLK cycle earl ier than it is shown in
Figure 3–10
Likewise, in a sequence of several consecutive write accesses to SRAM, the last write access will look like those shown in Figure 3–10 in that case will have data valid one cycle longer. Also, isolated write access will be identical to the one in Figure 3–10
The EMC supports sequential access burst reads of up to four consecutive lo ca tions in 8 , 16 or 32-bit memories. This feature supports burst mode ROM devices and increases the bandwidth by using reduced (configurable) ac cess time for three sequential reads following a quad-location boundary read. Figure 3–11 read transfer. The first burst read access has two wait states and subsequent accesses have zero wait states.
UM10114
Chapter 3: LPC2210/20 EMC
.
. On the other hand, leading write cycles
.
shows an external memory burst
Fig 11. External burst memory read access (WST1 = 0 and WST1 = 1 examp les)

7. External memory selection

Based on the description of the EMC operation and external memory in general (appropriate read and write access times t can be constructed and used for extern a l mem o ry se lect ion . t CCLK cycle (see Figure 3–9 cycle). f
is the maximum CCLK frequency achievable in the system with selected
max
and Figure 3–10 where one XCLK cycle equals one CCLK
external memory.
Table 10. External memory and system requirements
Access
Maximum frequency WST setting
cycle
Standard Read
User manual Rev. 02 — 27 April 2007 23 of 290
(WST>=0; round up to integer)
AA
and t
respectively), the following table
WRITE
is the period of a single
CYC
Required memory access time
NXP Semiconductors
f
MAX
1WST2+
t
WRITE
5ns+
------------------------------- -
≤
WST2
t
WRITEtCYC
5+–
t
CYC
-------------------------------------------
≥
t
WRITEtCYC
1WST2+()× 5ns–≤
f
MAX
2WST1+
t
INIT
20ns+
----------------------------- -
≤
WST1
t
INIT
20ns+
t
CYC
----------------------------- -
≥ 2–
t
INITtCYC
2WST1+()× 20ns–≤
f
MAX
1
t
ROM
20ns+
------------------------------ -
≤
t
ROMtCYC
20ns–≤
Table 10. External memory and system requirements
Access cycle
Standard Write
Burst read (initial)
Maximum frequency WST setting
(WST>=0; round up to integer)
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Chapter 3: LPC2210/20 EMC
Required memory access time
Burst read subsequent 3x
N/A
User manual Rev. 02 — 27 April 2007 24 of 290
UM10114

Chapter 4: System control

Rev. 02 — 27 April 2007 User manual

1. Summary of system control block functions

The System Control Block includes several system features and control registers for a number of functions that are not related to specific peripheral devices. These include:
• Crystal Oscillator
• External Interrupt Inputs
• Miscellaneous System Controls and Status
• Memory Mapping Control
• PLL
• Power Control
• Reset
• APB Divider
• Wakeup Timer
Each type of function has its own register(s) if any are required and unneeded bits are defined as reserved in order to allow future expansion. Unrelated functions never share the same register addresses

2. Pin description

Table 4–11 shows pins that are associated with System Control block functions.
Table 11. Pin summary
Pin name Pin
XTAL1 Input Crystal Oscillator Input - Input to the oscillator and internal clock
XTAL2 Output Crystal Oscillator Output - Output from the oscillator amplifier EINT0 Input External Interrupt Input 0 - An active low/high level or
EINT1 Input External Interrupt Input 1 - See the EINT0 description above.
Pin description
direction
generator circuits
falling/rising edge general purpose interrupt input. This pin may be used to wake up the processor from Idle or Power-down modes.
Pins P0.1 and P0.16 can be selected to perform EINT0 function.
Pins P0.3 and P0.14 can be selected to perform EINT1 function. Important: LOW level on pin P0.14 immediately after reset is
considered as an external hardware request to start the ISP command handler. More details on ISP and Serial Boot Loader can be found in "On-chip Serial Bootloader" chapter on page 242.
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Table 11. Pin summary
Pin name Pin
EINT2 Input External Interrupt Input 2 - See the EINT0 description above.
EINT3 Input External Interrupt Input 3 - See the EINT0 description above.
RESET

3. Register description

All registers, regardless of size, are on word address boundaries. Details of the registers appear in the description of each function.
T able 12. Summary of system control registers
Name Description Access Reset
External Interrupts
EXTINT External Interrupt Flag Register R/W 0 0xE01F C140 EXTWAKE External Interrupt Wakeup Register R/W 0 0xE01F C144 EXTMODE External Interrupt Mode Register R/W 0 0xE01FC148 EXTPOLAR External Interrupt Polarity Register R/W 0 0xE01F C14C
Memory Mapping Control
MEMMAP Memory Mapping Control R/W 0 0xE01F C040
Phase Locked Loop
PLLCON PLL Control Register R/W 0 0xE01F C080 PLLCFG PLL Configuration Register R/W 0 0xE01F C084 PLLSTAT PLL Status Register RO 0 0xE01F C088 PLLFEED PLL Fee d Register WO NA 0xE01F C08C
Power Control
PCON Power Control Register R/W 0 0xE01F C0C0 PCONP Power Control for Peripherals R/W 0x1FBE 0xE01F C0C4
APB Divider
APBDIV APB Divider Control R/W 0 0xE01F C100
Syscon Miscellaneous Registers
SCS System Controls and Status R/W 0 0xE01F C1A0
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Chapter 4: LPC2210/20 System control
Pin description
direction
Pins P0.7 and P0.15 can be selected to perform EINT2 function.
Pins P0.9, P0.20 and P0.30 can be selected to perform EINT3 function.
Input External Reset input - A LOW on this pin resets the chip, causing
I/O ports and peripherals to take on their default states, and the processor to begin execution at address 0x0000 0000.
Address
value
[1]
[1] Reset value reflects the data stored in used bits only. It does not include reserved bits content.
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LPC2xxx LPC2xxx
Clock
C
C
C
X1
C
X2
C
L
C
P
L
R
S
< = >
a) b) c)
Xtal
XTAL1 XTAL2
XTAL1 XTAL2

4. Crystal oscillator

While an input signal of 50-50 duty cycle within a frequency range from 1 MHz to 50 MHz can be used by the LPC2210/2220 and LPC2210/01 if supplied to its input XTAL1 pin, this microcontroller’s onboard oscillator circuit supports external crystals in the range of 1 MHz to 30 MHz only. If the on-chip PLL system or the boot-loader is used, the input clock frequency is limited to an exclusive range of 10 MHz to 25 MHz.
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Chapter 4: LPC2210/20 System control
The oscillator output frequency is called F referred to as CCLK for purposes of rate equations, etc. elsewhere in this document. F
and the ARM processor clock frequency is
OSC
OSC
and CCLK are the same value unless the PLL is running and connected. Refer to the
Section 4–8 “
Phase Locked Loop (PLL)” on page 35 for details and frequency limitations.
The onboard oscillator in the LPC2210/2220 and LPC2210/01 can operate in one of two modes: slave mode and oscillation mode.
In slave mode the input clock signal should be coupled by means of a capacitor of 100 pF (C
in Figure 4–12, drawing a), with an amplitude of at least 200 mVrms. The X2 pin in
C
this configuration can be left not connected. If slave mode is selected, the F
signal of
OSC
50-50 duty cycle can range from 1 MHz to 50 MHz. External components and models used in oscillation mode are shown in Figure 4–12
drawings b and c, and in Table 4–13 only a crystal and the capacitances C
. Since the feedback resistance is integrated on chip,
and CX2 need to be connected externally in case
X1
of fundamental mode oscillation (the fundamental frequency is represented by L, C R
). Capacitance CP in Figure 4–12, drawing c, repr e sen ts the parallel package
S
capacitance and should not be larger than 7 pF. Parameters F
, CL, RS and CP are
C
,
and
L
supplied by the crystal manufacturer. Choosing an oscillation mode as an on-board oscillator mode of operation limits F
OSC
clock selection to 1 MHz to 30 MHz.
Fig 12. Oscillator modes and models: a) slave mode of operation, b) oscillation mode of operation, c) external
User manual Rev. 02 — 27 April 2007 27 of 290
crystal model used for C
evaluation
X1/X2
NXP Semiconductors
true
MIN f
OSC
= 10 MHz
MAX f
OSC
= 25 MHz
true
MIN f
OSC
= 1 MHz
MAX f
OSC
= 50 MHz
MIN f
OSC
= 1 MHz
MAX f
OSC
= 30 MHz
mode a and/or b mode a mode b
on-chip PLL used
in application?
ISP used for initial
code download?
external crystal
oscillator used?
true
false
false
false
f
OSC
selection
T able 13. Recommended values for C
Fundamental oscillation frequency F
OSC
1 MHz - 5 MHz 10 pF NA NA
5 MHz - 10 MHz 10 pF < 300 Ω 18 pF, 18 pF
10 MHz - 15 MHz 10 pF < 300 Ω 18 pF, 18 pF
15 MHz - 20 MHz 10 pF < 220 Ω 18 pF, 18 pF
20 MHz - 25 MHz 10 pF < 160 Ω 18 pF, 18 pF
25 MHz - 30 MHz 10 pF < 130 Ω 18 pF, 18 pF
components parameters)
Crystal load capacitance C
20 pF NA NA 30 pF < 300 Ω 58pF, 58 pF
20 pF < 300 Ω 38 pF, 38 pF 30 pF < 300 Ω 58 pF, 58 pF
20 pF < 220 Ω 38 pF, 38 pF 30 pF < 140 Ω 58 pF, 58 pF
20 pF < 140 Ω 38 pF, 38 pF 30 pF < 80 Ω 58 pF, 58 pF
20 pF < 90 Ω 38 pF, 38 pF 30 pF < 50 Ω 58 pF, 58 pF
20 pF < 50 Ω 38 pF, 38 pF 30 pF NA NA
Chapter 4: LPC2210/20 System control
in oscillation mode (crystal and external
X1/X2
Maximum crystal
L
series resistance R
External load capacitors C
S
UM10114
X1, CX2
Fig 13. F
selection algorithm
OSC
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5. External interrupt inputs

The LPC2210/2220 and LPC2210/01 include four External Interrupt Inputs as select able pin functions. The External Interrupt Inputs can optionally be used to wake up the processor from Power-down mode.

5.1 Register description

The external interrupt function has four registers associated with it. The EXTINT register contains the interrupt flags, and the EXTWAKE register cont ains bits that enable individual external interrupts to wake up the microcontroller from Power-down mode. The EXTMODE and EXTPOLAR registers specify the level and edge sensitivity parameters.
Table 14. External interrupt registers
Name Description Access Reset
EXTINT The External Interrupt Flag Register contains
interrupt flags for EINT0, EINT1, EINT2 and EINT3. See Table 4–15
EXTWAKE The External Interrupt Wakeup Register
contains four enable bits that control whether each external interrupt will cause the processor to wake up from Power-down mode. See
Table 4–16
EXTMODE The External Interrupt Mode Register controls
whether each pin is edge- or level sensitive.
EXTPOLAR The External Interrupt Polarity Register controls
which level or edge on each pin will cause an interrupt.
UM10114
Chapter 4: LPC2210/20 System control
Address
[1]
value
R/W 0 0xE01F C140
.
R/W 0 0xE01F C144
.
R/W 0 0xE01F C148
R/W 0 0xE01F C14C
[1] Reset value reflects the data stored in used bits only. It does not include reserved bits content.

5.2 External Interrupt Flag register (EXTINT - 0xE01F C140)

When a pin is selected for its external interrupt function, the level or edge on that pin (selected by its bits in the EXTPOLAR a nd EXTMODE registers) will set its interrupt fla g in this register. This asserts the corresponding interrupt request to the VIC, which will cause an interrupt if interrupts from the pin are enabled.
Writing ones to bits EINT0 through EINT3 in EXTINT register clears the corre sp onding bits. In level-sensitive mode this action is efficacious only when the pin is in its inactive state.
Once a bit from EINT0 to EINT3 is set and an appropriate code star ts to execute (hand ling wakeup and/or external interrupt), this bit in EXTINT register must be cleared. Otherwise the event that was just triggered by activity on the EINT pin will not be recognized in the future.
Important: whenever a change of externa l interrupt operating mode (i.e. active level/edge) is performed (including the initialization of an external interrupt), the corresponding bit in the EXTINT register must be cleared! For details see Section
4–5.4 “External Interrupt Mode register (EXTMODE - 0xE01F C148)” and Section 4–5.5 “External Interrupt Polarity register (EXTPOLAR - 0xE01F C14C)”.
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Chapter 4: LPC2210/20 System control
For example, if a system wakes up from power-down using a low level on external interrupt 0 pin, its post-wakeup code must reset the EINT0 bit in order to a llow future entry into the power-down mode. If the EINT0 bit is left set to 1, subsequent attempt(s) to invoke power-down mode will fail. The same goes for external interrupt handling.
More details on power-down mode will be discussed in the following chapters.
Table 15. External Interrupt Flag register (EXTINT - address 0xE01F C140) bit description
Bit Symbol Description Reset
0 EINT0 In level-sensitive mode, this bit is set if the EINT0 function is selected for its pin, and the pin is in
1 EINT1 In level-sensitive mode, this bit is set if the EINT1 function is selected for its pin, and the pin is in
2 EINT2 In level-sensitive mode, this bit is set if the EINT2 function is selected for its pin, and the pin is in
3 EINT3 In level-sensitive mode, this bit is set if the EINT3 function is selected for its pin, and the pin is in
7:4 - Reserved, user software should not write ones to reserved bits. The value read from a reserved
value
0 its active state. In edge-sensitive mode, this bit is set if the EINT0 function is selected for its pin, and the selected edge occurs on the pin.
Up to two pins can be selected to perform the EINT0 function (see P0.1 and P0.16 description in "Pin Configuration" chapter page 63.)
This bit is cleared by writing a one to it, except in level sensitive mode when the pin is in its active state (e.g. if EINT0 is selected to be low level sensitive and a low level is present on the corresponding pin, this bit can not be cleared; this bit can be cleared only when the signal on the pin becomes high).
0 its active state. In edge-sensitive mode, this bit is set if the EINT1 function is selected for its pin, and the selected edge occurs on the pin.
Up to two pins can be selected to perform the EINT1 function (see P0.3 and P0.14 description in "Pin Configuration" chapter on page 63.)
This bit is cleared by writing a one to it, except in level sensitive mode when the pin is in its active state (e.g. if EINT1 is selected to be low level sensitive and a low level is present on the corresponding pin, this bit can not be cleared; this bit can be cleared only when the signal on the pin becomes high).
0 its active state. In edge-sensitive mode, this bit is set if the EINT2 function is selected for its pin, and the selected edge occurs on the pin.
Up to two pins can be selected to perform the EINT2 function (see P0.7 and P0.15 description in "Pin Configuration" chapter on page 63.)
This bit is cleared by writing a one to it, except in level sensitive mode when the pin is in its active state (e.g. if EINT2 is selected to be low level sensitive and a low level is present on the corresponding pin, this bit can not be cleared; this bit can be cleared only when the signal on the pin becomes high).
0 its active state. In edge-sensitive mode, this bit is set if the EINT3 function is selected for its pin, and the selected edge occurs on the pin.
Up to three pins can be selected to perform the EINT3 function (see P0.9, P0.20 and P0.30 description in "Pin Configuration" chapter on page 63.)
This bit is cleared by writing a one to it, except in level sensitive mode when the pin is in its active state (e.g. if EINT3 is selected to be low level sensitive and a low level is present on the corresponding pin, this bit can not be cleared; this bit can be cleared only when the signal on the pin becomes high).
NA bit is not defined.
User manual Rev. 02 — 27 April 2007 30 of 290
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