NXP Semiconductors DSPAUDIOEVM User Manual

This document contains information on a new product under development by Motorola.
Motorola reserves the right to change or discontinue this product without notice.

Order Number: DSPAUDEVMEBUM/D

Revision 1, January 2003

© Motorola, Inc., 2003. All rights reserved.

User’s Manual

DSPAUDIOEVM Evaluation Board

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MOTOROLA DSPAUDIOEVM Evaluation Board Users Manual TOC-1

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TABLE OF CONTENTS

SECTION 1
OVERVIEW

1.1 Introduction ............................................................................................................................. 1

1.2 DSPAUDIOEVM Architecture ..................................................................................................1

1.2.1 Daughterboard ................................................................................................................... 1

1.2.2 Motherboard ....................................................................................................................... 1

1.3 Debugger Interfaces ................................................................................................................ 2

1.3.1 Suite56 OnCE ‰ Debugger ............................................................................................... 2

1.3.2 Symphony Debugger Interface ........................................................................................... 2

1.4 Microcontrollers ....................................................................................................................... 2

1.5 Config MPU ............................................................................................................................. 2

1.6 Debug MPU ............................................................................................................................. 2

1.7 Getting Started......................................................................................................................... 2

1.8 Running the Passthru Code..................................................................................................... 3

SECTION 2

MOTHERBOARD

2.1 Introduction ............................................................................................................................. 4

2.2 Configuration Jumpers............................................................................................................. 4

2.2.1 JP1/JP2 - S/PDIF Transmitter Output ................................................................................ 4

2.2.2 JP3/JP4 – S/PDIF Receiver Input ..................................................................................... 4

2.2.3 JP5 — Pass-thru Header.................................................................................................... 5

2.2.4 Debugger and Microcontroller Configuration ...................................................................... 5

2.2.4.1 PJ6 Debug MPU Crystal Selection ............................................................................... 6

2.2.4.2 JP7 – MPU Program Control ........................................................................................ 6

2.2.4.3 JP8 – SHI Debug Source Selection .............................................................................. 6

2.2.4.4 JP9 – OnCE/JTAG Debugger Source Selection .......................................................... 6

2.2.4.5 JP10 – Config / Debug MPU Communication .............................................................. 6

2.2.4.6 JP11 – AUX Mode Input Source Selection ................................................................... 7

2.3 Signal Headers ........................................................................................................................7

2.3.1 P1 — PPI Header ..............................................................................................................7

2.3.2 P2 — OnCE Header ...........................................................................................................8

2.3.3 P3 — ANALOG I/O ............................................................................................................. 8

2.3.4 TP1 / TP2 Headers ............................................................................................................. 9

2.4 On-board Debugger Connections ........................................................................................... 9

2.4.1 J2 — USB Interface 9

2.4.2 J3 — RS232 Interface ........................................................................................................ 9

2.4.3 J4 — Parallel Port Debugger Interface ............................................................................... 9

2.5 External I/O ............................................................................................................................ 10

2.5.1 J9 / J10 — Microphone Inputs ......................................................................................... 10

2.5.1.1 RV1/RV2 - Microphone Gain Control ......................................................................... 10

2.5.2 J11 / J12 — Analog Outputs .................................................................................................. 10

2.5.3 J13 — Headphone Outputs ................................................................................................... 11

2.5.3.1 SW2 / SW3 — Channel Select ...................................................................................11

2.5.3.2 RV3 / RV4 — Headphone Volume Select ..................................................................11

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TOC-2 DSPAUDIOEVM Evaluation Board Users Manual MOTOROLA

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SECTION 3

DAUGHTERBOARD

3.1 DSPX36XDB1 ....................................................................................................................... 12

3.2 Mode Selection ...................................................................................................................... 12

3.3 Memory..................................................................................................................................13

3.4 JP11 - Clock Selection........................................................................................................... 13

3.5 Daughterboard Audio I / O and Clock Control Header .......................................................... 13

3.5.1 TIO0 – Timmer Port ......................................................................................................... 13

3.5.2 JP1 - Synchronous/Asynchronous Clock Control ............................................................. 13

3.5.3 JP2 – Single/Double Speed Clocking Control .................................................................. 13

3.5.4 JP3 - FST_1 Connection .................................................................................................. 14

3.5.5 JP4 – SCKT_1 Connection...............................................................................................14

3.5.6 JP5 - FSR_1 Connection ..................................................................................................14

3.5.7 JP6 - SCKR_1 Connection ...............................................................................................14

3.5.8 JP7 - DSP MUTE Control ................................................................................................. 14

3.5.9 JP8 - INT_0/SPDIF Error Flag Connection.......................................................................14

3.5.10 JP9 - SDO5/SDI0 Configuration .......................................................................................14

3.5.11 JP10 SDO4/SDI1 Configuration ....................................................................................... 14

SECTION 4

EVM BILL OF MATERIALS

EVM Bill of Materials ........................................................................................................ 15

APPENDIX A

Motherboard Schematics ................................................................................................. 31

Motherboard Layout ........................................................................................................ 43

Daughterboard Schematics .............................................................................................45

Daughterboard Layout ..................................................................................................... 49

APPENDIX B

PASSTHRU CODE

B.1 56362 / 366 / 367 Passthru Code ..........................................................................................50

B.2 56364 Passthru Code ...........................................................................................................55

SUPPORTING DOCUMENTATION

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MOTOROLA DSPAUDIOEVM Evaluation Board Users Manual LOF-1

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LIST OF FIGURES

Figure A.1 DSP563XX Evaluation Platform Block Diagram .............................................................. 31

Figure A.2 DSP563XX Evaluation Platform DACA 1-3 ..................................................................... 32

Figure A.3 DSP563XX Evaluation Platform DACB 4-6 ..................................................................... 33

Figure A.4 DSP563XX Evaluation Platform ADC 1-2 ........................................................................ 34

Figure A.5 DSP563XX Evaluation Platform Configuration MPU ....................................................... 35

Figure A.6 DSP563XX Evaluation Platform Headphone Amplifier and Mixer ................................... 36

Figure A.7 DSP563XX Evaluation Platform SPDIF ........................................................................... 37

Figure A.8 DSP563XX Evaluation Platform PPI and JTAG Command Converter ............................38

Figure A.9 DSP563XX Evaluation Platform JTAG/PPI Debugger MPU ............................................ 39

Figure A.10 DSP563XX Evaluation Platform DSP Daughter Card ..................................................... 40

Figure A.11 DSP563XX Evaluation Platform Power and MCLK Lost Detect and Systems Reset ......41

Figure A.12 DSP563XX Evaluation Platform Notes and Tables ......................................................... 42

Figure A.13 Top Motherboard Assembly Layout ................................................................................. 43

Figure A.14 Bottom Motherboard Assembly Layout ...........................................................................44

Figure A.15 Daughter Card DSP56362/366/367 .................................................................................45

Figure A.16 Daughter Card DSP56364 ...............................................................................................46

Figure A.17 DSP56367 Daughter Card Memory ................................................................................. 47

Figure A.16 DSP56367 Daughter Card Connectors ...........................................................................48

Figure A.19 Top Daughterboard Assembly Layout ............................................................................. 49

Figure A.20 Bottom Daughterboard Assembly Layout ........................................................................ 49

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LIST OF TABLES

Table 2.1 JP1 / JP2 – S/PDIF Transmitter Output ............................................................................. 4

Table 2.2 JP3 / JP4 – S/PDIF Receiver Input ................................................................................... 5

Table 2.3 JP5 — PASS-THRU Header ............................................................................................. 5

Table 2.4 JP6XXX – Debug MPU Crystal Selection .......................................................................... 5

Table 2.5 JP11 Selections ................................................................................................................. 7

Table 2.6 P1 — PPI Header ..............................................................................................................7

Table 2.7 P2 — OnCE Header ..........................................................................................................8

Table 2.8 P3 — Analog I / O .............................................................................................................. 8

Table 2.9 TP1 Header — GP TP1–8 .................................................................................................9

Table 2.10 TP2 Header — GP TP9–16 ...............................................................................................9

Table 2.11 J11 ...................................................................................................................................10

Table 2.12 J12....................................................................................................................................10

Table 3.1 Mode Selection for 56362/366/367 .................................................................................. 12

Table3.2 Mode Selection for 56364 ................................................................................................ 12

Table 3.3 Daughterboard Audio I / O and Clock Control Header ....................................................13

Table 4.1 EVM Bill of Materials ........................................................................................................15

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MOTOROLA DSPAUDIOEVM Evaluation Board Users Manual 1

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SECTION 1 OVERVIEW

1.1 Introduction

The DSPAUDIOEVM Evaluation Board is used to demonstrate the abilities of the DSP56362, DSP56364,
DSP56366, and DSP56367 Digital Signal Processors and to provide a hardware tool allowing the
development of applications that use these devices.

The DSPAUDIOEVM is designed for the following purposes:

• To allow new users to become familiar with the features of the 56300 architecture: The tools and examples
provided with the DSPAUDIOEVM facilitate evaluation of the feature set and the benefits of the family.

• To serve as a platform for real-time software development: The tool suite enables the user to develop and
simulate routines, download the software to on-chip or on-board RAM, and then run and debug the
software using a debugger via the JTAG/OnCE port or the Serial Host Interface port. The breakpoint
features of the OnCE port enable the user to easily specify break conditions and to execute user­developed software at full speed, until the break conditions are satisfied. The ability to examine and
modify all user-accessible registers, memory, and peripherals through the OnCE or SHI port greatly
facilitates the task of the developer.

• To serve as a platform for hardware development. The hardware platform enables the user to connect
external hardware peripherals. The on-board peripherals can be disabled, providing the user with the
ability to reassign any and all of the DSP’s peripherals. The OnCE port’s unobtrusive design means that
all of the memory on the board and on the DSP chip is available to the user.

1.2 DSPAUDIOEVM Architecture

The DSPAUDIOEVM Audio EVM system is a development tool for authoring and testing of Digital Audio
DSP software. It can also be used as a demo platform for Motorola’s digital audio DSP technologies. The
EVM system consists of a motherboard and a daughterboard (Ordered separately).

1.2.1 Daughterboard

The daughterboard connects to the motherboard by way of two 96 pin connectors and includes a 512Kx8
FLASH, three 128Kx8 SRAM (one 128Kx8 for the 56364 daughterboard) and one of the DSP options. The
daughterboard supports all of the 5636X DSPs but will be populated with the DSP associated with the part
number ordered. The daughterboard is designed to be upgraded/replaced as future DSPs become available
while reusing the existing EVM motherboard.

1.2.2 Motherboard

The motherboard has a variety of digital and analog audio I/O including:

• 4 switchable S/PDIF inputs (2 optical and 2 Coaxial)

• 4 simultaneous S/PDIF outputs(3 Coaxial and 1 Coaxial/Optical)

• 12 analog output channels(6 stereo RCA type connectors)

• 2 analog microphone inputs

• 2 analog inputs (1 stereo RCA type connectors)

• Headphone output (can mix any combination of analog signals using switch array)

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The motherboard uses an included external universal power supply (100-220VAC, 50-60 Hz). The power
supply uses an IEC three pin power connector for the AC supply. The user must supply the AC cable
required to connect power to the region specific AC power connection.

1.3 Debugger Interfaces

1.3.1 Suite56 OnCE  Debugger

The motherboard also supports multiple debugger interfaces. The Motorola high speed parallel port OnCE
command converter tool is embedded in the EVM (no special cables are required). An IEEE 1284 Parallel
port cable is included in the EVM kit for convenience.

This OnCE interface can be used with the Motorola Suite56 tool set software and documentation available
at http://www.metroworks.com/MW/Develop/Embedded/suite56.htm

1.3.2 Symphony Debugger Interface

In addition to OnCE debugging, the motherboard includes a real time Symphony Debugger Interface (SDI).
This debugger uses either a RS-232 or USB interface and allows SPI or I

2

C communication to the DSP from
a PC for real time debugging and configuration of the DSP. The software and documentation to enable use
of the SDI debugger are available off the Web:

http://e-www.motorola.com/webapp/sps/site/prod_summary.jsp?code=DSPAUDIOEVM&nodeld=10279539058775#

or go to

http://www.motorola.com, search for DSPAUDIOEVM, and follow the links to the user’s manual.

Note: The SDI software is primarily designed for users of ROMed Software Architecture DSPs,

and it is not the best tool to use for generic DSPs.

1.4 Microcontrollers

There are two HC08 Motorola microcontrollers included in this EVM. They each have a dedicated function
and are re-flashable in the event a field upgrade is required to the EVM.

1.5 Config MPU

This is an HC908GP32 microcontroller and is pre-programmed with software to enable all of the on-board
AKM components and clocking mode changes. This microcontroller also controls the mute functionality of
the final audio outputs and the switching of the inputs sourced to the DSP daughterboard.

1.6 Debug MPU

This is an HC908JB16 and is pre-programmed with software to allow communication (from a host PC to
the DSP) via the serial RS232 and USB ports in conjunction with the supplied SDI debugger software.

1.7 Getting Started

The first step to using your EVM system is to insert the daughterboard into the motherboard. The connectors
are keyed to be inserted in only one direction, but for reference the Motorola white silkscreen should be
oriented identically on the motherboard and daughterboard.

Connecting the power supply is the next step and we recommend always using a grounded AC power cord
for both improved audio performance and safety. Connect the power supply to the AC power source first
and then to the EVM at the round J1 connector. When the connector is properly seated, all five of the power
LEDs located next to the J1 connector should be illuminated.

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1.8 Running the Passthru Code

The daughterboards are shipped with a simple piece of audio passthru code stored in the on-board flash.
The SW1 switch on the daughterboard controls the DSP boot modes, to enable pass-thru mode switch
MODA "on" and MODB "off" on the DSP daughtercard. Switching MODA "off" and MODB "on" will disable
pass-thru mode but will enable use of the SDI debugger. (For more information, refer to the individual DSP
users manuals, as well as Table 3.1 and Table 3.2.)

For the above mentioned passthru function the source device is selected by setting the jumpers of JP11
(AUX in). The default setting from the factory configures the system to source audio data from the optical
RX1 S/PDIF input. Alternate settings are described in the Motherboard Configuration section of this manual.
The DSP passthru software passes the audio sourced from the selected input to the first 4 stereo analog
outputs. You can listen to these outputs by connecting an external amplifier and speaker to the RCA outputs
or by using the built-in headphone amplifier. To use the headphone output select the desired analog output
signals using the left and right channel select switches (SW2/SW3) and adjust the left and right volume
sliders (RV3/RV4).

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SECTION 2 MOTHERBOARD

2.1 Introduction

This section will define the motherboard and daughterboard jumper and switch functionality including their
default setting. The jumpers allow flexibility to re-route signals throughout the board and only the simple
jumper settings will be covered in this documentation. More advanced EVM users will be able to experiment
with alternate configurations using this section in conjunction with the schematic included in Appendix A.
The default jumper settings are indicated with the dark gray boxes.

2.2 Configuration Jumpers

2.2.1 JP1/JP2 - S/PDIF Transmitter Output

The JP1 and JP2 headers are designed to allow selection of the S/PDIF output sources driven by the
daughterboard (DSP), AKM 4101 S/PDIF transmitter, or AKM 4114 S/PDIF receiver. The DSP option on
these jumpers is for future flexibility to allow for multiple S/PDIF signals to be sourced from the
daughterboard directly. One of the S/PDIF signals (TXSD4, TXSD5, or TXSD6) can be directed to the TX4
output by selecting it, using JP2 and selecting the 4101TX4 option in the TX4 section of JP1. The 4114TX
jumper option on TX4 is to allow direct connection of the S/PDIF receiver relay to S/PDIF out. The ADO
jumper option on TX1 allows the S/PDIF transmitter (DAX port) of certain DSPs to be connected to the S/
PDIF output connector.

2.2.2 JP3/JP4 – S/PDIF Receiver Input

The JP3 jumper allows for hardware configuration of the AKM 4114 S/PDIF receiver. The default setting is
for software control mode and the AKM 4114 is configured by the Motorola HC908GP32 configuration
microcontroller on the motherboard.

The JP4 jumper controls the S/PDIF receiver input source to allow direct routing to the daughterboard using
the DSP setting or selecting connection to the AKM 4114 (default).

Table 2.1 JP1 / JP2 – S/PDIF Transmitter Output

TX1 TX2 TX3 TX4 4101TX4

* * * * * * * * * * * * *

* * * * * * * * * * * * *

ADO

DSP

4101

DSP

4101

DSP

4101

DSP

4101TX4

4114TX

TXSD4

TXSD5

TXSD6

JP1 JP2

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2.2.3 JP5 — Pass-thru Header

This jumper block is included to give convenient access to all the critical audio clocks and data lines. These
jumpers can be removed to allow for rerouting of the audio signals within the board and to allow for
expansion to external boards. As an example, this header could be used to connect to an external audio
codec board for evaluation of the Motorola DSP with a specific audio codec.

2.2.4 Debugger and Microcontroller Configuration

Table 2.2 JP3 / JP4 – S/PDIF Receiver Input

IN=HI RX1 RX2 RX3 RX4

* * * * * * * * * *

* * * * * * * * * *

DIF2

DIF0

DSP

4114

DSP

4114

DSP

4114

DSP

4114

JP3 JP4

Table 2.3 JP5 — PASS-THRU Header

MCLK BICK LRCLK SERIAL I / O

M
U
T
E

* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *

* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *

RX01

RX02TXADC

DACA

DACBRXTX

ADC

DACA

DACBRXTX

ADC

DACA

DACBRXADC1

ADC2

TXS01

DACA1/2

TXS02

DACA3/4

TXSD3

DACA5/6

TXSD4

DACB 1/2

TXSD5

DACB3/4

TXCD6

DACB5/6

MUTE

Table 2.4 JP6XXX – Debug MPU Crystal Selection

JB16

EXTAL

PGM MD SHI JTAG MPU COM AUX IN=HI

* * * * * * * * * * * * * * ******

* * * * * * * * * * * * * * ******

RS232

USB/PGM

DEBUG MPU

CONFIG MPU

PGM

PPI PORT

DEBUG MPU

CONFIG MPU

OnCE

USB/RS232

PARALLEL

COM0

COM1

COM2

COM3

AUX1

AUX2

AUX3

AUX4

AUX5

JP6 JP7 JP8 JP9 JP10 JP11

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2.2.4.1 PJ6 Debug MPU Crystal Selection

The JP6 jumper is for selection of RS232 or USB communication when using the SDI debugger. Note that
USB mode is not possible when using the Win NT software version. The RS232 position should be jumpered
when the RS232 interface is used for the SDI debugger, and the USB/PGM position should be used when
using the USB interface for the SDI debugger or when reprogramming of the Debug Micro is required. Only
one of these jumpers should be connected at any one time. Use of the wrong jumper setting will cause SDI
communication failure to occur or a reduction in the data transfer rate.

2.2.4.2 JP7 – MPU Program Control

The JP7 jumpers are only used when the on-board microcontrollers are to be re-programmed. Placing a
jumper in the PGM position places the selected microcontroller in program mode upon power-on. The
microcontroller to be programmed is selected by placing a jumper in either the DEBUG MPU or CONFIG
MPU positions. With no jumper in the PGM position, the other two jumpers are ignored.

2.2.4.3 JP8 – SHI Debug Source Selection

The JP8 jumpers are for selection of various debugger modes. The default selection is for SDI debugger
use. The PPI port can be used with legacy "PPP Development Interface" software and a PPI cable although
the latest SDI debugger software is the preferred option for future upgradability and support. The third
option, CONFIG MPU, is not currently supported on the EVM. Only one jumper position should be used at
any one time.

2.2.4.4 JP9 – OnCE/JTAG Debugger Source Selection

The JP9 jumpers are used for selection of alternative debugging tools such as the Suite 56 OnCE interface
mentioned earlier. To use this, simply connect to a host PC with a parallel cable and have a jumper in the
PARALLEL positions. The OnCE jumper option can be used if the user wishes to connect an external OnCE/
JTAG debugger interface to the board. The USB/RS232 option is not currently supported and only one
jumper should be inserted at a time.

2.2.4.5 JP10 – Config / Debug MPU Communication

The JP10 jumpers provide a communication port between the debug microcontroller and the configuration
microcontroller. When the SDI debugger is used and the AUX5 jumper is out, the SDI debugger interface
controls the audio input source. The JP10 jumpers provide a communication port between the debug
microcontroller and the configuration microcontroller. When the SDI debugger is used, and the AUX5 jumper
is out, the SDI debugger interface controls the audio input source. To allow this, all JP10 jumpers should be
populated.

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2.2.4.6 JP11 – AUX Mode Input Source Selection

The JP11 jumpers are present as an alternative to using the SDI debugger software to select between the
various inputs available. If the AUX5 jumper is present then the following jumper settings will result in the
input selection shown in Table 2.5

2.3 Signal Headers

These headers allow for external debugger connections, analog output signal measurement, and GPIO access.

2.3.1 P1 — PPI Header

The PPI header connections are to allow for backwards compatibility with existing PPI software tool set and
to allow easy access to the SHI port connections from the motherboard. Note that when using PPI source,
JP8 must have PPI Port jumper in place.

Table 2.5 JP11 Selections

Input

Selected

Aux5 Aux4* Aux3 Aux2 Aux1

RX1

1 0 0 0 0

RX2

1 0 0 0 1

RX3

1 0 0 1 0

RX4

1 0 0 1 1

AIN1

1 0 1 0 0

SDI
debugger
selects input

0 X X X X

* When the Aux5 jumper is present, the Aux4 jumper directly

controls the mute functionality of the EVM motherboard.

Table 2.6 P1 — PPI Header

NC(1) * * SS/HA2

GND * * SCK/SCL

GND * * HREQ

SDA * * MOSI / HA0

VDD * * MISO

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2.3.2 P2 — OnCE Header

The P2 OnCE header is for connection of an external OnCE/JTAG debugger tool to the OnCE/JTAG port of the
DSP on the daughterboard. Further explanation of the OnCE/JTAG signal definition can be found in the DSP
users manuals. The P2 OnCE header is for connection of an external OnCE/JTAG debugger tool to the OnCE/
JTAG port of the DSP on the daughterboard. Further explanation of the OnCE/JTAG signal definition can be found
in the DSP users manuals. Note that when using an external OnCE/JTAG debugger tool, the JP9 JTAG jumper
should be in the "OnCE" position.

2.3.3 P3 — ANALOG I/O

The Analog I/O header allows for analog access to input signals before the A/D (AIN1) op-amp stage and
the output signals after the D/A (AO1-6) op-amp stage. This section is provided for ease of analog
measurement and analog I/O connector relocation.

Table 2.7 P2 — OnCE Header

TDI(1) * * GND

TDO * * GND

TCK * * GND

N/C * KEY

RESET * * TMS

VDD * * N/C

N/C * * N/C

Table 2.8 P3 — Analog I / O

AO6 AO5 AO4 AO3 AO2 AO1 AIN1

R L R L R L R L R L R L R L

* * * * * * * * * * * * * *

* * * * * * * * * * * * * *

GND

P3

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2.3.4 TP1 / TP2 Headers

TP1 and TP2 jumper blocks route to daughterboard for GPIO test points and future flexibility. On the DSP
56362/6/7 parts, as an example, these headers are connected to the DSP HDI08 port. See daughterboard
schematics and appendix for device specifics.

2.4 On-board Debugger Connections

The connectors discussed in this section are the on-board debuggers. For specific information on using the
debuggers, see the relevant User’s Manuals.

2.4.1 J2 — USB Interface

This connector is used in conjunction with the SDI software to debug a DSP using USB communications.
See Section 2.2.4 Debugger and Microcontroller Configuration for the proper jumper settings to use this
interface.

2.4.2 J3 — RS232 Interface

This connector can be used for debugging or for in-field updating of the microcontroller code. To use this
port for debugging, the SDI software must be used. See Section 2.2.4 Debugger and Microcontroller

Configuration for the proper jumper settings to use this interface.

2.4.3 J4 — Parallel Port Debugger Interface

This connector is used for the on-board Suite56 Parallel Port Command Converter. In conjunction with the
Suite56 software, this interface provides a high-speed debugger connection through the JTAG/OnCE port
of the DSP. See Section 2.2.4 Debugger and Microcontroller Configuration for the proper jumper settings to
use this interface.

Table 2.9 TP1 Header — GP TP1–8

TP1 * * TP8

TP2 * * TP7

TP3 * * TP6

TP4 * * TP5

Table 2.10 TP2 Header — GP TP9–16

TP9 * * TP16

TP10 * * TP15

TP11 * * TP14

TP12 * * TP13

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2.5 External I/O

2.5.1 J9 / J10 — Microphone Inputs

There are two microphone inputs available at 1/8inch microphone connectors J9 and J10 labeled MIC1 and
MIC2. These can also be monitored via headphones by switching MIC1 and MIC2 on. The input levels of
these can be adjusted with the potentiometers at RV1 and RV2 labeled MIC1 LEVEL and MIC2 LEVEL.
These signals are connected to the ADC2 A/D converter.

Note: If 1/4 inch to 1/8 inch adaptors are used for the microphone connection use only stereo-

stereo or mono-mono style adapters. Stereo-mono or mono-stereo adapters will result in
a short of the incoming audio signal to ground.

2.5.1.1 RV1/RV2 - Microphone Gain Control

These potentiometers control the input levels for MIC1 and MIC2 respectively. To prevent damage, always
start with these controls in a low setting, i.e., twisted left. These inputs can be monitored directly, using the
on-board headphone amplifier.

2.5.2 J11 / J12 — Analog Outputs

Fixed pre-amp outputs (Variable through Digital Volume control on the DSP) are provided for 12 channels
of output. These RCA connections can be fed into a variable or fixed amplifier stage. Care should be taken
to verify signal integrity before connecting to large fixed amplifiers to avoid audible noise or speaker
damage.

These outputs are located at J11 and J12.

Table 2.11 J11

AOUT1 AOUT2 AOUT3

White White White

Red Red Red

Table 2.12 J12

AOUT4 AOUT5 AOUT6

White White White

Red Red Red

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If using the Software Architecture, the analog outputs correspond to the following:

AOUT1 WHITE Left Main

AOUT1 RED Right Main

AOUT2 WHITE Left Surround

AOUT2 RED Right Surround

AOUT3 WHITE Center

AOUT3 RED Subwoofer

AOUT4 WHITE Left Back

AOUT4 RED Right Back

AOUT5 WHITE Left Secondary

AOUT5 RED Right Secondary

AOUT6 WHITE Unassigned

AOUT6 RED Unassigned

2.5.3 J13 — Headphone Outputs

These channels can also be monitored with the on-board headphone amplifier. The channel listened to is
selected via switches SW2 and SW3. Moving the switch to the right will enable the corresponding channel.
There are right and left volume sliders (RV3 and RV4) to allow variations in volume level and balance
control. Headphones should be plugged in to the J13 1/8-inch headphone connector.

2.5.3.1 SW2 / SW3 — Channel Select

These switches control what is routed to the on-board headphone amplifier. Moving the switch to the right
will enable the corresponding channel. Multiple switches/channels can be enabled at one time, and the
signals will be summed into the the corresponding headphone channel.

2.5.3.2 RV3 / RV4 — Headphone Volume Select

These sliders allow for volume and balance adjustment for the headphone amplifier. To help prevent
damage to headphones or hearing, always start with the sliders in a low-volume position.

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SECTION 3 DAUGHTERBOARD

3.1 DSPX36XDB1

These daughterboard connection and jumper definitions are specific to the DSPX36XDB1 boards. Any
future alternate daughterboards will have additional documentation.

3.2 Mode Selection

Various boot-up modes can be selected via the MODE pins and pins PB13 and PB14 settings can be determined
using switch bank SW1. Switch position “ON”= signal high. Table 13 shows the modes available for the 56362/
366/367. Table 14 shows the modes available for 56364. See part-specific user manual for full details.

* These modes are only applicable to DSPs which have the embedded ROM based Software

Architecture (SA).

Note: All other modes are reserved and should not be used.

Table 3.1 Mode Selection for 56362/366/367

MODD MODC MODB MODA PB14* PB13* Mode

0 0 0 0 X X Expanded mode (execute from $C00000)

0 0 0 1 X X Bootstrap from external FLASH

0 0 1 0 0 1 Bootstrap SA in SPI mode*

0 0 1 0 1 1

Bootstrap SA in I2C mode*

0 1 0 1 X X Boot from SHI (slave SPI mode)

0 1 1 1 X X

Boot from SHI (slave I2C mode)

1 0 0 0 X X Expanded mode (execute from $008000)

1 1 0 0 X X Bootstrap in HDI08 ISA mode

1 1 0 1 X X Bootstrap in HDI08 HC11 mode

1 1 1 0 X X Bootstrap in HDI08 8051 mode

1 1 1 1 X X Bootstrap in HDI08 69302 mode

Table 3.2 Mode Selection for 56364

MODD MODC MODB MODA Mode

0 X 0 0 Jump to PROM starting address

0 X 0 1 Bootstrap from byte-wide memory

0 X 1 0 Reserved

0 X 1 1 Reserved for Burn-in testing

1 X 0 0 Reserved

1 X 0 1 Bootstrap from SHI (slave SPI mode)

1 X 1 0 Bootstrap from SHI (slave I2C mode, clock freeze

enabled)

1 X 1 1 Bootstrap from SHI (slave I2C mode, clock freeze disabled

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MOTOROLA DSPAUDIOEVM Evaluation Board Users Manual 13

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3.3 Memory

The daughterboard includes three 128Kx8 SRAM (one 128Kx8 SRAM for the 56364 daughterboard). There
is also a 512Kx8 FLASH device resident on the board. From factory the FLASH is programmed with an
audio passthru code to allow simple verification of initial board operations. See Section 1.8 Running the

Passthru Code for an explanation of running the passthru code.

3.4 JP11 - Clock Selection

Jumper bank JP11 allows for the following clocking modes:

OSC – Clock DSP from canned oscillator at U7 (not Populated)

XTAL – Clock DSP from 24.576MHz crystal at X1 (default mode)

EXT – Clock DSP from motherboard 24.576MHz clock source

Only one of the JP11 options should be populated at the same time.

3.5 Daughterboard Audio I / O and Clock Control Header

3.5.1 TIO0 – Timmer Port

This is connected directly to the TIO0 pin on the DSP.

3.5.2 JP1 - Synchronous/Asynchronous Clock Control

This jumper set controls whether or not the DSP is in synchronous or asynchronous mode. Position B allows
the DSP GPIO (pin PB9) to choose the mode. Position C forces the mode to be asynchronous, and no
jumper forces synchronous mode. In synchronous mode FST is connected to FSR, and SCKT is connected
to SCKR on the ESAI port of the DSP.

3.5.3 JP2 – Single/Double Speed Clocking Control

This jumper set controls whether or not the motherboard is in single or double speed mode. Position D
forces the motherboard into double speed mode. Position E allows the DSP GPIO pin PB11 to control the
mode (e.g., through a PPP), and no jumper forces single speed mode. An example of this signal’s use is for
decoding of DTS 96/24 content. In this mode, it is required to update the masterclock ration expectation in
the D/A converters and S/PDIF transmitters because the DTS 96/24 decoder doubles the audio sample rate
as part of the decoding process.

Table 3.3 Daughterboard Audio I / O and Clock Control Header

TIO0

Sync/Async

Sng/Dbl

FST_1

SCKT_1

FSR_1

SCKR_1

DSP MUTE

INTO

SDO5/SDI0

SDO4/SDI1

* * * * * * * * * * * * * * * * *

* * * * * * * * * * * * * * * * *

A B C D E F G H I J K L M N O P Q

TI0 JP1 JP2 JP3 JP4 JP5 JP6 JP7 JP8 JP9 JP10

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