NXP Semiconductors Digital DNA MSC8102 User Manual And Hardware Detailed Design Description

MSC8102PFCUG/D

Rev. 1.3

MSC8102 - Packet Telephony Farm Card (PFC)

User Guide and Hardware Detailed Design

Description

PFC_DDD_v1.3.doc

Author: Colin McEwan Mark Knox Email: colin.mcewan@motorola.com mark.knox@motorola.com Phone: +44 1355 356061 +44 1355 356034

Networking and Computing Systems Group (NCSG) Colvilles Road, Kelvin Industrial Estate, East Kilbride, Glasgow G75 OTG. 44 (0) 1355 355000. Fax:

44 (0) 1355 260780 Reg. Office: Motorola Ltd., Jays Close, Viables Industrial Estate, Basingstoke, Hants., RG22 4PD

(registration No. 912182 England)

Revision History

Revision By Date Descri p ti o n of Change

1.0 CM 24/1/3 First Issue

1.1 CM 7/3/3 Updated to reflect Pilot Production Boards

1.2 CM 27/3/3 MSC8102 SDRAM increased to 16MB

1.3 CM 21/4/3 Pilot Production Releas e (with quick start guide)

i PFC_DDD_v1.3.doc

CONTENTS

1 OVERVIEW......................................................................................................................................................................1

1.1 SCOPE..............................................................................................................................................................................1

1.2 REFERENCE DOCUMENTS................................................................................................................................................1

2 PFC OVERVIEW.............................................................................................................................................................2

3 PFC FEATURE LIST.......................................................................................................................................................3

4 USER GUIDE....................................................................................................................................................................4

4.1 QUICK START ..................................................................................................................................................................4

4.2 BOARD CONFIGURATION OPTIONS.................................................................................................................................. 5

4.2.1 Single MSC8101 with Default Configuration..........................................................................................................5

4.2.2 MSC8101 Boot thro ug h HD I1 6..................................................................................................... ..........................6

4.2.3 MSC8101 Ethernet /U t op i a Op t i on s .................. .......................................................................................................6

4.2.4 MSC8102 DSI Optio n s............................................................................................................................................6

4.2.5 JTAG options..........................................................................................................................................................6

4.3 PROGRAMMING FLASH....................................................................................................................................................7

5 HARDWARE DESCRIPTION........................................................................................................................................8

5.1 BOARD ARCHITECTURE................................................................................................................................................... 8

5.2 MSC8101 AGGREGATOR & 60X BUS INTERFACE............................................................................................................ 8

5.2.1 MSC8101 SDRAM Interface ................................................................................................................................... 9

5.2.1.1 SDRAM Initialization Command Sequence.................................................................................................. 10

5.2.1.2 SDRAM Refresh........................................................................................................................................... 11

5.2.2 MSC8101 FLA SH Inte rf ace..................................................................................................................................11

5.2.3 MSC8101 60x to DSI Interface.............................................................................................................................12

5.2.3.1 MSC8101 60x to DSI Interface: Synchronous mode.....................................................................................12

5.2.3.2 MSC8101 60x to DSI Interface: Asynchronous mode...................................................................................13

5.2.4 MSC8101 to MSC8102 Interrupt Connectivity......................................................................................................13

5.2.5 MSC8101 FCC Interf ac e.................................. ................................................... ..................... .............................15

5.2.6 RMII Interface.......................................................................................................................................................16

5.2.7 MSC8101 I2C Controlle r......................................................................................................................................16

5.2.8 MSC8101 RS232 Inter fa ce....................................................................................................................................16

5.2.9 MSC8101 Host Interf ace (H D I 16)........................................................................................................................16

5.3 MSC8102 DSP PROCESSING ARRAY.............................................................................................................................17

5.3.1 DSP Array SDRAM Configuration........................................................................................................................17

5.3.1.1 SDRAM Initialization Command Sequence.................................................................................................. 19

5.3.1.2 SDRAM Refresh........................................................................................................................................... 19

5.3.2 MSC8102 Array DSI Interface.............................................................................................................................. 19

5.3.3 MSC8102 Array TDM Interface............................................................................................................................19

5.3.4 MSC8102 RS232 Inter fa ce....................................................................................................................................21

5.4 GENERAL BOARD CONFIGURATION...............................................................................................................................21

5.4.1 Reset......................................................................................................................................................................21

5.4.2 Clock Distribution.................................................................................................................................................22

5.4.3 Power....................................................................................................................................................................24

5.4.4 FPGA Configuration.............................................................................................................................................24

5.4.5 PTMC Connectors.................................................................................................................................................24

5.4.6 JTAG Connectivity................................................................................................................................................29

5.4.7 LEDs.....................................................................................................................................................................30

5.5 PFC BOARD CONFIGURATION.......................................................................................................................................30

6 FIRMWARE IMPL E MEN TA TION.............................................................................................................................32

6.1 MSC8101 HOST MEMORY CONTROLLER SETTINGS......................................................................................................32

6.2 MSC8102 MEMORY CONTROLLER SETTINGS ............................................................................................................... 33

6.3 PFC RESET CONFIGURATION WORD (MSC8101).......................................................................................................... 34

6.4 PFC RESET CONFIGURATION WORD (MSC8102).......................................................................................................... 35

6.5 PFC BOOTSTRAP...........................................................................................................................................................35

7 PFC BASE CARD...........................................................................................................................................................37

7.1 UTOPIA INTERFACE.....................................................................................................................................................37

7.2 I2C INTERFACE ............................................................................................................................................................. 38

7.3 HDI16 INTERFACE ........................................................................................................................................................38

7.4 CT BUS INTERFACE.......................................................................................................................................................39

7.5 ETHERNET INTERFACE ..................................................................................................................................................39

APPENDIX A PFC PARTS..................................................................................................................................................... 41

ii PFC_DDD_v1.3.doc

APPENDIX B PFC BASE CARD PARTS..............................................................................................................................43

APPENDIX C JTAG CONFIGURATION FILE (21 CORES).............................................................................................44

APPENDIX D PFC LAYOUT.................................................................................................................................................45

FIGURES

FIGURE 1. MSC8102 - PACKET TELEPHONY FARM CARD .............................................................................................................. 2

FIGURE 2. PFC SETUP ....................................................................................................................................................................4

FIGURE 3. PACKET TELEPHONY FARM CARD ARCHITECTURE........................................................................................................8

FIGURE 4. SDRAM MODE REGISTER SETTINGS...........................................................................................................................11

FIGURE 5. REFRESH CALCULATIONS ............................................................................................................................................11

FIGURE 6. PFC TO DSI INTERFACE...............................................................................................................................................13

FIGURE 7. AGGREGATOR MSC8102 INTERRUPT CONNECTIVITY OPTIONS...................................................................................14

FIGURE 8. STANDARD INTERRUPT ROUTING ................................................................................................................................14

FIGURE 9. SDRAM MODE REGISTER SETTINGS...........................................................................................................................19

FIGURE 10. REFRESH CALCULATIONS ........................................................................................................................................... 19

FIGURE 11. TDM TO CT ROUTING ............................................................................................................................................... 20

FIGURE 12. PORESET SCHEME ...................................................................................................................................................22

FIGURE 13. HRESET SCHEME .....................................................................................................................................................22

FIGURE 14. MSC8101 AGGREGATOR CLOCKING SCHEME ...........................................................................................................23

FIGURE 15. MSC8102 AND SDRAM CLOCKING .......................................................................................................................... 23

FIGURE 16. SETTING VOUT WITH RESISTOR-DIVIDER..................................................................................................................24

FIGURE 17. JTAG CHAIN .............................................................................................................................................................30

FIGURE 18. MSC8101 HOST MEMORY MAP ................................................................................................................................33

FIGURE 19. MSC8102 MEMORY MAP ..........................................................................................................................................34

FIGURE 20. PFC BOOTSTRAP METHOD ........................................................................................................................................36

FIGURE 21. PFC & BASE CARD LAYOUT......................................................................................................................................37

FIGURE 22. PFC LAYOUT - TOP.................................................................................................................................................... 45

FIGURE 23. PFC LAYOUT - BOTTOM ............................................................................................................................................45

TABLES

TABLE 1. REFERENCE DOCUMENTS................................................................................................................................................1

TABLE 2. MSC8101 BOOT FROM FLASH ........................................................................................................................................ 5

TABLE 3. MSC8102 BOOT THROUGH DSI......................................................................................................................................5

TABLE 4. FULL CHAIN (JTAG OF 21)..............................................................................................................................................5

TABLE 5. MSC8101 DEFAULT RESET CONFIGURATION WORD......................................................................................................5

TABLE 6. MSC8101 HDI16 BOOT..................................................................................................................................................6

TABLE 7. JTAG OPTIONS...............................................................................................................................................................6

TABLE 8. MSC8101 MEMORY CONTROLLER RESOURCES..............................................................................................................9

TABLE 9. PSDMR SETTINGS ..........................................................................................................................................................9

TABLE 10. OR & BR SETTINGS....................................................................................................................................................10

TABLE 11. MSC8102 DSI ADDRESSES.........................................................................................................................................11

TABLE 12. MSC8102 DSI ADDRESSES.........................................................................................................................................12

TABLE 13. DSI ASYNCHRONOUS SIGNALS ................................................................................................................................... 1 3

TABLE 14. FCC1 INTERFACE........................................................................................................................................................15

TABLE 15. MSC8101 AGGREGATOR FCC2 PTMC CONNECTIVITY ............................................................................................. 16

TABLE 16. HDI6 CONFIGURATION...............................................................................................................................................17

TABLE 17. PSDMR SETTINGS ......................................................................................................................................................18

TABLE 18. OR SETTINGS ..............................................................................................................................................................18

TABLE 19. TDM TO CT STREAM ROUTING..................................................................................................................................21

TABLE 20. MSC8101 CLOCK FREQUENCIES .................................................................................................................................22

TABLE 21. MSC8102 CLOCK FREQUENCIES .................................................................................................................................22

TABLE 22. PN1/JN1 CONNECTOR PIN OUT (CPORT INTERFACE).................................................................................................25

TABLE 23. PN2/JN2 CONNECTOR PIN OUT (HOST PORT INTERFACE)...........................................................................................26

TABLE 24. PN3/JN3 CONNECTOR PIN OUT (CT BUS & RMII)......................................................................................................27

TABLE 25. PN4/JN4 CONNECTOR PIN OUT (UTOPIA) .................................................................................................................28

TABLE 26. PN5/JN5 CONNECTOR PIN OUT (ETHERNET)............................................................................................................... 29

TABLE 27. SWITCH 3 DESCRIPTIONS ............................................................................................................................................ 30

TABLE 28. SWITCH 2 DESCRIPTIONS ............................................................................................................................................ 30

TABLE 29. MSC8101 MEMORY CONTROLLER RESOURCES.......................................................................................................... 32

TABLE 30. MSC8102 MEMORY CONTROLLER RESOURCES.......................................................................................................... 33

TABLE 31. MSC8101 HARD RESET CONFIGURATION WORD .......................................................................................................34

TABLE 32. MSC8102 HARD RESET CONFIGURATION WORD .......................................................................................................35

TABLE 33. UTOPIA INTERFACE...................................................................................................................................................37

TABLE 34. I2C INTERFACE ...........................................................................................................................................................38

TABLE 35. HDI16 INTERFACE ......................................................................................................................................................38

iii PFC_DDD_v1.3.doc

TABLE 36. CT BUS .......................................................................................................................................................................39

TABLE 37. ETHERNET INTERFACE ................................................................................................................................................40

TABLE 38. MISCELLANEOUS SIGNALS.......................................................................................................................................... 40

iv PFC_DDD_v1.3.doc

1 Overview

1.1 Scope

This document provides user guide information and a detailed design description of the MSC8102 Packet Telephony Farm Card.

1.2 Reference Documents

The documents listed in the table below are referenced in this document.

Table 1. Reference Documents

Reference Document

Number

1 IEEE P1386.1 Standard Physical and Environmental

2 IEEE P1386 Standard for a Common Mezzanine

3 PICMG 2.15 CompactPCI PCI Telecom

4 H.100 H.100 Hardware Compatability

Description Revision Date

Layers for PCI Mezzanine Cards: PMC

Card Fa mi l y: CMC

Mezzanine/Card Card Specification

Specification : CT Bus

Draft 2.4 January 12,

2001

Draft 2.4a March 21,

2001

R1.0 April 11, 2001

1.0

1 PFC_DDD_v1.3.doc

2 PFC Overview

The Packet Telephony Farm Card is a PCI Telephony Mezzanine Card (PTMC) designed primarily as an MSC8102 upgrade and Media Gateway evaluation product for Media Gateway Systems. It is designed around the Star-Core MSC8102 16 bit fixed point DSP device from Motorola Semiconductor. The PFC DSP farm card utilizes five MSC8102 devices and a MSC8101 to aggregate the data to/from the DSP farm. Each MSC8102 DSP has an associated 4M x 32 (16MB) SDRAM. The aggregator has a separate 2M x32 (8MB) SDRAM.

The PFC interfaces with a baseboard platform via its PTMC site. A PTMC is a PMC module, which conforms to the PMC standard for Jn1 and Jn2, but uses Jn3 and Jn4 to support a variety of telecom interfaces. The PTMC site on the Media Gateway is configured as PT3MC, a subset of the PTMC specification, which supports UTOPIA, RMII and CT bus interfaces on Jn3/4. An optional fifth connector (Jn5) has been added to support the two MII interfaces available from the MSC8101; Jn5 is a proprietary connector, effectively supporting an enhanced PTMC, which is backward compatible with existing PTMCs.

Data movement around the board is primarily through the use of 10/100 Mb/s Ethernet (single RMII or dual MII interfaces) or UTOPIA and a Computer Telephony local bus through the PTMC connectors. Additionally an I2C management interface is facilitated through PTMC J3 connect or. Additional I/O includes HDI16, RS232 and OnCE JTAG ports for Debug.

The PFC is targeted to interface with Motorola Packet Telephony enhanced PTMC baseboards such as the PDK demonstration system, as well as interfacing with standard customer PTMC Type III baseboards.

Figure 1. MSC8102 - Packet Telephony Farm Card

2 PFC_DDD_v1.3.doc

3 PFC Feature List

 PFC Platfor m

 Digital Support for up to 672 chan nels  PTMC Type 3 form card for interfacing to standard subsystems

 MSC8101 Aggregator

 One MSC8101 DSP communications processor with:

 10/100BaseT Fast Ethernet via PTMC Interface  RMII Ethernet via PTMC Interface  UTOPIA interface via PTMC Interface  Host Interface to enable Host control of Aggregator via PTMC Interface  64-bit/32-bit PPC interface to the MSC8102 DSI port for on board data

distribution to DSP Farm

 RS232 interface on board  4MByte of Flash for System Bootstrap  8MByte of SDRAM

MSC810 2 Farm

 Five MSC8102s DSPs each with

 TDM interface (CT Bus) via PTMC interface  64-bit/32-bit DSI Slave port interfacing to the MSC8101 PPC (via FPGA) for data

distribution

 DSI-Asynchronous mode of ope ration

 DSI-Synchronous mode of operation  16MByte of SDRAM  MSC8102 DSP1 has RS232 interface on board

 FPGA

 PPC to DSI translation for synchronous DSI  Transparent mode for asynchronous DSI  Routing of MSC8102 to MSC8101 interrupts  CPORT cluster interface  MII to RMII conversion

 Debug

 Chained DSP EONCE port with option to configure the full 5 MSC8102s and

MSC8101 chain or only the MSC8101 DSP.

 SMC2 RS232 Connection to the MSC8101  UART connection to one MSC8102  Break out card allows access to Utopia interfaces via connectors

 Power Supply

 For stand al one ope rat i on 5V / 3.3V su ppl ie d e xte rn ally via bas e ca rd w it h opti on t o

supply 1.6V externally or via on board PFC 5V to 1.6V step down.

3 PFC_DDD_v1.3.doc

4 User Guide

4.1 Quick Start

1. Start the Start the Codewarrior tools and ensure that the command converter is running

2. Connect a dual supply to the 5V, 3.3V and 0V on the JP1 connector of the Base Card.

3. The parallel command converter should also be connected to P 3 on the P FC to enable JTAG

access, reference Figure 2.

3.3V

Host

Computer

Command

Converter

Figure 2. PFC Setup

4. Set the switch settings as per Table 2, Table 3 and Table 4.

5. Power up the PFC, which will now automatically bootstrap in the following modes:

• MSC8101 Boot from Flash

o Operating frequency: 275 MHz Core/ 138 MHz CPM / 69MHz system bus

• MSC8102 Boot through DSI

o Operating frequency: 250MHz core/ 83MHz system bus o 32-bit asynchronous DSI

• JTAG of 21 cores Each DSP LED will light after approximately 4 seconds (delay due to FPGA programming)

indicating a successful bootstrap.

6. The user can now use the StarCore Codewarrior tools to access the DSPs. Note that the user

should ensure the following:

o That reset on connect is NOT selected (a tools reset will restart the boot process,

preventing MSC8102 DSP JTAG access)

4 PFC_DDD_v1.3.doc

o The JTAG file “PFCjtag21.cfg” is selected. The file listing and core JTAG

numbering is detailed in Appendix C.

Table 2. MSC8101 Boot from Flash

Feature Settings Comments

SW3.1 OFF SW3.2 OFF SW3.3 ON SW3.4 ON Boot=0, Host Port disabled, Boot from external memory. SW3.8 ON RSTCONF=0, Reset Configuration Master

Feature Settings Comm ents

SW2.1 OFF CNFGS=1 [MSC8102 Boot Over DSI]. Keeps MSC8102s in reset

SW2.2 ON SW2.3 OFF

SW2.4 ON DSI64 =0, DSI is 32-bit SW2.5 ON DSISYNC=0, DSI operates in asynchronous mode SW2.6 ON SWTE=0, Software WDT disabled SW2.7 ON RSTCONF=0 [MSC8102 Boot over DSI]. Keeps MSC8102s in reset

A_MODCK1 = 1 A_MODCK2= 1 A_MODCK3= 0

Table 3. MSC8102 Boot through DSI

until RCW received MODCK2=0

MODCK1=1

until RCW received

MODCK 46 [101-110]. CLKIN=34.5MHz Core/CPM/Bus= 275/138/69 MHz

MODCK 10 [010-10]. CLKIN=41.6MHz Core/Bus= 250/83 MHz

SW3.6 SW3.7

OFF ON

BM2: MSC8102 Boot Sequence through DSI BM1

Table 4. Full chain (JTAG of 21)

Feature Settings Comments

JP1 Pos 1-2 Full Cha in SW2.8 ON Full Chain

4.2 Board Configuration Options

4.2.1 Single MSC8101 with Default Configuration

To initialize the MSC8101 with its default Reset Configuration Word, set the switch settings detailed in Table 5 and Table 8 (MSC8101 only). Note that this mode allow tools access to the MSC8101 only (the MSC8102s will remain in reset), and should be used when the flash is blank or corrupted.

Table 5. MSC8101 Default Reset Configuration Word

Feature Settings Comments

SW3.1 OFF SW3.2 OFF SW3.3 ON

A_MODCK1 = 1 A_MODCK2= 1 A_MODCK3= 0

MODCK 6 [000-110]. CLKIN=34.5MHz Core/CPM/Bus= 138/69/34.5 MHz

5 PFC_DDD_v1.3.doc

SW3.4 ON Boot=0, Host Port disabled, Boot from external memory SW3.8 OFF RSTCONF=1, Reset Configuration Slave

4.2.2 MSC8101 Boot through HDI16

To bootstrap the PFC through the MSC8101 HDI16 interface, set the switch settings detailed in Table 6 and Table 3.

Table 6. MSC8101 HDI16 Boot

Feature Settings Comments

SW3.1 OFF SW3.2 OFF SW3.3 ON SW3.4 OFF Boot=1, Host Port enabled, MSC8101 boot from HDI16 SW3.8 OFF RSTCONF=1, Reset Configuration Slave

A_MODCK1 = 1 A_MODCK2= 1 A_MODCK3= 0

4.2.3 MSC8101 Ethernet/Utopia Options

Switch SW3.5 can be used to select the required MSC8101 CPM options as detailed below

Table 7. MSC8101 Ethernet/Utopia Options

Feature Settings Comments

SW3.5 ON FCC1

UTOPIA

SW3.5 OFF FCC1

Ethernet MII1

MODCK 46 [101-110]. CLKIN=34.5MHz Core/CPM/Bus= 275/138/69 MHz

FCC2 Ethernet (MII2)

4.2.4 MSC8102 DSI Options

The MSC8102 DSI port cam be configured into 1 of 4 modes

• 32-bit wide Asynchronous Mode

• 64-bit wide Asynchronous Mode

• 32-bit wide Synchronous Mode

• 64-bit wide Synchronous Mode

The PFC is delivered with 32-bit wide asynchronous mode as standard, which is preprogrammed in Flash memory. To implement a different mode the user should contact Motorola to obtain the required firmware.

4.2.5 JTAG options

There are 2 JTAG options available as detailed in Table 8:

Table 8. JTAG Options

Description Feature Settings

MSC8101 only JP1 P os 2-3

6 PFC_DDD_v1.3.doc

SW2.8 OFF

JP1 Pos 1-2 Full Chain (21 cores)

The JTAG configuration file for 21 cores is listed in Appendix C.

4.3 Programming Flash

The PFC uses the same Flash (AM29LV320DB) as the MSC8102ADS so the option exists to use either the Metrowerks Code-warrior or PFC specific Flash Programmer (consult Motorola for additi onal details on program ming Flash).

SW2.8 ON

7 PFC_DDD_v1.3.doc

5 Hardware Description

This section describes the Packet Telephony Farm Card Hardware. The Hardware architecture has been partitioned into the following logical sections: Aggregator, DSP Processing Array, General Board Config ur at i o n, Fi r mware and P FC Ba s e Ca rd.

5.1 Board Architecture

The board architecture of the Packet Telephony Farm Card is shown in Figure 3.

CT Bus

PN2

CT Bus

PN2

PN1

PN2

PN4

PN5

PN3

CPORT GMII

Interface

Host

UTOPIA

Ethernet

(MII 1)

Ethernet

(MII 2)

Ethernet

(RMII)

MUX

FPGA

FCC1

FCC2

SMC2

MSC8101

LATCH

MUX

8MB

SDRAM

Buffer

64/32-bit

60x

LATCH

FLASH

4MB

FPGA

8-bit32-bit

32/64-bit

DSI

MSC8102

32-bit

16MB

SDRAM

16MB

SDRAM

16MB

SDRAM

16MB

SDRAM

16MB

SDRAM

Figure 3. Packet Telephony Farm Card Architecture

This can be split into 2 main blocks

1. MSC8101 Aggregator Processor

2. MSC8102 Farm

Under typical operating conditions the MSC8101 is used to terminate ATM or 10/100BaseT Ethernet packet traffic from a host card via its PTMC interface, with the subsequent data placed in the MSC8101’s internal SRAM or external SDRAM. The data is then distributed to the MSC8102 farm for processing via the MSC8102 DSI port with the FPGA performing the 60x bus to DSI translation (NOTE: the FPGA has been incorporated to allow synchronous DSI transfer – it is not required for asynchronous DSI transfers). After MSC8102 processing the data is dispatched through the MSC8102 TDM interfaces to the PTMC CT Bus.

5.2 MSC8101 Aggregator & 60x Bus Interface

The Aggregator terminates the packet protocol and transfers Media Data to and from the DSP Array through its 60x bus. The 60x interface to the MSC8102 DSI can be configured as 32 or 64-bit wide. When configured for 32-bit operation an external host can access the host port (HDI16) of the MSC8101 aggregator for bootstrap and ongoing data exchange and control. 4 MB of 8-bit wide Flash is connected to the MSC8101 60x bus for configuration, boot and execution code (for all 6 DSPs). 8 MBytes of 32-bit wide SDRAM also hangs off this bus to provide adequate storage during real time operation. It should be noted that the address bus is latched to the SDRAM and Flash memories due to the 60x compatible mode used (when running in DSI Synchronous mode). The data bus is un-buffered to the memories and FPGA but buffered for the HDI16 port. The SDRAM is not required for normal Aggregation functions and has been incorporated purely for maximum flexibility.

Table 9 details the MSC8101 Chip selects used for the 60x bus devices.

8 PFC_DDD_v1.3.doc

Table 9. MSC8101 Memory Controller Resources

Chip Select

CS0 Flash (Boot) CS2

CS3 DSI Asynchronous (Individual Chip Selects) CS4 DSI Asynchronous (Broadcast mode)

SDRAM

5.2.1 MSC8101 SDRAM Interface

The Aggregator 60x bus incorporates 64M-bit x32-bit wide x4 bank Micron MT48LC2M32B2 SDRAM surface mounted onto the board providing 8 MBytes of general-purpose system RAM. The MSC8101’s Chip Select 2 is used to select the SDRAM devices through the SDRAM controller, which is capable of interfacing to JEDEC compatible SDRAM, the settings of which are now described.

• SDRAM size is 512k x 32 x 4 Ba nks = 8MBytes, which requires 2 3 a ddress lines.

• Device has 8 column and 11 Row lines, 2 Bank Selects. The 32-bit port size means addresses

30 and 31 are not used.

For Page based Interleaving the 60x bus is arranged as follows:

A[9:19] A[20:21] A[22:29] A[30:31]

Row (x11) Bank Select Column (x8) LSB

This gives the following MSC8101 Registers settings:

• PSDMR[PBI] = 1, Page Based Interleaving

• ORx[BPD] = 01, 4 Ba nks per device

• ORx[ROWST] = 1001, Row Starts at A9

• ORx[NUMR]= 010, SDRAM has 11 Row lines

From the SDRAM perspective during an ACTIVATE command it’s address port will look like:

A9:A19 A17:A18 A19:A29 A30:A31

--- Internal Bank Select (A[20:21])

Peripheral

Row(A[9:19]) LSB

While a Read/Write will look like:

A9:A19 A17:A18 A[19:21] A[22:29] A30:A31

--- Internal Bank Select (A[20:21])

Which gives the following regist er settings:

• PSDMR[SDAM] = 010, A[9:19] muxed to A[19:29]

• PSMDR[BSMA] = 100, A[17-18] are used as Bank Selects Signals

• PSMDR[SDA10] = 001, A9 maps to A10/AP pin

The full PSDMR settings are described in table

Table 10. MSC8101 PSDMR settings

PBI = 1 Paged Based Interleaving RFEN = 1 Refresh services required

9 PFC_DDD_v1.3.doc

Don’t

care

Column

(A[22:29])

LSB

OP = 000 Normal Operation SDAM = 010 A[9:19] multiplexed to A[19:29] BSMA = 100 A17-A18 are used as Bank Selects Signals SDA10 = 001 A9 maps to A10/AP pin RFRC = 110 8 Clock Cycles Refresh Recovery PRETOACT = 011 Pre-charge to Activate 3 cycle interval ACTTORW= 011 Activate to Read/Write 3 clock cycles BL 23 = 1 Burst Length is 8 LDOTOPRE = 10 Precharge can be set 2 cycles before last data is read from SDRAM WRC = 00 Precharge is set 4 cycles after the last data is written to SDRAM EAMUX= 1 External Address Multiplexing, Fastest timing (set to 0 for MSC8102

SDRAM) BUFCMD = 0 Normal Timing for the control lines CL = 10 Cycle CA S Lat e ncy=2

These SDRAM settings are conservative and can be optimized for future configurations. The OR & BR settings are described below:

BA=0x2000_0 Base Addre ss = 0x20000000 PS=11 32-bit port size MSEL =010 SDRAM machine

SDAM = 1111 1111 1000

LSDAM = 0000 0 8MB SDRAM BPD= 01 4 Banks Per Device ROWST = 1001 R ow Star ts at A9 NUMR = 010 SDRAM has 11 Row lines PMSEL = 0 Back to Back Page Mode (Normal Operation)

PSDMR = 0xC287378A: MSC8101 SDRAM

Table 11. MSC8101 BR & OR settings

0x20001841

IBID = 1 Bank Interleaving Disabled

After Power On a JEDEC standard initialization sequence is performed to configure the SDRAM. This is carried out in Software utilizing the SDRAM controller PSDMR register:

OR = 0xFF803290

5.2.1.1 SDRAM Initialization Command Sequence

Step 1. Apply power and start clock. Maintain No Operation (NOP) condition at the inputs. Step 2. Maintain stable power, stable clock and NOP input conditions at the inputs.

10 PFC_DDD_v1.3.doc

Step 3. Issue Precharge All command (PALL) to all banks of the device. Program PSDMR[OP] bits to [101] and then perform an access to the SDRAM bank.

Step 4. Issue 8 or more CBR Refresh (REF) commands. Program PSDMR[OP] bits to [001] and then perform 8 accesses to the SDRAM bank.

Step 5. Issue Mode Register Set (MRS) command to initialise the mode register. Program PSDMR[OP] bits to [011] and then performing an access to the SDRAM bank at an address offset to 0x08Csee figure below.

BL = Burst Length 8 for 32 Bit b us. BT = 0 Sequential B ur s t s CAS Latency = 2 OP MODE = Standard Operation WB = 0 Programmed Burst Length

A10/

A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

SDRAM Address

Lines

RSVD Burst Length

0 0 0 0 1 0 0 0 1 1

BTCAS LatencyWB Op Mode

MSC8101

Address

Lines

A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31

0 0 0 0 1 0 0 0 1 10 0 0

SDRAM Only sees this part of the Bus

Figure 4. MSC8101 SDRAM Mode Reg ister Settings

5.2.1.2 SDRAM Refresh

The SDRAM requires 4096 refresh cycles per 64ms or one refresh cycle per 15.625µs. The MSC8101 can be programmed to carry out the refresh cycle periodically using the SDRAM Refresh Timer (PSRT). By setting the memory refresh timer prescaler register, MPTPR[PTP] to divide by 32, and the PSRT to 0x30 a timer period of 15.625µs is realized for a 100MHz system clock . For a 69MHz System clock PSRT = 0x17.

odxTimerPeriFPSRT

1625.15

usx

−=

PSRT

MPTC

MHz

32 200

xPSRT

MPTC

100

MHz

300

xPSRT

odxTimerPeriFPSRT

1625.15

−=

usx

Figure 5. Refresh Calculations

5.2.2 MSC8101 FLASH Interface

The Aggregator incorporates an AM29LV320DB-120E 4Mx8-bit FLASH for Stand-alone reset configuration and boot. To enable bootstrapping from reset the Flash is mapped to GPCM CS0 and utilizes the following signals

Table 12. MSC8102 DSI Ad dresses

MSC8102 GPCM Signal

A_CS_FLASH CS0

A_PSDRAS POE

A_PSDDQMO WE

A_BADDR[27:30] A[3:0]

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NXP Semiconductors Digital DNA MSC8102 User Manual And Hardware Detailed Design Description

Specifications and Main Features

Frequently Asked Questions

User Manual