NXP Semiconductors ColdFire MCF52235, ColdFire MCF52230, ColdFire MCF52231, ColdFire MCF52233, ColdFire MCF52234 Reference Manual
MCF52235 ColdFire® Integrated
Microcontroller Reference Manual
Devices Supported:
MCF52230
MCF52231
MCF52233
MCF52234
MCF52235
Document Number:
MCF52235RM
Rev. 0
04/2006
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© Freescale Semiconductor, Inc. 2006. All rights reserved.
Document Number: MCF52235RM
Rev. 0
04/2006
Table of Contents
Chapter 1
Overview
1.1 MCF52235 Family Configurations ...................................................................................................2
1.2 Block Diagram ..................................................................................................................................2
1.3 Part Numbers and Packaging ............................................................................................................4
1.4 Features .............................................................................................................................................4
Chapter 2
Signal Descriptions
2.1 Introduction .......................................................................................................................................1
2.2 Overview ...........................................................................................................................................1
2.3 Reset Signals .....................................................................................................................................8
2.4 PLL and Clock Signals ......................................................................................................................8
2.5 Mode Selection ..................................................................................................................................8
2.6 External Interrupt Signals ..................................................................................................................8
2.7 Queued Serial Peripheral Interface (QSPI) .......................................................................................9
2.8 Fast Ethernet Controller PHY Signals ............................................................................................10
2.9 I2C I/O Signals ................................................................................................................................10
2.10 UART Module Signals ....................................................................................................................11
2.11 DMA Timer Signals ........................................................................................................................11
2.12 ADC Signals ....................................................................................................................................11
2.13 General Purpose Timer Signals .......................................................................................................12
2.14 Pulse Width Modulator Signals .......................................................................................................12
2.15 Debug Support Signals ....................................................................................................................12
2.16 EzPort Signal Descriptions ..............................................................................................................13
2.17 Power and Ground Pins ...................................................................................................................14
Chapter 3
ColdFire Core
3.1 Processor Pipelines ............................................................................................................................1
3.2 Memory Map/Register Description ...................................................................................................2
3.3 Instruction Set Architecture (ISA_A+) .............................................................................................8
3.4 Exception Processing Overview ........................................................................................................8
3.5 Exception Stack Frame Definition ..................................................................................................10
3.6 Processor Exceptions .......................................................................................................................11
3.7 Instruction Execution Timing ..........................................................................................................18
3.8 Standard One Operand Instruction Execution Times ......................................................................20
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Preliminary
3.9 Standard Two Operand Instruction Execution Times ......................................................................21
3.10 Miscellaneous Instruction Execution Times ...................................................................................22
3.11 EMAC Instruction Execution Times ...............................................................................................23
3.12 Branch Instruction Execution Times ...............................................................................................24
Chapter 4
Enhanced Multiply-Accumulate Unit (EMAC)
4.1 Multiply-Accumulate Unit ................................................................................................................1
4.2 Introduction to the MAC ...................................................................................................................2
4.3 General Operation .............................................................................................................................2
4.4 Memory Map/Register Definition .....................................................................................................5
4.5 EMAC Instruction Set Summary ....................................................................................................11
Chapter 5
Cryptographic Acceleration Unit
5.1 CAU Registers ...................................................................................................................................1
5.2 CAU Operation .................................................................................................................................2
5.3 CAU Commands ...............................................................................................................................2
5.4 CAU Equate Values ...........................................................................................................................7
Chapter 6
Random Number Generator Accelerator (RNGA)
6.1 Overview ...........................................................................................................................................1
6.2 Features .............................................................................................................................................2
6.3 Modes of Operation ...........................................................................................................................2
6.4 Memory Map/Register Definition .....................................................................................................3
6.5 Functional Description ....................................................................................................................11
6.6 Initialization/Application Information ............................................................................................12
Chapter 7
Clock Module
7.1 Introduction .......................................................................................................................................1
7.2 Features .............................................................................................................................................1
7.3 Modes of Operation ...........................................................................................................................1
7.4 Low-power Mode Operation .............................................................................................................2
7.5 Block Diagram ..................................................................................................................................2
7.6 Signal Descriptions ...........................................................................................................................4
7.7 Memory Map and Registers ..............................................................................................................5
7.8 Functional Description ....................................................................................................................11
Chapter 8
Real Time Clock
8.1 Introduction .......................................................................................................................................1
8.2 Memory Map/Register Definition .....................................................................................................2
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8.3 Functional Description ....................................................................................................................12
8.4 Initialization/Application Information ............................................................................................13
Chapter 9
Power Management
9.1 Introduction .......................................................................................................................................1
9.2 Memory Map/Register Definition .....................................................................................................1
9.3 IPS Bus Timeout Monitor ...............................................................................................................10
9.4 Functional Description ....................................................................................................................11
Chapter 10
Reset Controller Module
10.1 Introduction .......................................................................................................................................1
10.2 Features .............................................................................................................................................1
10.3 Block Diagram ..................................................................................................................................1
10.4 Signals ...............................................................................................................................................2
10.5 Memory Map and Registers ..............................................................................................................2
10.6 Functional Description ......................................................................................................................5
Chapter 11
Static RAM (SRAM)
11.1 Introduction .......................................................................................................................................1
11.2 Memory Map/Register Description ...................................................................................................1
11.3 Initialization/Application Information ..............................................................................................3
Chapter 12
Chip Configuration Module (CCM)
12.1 Introduction .......................................................................................................................................1
12.2 External Signal Descriptions .............................................................................................................2
12.3 Memory Map/Register Definition .....................................................................................................2
12.4 Functional Description ......................................................................................................................5
12.5 Reset ..................................................................................................................................................6
Chapter 13
System Control Module (SCM)
13.1 Introduction .......................................................................................................................................1
13.2 Overview ...........................................................................................................................................1
13.3 Features .............................................................................................................................................1
13.4 Memory Map and Register Definition ..............................................................................................2
13.5 Register Descriptions ........................................................................................................................3
13.6 Internal Bus Arbitration ..................................................................................................................11
13.7 System Access Control Unit (SACU) .............................................................................................14
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Preliminary
Chapter 14
General Purpose I/O Module
14.1 Introduction .......................................................................................................................................1
14.2 Overview ...........................................................................................................................................2
14.3 Features .............................................................................................................................................3
14.4 Signal Descriptions ...........................................................................................................................3
14.5 Memory Map/Register Definition .....................................................................................................4
14.6 Register Descriptions ........................................................................................................................6
14.7 Ports Interrupts ................................................................................................................................15
Chapter 15
Interrupt Controller Module
15.1 68K/ColdFire Interrupt Architecture Overview ................................................................................1
15.2 Memory Map .....................................................................................................................................4
15.3 Register Descriptions ........................................................................................................................5
15.4 Low-Power Wakeup Operation .......................................................................................................18
Chapter 16
Edge Port Module (EPORT)
16.1 Introduction .......................................................................................................................................1
16.2 Low-Power Mode Operation .............................................................................................................2
16.3 Interrupt/GPIO Pin Descriptions .......................................................................................................2
16.4 Memory Map/Register Definition .....................................................................................................3
Chapter 17
ColdFire Flash Module (CFM)
17.1 Introduction .......................................................................................................................................1
17.2 External Signal Description ..............................................................................................................3
17.3 Memory Map and Register Definition ..............................................................................................3
17.4 Functional Description ....................................................................................................................14
Chapter 18
Fast Ethernet Controller (FEC)
18.1 Overview ...........................................................................................................................................1
18.2 Modes of Operation ...........................................................................................................................1
18.3 FEC Top-Level Functional Diagram .................................................................................................3
18.4 Functional Description ......................................................................................................................4
18.5 Programming Model .......................................................................................................................17
18.6 Buffer Descriptors ...........................................................................................................................42
Chapter 19
Ethernet Physical Transceiver (EPHY) Block Description
19.1 Introduction .......................................................................................................................................1
19.2 External Signal Descriptions .............................................................................................................3
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Preliminary
19.3 Memory Map and Register Descriptions ..........................................................................................5
19.4 Functional Description ....................................................................................................................21
Chapter 20
DMA Controller Module
20.1 Introduction .......................................................................................................................................1
20.2 M-bus Priority Level (MPL) .............................................................................................................4
20.3 DMA Transfer Overview ..................................................................................................................4
20.4 Memory Map/Register Definition .....................................................................................................5
20.5 Functional Description ....................................................................................................................16
Chapter 21
EzPort
21.1 Features .............................................................................................................................................1
21.2 Modes of Operation ...........................................................................................................................1
21.3 External Signal Description ..............................................................................................................2
21.4 Command Definition .........................................................................................................................3
21.5 Functional Description ......................................................................................................................7
21.6 Initialization/Application Information ..............................................................................................8
Chapter 22
Programmable Interrupt Timer Modules (PIT0–PIT1)
22.1 Introduction .......................................................................................................................................1
22.2 Memory Map/Register Definition .....................................................................................................2
22.3 Functional Description ......................................................................................................................5
Chapter 23
General Purpose Timer Module (GPT)
23.1 Introduction .......................................................................................................................................1
23.2 Features .............................................................................................................................................1
23.3 Block Diagram ..................................................................................................................................2
23.4 Low-Power Mode Operation .............................................................................................................3
23.5 Signal Description .............................................................................................................................3
23.6 Memory Map and Registers ..............................................................................................................4
23.7 Functional Description ....................................................................................................................17
23.8 Reset ................................................................................................................................................21
23.9 Interrupts .........................................................................................................................................21
Chapter 24
DMA Timers (DTIM0–DTIM3)
24.1 Introduction .......................................................................................................................................1
24.2 Memory Map/Register Definition .....................................................................................................2
24.3 Functional Description ......................................................................................................................8
24.4 Initialization/Application Information ..............................................................................................8
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Freescale Semiconductor vii
Preliminary
Chapter 25
Queued Serial Peripheral Interface (QSPI)
25.1 Introduction .......................................................................................................................................1
25.2 External Signal Description ..............................................................................................................2
25.3 Memory Map/Register Definition .....................................................................................................3
25.4 Functional Description ....................................................................................................................10
25.5 Initialization/Application Information ............................................................................................16
Chapter 26
UART Modules
26.1 Introduction .......................................................................................................................................1
26.2 External Signal Description ..............................................................................................................3
26.3 Memory Map/Register Definition .....................................................................................................4
26.4 Functional Description ....................................................................................................................18
Chapter 27
2
C Interface
I
27.1 Introduction .......................................................................................................................................1
27.2 Overview ...........................................................................................................................................1
27.3 Features .............................................................................................................................................1
27.4 I2C System Configuration .................................................................................................................3
27.5 Memory Map/Register Definition .....................................................................................................7
27.6 I2C Programming Examples ............................................................................................................12
Chapter 28
Analog-to-Digital Converter (ADC)
28.1 Introduction .......................................................................................................................................1
28.2 Features .............................................................................................................................................1
28.3 Block Diagram ..................................................................................................................................1
28.4 Functional Description ......................................................................................................................2
28.5 Register Definitions .........................................................................................................................18
Chapter 29
Pulse Width Modulation (PWM) Module
29.1 Introduction .......................................................................................................................................1
29.2 Memory Map/Register Definition .....................................................................................................2
29.3 Functional Description ....................................................................................................................12
Chapter 30
FlexCAN
30.1 Introduction .......................................................................................................................................1
30.2 External Signal Description ..............................................................................................................5
30.3 Memory Map/Register Definition .....................................................................................................5
30.4 Functional Overview .......................................................................................................................20
30.5 FlexCAN Initialization Sequence ....................................................................................................28
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viii Freescale Semiconductor
Preliminary
Chapter 31
Debug Module
31.1 Introduction .......................................................................................................................................1
31.2 External Signal Description ..............................................................................................................2
31.3 Real-Time Trace Support ..................................................................................................................3
31.4 Memory Map/Register Definition .....................................................................................................6
31.5 Background Debug Mode (BDM) ...................................................................................................17
31.6 Real-Time Debug Support ...............................................................................................................37
31.7 Processor Status, DDATA Definition ..............................................................................................40
31.8 Freescale-Recommended BDM Pinout ...........................................................................................44
Chapter 32
IEEE 1149.1 Test Access Port (JTAG)
32.1 Introduction .......................................................................................................................................1
32.2 External Signal Description ..............................................................................................................2
32.3 Memory Map/Register Definition .....................................................................................................4
32.4 Functional Description ......................................................................................................................6
32.5 Initialization/Application Information ............................................................................................10
Appendix A
Register Memory Map Quick Reference
MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 0
Freescale Semiconductor ix
Preliminary
MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 0
x Freescale Semiconductor
Preliminary
Chapter 1 Overview
This chapter provides an overview of the major features and functional components of the MCF52235
family of microcontrollers. The MCF52235 family is a highly integrated implementation of the ColdFire®
family of reduced instruction set computing (RISC) microcontrollers that also includes the MC52230,
MCF52231, MC52233 and MC52234 . The differences between these parts are summarized in Tab le 1-1.
This document is written from the perspective of the MC52235 .The MC52235 represents a family of
highly-integrated 32-bit microcontrollers based on the V2 ColdFire microarchitecture. Featuring up to 32
Kbytes of internal SRAM and 256 Kbytes of Flash memory, four 32-bit timers with DMA request
capability, a 4-channel DMA controller, fast Ethernet, a CAN module, an I2C™ module, 3 UARTs and a
queued SPI, the MC52235 family has been designed for general-purpose industrial control applications.
n enhanced multiply-accumulate unit (EMAC) and divider providing 56Drystone 2.1 MIPS at a frequency
up to 60MHz from internal Flash. On-chip modules include the following:
• V2 ColdFire core with enhanced multiply-accumulate unit (EMAC)
• Cryptographic Acceleration Unit (CAU)
• 32 Kbytes of internal SRAM
• 256 Kbytes of on-chip Flash memory
• Fast Ethernet Controller (FEC) with on-chip transceiver (ePHY)
• Three universal asynchronous receiver/transmitters (UARTs)
• Controller area network 2.0B (FlexCAN) module
• Inter-integrated circuit (I2C) bus controller
• 12-bit analog-to-digital converter (ADC)
• Queued serial peripheral interface (QSPI) module
• Four-channel, 32-bit direct memory access (DMA) controller
• Four-channel, 32-bit input capture/output compare timers with optional DMA support
• Two 16-bit periodic interrupt timers (PITs)
• Programmable software watchdog timer
• Two interrupt controllers, each capable of handling up to 63 interrupt sources (126 total)
These devices are ideal for cost-sensitive applications requiring significant control processing for
connectivity, data buffering, and user interface, as well as signal processing in a variety of key markets
such as security, imaging, networking, gaming, and medical. This leading package of integration and high
performance allows fast time to market through easy code reuse and extensive third party tool support.
To locate any published errata or updates for this document, refer to the ColdFire products website at
http://www.freescale.com/coldfire.
MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 0
Freescale Semiconductor 1-1
Preliminary
Overview
1.1 MCF52235 Family Configurations
Table 1. MCF52235 Family Configurations
Module 52230 52231 52233 52234 52235
ColdFire Version 2 Core with EMAC (Enhanced
Multiply-Accumulate Unit)
System Clock 60 MHz
Performance (Dhrystone 2.1 MIPS) 56
Flash / Static RAM (SRAM) 128/32 Kbytes 128/32 Kbytes 256/32 Kbytes
Interrupt Controllers (INTC0/INTC1) x x x x x
Fast Analog-to-Digital Converter (ADC) x x x x x
Random Number Generator and Crypto
Acceleration Unit (CAU)
FlexCAN 2.0B Module - x - x x
Fast Ethernet Controller (FEC) with on-chip
interface (EPHY)
Four-channel Direct-Memory Access (DMA) x x x x x
Software Watchdog Timer (WDT) x x x x x
Programmable Interrupt Timer 2 2 2 2 2
Four-Channel General Purpose Timer x x x x x
32-bit DMA Timers 4 4 4 4 4
QSPI x x x x x
UART(s) 3 3 3 3 3
2
Cxxxxx
I
Eight/Four-channel 8/16-bit PWM Timer x x x x x
xxxxx
----x
xxxxx
General Purpose I/O Module (GPIO) x x x x x
Chip Configuration and Reset Controller Module x x x x x
Background Debug Mode (BDM) x x x x x
JTAG - IEEE 1149.1 Test Access Port
Package 80, 112-pin
1
The full debug/trace interface is available only on the 112- and 121-pin packages. A reduced debug
1
xxxxx
LQFP
80, 112-pin
LQFP
80, 112-pin
LQFP
121 MAPBGA
80, 112-pin
LQFP
121 MAPBGA
112-pin LQFP
121 MAPBGA
interface is bonded on the 80-pin package.
1.2 Block Diagram
The superset device in the MCF52235 family comes in a 112-leaded quad flat package (LQFP) and a 121
pin MAPBGA. Figure 1-1 shows a top-level block diagram of the MCF52235 .
MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 0
1-2 Freescale Semiconductor
Preliminary
Overview
EPHY_TX
EPHY_RX
JTAG_EN
EPHY
Fast
Ethernet
Controller
(FEC)
4 CH DMA
To/From PADI
MUX
JTAG
TAP
EzPD EzPCK
EzPQ
EzPort
EzPCS
Arbiter
UART
UART
0
1
DTIM0DTIM1DTIM2DTIM
V2 ColdFire CPU
OEP
IFP
Interrupt
Controller 1
UART
2
CAU
I2C
3
EMAC
Interrupt
Controller 2
QSPI
RTC
PADI – Pin Muxing
PMM
ICOCn
QSPI_DIN,
QSPI_DOUT
QSPI_SCK,
QSPI_PCSn
I2C_SDA
I2C_SCL
UnTXD
UnRXD
UnRTS
UnCTS
DTINn/DTOUTn
CANRX
CANTX
PWMn
ADCAN[7:0]
V
RHVRL
Edge
Port 1
Edge
Port 2
EXTAL XTAL CLKOUT
To/From Interrupt Controller
32 Kbytes
SRAM
(4Kx16)x4
256 Kbytes
Flash
(32Kx16)x4
PLL
CLKGEN
RNGA
Figure 1-1. MCF52235 Block Diagram
PORTS
(GPIO)
FlexCAN
PIT0
PIT1
CIM
RSTIN
RSTOUT
PWM
GPT
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Freescale Semiconductor 1-3
Preliminary
Overview
1.3 Part Numbers and Packaging
Table 1-2. Part Number Summary
Part Number Flash / SRAM Key Features Package Speed
MCF52230 128 Kbytes / 32 Kbytes 3 UARTs, I
MCF52231 128 Kbytes / 32 Kbytes 3 UARTs, I
MCF52233 256 Kbytes / 32 Kbytes 3 UARTs, I
MDCF52234 256 Kbytes / 32 Kbytes 3 UARTs, I
MCF52235 256 Kbytes / 32 Kbytes 3 UARTs, I
EPHY, DMA, 16-/32-bit/PWM Timers, CAN
Table 1-2 summarizes the features of the MCF52235 product family. Several speed/package options are
available to match cost- or performance-sensitive applications.
2
C, QSPI, A/D, FEC EPHY, DMA,
16-/32-bit/PWM Timers
2
C, QSPI, A/D, FEC EPHY, DMA,
16-/32-bit/PWM Timers, CAN
2
C, QSPI, A/D, FEC EPHY, DMA,
16-/32-bit/PWM Timers
2
C, QSPI, A/D, FEC, EPHY, DMA,
16-/32-bit/PWM Timers, CAN
2
C, QSPI, A/D, Crypto, FEC,
80-pin TQFP
112-pin LQFP
80-pin TQFP
112-pin LQFP
80-pin TQFP
112-pin LQFP
80-pin TQFP 112-pin LQFP 121 MAPBGA
112-pin LQFP 121 MAPBGA
60 MHz
60 MHz
60 MHz
60 MHz
60 MHz
1.4 Features
The MCF52235 family includes the following features:
• Version 2 ColdFire variable-length RISC processor core
— Static operation
— 32-bit address and data paths on-chip
— Up to 60 MHz processor core frequency
— Sixteen general-purpose, 32-bit data and address registers
— Implements ColdFire ISA_A with extensions to support the user stack pointer register and four
new instructions for improved bit processing (ISA_A+)
— Enhanced Multiply-Accumulate (EMAC) unit with 32-bit accumulator to support
16 × 16 → 32 or 32 × 32 → 32 operations
— Cryptography Acceleration Unit (CAU)
– Tightly-coupled coprocessor to accelerate software-based encryption and message digest
functions
– FIPS-140 compliant random number generator
— Support for DES, 3DES, AES, MD5, and SHA-1 algorithms
— Illegal instruction decode that allows for 68K emulation support
• System debug support
— Real time trace for determining dynamic execution path
— Background debug mode (BDM) for in-circuit debugging (DEBUG_B+)
— Real time debug support, with six hardware breakpoints (4 PC, 1 address and 1 data) that can
be configured into a 1- or 2-level trigger
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Preliminary
• On-chip memories
— 32-Kbyte dual-ported SRAM on CPU internal bus, supporting core and DMA access with
standby power supply support
— 256 Kbytes of interleaved Flash memory supporting 2-1-1-1 accesses
• Power management
— Fully static operation with processor sleep and whole chip stop modes
— Very rapid response to interrupts from the low-power sleep mode (wake-up feature)
— Clock enable/disable for each peripheral when not used
• Fast Ethernet Controller (FEC)
— 10/100 BaseT/TX capability, half duplex or full duplex
— On-chip transmit and receive FIFOs
— Built-in dedicated DMA controller
— Memory-based flexible descriptor rings
• On-chip Ethernet Transceiver (EPHY)
— Digital adaptive equalization
— Supports auto-negotiation
Overview
— Baseline wander correction
— Full-/Half-duplex support in all modes
— Loopback modes
— Supports MDIO preamble suppression
— Jumbo packet
• FlexCAN 2.0B module
— Based on and includes all existing features of the Freescale TouCAN module
— Full implementation of the CAN protocol specification version 2.0B
– Standard Data and Remote Frames (up to 109 bits long)
– Extended Data and Remote Frames (up to 127 bits long)
– 0–8 bytes data length
– Programmable bit rate up to 1 Mbit/sec
— Flexible Message Buffers (MBs), totalling up to 16 message buffers of 0–8 byte data length
each, configurable as Rx or Tx, all supporting standard and extended messages
— Unused Message Buffer space can be used as general purpose RAM space
— Listen only mode capability
— Content-related addressing
— No read/write semaphores required
— Three programmable mask registers: global for MBs 0-13, special for MB14, and special for
MB15
— Programmable transmit-first scheme: lowest ID or lowest buffer number
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Preliminary
Overview
— “Time stamp” based on 16-bit free-running timer
— Global network time, synchronized by a specific message
— Maskable interrupts
• Three universal asynchronous/synchronous receiver transmitters (UARTs)
— 16-bit divider for clock generation
— Interrupt control logic with maskable interrupts
— DMA support
— Data formats can be 5, 6, 7 or 8 bits with even, odd or no parity
— Up to 2 stop bits in 1/16 increments
— Error-detection capabilities
— Modem support includes request-to-send (RTS) and clear-to-send (CTS) lines for two UARTs
— Transmit and receive FIFO buffers
•I2C module
— Interchip bus interface for EEPROMs, LCD controllers, A/D converters, and keypads
— Fully compatible with industry-standard I2C bus
— Master and slave modes support multiple masters
— Automatic interrupt generation with programmable level
• Queued serial peripheral interface (QSPI)
— Full-duplex, three-wire synchronous transfers
— Up to four chip selects available
— Master mode operation only
— Programmable bit rates up to half the CPU clock frequency
— Up to 16 pre-programmed transfers
• Fast analog-to-digital converter (ADC)
— Eight analog input channels
— 12-bit resolution
— Minimum 1.125 µs conversion time
— Simultaneous sampling of two channels for motor control applications
— Single-scan or continuous operation
— Optional interrupts on conversion complete, zero crossing (sign change), or under/over
low/high limit
— Unused analog channels can be used as digital I/O
• Four 32-bit DMA timers
— 16.7-ns resolution at 60 MHz
— Programmable sources for clock input, including an external clock option
— Programmable prescaler
— Input capture capability with programmable trigger edge on input pin
MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 0
1-6 Freescale Semiconductor
Preliminary
— Output compare with programmable mode for the output pin
— Free run and restart modes
— Maskable interrupts on input capture or output compare
— DMA trigger capability on input capture or output compare
• Four-channel general purpose timer
— 16-bit architecture
— Programmable prescaler
— Output pulse widths variable from microseconds to seconds
— Single 16-bit input pulse accumulator
— Toggle-on-overflow feature for pulse-width modulator (PWM) generation
— One dual-mode pulse accumulation channel
• Pulse-width modulation timer
— Operates as eight channels with 8-bit resolution or four channels with 16-bit resolution
— Programmable period and duty cycle
— Programmable enable/disable for each channel
— Software selectable polarity for each channel
Overview
— Period and duty cycle are double buffered. Change takes effect when the end of the current
period is reached (PWM counter reaches zero) or when the channel is disabled.
— Programmable center or left aligned outputs on individual channels
— Four clock sources (A, B, SA, and SB) provide for a wide range of frequencies
— Emergency shutdown
• Real-Time Clock (RTC)
— Maintains system time-of-day clock
— Provides stopwatch and alarm interrupt functions
MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 0
Freescale Semiconductor 1-7
Preliminary
Overview
• Two periodic interrupt timers (PITs)
— 16-bit counter
— Selectable as free running or count down
• Software watchdog timer
— 32-bit counter
— Low power mode support
• Clock Generation Features
— 25 MHz crystal input
— On-chip PLL can generate core frequencies up to maximum 60MHz operating frequency
— Provides clock for integrated EPHY
• Dual Interrupt Controllers (INTC0/INTC1)
— Support for multiple interrupt sources organized as follows:
– Fully-programmable interrupt sources for each peripheral
– 7 fixed-level interrupt sources
– Seven external interrupt signals
— Unique vector number for each interrupt source
— Ability to mask any individual interrupt source or all interrupt sources (global mask-all)
— Support for hardware and software interrupt acknowledge (IACK) cycles
— Combinatorial path to provide wake-up from low power modes
• DMA controller
— Four fully programmable channels
— Dual-address transfer support with 8-, 16-, and 32-bit data capability, along with support for
16-byte (4 x 32-bit) burst transfers
— Source/destination address pointers that can increment or remain constant
— 24-bit byte transfer counter per channel
— Auto-alignment transfers supported for efficient block movement
— Bursting and cycle steal support
— Software-programmable DMA requesters for the UARTs (3) and 32-bit timers (4)
•Reset
— Separate reset in and reset out signals
— Seven sources of reset:
– Power-on reset (POR)
– External
– Software
– Watchdog
– Loss of clock
– Loss of lock
MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 0
1-8 Freescale Semiconductor
Preliminary
Overview
– Low-voltage detection (LVD)
— Status flag indication of source of last reset
• Chip integration module (CIM)
— System configuration during reset
— Selects one of three clock modes
— Configures output pad drive strength
— Unique part identification number and part revision number
• General purpose I/O interface
— Up to 56 bits of general purpose I/O
— Bit manipulation supported via set/clear functions
— Programmable drive strengths
— Unused peripheral pins may be used as extra GPIO
• JTAG support for system level board testing
1.4.1 V2 Core Overview
The version 2 ColdFire processor core is comprised of two separate pipelines that are decoupled by an
instruction buffer. The two-stage instruction fetch pipeline (IFP) is responsible for instruction-address
generation and instruction fetch. The instruction buffer is a first-in-first-out (FIFO) buffer that holds
prefetched instructions awaiting execution in the operand execution pipeline (OEP). The OEP includes
two pipeline stages. The first stage decodes instructions and selects operands (DSOC); the second stage
(AGEX) performs instruction execution and calculates operand effective addresses, if needed.
The V2 core implements the ColdFire instruction set architecture revision A+ with added support for a
separate user stack pointer register and four new instructions to assist in bit processing. Additionally, the
MCF52235 core includes the enhanced multiply-accumulate (EMAC) unit for improved signal
processing capabilities. The MAC implements a three-stage arithmetic pipeline, optimized for 16 x 16 bit
operations, with support for one 32-bit accumulator. Supported operands include 16- and 32-bit signed and
unsigned integers, signed fractional operands, and a complete set of instructions to process these data
types. The EMAC provides support for execution of DSP operations within the context of a single
processor at a minimal hardware cost.
1.4.2 Integrated Debug Module
The ColdFire processor core debug interface is provided to support system debugging in conjunction with
low-cost debug and emulator development tools. Through a standard debug interface, users can access
debug information and real-time tracing capability is provided on 112-and 121-lead packages. This allows
the processor and system to be debugged at full speed without the need for costly in-circuit emulators.
The on-chip breakpoint resources include a total of nine programmable 32-bit registers: an address and an
address mask register, a data and a data mask register, four PC registers, and one PC mask register. These
registers can be accessed through the dedicated debug serial communication channel or from the
processor’s supervisor mode programming model. The breakpoint registers can be configured to generate
triggers by combining the address, data, and PC conditions in a variety of single- or dual-level definitions.
MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 0
Freescale Semiconductor 1-9
Preliminary
Overview
The trigger event can be programmed to generate a processor halt or initiate a debug interrupt exception.
The MCF52235 implements revision B+ of the coldfire Debug Architecture.
The MCF52235 ’s interrupt servicing options during emulator mode allow real-time critical interrupt
service routines to be serviced while processing a debug interrupt event, thereby ensuring that the system
continues to operate even during debugging.
To support program trace, the V2 debug module provides processor status (PST[3:0]) and debug data
(DDATA[3:0]) ports. These buses and the PSTCLK output provide execution status, captured operand
data, and branch target addresses defining processor activity at the CPU’s clock rate. The MCF52235
includes a new debug signal, ALLPST. This signal is the logical ‘AND’ of the processor status (PST[3:0])
signals and is useful for detecting when the processor is in a halted state (PST[3:0] = 1111).
The full debug/trace interface is available only on the 112 and 121-pin packages. However, every product
features the dedicated debug serial communication channel (DSI, DSO, DSCLK) and the ALLPST signal.
1.4.3 JTAG
The MCF52235 supports circuit board test strategies based on the Test Technology Committee of IEEE
and the Joint Test Action Group (JTAG). The test logic includes a test access port (TAP) consisting of a
16-state controller, an instruction register, and three test registers (a 1-bit bypass register, a -bit
boundary-scan register, and a 32-bit ID register). The boundary scan register links the device’s pins into
one shift register. Test logic, implemented using static logic design, is independent of the device system
logic.
The MCF52235 implementation can do the following:
• Perform boundary-scan operations to test circuit board electrical continuity
• Sample MCF52235 system pins during operation and transparently shift out the result in the
boundary scan register
• Bypass the MCF52235 for a given circuit board test by effectively reducing the boundary-scan
register to a single bit
• Disable the output drive to pins during circuit-board testing
• Drive output pins to stable levels
1.4.4 On-Chip Memories
1.4.4.1 SRAM
The dual-ported SRAM module provides a general-purpose 32-Kbyte memory block that the ColdFire
core can access in a single cycle. The location of the memory block can be set to any 32-Kbyte boundary
within the 4-Gbyte address space. This memory is ideal for storing critical code or data structures and for
use as the system stack. Because the SRAM module is physically connected to the processor's high-speed
local bus, it can quickly service core-initiated accesses or memory-referencing commands from the debug
module.
MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 0
1-10 Freescale Semiconductor
Preliminary
Overview
The SRAM module is also accessible by the DMA. The dual-ported nature of the SRAM makes it ideal
for implementing applications with double-buffer schemes, where the processor and a DMA device
operate in alternate regions of the SRAM to maximize system performance.
1.4.4.2 Flash
The ColdFire Flash module (CFM) is a non-volatile memory (NVM) module that connects to the
processor’s high-speed local bus. The CFM is constructed with four banks of 32K x 16-bit Flash arrays to
generate 256 Kbytes of 32-bit Flash memory. These arrays serve as electrically erasable and
programmable, non-volatile program and data memory. The Flash memory is ideal for program and data
storage for single-chip applications, allowing for field reprogramming without requiring an external high
voltage source. The CFM interfaces to the ColdFire core through an optimized read-only memory
controller which supports interleaved accesses from the 2-cycle Flash arrays. A backdoor mapping of the
Flash memory is used for all program, erase, and verify operations, as well as providing a read datapath
for the DMA. Flash memory may also be programmed via the EzPort, which is a serial Flash programming
interface that allows the Flash to be read, erased and programmed by an external controller in a format
compatible with most SPI bus Flash memory chips. This allows easy device programming via Automated
Test Equipment or bulk programming tools.
1.4.5 Cryptography Acceleration Unit
The MCF52235 device incorporates two hardware accelerators for cryptographic functions. First, the
CAU is a coprocessor tightly-coupled to the V2 ColdFire core that implements a set of specialized
operations to increase the throughput of software-based encryption and message digest functions,
specifically the DES, 3DES, AES, MD5 and SHA-1 algorithms. Second, a random number generator
provides FIPS-140 compliant 32-bit values to security processing routines. Both modules supply critical
acceleration to software-based cryptographic algorithms at a minimal hardware cost.
1.4.6 Power Management
The MCF52235 incorporates several low power modes of operation which are entered under program
control and exited by several external trigger events. An integrated power-on reset (POR) circuit monitors
the input supply and forces an MCU reset as the supply voltage rises. The low voltage detector (LVD)
monitors the supply voltage and is configurable to force a reset or interrupt condition if it falls below the
LVD trip point.
1.4.7 FlexCAN
The FlexCAN module is a communication controller implementing version 2.0 of the CAN protocol parts
A and B. The CAN protocol can be used as an industrial control serial data bus, meeting the specific
requirements of reliable operation in a harsh EMI environment with high bandwidth. This instantiation of
FlexCAN has 16 message buffers.
MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 0
Freescale Semiconductor 1-11
Preliminary
Overview
1.4.8 UARTs
The MCF52235 has three full-duplex UARTs that function independently. The three UARTs can be
clocked by the system bus clock, eliminating the need for an external clock source. On smaller packages,
the third UART is multiplexed with other digital I/O functions.
1.4.9 I2C Bus
The I2C bus is a two-wire, bidirectional serial bus that provides a simple, efficient method of data exchange
and minimizes the interconnection between devices. This bus is suitable for applications requiring
occasional communications over a short distance between many devices on a circuit board.
1.4.10 QSPI
The queued serial peripheral interface (QSPI) provides a synchronous serial peripheral interface with
queued transfer capability. It allows up to 16 transfers to be queued at once, minimizing the need for CPU
intervention between transfers.
1.4.11 Fast ADC
The Fast ADC consists of an eight-channel input select multiplexer and two independent sample and hold
(S/H) circuits feeding separate 12-bit ADCs. The two separate converters store their results in accessible
buffers for further processing.
The ADC can be configured to perform a single scan and halt, perform a scan whenever triggered, or
perform a programmed scan sequence repeatedly until manually stopped.
The ADC can be configured for either sequential or simultaneous conversion. When configured for
sequential conversions, up to eight channels can be sampled and stored in any order specified by the
channel list register. Both ADCs may be required during a scan, depending on the inputs to be sampled.
During a simultaneous conversion, both S/H circuits are used to capture two different channels at the same
time. This configuration requires that a single channel may not be sampled by both S/H circuits
simultaneously.
Optional interrupts can be generated at the end of the scan sequence if a channel is out of range (measures
below the low threshold limit or above the high threshold limit set in the limit registers) or at several
different zero crossing conditions.
1.4.12 DMA Timers (DTIM0–DTIM3)
There are four independent, DMA transfer capable 32-bit timers (DTIM0, DTIM1, DTIM2, and DTIM3)
on the each device. Each module incorporates a 32-bit timer with a separate register set for configuration
and control. The timers can be configured to operate from the system clock or from an external clock
source using one of the DTINx signals. If the system clock is selected, it can be divided by 16 or 1. The
input clock is further divided by a user-programmable 8-bit prescaler which clocks the actual timer counter
register (TCRn). Each of these timers can be configured for input capture or reference (output) compare
mode. Timer events may optionally cause interrupt requests or DMA transfers.
MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 0
1-12 Freescale Semiconductor
Preliminary
Overview
1.4.13 General Purpose Timer (GPT)
The general purpose timer (GPT) is a 4-channel timer module consisting of a 16-bit programmable counter
driven by a 7-stage programmable prescaler. Each of the four channels can be configured for input capture
or output compare. Additionally, one of the channels, channel 3, can be configured as a pulse accumulator.
A timer overflow function allows software to extend the timing capability of the system beyond the 16-bit
range of the counter. The input capture and output compare functions allow simultaneous input waveform
measurements and output waveform generation. The input capture function can capture the time of a
selected transition edge. The output compare function can generate output waveforms and timer software
delays. The 16-bit pulse accumulator can operate as a simple event counter or a gated time accumulator.
1.4.14 Periodic Interrupt Timers (PIT0 and PIT1)
The two periodic interrupt timers (PIT0 and PIT1) are 16-bit timers that provide interrupts at regular
intervals with minimal processor intervention. Each timer can either count down from the value written in
its PIT modulus register, or it can be a free-running down-counter.
1.4.15 Pulse Width Modulation (PWM) Timers
The MCF52235 has an 8-channel, 8-bit PWM timer. Each channel has a programmable period and duty
cycle as well as a dedicated counter. Each of the modulators can create independent continuous waveforms
with software-selectable duty rates from 0% to 100%. The PWM outputs have programmable polarity, and
can be programmed as left aligned outputs or center aligned outputs. For higher period and duty cycle
resolution, each pair of adjacent channels ([7:6], [5:4], [3:2], and [1:0]) can be concatenated to form a
single 16-bit channel. The module can thus be configured to support 8/0, 6/1, 4/2, 2/3, or 0/4 8-/16-bit
channels.
1.4.16 Software Watchdog Timer
The watchdog timer is a 32-bit timer that facilitates recovery from runaway code. The watchdog counter
is a free-running down-counter that generates a reset on underflow. To prevent a reset, software must
periodically restart the countdown.
1.4.17 Phase Locked Loop (PLL)
The clock module contains a crystal oscillator, 8 MHz on-chip relaxation oscillator (OCO), phase-locked
loop (PLL), reduced frequency divider (RFD), low-power divider status/control registers, and control
logic. In order to improve noise immunity, the PLL, crystal oscillator, and relaxation oscillator have their
own power supply inputs: VDDPLL and VSSPLL. All other circuits are powered by the normal supply
pins, VDD and VSS.
MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 0
Freescale Semiconductor 1-13
Preliminary
Overview
1.4.18 Interrupt Controller (INTC0/INTC1)
There are two interrupt controllers on the MCF52235. These interrupt controllers are organized as seven
levels with up to nine interrupt sources per level. Each interrupt source has a unique interrupt vector, and
provide each peripheral with all necessary interrupts. Each internal interrupt has a programmable level
[1-7] and priority within the level. The seven external interrupts have fixed levels/priorities.
1.4.19 DMA Controller
The direct memory access (DMA) controller provides an efficient way to move blocks of data with
minimal processor intervention. It has four channels that allow byte, word, longword, or 16-byte burst line
transfers. These transfers are triggered by software explicitly setting a DCRn[START] bit or by the
occurrence of certain UART or DMA timer events.
1.4.20 Reset
The reset controller determines the source of reset, asserts the appropriate reset signals to the system, and
keeps track of what caused the last reset. There are seven sources of reset:
• External reset input
• Power-on reset (POR)
• Watchdog timer
• Phase locked-loop (PLL) loss of lock
• PLL loss of clock
• Software
• Low-voltage detector (LVD)
Control of the LVD and its associated reset and interrupt are handled by the reset controller. Other registers
provide status flags indicating the last source of reset and a control bit for software assertion of the RSTO
pin.
1.4.21 GPIO
Nearly all pins on the MCF52235 have general purpose I/O capability in addition to their primary
functions, and are grouped into 8-bit ports. Some ports do not utilize all 8 bits. Each port has registers that
configure, monitor, and control the port pins.
MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 0
1-14 Freescale Semiconductor
Preliminary
Signal Descriptions
Chapter 2 Signal Descriptions
2.1 Introduction
This chapter describes signals implemented on this device and includes an alphabetical listing of signals
that characterizes each signal as an input or output, defines its state at reset, and identifies whether a
pull-up resistor should be used.
NOTE
The terms ‘assertion’ and ‘negation’ are used to avoid confusion when
dealing with a mixture of active-low and active-high signals. The term
‘asserted’ indicates that a signal is active, independent of the voltage level.
The term ‘negated’ indicates that a signal is inactive.
Active-low signals, such as SRAS and TA, are indicated with an overbar.
2.2 Overview
Figure 2-1 shows the block diagram of the device with the signal interface.
MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 0
Freescale Semiconductor 2-1
Preliminary
Signal Descriptions
EPHY_TX
EPHY_RX
JTAG_EN
EPHY
Fast
Ethernet
Controller
(FEC)
4 CH DMA
To/From PADI
MUX
JTAG
TAP
EzPD EzPCK
EzPQ
EzPort
Arbiter
UART
0
DTIM0DTIM1DTIM2DTIM
EzPCS
UART
1
V2 ColdFire CPU
OEP
IFP
Interrupt
Controller 1
UART
2
CAU
I2C
3
EMAC
Interrupt
Controller 2
QSPI
RTC
PADI – Pin Muxing
PMM
ICOCn
QSPI_DIN,
QSPI_DOUT
QSPI_SCK,
QSPI_PCSn
I2C_SDA
I2C_SCL
UnTXD
UnRXD
UnRTS
UnCTS
DTINn/DTOUTn
CANRX
CANTX
PWMn
ADCAN[7:0]
V
RHVRL
Edge
Port 1
Edge
Port 2
To/From Interrupt Controller
EXTAL XTAL CLKOUT
32 Kbytes
SRAM
(4Kx16)x4
PLL
CLKGEN
256 Kbytes
Flash
(32Kx16)x4
RNGA
PORTS
(GPIO)
FlexCAN
PIT0
PIT1
CIM
RSTIN
RSTOUT
PWM
GPT
Figure 2-1. Block Diagram with Signal Interfaces
Table 2-1 shows the pin functions by primary and alternate purpose, and illustrates which packages contain
each pin.
MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 0
2-2 Freescale Semiconductor
Preliminary
Freescale Semiconductor 2-3
Table 2-1. Pin Functions by Primary and Alternate Purpose
Pin
Group
Primary
Function
Secondary
Function
Ter tiary
Function
Quaternary
Function
Drive
Strength /
Control
Wired OR
1
Control
Pull-up /
Pull-down
Pin on121
2
MAPBGA
Pin on 112
LQFP
Pin on 80
LQFP
Notes
ADC AN7 — — PAN[7] Low — — — 88 64
AN6 — — PAN[6] Low — — — 87 63
MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 0
AN5 — — PAN[5] Low — — — 86 62
AN4 — — PAN[4] Low — — — 85 61
AN3 — — PAN[3] Low — — — 89 65
AN2 — — PAN[2] Low — — — 90 66
AN1 — — PAN[1] Low — — — 91 67
AN0 — — PAN[0] Low — — — 92 68
3
SYNCA CANTX
Preliminary
SYNCB CANRX
FEC_MDIO PAS[3] PDSR[39] — — — 28 20
3
FEC_MDC PAS[2] PDSR[39] — — — 27 19
VDDA — — — N/A N/A — — 93 69
VSSA — — — N/A N/A — — 94 72
VRH — — — N/A N/A — — 95 70
VRL — — — N/A N/A — — 96 71
Clock
Generation
Debug
Data
EXTAL — — — N/A N/A — — 48 36
XTAL — — — N/A N/A — — 49 37
VDDPLL — — — N/A N/A — — 45 33
VSSPLL — — — N/A N/A — — 47 35
ALLPST — — — High — — — 7 7
DDATA[3:0] — — PDD[7:4] High — — — 12,13,
16,17
PST[3:0] — — PDD[3:0] High — — — 80,79,
78,77
—
Signal Descriptions
—
2-4 Freescale Semiconductor
Pin
Group
Primary
Function
Secondary
Function
Ter tiary
Function
Quaternary
Function
Drive
Strength /
Control
Wired OR
1
Control
Pull-up /
Pull-down
Pin on121
2
MAPBGA
Pin on 112
LQFP
Pin on 80
LQFP
Signal Descriptions
Notes
Ethernet
LEDs
MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 0
ACTLED — — PLD[0] PDSR[32] PWOR[8] — — 84 60
COLLED — — PLD[4] PDSR[36] PWOR[12] — — 58 42
DUPLED — — PLD[3] PDSR[35] PWOR[11] — — 59 43
LNKLED — — PLD[1] PDSR[33] PWOR[9] — — 83 59
SPDLED — — PLD[2] PDSR[34] PWOR[10] — — 81 57
RXLED — — PLD[5] PDSR[37] PWOR[13] — — 52 —
TXLED — — PLD[6] PDSR[38] PWOR[14] — — 51 —
Ethernet
PHY
PHY_RBIAS — — — — — — 66 46
PHY_RXN — — — — — — 74 54
PHY_RXP — — — — — — 73 53
Preliminary
PHY_TXN — — — — — — 71 51
PHY_TXP — — — — — — 70 50
PHY_VDDA — — — N/A — 68 48
PHY_VDDRX — — — N/A — 75 55
PHY_VDDTX — — — N/A — 69 49
PHY_VSSA — — — N/A — 67 47
PHY_VSSRX — — — N/A — 76 56
PHY_VSSTX — — — N/A — 72 52
I2C SCL CANTX
SDA CANRX
3
3
TXD2 PAS[0] PDSR[0] — pull-up
RXD2 PAS[1] PDSR[0] — pull-up
4
4
— 111 79
— 112 80
Freescale Semiconductor 2-5
Pin
Group
Primary
Function
Secondary
Function
Ter tiary
Function
Quaternary
Function
Interrupts IRQ15 — — PGP[7] PSDR[47] — pull-up
IRQ14 — — PGP[6] PSDR[46] — pull-up
MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 0
IRQ13 — — PGP[5] PSDR[45] — pull-up
IRQ12 — — PGP[4] PSDR[44] — pull-up
IRQ11 — — PGP[3] PSDR[43] — pull-up
IRQ10 — — PGP[2] PSDR[42] — pull-up
IRQ9 — — PGP[1] PSDR[41] — pull-up
IRQ8 — — PGP[0] PSDR[40] — pull-up
IRQ7 — — PNQ[7] Low — pull-up
IRQ6 — FEC_RXER PNQ[6] Low — pull-up
Preliminary
IRQ5 — FEC_RXD[1] PNQ[5] Low — pull-up
IRQ4 — — PNQ[4] Low — pull-up
IRQ3 — FEC_RXD[2] PNQ[3] Low — pull-up
IRQ2 — FEC_RXD[3] PNQ[2] Low — pull-up
IRQ1 SYNCA PWM1 PNQ[1] High — pull-up
Drive
Strength /
Control
Wired OR
1
Control
Pull-up /
Pull-down
2
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
Pin on121
MAPBGA
Pin on 112
LQFP
Pin on 80
LQFP
— 106 —
— 105 —
—98—
—97—
—57—
—29—
—11—
—10—
—5640
—19—
—20—
—4129
—53—
—54—
—5539
Notes
JTAG/BDM JTAG_EN — — — N/A N/A pull-down — 18 12
TCLK/
CLKOUT — — High — pull-up
5
—1 1
PSTCLK
TDI/DSI — — — N/A N/A pull-up
5
—4 4
TDO/DSO — — — High N/A — — 5 5
TMS
— — — N/A N/A pull-up
5
—2 2
/BKPT
TRST
— — — N/A N/A pull-up
5
—6 6
/DSCLK
Mode
Selection
RCON
EZPCS
/
— — — N/A N/A pull-up — 3 3
Signal Descriptions
Freescale Semiconductor 2-6
Pin
Group
Primary
Function
Secondary
Function
Ter tiary
Function
Quaternary
Function
Drive
Strength /
Control
Wired OR
1
Control
Pull-up /
Pull-down
Pin on121
2
MAPBGA
Pin on 112
LQFP
Pin on 80
LQFP
PWM PWM7 — — PTD[3] PDSR[31] — — — 104 —
PWM5 — — PTD[2] PDSR[30] — — — 103 —
Notes
MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 0
PWM3 — — PTD[1] PDSR[29] — — — 100 —
PWM1 — — PTD[0] PDSR[28] — — — 99 —
QSPI QSPI_DIN/
CANRX
3
RXD1 PQS[1] PDSR[2] PWOR[4] — — 34 25
EZPD
QSPI_DOUT/
CANTX
3
TXD1 PQS[0] PDSR[1] PWOR[5] — — 35 26
EZPQ
QSPI_SCK/
SCL RTS1 PQS[2] PDSR[3] PWOR[6] pull-up
6
—3627
EZPCK
QSPI_CS3 SYNCA SYNCB PQS[6] PDSR[7] — — — 40 —
Preliminary
QSPI_CS2 — — PQS[5] PDSR[6] — — — 39 —
QSPI_CS1 — — PQS[4] PDSR[5] — — — 38 —
6
7
—3758
—4432
Reset
QSPI_CS0 SDA CTS1
7
RSTI — — — N/A N/A pull-up
PQS[3] PDSR[4] PWOR[7] pull-up
RSTO — — — high — — — 46 34
Test TEST — — — N/A N/A pull-down — 50 38
Timers,
16-bit
GPT3 FEC_TXD[3] PWM7 PTA[3] PDSR[23] — pull-up
GPT2 FEC_TXD[2] PWM5 PTA[2] PDSR[22] — pull-up
GPT1 FEC_TXD[1] PWM3 PTA[1] PDSR[21] — pull-up
GPT0 FEC_TXER PWM1 PTA[0] PDSR[20] — pull-up
8
8
8
8
— 107 75
— 108 76
— 109 77
— 110 78
Timers,
32-bit
TIN3 TOUT3 PWM6 PTC[3] PDSR[19] — — — 22 14
TIN2 TOUT2 PWM4 PTC[2] PDSR[18] — — — 21 13
TIN1 TOUT1 PWM2 PTC[1] PDSR[17] — — — 9 9
TIN0 TOUT0 PWM0 PTC[0] PDSR[16] — — — 8 8
Signal Descriptions
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