NXP Semiconductors 56F803, 56F800 User Manual

56F803

Evaluation Module User Manual

56F800
16-bit Digital Signal Controllers

DSP56F803EVMUM
Rev. 5
07/2005

freescale.com

TABLE OF CONTENTS

Preface vii

Audience . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vii

Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vii

Suggested Reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vii

Notation Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . viii

Definitions, Acronyms, and Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ix

References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . x

Chapter 1

Introduction

1.1 56F803EVM Architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2

1.2 56F803EVM Configuration Jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3

1.3 56F803EVM Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4

Chapter 2

Technical Summary

2.1 56F803. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2

2.2 Program and Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4

2.3 RS-232 Serial Communications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5

2.4 Clock Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6

2.5 Operating Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6

2.6 Debug LED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7

2.7 Debug Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7

2.7.1 JTAG Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7

2.7.2 Parallel JTAG Interface Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8

2.8 External Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10

2.9 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11

2.10 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11

2.11 UNI-3 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12

2.12 Run/Stop Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13

2.13 Motor Control PWM Signals and LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14

2.14 Motor Protection Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14

2.14.1 UNI-3 Motor Protection Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15

2.15 Back-EMF and Motor Phase Current Sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16

Freescale Semiconductor i

Table of Contents, Rev. 5

2.16 Quadrature Encoder/Hall-Effect Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17

2.17 Zero-Crossing Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17

2.18 CAN Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18

2.19 Peripheral Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19

2.19.1 External Memory Control Signal Expansion Connector . . . . . . . . . . . . . . . . . . . . . 2-20

2.19.2 Encoder/Timer Channel Expansion Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20

2.19.3 Timer Channel Expansion Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21

2.19.4 Address Bus Expansion Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21

2.19.5 Data Bus Expansion Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22

2.19.6 A/D Port Expansion Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-23

2.19.7 Serial Communications Port Expansion Connector . . . . . . . . . . . . . . . . . . . . . . . . 2-23

2.19.8 Serial Peripheral Interface Expansion Connector . . . . . . . . . . . . . . . . . . . . . . . . . . 2-24

2.19.9 CAN Expansion Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-24

2.19.10 PWM Port Expansion Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-25

2.20 Test Points. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-25

Appendix A

56F803EVM Schematics

Appendix B

56F803EVM Bill of Material

ii Freescale Semiconductor

DSP56F803EVM User Manual, Rev. 5

LIST OF FIGURES

1-1 Block Diagram of the 56F803EVM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2

1-2 56F803EVM Jumper Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3

1-3 Connecting the 56F803EVM Cables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4

2-1 Schematic Diagram of the External Memory Interface. . . . . . . . . . . . . . . . . . . . . . . 2-4

2-2 Schematic Diagram of the RS-232 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5

2-3 Schematic Diagram of the Clock Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6

2-4 Schematic Diagram of the Debug LED Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7

2-5 Block Diagram of the Parallel JTAG Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9

2-6 Schematic Diagram of the User Interrupt Interface. . . . . . . . . . . . . . . . . . . . . . . . . 2-10

2-7 Schematic Diagram of the RESET Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11

2-8 Schematic Diagram of the Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11

2-9 Run/Stop Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13

2-10 PWM Group Interface and LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14

2-11 DC Bus Over-Voltage and Over-Current Detection Schematic Diagram . . . . . . . . 2-15

2-12 Primary Back-EMF or Motor Phase Current Sense Signals . . . . . . . . . . . . . . . . . . 2-16

2-13 Zero-Crossing Encoder Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17

2-14 CAN Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18

A-1 56F803 Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-2

A-2 Reset, Mode, Clock & IRQsL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-3

A-3 Program & Data SRAM Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-4

A-4 RS-232 and SCI Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-5

A-5 56F803 PWM LEDs and User LED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-6

A-6 UNI-3 Over-Voltage and Current Sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-7

A-7 Zero-Crossing/ Encoder or Hall-Effect Selection . . . . . . . . . . . . . . . . . . . . . . . . A-8

A-8 High Speed CAN Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-9

A-9 Port Timer D, Address, Data, A/D and Control Line Connectors . . . . . . . . . . . A-10

A-10 UNI-3 Interface and General Purpose Switches . . . . . . . . . . . . . . . . . . . . . . . . A-11

Freescale Semiconductor iii

List of Figures, Rev. 5

A-11 Back-EMF and Phase Current Sense Analog Input Selectors . . . . . . . . . . . . . . A-12

A-12 Parallel JTAG Host/Target Interface and JTAG Connector . . . . . . . . . . . . . . . A-13

A-13 Power Supplies 3.3V and 5.0V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-14

A-14 Bypass Capacitors and Spare Gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-15

iv Freescale Semiconductor

DSP56F803EVM User Manual, Rev. 5

LIST OF TABLES

1-1 56F803EVM Default Jumper Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3

2-1 RS-232 Serial Connector Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5

2-2 Operating Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6

2-3 JTAG Connector Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8

2-4 Parallel JTAG Interface Disable Jumper Selection . . . . . . . . . . . . . . . . . . . . . . . 2-8

2-5 Parallel JTAG Interface Connector Description . . . . . . . . . . . . . . . . . . . . . . . . . 2-9

2-6 On-Board Host Target Interface Power Source Jumper Selection . . . . . . . . . . 2-10

2-7 UNI-3 Connector Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12

2-8 CAN Header Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19

2-9 External Memory Control Signal Connector Description . . . . . . . . . . . . . . . . . 2-20

2-10 Timer Connector Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20

2-11 Timer D Connector Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21

2-12 External Memory Address Bus Connector Description. . . . . . . . . . . . . . . . . . . 2-21

2-13 External Memory Address Bus Connector Description. . . . . . . . . . . . . . . . . . . 2-22

2-14 A/D Connector Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-23

2-15 SCI Connector Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-23

2-16 SPI Connector Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-24

2-17 CAN Connector Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-24

2-18 PWM Port Connector Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-25

Freescale Semiconductor v

List of Tables, Rev. 5

vi Freescale Semiconductor

DSP56F803EVM User Manual, Rev. 5

Preface

This reference manual describes in detail the hardware on the 56F803 Evaluation Module.

Audience

This document is intended for application developers who are creating software for
devices using the Freescale 56F803 part.

Organization

This manual is organized into two chapters and two appendixes.

• Chapter 1, Introduction - provides an overview of the 56F803EVM and its
features.

• Chapter 2, Technical Summary - describes in detail the 56F803EVM hardware.

• Appendix A, 56F803EVM Schematics - contains the schematics of the
56F803EVM.

• Appendix B, 56F803EVM Bill of Material - provides a list of the materials used
on the 56F803EVM board.

Suggested Reading

More documentation on the 56F803 and the 56F803EVM kit may be found at the URL:

Freescale Semiconductor vii

http://www.freescale.com

Preface, Rev. 5

Notation Conventions

This document uses the following conventions:

Term or Value Symbol Examples Exceptions

Active High Signals
(Logic One)

Active Low Signals
(Logic Zero)

Hexadecimal Values Begin with a “$”

Decimal Values No special symbol

Binary Values Begin with the letter

Numbers Considered positive

Bold Reference sources,

No special symbol
attached to the sig­nal name

Noted with an
overbar in text and in
most figures

symbol

attached to the
number

“b” attached to the
number

unless specifically
noted as a negative
value

paths, emphasis

A0
CLKO

WE
OE

$0FF0
$80

10
34

b1010
b0011

5

-10

...see:

www.freescale.com

In schematic drawings,
Active Low Signals may
be noted by a backslash:
/WE

Voltage is often shown
as positive: +3.3V

...

viii Freescale Semiconductor

DSP56F801EVM User Manual, Rev. 5

Definitions, Acronyms, and Abbreviations

Definitions, acronyms and abbreviations for terms used in this document are defined below for
reference.

A/D

CAN

CiA

EVM

GPIO

IC

JTAG

LQFP

MPIO

OnCE

PCB

PLL

TM

Analog-to-Digital

Controller Area Network; serial communications peripheral and method

CAN in Automation, an international CAN user’s group that coordinates
standards for CAN communications protocols

Evaluation Module

General Purpose Input and Output Port

Integrated Circuit

Joint Test Action Group, a bus protocol/interface used for test and debug

Low-profile Quad Flat Pack

Multi Purpose Input and Output Port; shares package pins with other
peripherals on the chip and can function as a GPIO

On-Chip Emulation, a debug bus and port created by Freescale to enable
designers to create a low-cost hardware interface for a professional
quality debug environment

Printed Circuit Board

Phase Locked Loop

PWM

RAM

ROM

SCI

SPI

Pulse Width Modulation

Random Access Memory

Read Only Memory

Serial Communications Interface

Serial Peripheral Interface Port

SRAM Static Random Access Memory

UART

Freescale Semiconductor ix

Universal Asynchronous Receiver/Transmitter

Preface, Rev. 5

References

The following sources were referenced to produce this manual:

[1] DSP56800 Family Manual, Freescale Semiconductor, DSP56800FM

[2] DSP56F801/803/805/807 User’s Manual, Freescale Semiconductor,

DSP56F801-7UM

[3] 56F803 Technical Data, Freescale Semiconductor, DSP56F803

[4] CiA Draft Recommendation DR-303-1, Cabling and Connector Pin Assignment,

Version 1.0, CAN in Automation

[5] CAN Specification 2.0B, BOSCH or CAN in Automation

x Freescale Semiconductor

DSP56F801EVM User Manual, Rev. 5

Chapter 1
Introduction

The 56F803EVM is used to demonstrate the abilities of the 56F803 and to provide a hardware
tool allowing the development of applications that use the 56F803.

The 56F803EVM is an evaluation module board that includes a 56F803 part, peripheral
expansion connectors, external memory, RS-232 interface and a CAN interface. The expansion
connectors are for signal monitoring and user feature expandability.

The 56F803EVM is designed for the following purposes:

• Allowing new users to become familiar with the features of the 56800 architecture. The
tools and examples provided with the 56F803EVM facilitate evaluation of the feature set
and the benefits of the family.

• Serving as a platform for real-time software development. The tool suite enables the user
to develop and simulate routines, download the software to on-chip or on-board RAM, run

TM

it, and debug it using a debugger via the JTAG/OnCE
the OnCE port enable the user to easily specify complex break conditions and to execute
user-developed software at full-speed, until the break conditions are satisfied. The ability
to examine and modify all user accessible registers, memory and peripherals through the
OnCE port greatly facilitates the task of the developer.

port. The breakpoint features of

• Serving as a platform for hardware development. The hardware platform enables the user
to connect external hardware peripherals. The on-board peripherals can be disabled,
providing the user with the ability to reassign any and all of the controller’s peripherals.
The OnCE port's unobtrusive design means that all of the memory on the board and on the
chip are available to the user.

Freescale Semiconductor 1-1

Introduction, Rev. 5

1.1 56F803EVM Architecture

The 56F803EVM facilitates the evaluation of various features present in the 56F803 part. The
56F803EVM can be used to develop real-time software and hardware products based on the
56F803. The 56F803EVM provides the features necessary for a user to write and debug
software, demonstrate the functionality of that software and interface with the customer's
application-specific device(s). The 56F803EVM is flexible enough to allow a user to fully
exploit the 56F803's features to optimize the performance of their product, as shown in

Figure 1-1.

56F803

Low Freq

Crystal

RESET

LOGIC

XTAL/EXTAL

RESET

DSub

25-Pin

MODE / IRQ

LOGIC

Program

Memory

64Kx16-bit

Data Memory

64Kx16-bit

Memory

Expansion

Connector(s)

JTAG

Connector

Parallel

JTAG Interface

RS-232

Interface

Peripheral
Expansion

Connector(s)

UNI-3

Power Supply

3.3V, 5V &

3.3VA

MODE / IRQ

Address,
Data &
Control

JTAG / OnCE

SCI

SPI

CAN

TIMER

GPIO

PWM

A / D

3.3 V & GND

Figure 1-1. Block Diagram of the 56F803EVM

DSub
9-Pin

CAN Interface

Debug LEDs

PWM LEDs

Over V Sense

Over I Sense

Zero Crossing

Detect

1-2 Freescale Semiconductor 

DSP56F803EVM User Manual, Rev. 5

56F803EVM Configuration Jumpers

1.2 56F803EVM Configuration Jumpers

Ten jumper groups, (JG1-JG10), shown in Figure 1-2, are used to configure various
features on the 56F803EVM board. Table 1-1 describes the default jumper group settings.

7

8

9

1

J9

JG9

JG2

U6

J4

DSP56F803EVM

1

JG4

JTAG

JG8

J1

U7

3

JG9

P3

JG6

2

1

3

3

12

JG6

P1

1

738

USER LED

789

2

9

PWM LEDs

LED3

9

7

8

JG1

1

2

7

8

JG7

JG7

132

JG5

P4

JG10

JG3

J3

J2

JG10

JG1

1

S2

J8

J10

Y1

1

JG3

1

U1

U15

S/N

S1

JG4

RUN/STOP

S4

S3

P2

IRQBIRQA

RESET

JG5

JG4

JG2

JG8

Figure 1-2. 56F803EVM Jumper Reference

Table 1-1. 56F803EVM Default Jumper Options

Jumper

Group

Comment

JG1 UNI-3 serial selected 1–2, 3–4, 5–6 & 7–8

JG2 Enable on-board Parallel JTAG Command Converter Interface NC

JG3 Use on-board crystal for oscillator input 1–2

JG4 Selects device’s Mode 0, BOOT From FLASH, operation upon exit from

reset

JG5 Enable external SRAM 1–2

JG6 UNI-3 3-Phase Current Source Selected 2–3, 5–6 & 8–9

Jumpers

Connections

1–2

JG7 Encoder Input Selected 2–3, 5–6 & 8–9

JG8 On-board Parallel JTAG Command Converter powered by Host System 1-2

JG9 Use on-board crystal for oscillator input 1–2

JG10 Leave CAN bus un-terminated NC

Freescale Semiconductor 1-3

Introduction, Rev. 5

1.3 56F803EVM Connections

An interconnection diagram is shown in Figure 1-3 for connecting the PC and the external +12V
DC power supply to the 56F803EVM board.

Parallel Extension

Cable

56F803EVM
PC-compatible
Computer

P2

Connect cable

to Parallel/Printer port

External

+12V

Power

P3

with 2.1mm,
receptacle
connector

Figure 1-3. Connecting the 56F803EVM Cables

Perform the following steps to connect the 56F803EVM cables:

1. Connect the parallel extension cable to the Parallel port of the host computer.

2. Connect the other end of the parallel extension cable to P2, shown in Figure 1-3, on the
56F803EVM board. This provides the connection which allows the host computer to
control the board.

3. Make sure that the external +12V DC, 4.0A power supply is not plugged into a +120V AC
power source.

4. Connect the 2.1mm output power plug from the external power supply into P3, shown in

Figure 1-3, on the 56F803EVM board.

5. Apply power to the external power supply. The green Power-On LED will illuminate
when power is correctly applied.

1-4 Freescale Semiconductor 

DSP56F803EVM User Manual, Rev. 5

Chapter 2
Technical Summary

The 56F803EVM is designed as a versatile controller development card for developing real-time
software and hardware products to support a new generation of applications in digital and
wireless messaging, servo and motor control, digital answering machines, feature phones,
modems, and digital cameras. The power of the 16-bit 56F803 controller, combined with the
on-board 64K u16-bit external program Static RAM (SRAM), 64K u16-bit external data
SRAM, CAN interface, Hall-Effect/Quadrature Encoder interface, motor zero crossing logic,
motor bus over-current logic, motor bus over-voltage logic and parallel JTAG interface, makes
the 56F803EVM ideal for developing and implementing many motor controlling algorithms, as
well as for learning the architecture and instruction set of the 56F803 processor.

The main features of the 56F803EVM include:

• 56F803 16-bit +3.3V controller operating at 80MHz [U1]

• External fast Static RAM (FSRAM) memory [U2], configured as:

— 64Ku16-bit of Program memory with 0 wait states at 70MHz

— 64Ku16-bit of Data memory with 0 wait states at 70MHz

• 8.00MHz crystal oscillator for device frequency generation [Y1]

• Optional external oscillator frequency input connector [JG3 and JG9]

• Joint Test Action Group (JTAG) port interface connector for an external debug Host
Target Interface [J1]

• On-board Parallel JTAG Host Target Interface, with a connector for a PC printer port
cable [P2]

• RS-232 interface for easy connection to a host processor [U3 and P4]

• CAN interface for high speed, 1.0Mbps, communications [U15 and J3]

• CAN bypass and bus termination [J13 and JG10]

• Connector to allow the user to connect his own SCI / GPIO-compatible peripheral [J12]

• Connector to allow the user to connect his own SPI / MPIO-compatible peripheral [J6]

• Connector to allow the user to connect his own PWM / GPIO-compatible peripheral [J4]

• Connector to allow the user to connect his own CAN physical layer peripheral [J5]

• Connector to allow the user to connect his own Timer / MPIO-compatible peripheral [J10]

Freescale Semiconductor 2-1

Technical Summary, Rev. 5

• Connector to allow the user to connect to the device’s A/D Port [J9]

• 56F803’s external memory expansion connectors [J7, J8 and J11]

• On-board power regulation from an external +12V DC-supplied power input [P3]

• Light Emitting Diode (LED) power indicator [LED1]

• Six on-board PWM monitoring LEDs [LED2-LED7]

• On-board real-time user debugging LED [LED8]

• UNI-3 Motor interface [P1]

— Encoder/Hall-Effect interface

— Over-Voltage sensing [U14]

— Over-Current sensing [U14]

— DC Bus Voltage sensing [U13]

— DC Bus Current sensing [U13]

— Back-EMF sensing

— Temperature sensing

— Zero Crossing detection

— Pulse Width Modulation

— Power Factor Correction (PFC) sensing

• Manual RESET push-button [S4]

• Manual interrupt push-button for IRQA

• Manual interrupt push-button for IRQB

[S2]

[S3]

• General purpose toggle switch for RUN/STOP control(AN7) [S1]

2.1 56F803

The 56F803EVM uses a Freescale DSP56F803BU80 part, designated as U1 on the board and in
the schematics. This part will operate at a maximum speed of 80MHz. A full description of the
56F803, including functionality and user information, is provided in the following documents:

• 56F803 Technical Data, (DSP56F803): Provides features list and specifications including
signal descriptions, DC power requirements, AC timing requirements and available
packaging.

2-2 Freescale Semiconductor 

DSP56F803EVM User Manual, Rev. 5

56F803

• DSP56F801/803/805/807 User’s Manual, (DSP56F801-7UM): Provides an overview
description of the controller and detailed information about the on-chip components
including the memory and I/O maps, peripheral functionality, and control/status register
descriptions for each subsystem.

• DSP56800 Family Manual, (DSP56800FM): Provides a detailed description of the core
processor including internal status and control registers and a detailed description of the
family instruction set.

These manuals contain detailed information about chip functionality and operation and can be
found at this URL:

http://www.freescale.com

Freescale Semiconductor 2-3

Technical Summary, Rev. 5

2.2 Program and Data Memory

The 56F803EVM uses one bank of 128Ku16-bit Fast Static RAM (GSI GS72116, labeled U2)
for external memory expansion; see the FSRAM schematic diagram in Figure 2-1. This physical
memory bank is split into two logical memory banks of 64Kx16-bits: one for Program memory
and the other for Data memory. By using the device’s program strobe, PS
the memory chip’s A0 signal line, half of the memory chip is selected when Program memory
accesses are requested and the other half of the memory chip is selected when Data memory
accesses are requested. This memory bank will operate with zero wait-state accesses while the
56F803 is running at 70MHz. However, when running at 80MHz, the memory bank operates
with four wait-state accesses. This memory bank can be disabled by removing the jumper at JG5.

, signal line along with

56F803

A0-A15

PS

D0-D15

RD

WR

Connect Pin 1-2:
Enable SRAM

Jumper Removed:
Disable SRAM

JG5

+3.3V

1

2

GS72116

A1-A16

A0

D0-D15

RD

WR

CS

Figure 2-1. Schematic Diagram of the External Memory Interface

2-4 Freescale Semiconductor 

DSP56F803EVM User Manual, Rev. 5

RS-232 Serial Communications

2.3 RS-232 Serial Communications

The 56F803EVM provides an RS-232 interface by the use of an RS-232 level converter,
(Analog Devices ADM3311EARS, designated as U3); refer to the RS-232 schematic
diagram in Figure 2-2. The RS-232 level converter transitions the SCI UART’s +3.3V
signal levels to RS-232 compatible signal levels and connects to the host’s serial port via
connector P4. Flow control is not provided, but could be implemented using uncommitted
GPIO signals. The pin-out of connector P4 is listed in Table 2-1.

RS-232

56F803

TXD0

RXD0 R1in

Level Interface

R1out

RS-232 DB9

1

6

T1outT1in

2

7

3
8

4
9

x

5

P4

Figure 2-2. Schematic Diagram of the RS-232 Interface

Table 2-1. RS-232 Serial Connector Description

P4

Pin # Signal Pin # Signal

1 Jumper to 6 & 4 6 Jumper to 1 & 4

2 TXD 7 Jumper to 8

3 RXD 8 Jumper to 7

4 Jumper to 1 & 6 9 N/C

5GND

Freescale Semiconductor 2-5

Technical Summary, Rev. 5

2.4 Clock Source

The 56F803EVM uses an 8.00MHz crystal, Y1, connected to its External Crystal Inputs, EXTAL
and XTAL. The 56F803 uses its internal PLL to multiply the input frequency by 10 to achieve its
80MHz maximum operating frequency. An external oscillator source can be connected to the
controller by using the oscillator bypass connectors, JG3 and JG9; see Figure 2-3.

EXTERNAL

OSCILLATOR

HEADERS

8.00MHz

JG3

321

JG9

56F803

EXTAL

1

2

XTAL

Figure 2-3. Schematic Diagram of the Clock Interface

2.5 Operating Mode

The 56F803EVM provides a boot-up MODE selection jumper, JG4. This jumper is used to select
the operating mode of the controller as it exits RESET. Refer to the DSP56F801-7 User’s Manual
for a complete description of the chip’s operating modes. Table 2-2 shows the two operation
modes available on the 56F803.

Table 2-2. Operating Mode Selection

Operating Mode JG4 Comment

0 1–2 Bootstrap from internal memory (GND)

3 No Jumper Bootstrap from external memory (+3.3V)

2-6 Freescale Semiconductor 

DSP56F803EVM User Manual, Rev. 5

Debug Support

2.6 Debug LED

An on-board Light-Emitting Diode, (LED), is provided to allow real-time debugging for user
programs. This LED allows the programmer to monitor program execution without having to
stop the program during debugging; refer to Figure 2-4. LED8 is controlled by the MOSI signal
line. Setting MOSI to a Logic One value will turn on the LED.

56F803

LED 8

BUFFERMOSI

GREEN LED

+3.3V

Figure 2-4. Schematic Diagram of the Debug LED Interface

2.7 Debug Support

The 56F803EVM provides an on-board Parallel JTAG Host Target Interface and a JTAG
interface connector for external Host Target Interface support. Two interface connectors are
provided to support each of these debugging approaches. These two connectors are designated
the JTAG connector and the Host Parallel Interface Connector.

2.7.1 JTAG Connector

The JTAG connector on the 56F803EVM allows the connection of an external Host Target
Interface for downloading programs and working with the 56F803’s registers. This connector is
used to communicate with an external Host Target Interface which passes information and data
back and forth with a host processor running a debugger program. Table 2-3 shows the pin-out
for this connector.

Freescale Semiconductor 2-7

Technical Summary, Rev. 5

Table 2-3. JTAG Connector Description

J1

Pin # Signal Pin # Signal

1 TDI 2 GND

3 TDO 4 GND

5 TCK 6 GND

7 NC 8 KEY

9 RESET

11 +3.3V 12 NC

13 NC 14 TRST

10 TMS

When this connector is used with an external Host Target Interface, the parallel JTAG
interface should be disabled by placing a jumper in jumper block JG2. Reference

Table 2-4 for this jumper’s selection options.

Table 2-4. Parallel JTAG Interface Disable Jumper Selection

JG2 Comment

No jumper On-board Parallel JTAG Interface Enabled

1–2 Disable on-board Parallel JTAG Interface

2.7.2 Parallel JTAG Interface Connector

The Parallel JTAG Interface Connector, P2, allows the 56F803 to communicate with a
Parallel Printer Port on a Windows PC; see Figure 2-5. By using this connector, the user
can download programs and work with the 56F803’s registers. Table 2-5 shows the
pin-out for this connector. When using the parallel JTAG interface, the jumper at JG2
should be removed; refer to Table 2-4. A jumper, JG8, is provided to allow the on-board
Host Target Interface to be powered by the Target board instead of the Host system, as
shown in Table 2-6.

2-8 Freescale Semiconductor 

DSP56F803EVM User Manual, Rev. 5

Debug Support

DB-25

PORT_TDI

PORT_TDO

PORT_TRST

PORT_TMS

PORT_TCK

PORT_RESET

PARALLEL JTAG

INTERFACE LOGIC

56F803

TDI

TDO

TRST

TMS

TCK

RESET

Figure 2-5. Block Diagram of the Parallel JTAG Interface

Table 2-5. Parallel JTAG Interface Connector Description

P2

Pin # Signal Pin # Signal

1NC14NC

2 PORT_RESET 15 PORT_IDENT

3 PORT_TMS 16 NC

4 PORT_TCK 17 NC

5 PORT_TDI 18 GND

6 PORT_

7 NC 20 GND

8 PORT_IDENT 21 GND

9 PORT_VCC 22 GND

10 NC 23 GND

11 PORT_TDO 24 GND

12 NC 25 GND

13 PORT_CONNECT

TRST 19 GND

Freescale Semiconductor 2-9

Technical Summary, Rev. 5

Table 2-6. On-Board Host Target Interface Power Source Jumper Selection

JG8 Comment

1–2 Host supplied power

2–3 Target supplied power

2.8 External Interrupts

Two on-board push-button switches are provided for external interrupt generation, as
shown in Figure 2-9. S2 allows the user to generate a hardware interrupt for signal line
IRQA
two switches allow the user to generate interrupts for his user-specific programs.

.; S3 allows the user to generate a hardware interrupt for signal line IRQB. These

+3.3V

56F803

IRQA

IRQA

+3.3V

IRQB

IRQB

Figure 2-6. Schematic Diagram of the User Interrupt Interface

2-10 Freescale Semiconductor 

DSP56F803EVM User Manual, Rev. 5

Power Supply

2.9 Reset

Logic is provided in the 56F803 to generate a clean power-on RESET signal. Additional,
reset logic is provided to support the RESET signals from the JTAG connector, the
Parallel JTAG Interface and the user RESET push-button; see Figure 2-7.

+3.3V

RESET

PUSHBUTTON

MANUAL RESET

P_RESET

RESET

Figure 2-7. Schematic Diagram of the RESET Interface

2.10 Power Supply

The main power input, +12V DC at 4.0A, to the 56F803EVM is through a 2.1mm coax
power jack. A 4.0A power supply is provided with the 56F803EVM; however, less than
500mA is required by the EVM. The remaining current is available for user motor control
applications. The 56F803EVM provides +3.3V DC voltage regulation for the device,
memory, RS-232, CAN, parallel JTAG interface and supporting logic; refer to Figure 2-8.
Power applied to the 56F803EVM is indicated with a Power-On LED, referenced as
LED1.

+12V DC

+5.0V

Regulator

+5.0V DC

+3.3V

Regulator

+3.3V DC

56F803

56F803EVM

PARTS

Figure 2-8. Schematic Diagram of the Power Supply

Freescale Semiconductor 2-11

Technical Summary, Rev. 5

2.11 UNI-3 Interface

Motor control signals from a family of motor driver boards can be connected to the EVM board
via the UNI-3 connector/interface. The UNI-3 connector/interface contains all of the signals
needed to drive and control the motor drive boards. These signals are connected to differing
groups of the device’s input and output ports: A/D, TIMER and PWM. Refer to Table 2-7 for the
pin out of the UNI-3 connector.

Table 2-7. UNI-3 Connector Description

P1

Pin # Signal Pin # Signal

1 PWM_AT 2 Shield

3 PWM_AB 4 Shield

5 PWM_BT 6 Shield

7 PWM_BB 8 Shield

9 PWM_CT 10 Shield

11 PWM_CB 12 GND

13 GND 14 +5.0V DC

15 +5.0V DC 16 Analog +3.3V DC

17 Analog GND 18 Analog GND

19 Analog +15V DC 20 Analog -15V DC

21 Motor DC Bus Voltage

Sense

23 Motor Phase A Current

Sense

25 Motor Phase C Current

Sense

27 NC 28 Shield

29 Motor Drive Brake Control 30 Serial COM

31 PFC PWM 32 PFC Inhibit

33 PFC Zero Cross 34 Zero Cross A

22 Motor DC Bus Current

Sense

24 Motor Phase B Current

Sense

26 Motor Drive Temperature

Sense

2-12 Freescale Semiconductor 

DSP56F803EVM User Manual, Rev. 5

Run/Stop Switch

Table 2-7. UNI-3 Connector Description (Continued)

P1

Pin # Signal Pin # Signal

35 Zero Cross B 36 Zero Cross C

37 Shield 38 Back-EMF Phase A Sense

39 Back-EMF Phase B Sense 40 Back-EMF Phase C Sense

2.12 Run/Stop Switch

A Run/Stop toggle switch is connected to GPIO signal AN7, as shown in Figure 2-9. An optional
series resistor is provided which, when removed, allows the user to utilize the AN7 signal for
other purposes.

RUN/STOP SWITCH

Figure 2-9. Run/Stop Switch

56F803

+3.3V

AN7

Freescale Semiconductor 2-13

Technical Summary, Rev. 5

2.13 Motor Control PWM Signals and LEDs

The 56F803 has a dedicated PWM unit. The unit contains six PWM, three Phase Current sense
and four Fault input lines. The PWM lines are connected to the UNI-3 interface connector and to
a set of six PWM LEDs via inverting buffers. The buffers are used to isolate and drive the
controller’s PWM outputs to the PWM LEDs. The PWM LEDs indicate the status of PWM group
signals, refer to Figure 2-12. The PWM group signals are routed out to headers and are available
for use by the end user.

56F803

PWMA0
PWMA1
PWMA2
PWMA3
PWMA4
PWMA5

UNI-3

PWMA0
PWMA1
PWMA2
PWMA3
PWMA4
PWMA5

YELLOW LED

GREEN LED

YELLOW LED

GREEN LED

BUFFER

YELLOW LED

GREEN LED

Figure 2-10. PWM Group Interface and LEDs

LED 2

LED 3

LED 4

LED 5

LED 6

LED 7

+3.3V

PWM_AT / 0

PWM_AB / 1

PWM_BT / 2

PWM_BB / 3

PWM_CT / 4

PWM_CB / 5

2.14 Motor Protection Logic

The 56F803EVM contains a UNI-3 connector that interfaces with various motor drive boards.
The controller can sense error conditions generated by the motor power stage boards via signals
on the UNI-3 connector. The motor driver board’s Motor Supply DC Bus Voltage, Current and
Motor Phase Currents are sensed on the power stage board. The conditioned signals are
transferred to the device board via the UNI-3 connector. These analog input signals are compared
to limits set by trimpots. If the input analog signals are greater than the limit set by the trimpot, a
digital-compatible, +3.3V DC, fault signal is generated.

2-14 Freescale Semiconductor 

DSP56F803EVM User Manual, Rev. 5

Motor Protection Logic

2.14.1 UNI-3 Motor Protection Logic

The UNI-3 DC Bus Over-Voltage signal is connected to the controller’s PWM group’s fault
input, FAULT0. The UNI-3 DC Bus Over-Current signal is connected to the device’s PWM
group’s fault input, FAULT1. Additionally, the UNI-3 DC Bus Over-Voltage and Over-Current
analog signals are connected to two A/D inputs, AN0 and AN1, respectively. Figure 2-11
contains the diagram of the DC Bus Over-Voltage and DC Bus Over-Current circuit for the
UNI-3 interface.

DC BUS VOLTAGE SENSE

V_sense_DCB

+3.3V

+5.0V

+5.0V

+

–

LM393

FAU LT0

DC BUS CURRENT SENSE

I_sense_DCB

+3.3V

+5.0V

+5.0V

+

–

LM393

FAU LT1

Figure 2-11. DC Bus Over-Voltage and Over-Current Detection Schematic Diagram

Freescale Semiconductor 2-15

Technical Summary, Rev. 5

2.15 Back-EMF and Motor Phase Current Sensing

The UNI-3 connector supplies Back-EMF and Motor Phase Current signals from the three
phases of a motor attached to a motor drive unit. The Back-EMF signals on the UNI-3
connectors are derived from a resistor divider network contained in the motor drive unit.
These resistors divide down the attached motor’s Back-EMF voltages to a 0 to +3.3V
level. In certain instances, the Back-EMF signals can exceed this maximum range. The
Motor Phase Current signals are derived from current sense resistors. Both of these signal
groups are then routed to a group of header pins that allow the end user to select which
signal group the device’s A/D will monitor. Refer to Figure 2-12 for the design of a single
channel.

JG6

BACK_EMF_A

PHASE_A_I_SENSE

1

2

3

AN2

Figure 2-12. Primary Back-EMF or Motor Phase Current Sense Signals

2-16 Freescale Semiconductor 

DSP56F803EVM User Manual, Rev. 5

Zero-Crossing Detection

2.16 Quadrature Encoder/Hall-Effect Interface

The 56F803EVM board contains a Quadrature Encoder/Hall-Effect interface connected to the
device’s Quad Encoder input port. The circuit is designed to accept +3.0V to +5.0V encoder or
Hall-Effect sensor inputs. Input noise filtering is supplied on the input path for the Quadrature
Encoder/Hall-Effect interface, along with additional noise rejection circuitry inside the
controller. Figure 2-13 shows the encoder interface.

2.17 Zero-Crossing Detection

An attached UNI-3 motor drive board contains logic that can send out pulses when the phase
voltage of an attached 3-phase motor drops to zero. The motor drive board circuits generate a 0 to
+3.3V DC pulse via voltage comparators. The resulting pulse signals are sent to a set of jumper
blocks shared with the Encoder/Hall-Effect interface. The jumper blocks allow the selection of
Zero-Crossing signals or Quadrature Encoder/Hall-Effect signals. When in operation, the
controller will only monitor one set of signals, either the Encoder/Hall-Effect or the
Zero-Crossing. Figure 2-13 shows the Zero-Crossing and Encoder/Hall circuits.

ZERO_X_A

ZERO_X_B

ZERO_X_C

+5.0V

J2

1
2
3
4
5
6

PIN 1: +5.0V
PIN 2: GROUND
PIN 3: PHASE A
PIN 4: PHASE B
PIN 5: INDEX
PIN 6: HOME

JG7

1

3

FILTER

FILTER

FILTER

FILTER

4

6

7

9

Figure 2-13. Zero-Crossing Encoder Interface

56F803

2

5

8

PHASEA

PHASEB

INDEX

HOME

Freescale Semiconductor 2-17

Technical Summary, Rev. 5

2.18 CAN Interface

The 56F803EVM board contains a CAN physical-layer interface chip that is attached to the
MSCAN_RX and MSCAN_TX pins on the 56F803. The EVM board uses a Philips,
PCA82C250, high speed, 1Mbps, physical layer interface chip. Due to the +5.0V operating
voltage of the CAN chip, a pull-up to +5.0V is required to level shift the Transmit Data output
line from the 56F803. A primary, J3, and a daisy-chain, J13, CAN connector are provided to
allow easy daisy-chaining of CAN devices. Refer to Figure 2-14 for a connection diagram and to

Table 2-8 for the CAN signals.

CAN CONNECTOR

J3

X

56F803

MSCAN_TX

MSCAN_RX

1

TXD

4

RXD

8

SLOPE

PCA82C250T

U15

VCC

VREF

CANH

CANL

GND

1
3

+5.0V

3
5

7
6

2

120

5

X

7
9

X

JG10

2

CAN TERMINATION

X

2
4

X

6

X

8

X

10

1

Figure 2-14. CAN Interface

J13
1

X

X
X

2

3

4

5

6

7

8

9

10

DAISY-CHAIN

CAN CONNECTOR

X

X
X
X

2-18 Freescale Semiconductor 

DSP56F803EVM User Manual, Rev. 5

Peripheral Connectors

Table 2-8. CAN Header Description

J3 and J13

Pin # Signal Pin # Signal

1NC2NC

3 CANL 4 CANH

5 GND 6 NC

7NC8NC

9NC10NC

2.19 Peripheral Connectors

The EVM board contains a group of Peripheral Expansion Connectors used to gain access
to the resources of the 56F803. The following signal groups have Expansion Connectors:

• External Memory Control

• Encoder/Timer Channel

• Timer Channel

• Address Bus

• Data Bus

• A/D Input Port

• Serial Communications Port

• Serial Peripheral Interface Port

• CAN Port

• PWM Port

Freescale Semiconductor 2-19

Technical Summary, Rev. 5

2.19.1 External Memory Control Signal Expansion Connector

The External Memory Control Signal connector contains the device’s external memory control
signal lines. See Table 2-9 for the names of these signals.

Table 2-9. External Memory Control Signal Connector Description

J8

Pin # Signal Pin # Signal

1RD

3WR4IRQB

5PS6 RESET

7DS8NC

9CLKO10 DE

11 GND 12 +3.3V

2IRQA

2.19.2 Encoder/Timer Channel Expansion Connector

The Encoder/Timer Channel port is an MPIO port attached to the Timer expansion connector.
The port can act as a Quadrature Decoder interface port or as a general purpose Timer port. Refer
to Table 2-10 for the signals attached to the connector.

Table 2-10. Timer Connector Description

J2

2-20 Freescale Semiconductor 

Pin # Signal

1 +5.0V

2 GND

3PhaseA

4PhaseB

5INDEX

6 HOME

DSP56F803EVM User Manual, Rev. 5

Peripheral Connectors

2.19.3 Timer Channel Expansion Connector

The Timer Channel port is a GPIO timer port attached to the Timer D expansion connector. See

Table 2-11 for the signals attached to the connector.

Table 2-11. Timer D Connector Description

J10

Pin # Signal

1 TD1

2 TD2

3 GND

4 +3.3V

2.19.4 Address Bus Expansion Connector

The 16-bit Address bus connector contains the controller’s external memory address signal lines.
The upper 8 bits, A8 - A15, can also be used as Port A GPIO lines. See Table 2-12 for the
Address bus connector information.

Table 2-12. External Memory Address Bus Connector Description

J7

Pin # Signal Pin # Signal

1A02A1

3A24A3

5A46A5

7A68A7

9A810A9

11 A10 12 A11

Freescale Semiconductor 2-21

13 A12 14 A13

15 A14 16 A15

17 GND 18 +3.3V

Technical Summary, Rev. 5

2.19.5 Data Bus Expansion Connector

The 16-bit Data bus connector contains the controller’s external memory data signal lines. Refer
to Table 2-13 for the Data bus connector information.

Table 2-13. External Memory Address Bus Connector Description

J11

Pin # Signal Pin # Signal

1D02D1

3D24D3

5D46D5

7D68D7

9D810D9

11 D10 12 D11

13 D12 14 D13

15 D14 16 D15

17 GND 18 +3.3V

2-22 Freescale Semiconductor 

DSP56F803EVM User Manual, Rev. 5

Peripheral Connectors

2.19.6 A/D Port Expansion Connector

The 8-channel Analog-to-Digital conversion port is attached to this connector. See Table 2-14 for
connection information.

Table 2-14. A/D Connector Description

J9

Pin # Signal

1 AN0

2 AN1

3 AN2

4 AN3

5 AN4

6 AN5

7 AN6

8 AN7

9 GNDA

10 +3.3VA

2.19.7 Serial Communications Port Expansion Connector

The Serial Communications Port, SCI, is attached to this connector. Refer to Table 2-15 for
connection information.

Table 2-15. SCI Connector Description

J12

Pin # Signal

1 TXD

Freescale Semiconductor 2-23

2 RXD

3 GND

Technical Summary, Rev. 5

2.19.8 Serial Peripheral Interface Expansion Connector

The Serial Peripheral Interface, SPI, is attached to this connector. See Table 2-16 for connection
information.

Table 2-16. SPI Connector Description

J6

Pin # Signal Pin # Signal

1 SCLK 2 MOSI

3MISO4 SS

5 GND 6 +3.3V

2.19.9 CAN Expansion Connector

The CAN port is attached to this connector. Refer to Table 2-17 for connection information.

Table 2-17. CAN Connector Description

J5

Pin # Signal

1 MSCAN_TX

2 MSCAN_RX

3 GND

2-24 Freescale Semiconductor 

DSP56F803EVM User Manual, Rev. 5

Test Points

2.19.10 PWM Port Expansion Connector

The PWM port is attached to this connector. Refer to Table 2-18 for connection information.

Table 2-18. PWM Port Connector Description

J4

Pin # Signal Pin # Signal

1 ISA0 2 ISA1

3 ISA2 4 FAULT0

5 FAULT1 6 FAULT2

7 PWM0 8 PWM1

9 PWM2 10 PWM3

11 PWM4 12 PWM5

13 GND 14 +3.3V

2.20 Test Points

The 56F803EVM board has nine test points: Five near the breadboard, (+3.3V, GND, +3.3VA,
AGND and +5.0V), and four near the UNI-3 connector, (-15VA, GND, +15VA and GND).

Freescale Semiconductor 2-25

Technical Summary, Rev. 5

2-26 Freescale Semiconductor 

DSP56F803EVM User Manual, Rev. 5

Appendix A
56F803EVM Schematics

Freescale Semiconductor Appendix A-1

56F803EVM Schematics, Rev. 5

5

5

4

4

3

3

2

2

1

1

DDC

C

B

B

A

A

JTAG

DSP56803 Pro

cessor

B

DSP56803

EVM.DSN

Monday, June

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Development

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14

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Title

Size

Docu

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Nu

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Date

:

Design

er:

Re

v.

Shee

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of

A0A1A2A3A4A5A6A7A8A9A10

A11

A12

A13

A14

A15D0D1D2D3D4D5D6D7D8D9

D10

D11

D12

D13

D14

D15

A[0..15]

D[0..15]

XTAL

RXD

MSCAN_RX

TD1

TD2

TXD

CLKO

EXTAL

MSCAN_TX

PHASEA

PHASEB

INDEX

HOME

AN0

AN4

AN5

AN6

AN7

AN1

PWM1

PWM2

PWM5

IS1

IS0

IS2

FAULT0

FAULT1

FAULT2

PWM0

PWM4

PWM3

AN2

TDO

TCK

TMS

TDI

/TRST

/DE

AN3

/PS

/DS

/WR

/RD

/IRQA

/IRQB

/RESET

EXTBOOT

MISO

SCLK

MOSI

/SS

+3.3V

+3.3VA

C2

2.2uF

50VDC

C1

2.2uF

50VDC

U1

DSP56F803BU80

A07A110A211A312A413A514A6/PE215A7/PE316A8/A017A9/A118A10/A219A11/A320A12/A421A13/A522A14/A626A15/A727D089D190D291D394D495D596D697D798D899D9

100

D101D112D123D134D145D156VSS93VSS67VSS63VSS28VSS

9

VDD92VDD66VDD61VDD23VDD

8

VSSA

59

VDDA

62

VCAPC88VCAPC

39

VRH

48

AN049AN150AN251AN352AN453AN554AN655AN7

56

PWMA070PWMA171PWMA272PWMA373PWMA474PWMA5

75

ISA040ISA141ISA2

42

FAULTA043FAULTA145FAULTA2

47

PS24RS25WR29RD30IRQA31IRQB32RESET79EXTBOOT78CLK081XTAL57EXTAL

58

TCK

34

TMS

35

TDI36TDO

37

TRST

38

PHASEA0/TA0

64

PHASEB0/TA1

65

INDEX0/TA2

68

HOME0/TA3

69

TD182TD2

83

TXD0/PE0

76

RXD0/PE1

77

MOSI/PE586MISO/PE6

85

SCLK/PE4

87

SS/PE7

84

TCS

33

MSCAN_TX

44

MSCAN_RX

46

VDDA

60

DE

80

PFC INHIBIT

BRAKE CONTROL

serial_com

USER LED 0

ENCODER / HALL EFFECT INPUT

RS-232

PFC PWM

PFC ZERO CROSSING

CAN

PULSE WIDTH MODULATION

PHASE CURRENT SENSE

BACK EMF PHASE C

BACK EMF PHASE A

BACK EMF PHASE B

PHASE A CURRENT

PHASE B CURRENT

PHASE C CURRENT

DRIVE TEMPERATURE

DC BUS OVERVOLTAGE

DC BUS OVERCURRENT

DC BUS OVERVOLTAGE FAULT

DC BUS OVERCURRENT FAULT

START / STOP

+

+

Figure A-1. 56F803 Processor

Appendix A-2 Freescale Semiconductor 

DSP56F803EVM User Manual, Rev. 5

5

5

4

4

3

3

2

2

1

1DDCC

BBA

A

BOOT MODE JU

MPER

IRQA PUSHBUTTON

RES

ET, MODES, CLOCK, IRQS

A

DSP56803EVM.DSN

Monday, July 10, 2000

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Title

Size

Doc

ument

Num

ber

Date:

Designer

:

Rev

.

Sheet

of

EXT

AL

/RESET

/IRQA

/IRQB

EXTB

OOT

XT

AL

+3.3V

+3.3V

+3.3V

S2

S4

Y1

8.00MHz

R20

10K

C36

0.1uF

S3

JG4

1

2

R17

10

M

R16

10K

R18

10K

C39

0.1uF

JG3

123

JG9

1

2

OSC BYPASS

IRQB PUSHBUTTON

NC

EXT BOOT

INT BOOT 1 - 2

RESET PUSHBUTTON

Figure A-2. Reset, Mode, Clock & IRQsL

Freescale Semiconductor Appendix A-3

56F803EVM Schematics, Rev. 5

5

5

443

3

2

2

1

1DDCC

BBA

A

64Kx16-bit Program and 64Kx16-bit Data Memory

SRAM ENABLE JUMPE

R

PR

OGRAM and DATA SRAM MEMORY

A

DSP56803EVM.DSN

Monday, June 22, 1998

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Date:

Designer

:

Rev

.

Sheet

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D2D5D13D4D0D6D15

D11D3D10D1D7

D12D9D8

D14

A15

A11A1A12

A10A3A14A5A9A6A8A0A7

A13A2A4

/RD

/WR

D[0..15]

A[0..15]

/PS

+3.3V

+3.3V

JG5

1

2

U2

GS72116TP-12

DQ17DQ2

8A41

DQ39DQ4

10A32

DQ513DQ6

14A23

DQ715DQ8

16A14

DQ9

29

DQ10

30A05

DQ1131DQ12

32

A15

18

DQ1335DQ14

36

A14

19

DQ1537DQ16

38

A1320A1221A1124A1025A926A827A742A643A544UB40LB39OE41WE17CE6A16

22

VSS34VSS

12

VDD33VDD

11

R21

10K

R67

10K

R66

10K

Figure A-3. Program & Data SRAM Memory

NCSRAM DISABLE

1 - 2SRAM ENABLE

JUMPER

OPTION

DSP56F803EVM User Manual, Rev. 5

Appendix A-4 Freescale Semiconductor 

5

5

4

4

3

3

2

2

1

1

DDC

C

BBA

A

SCI

RS-232 A

ND SCI CONNECTORS

A

DSP56803EVM.DSN

Monday, June 22, 1998

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Doc

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Date:

Designer

:

Rev

.

Sheet

of

R2IN

R3IN

R2IN

R3IN

R4IN

R5IN

T2IN

T3IN

T2IN

T3IN

/EN

/EN

R5IN

R4IN

TX

D

RXD

+3.3V

R281KR221KR231KR24

1K

P4

DB9S

594837261

C43

0.1uF

C41

0.1uF

R251KR27

1K

C40

0.1uF

C42

0.1uF

R26

1K

C44

0.1uF

U3

ADM3311EARS

V+1C2+2VCC3C2-4EN5C1+6T1IN7T2IN8T3IN9R1OUT

10

R2OUT

11

R3OUT

12

R4OUT

13

R5OUT

14

R5IN15R4IN16R3IN17R2IN18R1IN

19

T3OUT

20

T2OUT

21

T1OUT

22

SD

23

C1-

24V-25

C3-

26

GND

27

C3+

28

R68

1K

TP791TP80

1

TP811TP821TP831TP85

1

RS-232

CONNECTOR

2: TXD

3: RXD

Freescale Semiconductor Appendix A-5

Figure A-4. RS-232 and SCI Connectors

56F803EVM Schematics, Rev. 5

5

5

443

3

2

2

1

1DDCC

BBA

A

LEDS

DSP56803 PWM LEDS AND USER LE

D

A

DSP56803EVM.DSN

Monday, June 22, 1998

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Date:

Designer

:

Rev

.

Sheet

of

PWM1PWM0PWM

2

MOSI

PWM4PWM5PWM

3

+3.3V

+3.3V

R29

270

R30

270

R31

270

R33

270

R32

270

R34

270

R35

270

U10C

74AC04

5

6

U10A

74AC04

1

2

U10B

74AC04

3

4

U10D

74AC04

9

8

U10F

74AC04

13

12

U10E

74AC04

11

10

U12A

74AC04

1

2

LED2

YELLOW LED

LED3

GREEN

LED

LED4

YELLOW LED

LED5

GREEN

LED

LED6

YELLOW LED

LED7

GREEN

LED

LED8

GREEN

LED

PWM STATE

USER LED

Figure A-5. 56F803 PWM LEDs and User LED

Appendix A-6 Freescale Semiconductor 

USER LED

DSP56F803EVM User Manual, Rev. 5

5

5

4

4

3

3

2

2

1

1

DDC

C

B

B

A

A

DSP PWM

UNI-3 OVER VOLTAGE AND CU

RRENT SENSE

B

DSP56803

EVM.DSN

Monday, June

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Docu

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Date

:

Design

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Re

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AN0

FAULT1

FAULT0

AN1

+3.3V

+3.3V

+5.0V

+5.0V

+5.0V

+5.0V

R44

5.1K

R43

1M

U14A

LM393A

3

2

1

C45

0.1uF

R42

16K

R41

16K

R39

5.1K

C46

0.1uF

U14B

LM393A

5

6

7

R38

1M

R37

16K

R36

16K

R40

R45

FAULT SENSE 0

DSP PWM

FAULT SENSE 1

FAULT DETECTION

UNI-3 OVER-VOLTAGE

8

4

+

-

10K

V_S_DCB

VOLTAGE SENSE

FAULT DETECTION

UNI-3 OVER-CURRENT

8

4

+

-

10K

I_S_DCB

CURRENT SENSE

Figure A-6. UNI-3 Over-Voltage and Current Sense

Freescale Semiconductor Appendix A-7

56F803EVM Schematics, Rev. 5

5

5

443

3

2

2

1

1DDCC

BBA

A

CONNE

CT

1-2: ZERO CROSSING

ZERO CROSSING, ENCODER, HAL

L EFFECT SELECTION

A

DSP56803EVM.DSN

Monday, June 22, 1998

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HOME

ZERO_X_C

ZERO_X_B

ZERO_X_A

PHASEB

INDEX

PHASEA

+5.0V

+5.0V

+5.0V

+5.0V

+5.0V

R55

1K

R56

24

C52

470pF

R57

24

JG7A

123

R52

1K

R53

24

R54

24

R49

1K

R50

24

R51

24

C51

470pF

R48

24

C49

470pF

R46

1K

C50

470pF

J2

12345

6

C47

0.1uF

C48

2.2uF

50VDC

R47

24

JG7B

456

JG7C

789

INFORMATION

2-3: ENCODER / HALL

EFFECT INFORMATION

UNI-3: ZERO CROSSING

Appendix A-8 Freescale Semiconductor 

+

ENCODER /

HALL

DSP56F803EVM User Manual, Rev. 5

EFFECT

CONNECTOR

PIN 1: +5.0V

PIN 3: PHASE A

PIN 4: PHASE B

PIN 2: GROUND

PIN 5: INDEX

PIN 6: HOME

Figure A-7. Zero-Crossing/ Encoder or Hall-Effect Selection

5

5

4

4

3

3

2

2

1

1

DDC

C

BBA

A

DAISY-CHAIN

HIGH SPEED CAN IN

TERFACE

A

DSP56803EVM.DSN

Wednesday, July 05, 2000

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:

Rev

.

Sheet

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CANL

CANH

CANL

CANH

CANH

CANL

MSCAN_T

X

MSCAN_RX

+5.0V

+5.0V

J3

123456789

10

R58

1K

U15

PCA82C250T

TX

D

1

RXD

4

GND2VCC

3

VREF5CANL6CANH

7

SLOPE

8

J13

123456789

10

JG10

1

2

R61

120

1/4W

TP86

1

CAN BUS CONNECTOR

CAN BUS CONNECTOR

Figure A-8. High Speed CAN Interface

Freescale Semiconductor Appendix A-9

56F803EVM Schematics, Rev. 5

5

5

4

4

3

3

2

2

1

1

DDC

C

B

B

A

A

ADDRESS BUS CONNECTOR 0-15

PORT TIMER D, ADDRESS, DATA, A/D AND CONTROL

LINES CONNECTORS

B

DSP56803

EVM.DSN

Monday, June

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Title

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Docu

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Nu

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Date

:

Design

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Re

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Shee

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A0A2A4A6A8

A10

A12

A14

A1A3A5A7A9

A11

A13

A15

D0D2D4D6D8

D10

D12

D14

D1D3D5D7D9

D11

D13

D15

/DS

/IRQB

/RESET

/IRQA

/WR

/RD

/PS

CLKO

TD2

TD1

/DE

AN1

AN3

AN5

A[0..15]

A[0..15]

D[0..15]

D[0..15]

MOSI

/SS

SCLK

MISO

MSCAN_TX

MSCAN_RX

TXD

RXD

IS0

IS2

FAULT1

PWM4

PWM0

PWM2

IS1

FAULT0

FAULT2

PWM1

PWM5

PWM3

AN0

AN2

AN4

AN6

AN7

+3.3V

+3.3V

+3.3V

+3.3V

+3.3V

+3.3V

+3.3VA

J101234

J7

1234567891011121314151617

18

J5

123

J11

123456789101112131415161718J12

J8

1234567891011

12

J6

12345

6

J41357911

13

246

8

101214

J913579246

8

10

PWM PORT

DATA BUS CONNECTOR 0-15

PORT PA:0-7 SHARE ADDRESS BUS PINS A:8-15

3
2
1

SCI

DSP A/D PORT

RAW SIGNALS

RAW CAN

SIGNAL

CONNECTOR

Appendix A-10 Freescale Semiconductor 

CONTROL LINES

TIMER CHANNEL D

DSP56F803EVM User Manual, Rev. 5

Figure A-9. Port Timer D, Address, Data, A/D and Control Line Connectors

SPI PORT

5

5

4

4

3

3

2

2

1

1

DDC

C

B

B

A

A

UNI-3 INTERFACE AND GPENERAL P

URPOSE SWITCHES

B

DSP56803

EVM.DSN

Monday, June

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Date

:

Design

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Re

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PFC_PWM

SERIAL_COM

PFC_INHIBIT

PFC_ZERO_CROSS

PFC_PWM

SERIAL_COM

PFC_INHIBIT

PFC_ZERO_CROSS

UNI_3_-15

UNI_3_+15

UNI_3_+15

UNI_3_-15

PWM0

PWM1

PWM2

PWM3

PWM4

PWM5

AN0

AN1

U3_PHB_IS

ZERO_X_A

ZERO_X_B

ZERO_X_C

BK_EMF_A

BK_EMF_B

BK_EMF_C

/SS

SCLK

U3_PHA_IS

TD1

TD2

MISO

AN5

U3_PHC_IS

AN7

+5.0V_UNI3

+5.0V_UNI3

+3.3VA

+3.3VAR110K

JG1

1234567

8

P1

123456789101112131415161718192021222324252627282930313233343536373839

40

S1

SW SPST

TP6

TP7

R9

1K

TP8

1

TP9

+15VA GND

1

TEST POINTS

GND-15VA

1

1

PHASE C BACK EMF

PHASE A BACK EMF

MOTOR DRIVE TEMPERATURE SENSE

MOT OR PHASE B CURRENT SENSE

RUN / STOP SWITCH

RUN/STOP

CROSSING JUMPER

JUMPER

PFC ZERO

PFC PWM

UNI-3 CONNECTOR

PWM_AT

PWM_AB

PWM_BT

PWM_BB

Freescale Semiconductor Appendix A-11

PWM_CT

PWM_CB

V_S_DCB I_S_DCB

MOT OR PHASE A CURRENT SENSE

PHASE B BACK EMF

MOT OR PHASE C CURRENT SENSE

MOTOR DRIVE BRAKE CONTROL

56F803EVM Schematics, Rev. 5

Figure A-10. UNI-3 Interface and General Purpose Switches

COM JUMPER

PFC INHIBIT JUMPER

UNI-3 SERIAL

DSP56F803EVM User Manual, Rev. 5

5

5

4

4

3

3

2

2

1

1

DDC

C

BBA

A

BACK-EMF AND PHASE CURRENT SENSE ANALOG INPUT

SELECTORS

A

DSP56803EVM.DSN

Monday, June 22, 1998

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Num

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Date:

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:

Rev

.

Sheet

of

BK_EMF_A

AN2

U3_PHA_IS

BK_EMF_C

AN4

U3_PHC_IS

AN3

BK_EMF_B

U3_PHB_IS

JG6A

123

JG6B

456

JG6C

789

Appendix A-12 Freescale Semiconductor 

Figure A-11. Back-EMF and Phase Current Sense Analog Input Selectors

5

5

4

4

3

3

2

2

1

1

DDC

C

B

B

A

A

On-Board

PARALLEL JTAG HOST TARGET INTERFAC

E AND JTAG CONNECTOR

B

DSP56803

EVM.DSN

Monday, June

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Date

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Design

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Re

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PORT_TDO

PORT_CONNECT

PORT_RESET

PORT_TMS

PORT_TCK

PORT_IDENT

PORT_TDI

/PORT_TRST

/RESET

TDO

TMS

TCK

TDI

P_RESET

/TRST

P_RESET

/TRST

TDO

PORT_VCC

TMS

TCK

TDI

TDO

/RESET

/TRST

+3.3V

+3.3V

+3.3V

+3.3V

+3.3V

+3.3V

P2

DB25M

132

15141641751861972082192210231124122513J1

12345678910111213

14

R351R4

51

U7

MC74HC244DW

1Y1181Y2161Y3141Y4122Y192Y2

7

2Y352Y432G191G11A121A241A361A482A1112A2

13

2A3152A4

17

VCC20GND

10

U6

MC74HC244DW

1Y1181Y2161Y3141Y4122Y192Y2

7

2Y352Y4

3

2G191G

1

1A121A241A361A482A1112A2

13

2A3152A4

17

VCC20GND

10R25.1K

R7

5.1K

R6

5.1K

R5

5.1K

R8

10K

Q1

2N2222/TO

R60

5.1K

JG8

C3

0.1uF

R65

5.1K

R63

5.1K

R62

5.1K

R64

5.1K

JG2

1

2

TP46

1

TP47

1

Host Target

Interface

Disable

JTAG Connector

DSP /JTAG-RESET

On-Board

Host Target Interface

Power Source

3
2
1

KEY

Parallel JTAG Interface

DSP /RESET

Figure A-12. Parallel JTAG Host/Target Interface and JTAG Connector

56F803EVM Schematics, Rev. 5

Freescale Semiconductor Appendix A-13

5

5

4

4

3

3

2

2

1

1

DDC

C

B

B

A

A

POWER GOOD LED

POWER SUPPLIES +3.3V AND

+5.0V

B

DSP56803

EVM.DSN

Monday, June

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Date

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Re

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Shee

t

of

+5.0V

+3.3V

+3.3VA

+5.0V

+5.0V_UNI3

+3.3VA

+3.3V

+5.0V

+3.3V

U9

MC33269DT_3.3

VIN

3

VOUT2VOUT

4

GND

1

C7

0.1uFP31

2

R10

470

L2

FERRITE BEAD

L4

FERRITE BEAD

L1

FERRITE BEAD

U8

MC33269DT_5.0

VIN3VOUT2VOUT4GND

1

TP3

L3

FERRITE BEAD

C4

470uF

16VDC

TP5

TP1

C6

47uF

10VDC

C5

0.1uF

TP2

TP4

C8

47uF

10VDC

D2

FM4001

D1

FM4001

D3

FM4001

LED1

GREEN LED

+

+

4

123

REGULATOR

MC33269

3.3V AND 5.0V

+

3

INPUT 12V DC

EXTERNAL POWER IN

Appendix A-14 Freescale Semiconductor 

DSP56F803EVM User Manual, Rev. 5

Figure A-13. Power Supplies 3.3V and 5.0V

+3.3VA +3.3V +5.0V GND GNDA

1

1

1

1

1

NEAR THE BREADBOARD AREA

5

5

4

4

3

3

2

2

1

1

DDC

C

B

B

A

A

HEADER

BYPASS CAPACITORS AND SPARE G

ATES

B

DSP56803

EVM.DSN

Monday, June

22, 1998

Development

Tools

14

14

1.3

Wireless Subscriber Divisi

on

6501

William Cannon Drive West

Austin, TX

, 78735-8598

[phone] FAX: [phone]

MD:OE314

Title

Size

Docu

ment

Nu

mber

Date

:

Design

er:

Re

v.

Sheetof

+3.3V

+3.3V

+3.3V

+5.0V

+3.3V

+3.3VA

+3.3V

+3.3V

+5.0V

+3.3V

+3.3VA

+3.3V

+3.3V

+3.3V

+3.3V

+3.3V

+5.0V

+3.3VA

+3.3V

C19

0.1uF

C18

0.1uF

C17

0.1uF

C12

0.1uF

C14

0.1uF

C13

0.1uF

C33

0.01uF

C9

0.1uF

C10

0.1uF

C11

0.1uF

C30

0.1uF

C26

0.1uF

C31

0.1uF

C32

0.01uF

C25

1.0uF

50VDC

C24

0.1uF

R11

5.1K

C23

0.1uF

C27

0.01uF

U12B

74AC0434

C22

0.1uF

C15

0.1uF

C16

0.1uF

U12C

74AC0456

C20

0.1uF

U12D

74AC04

9

8

C21

0.1uF

U12E

74AC04

1110R12

5.1K

R13

5.1K

R14

5.1K

U12F

74AC041312

R59

5.1K

TP54

1

TP531TP56

1

TP551TP52

1

HEADER

CONTROL TIMER D

CAN

INTERFACE

DATA BUS

GS72116

UNI-3

+3.3 VA

UNI-3

+5.0 VOLT

DSP56F803

CONNECTOR CONNECTOR

ADDRESS BUS

LM393 74AC0474AC04ADM3311E 74HC244

A/D CONNECTOR

Figure A-14. Bypass Capacitors and Spare Gates

Freescale Semiconductor Appendix A-15

PWM

HEADER

56F803EVM Schematics, Rev. 5

Appendix A-16 Freescale Semiconductor 

DSP56F803EVM User Manual, Rev. 5

Appendix B
56F803EVM Bill of Material

Qty Description Ref. Designators Vendor Part #s

Integrated Circuits

1 DSP56F803BU80 U1 Freescale, DSP56F803BU80

1 GS72116TP-12 U2 GSI, GS72116TP-12

1 ADM3311EARS U3 Analog Devices, ADM3311EARS

2 MC74HC244DW U6, U7 ON Semiconductor, MC74HC244DW

1 MC33269DT-5.0 U8 ON Semiconductor, MC33269DT-5.0

1 MC33269DT-3.3 U9 ON Semiconductor, MC33269DT-3.3

2 74AC04SC U10, U12 Fairchild, 74AC04SC

1 LM393 U14 National Semiconductor, LM393

1 PCA82C250T U15 Philips Semiconductor, PCA82C250T

Resistors

4 16K : R36, R37, R41, R42 SMEC RC73L2A16KOHMJT

21M : R43, R38 SMEC RC73L2A1MOHMJT

16 5.1K : R2, R5 - R7, R11 - R14, R39,

R44, R59, R60, R62 - R65

8 10K : R1, R8, R16, R18, R20, R21,

R66, R67

251: R3, R4 SMEC RC73L2A51OHMJT

1 470 : R10 SMEC RC73L2A470OHMJT

1 10M : R17 SMEC RC73L2A10MOHMJT

14 1K : R9, R22 - R28, R46, R49, R52,

R55, R58, R68

56F803EVM Bill of Material, Rev. 5

SMEC RC73L2A5.1KOHMJT

SMEC RC73L2A10KOHMJT

SMEC RC73L2A1KOHMJT

Freescale Semiconductor Appendix B-1

Qty Description Ref. Designators Vendor Part #s

Resistors (Continued)

7 270 : R29 - R35 SMEC RC73L2A270OHMJT

824: R47, R48, R50, R51, R53, R54,

SMEC RC73L2A24OHMJT

R56, R57

1 120 :, 1/4W R61 YAGEO CFR 120QBK

Potentioneters

2 10K : R40, R45 BC/MEPCOPAL ST4B103CT

Inductors

4 1.0mH L1 - L4 Fair-Rite 2743015112

LEDs

5 Green LED LED1, LED3, LED5, LED7,

Hewlett-Packard HSMG-C650

LED8

3 Yellow LED LED2, LED4, LED6 Hewlett-Packard HSMY-C650

Diode

3 FM4001 D1, D2, D3 Vishay DL4001DICT

Capacitors

3 2.2PF, 50V DC C1, C2, C48 TTI UWX1H2R2MCR2GB

32 0.1PF C3, C5, C7, C9 - C24, C26,

SMEC MCCE104K2NR-T1

C30, C31, C35, C36,

C39 - C47

3 0.01PF C27, C32, C33 SMEC MCCE103K2NR-T1

1 470PF, 16V DC C4 PANASONIC ECE-V1CA471P

247PF, 10V DC C6, C8 PANASONIC ECE-V1AA470P

1 1.0PF, 50V DC C25 TTI UWT1H010MCR1GB

4 470pF C49 - C52 SMEC MCCE471J2NO-T1

Jumpers

43u 1 Bergstick JG3, JG8, J5, J12 SAMTEC TSW-103-07-S-S

14u 2 Bergstick JG1 SAMTEC TSW-104-07-S-D

51u 2 Bergstick JG2, JG4, JG5, JG9, JG10 SAMTEC TSW-102-07-S-S

DSP56F803EVM User Manual, Rev. 5

Appendix B-2 Freescale Semiconductor

Qty Description Ref. Designators Vendor Part #s

Jumpers (Continued)

2 3 x 3 Bergstick JG6, JG7 SAMTEC TSW-103-07-S-T

3 5 x 2 Bergstick J3, J9, J13 SAMTEC TSW-105-07-S-D

1 4 x 1 Bergstick J10 SAMTEC TSW-104-07-S-S

1 3 x 2 Bergstick J6 SAMTEC TSW-103-07-S-D

2 9 x 2 Bergstick J7, J11 SAMTEC TSW-109-07-S-D

2 7 x 2 Bergstick J1, J4 SAMTEC TSW-107-07-S-D

1 6 x 1 MTA J2 AMP MTA 640456-6

1 6 x 2 Bergstick J8 SAMTEC TSW-106-07-S-D

Test Points

91u 1 Bergstick TP1, TP2, TP3, TP4, TP5, TP6,

Samtec TSW-101-07-S-S

TP7, TP8, TP9

Crystals

1 8.00MHz Crystal Y1 ECS-80-18-5P

Connectors

1 20 x 2 Shrouded P1 3M 2540-6002UB

1 DB25M Connector P2 AMPHENOL 617-C025P-AJ121

1 2.1mm coax

P3 Switch Craft RAPC-722

Power Connector

1 DE9F Connector P4 AMPHENOL 617-C009S-AJ120

Switches

1 SPDT Toggle S1 C&K GT11MSCKE

3 SPST Pushbutton S2, S3, S4 Panasonic EVQ-QS205K

Transistors

1 2N2222A Q1 ZETEX FMMT2222ACT

11 Shunt SH1–SH11 Samtec SNT-100-BL-T

6 Rubber Feet RF1–RF6 3M SJ5018BLKC

Freescale Semiconductor Appendix B-3

Miscellaneous

56F803EVM Bill of Material, Rev. 5

Appendix B-4 Freescale Semiconductor

DSP56F803EVM User Manual, Rev. 5

INDEX

Symbols

+12VDC power supply 4

Numerics

4.0Amp power supply 11

56F803 Technical Data x
64Kx16-bit of data memory 1
64Kx16-bit of program memory 1

8.00MHz crystal oscillator 1

A

A/D ix
A/D Port 2
Analog-to Digital

A/D ix

B

Back-EMF

signals 16
voltages 16

Connector

A/D 23
Address bus 21
CAN 24
Data bus 22
Encoder/Timer Channel 20
External Memory Control 20
PWM 25
SCI 23
SPI 24
Timer Channel 21

Connectors

Peripheral Expansion 19

Controller Area Network

CAN ix

D

Data memory 4
Development Card 1
DSP56800 Family Manual x
DSP56F801/803/805/807 User’s Manual x

E

C

CAN ix

bus termination 1
bypass 1
interface 1

CAN in Automation

CiA ix

CAN interface 1
CAN physical layer peripheral 1
CAN Specification 2.0B x
CiA ix
CiA Draft Recommendation DR-303-1, Cabling and

Connector Pin Assignment x

Encoder/Hall-Effect

circuits 17
Encoder/Timer Channel 20
Evaluation Module

EVM ix
EVM ix
External Memory Control Signal 20
external memory expansion connectors 2
External Memory Interface

Schematic Diagram 4
external oscillator frequency input 1

Freescale Semiconductor Index - 1

Index, Rev. 5

F

M

FSRAM 1,4

G

General Purpose Input and Output Port

GPIO ix
GPIO ix
GPIO-compatible peripheral 1

,1,13,

21

H

Hall-Effect/Quadrature Encoder interface 1
Host Parallel Interface Connector 7
Host Target Interface 1

external 7

,

7

I

IC ix
Integrated Circuit

IC ix

J

Joint Test Action Group

JTAG ix
JTAG ix

JTAG port interface 1
Jumper Group 3

,

1

connector 7

JG1 3

JG10 3

JG2 3

JG3 3

JG4 3

JG5 3

JG6 3

JG7 3

JG8 3

JG9 3

MOSI 7
motor bus

over-current 1

over-voltage 1
MPIO ix
MPIO-compatible peripheral 1
Multi Purpose Input and Output Port

MPIO ix

O

On-board power regulation 2
OnCE ix
OnCE(TM) 1
On-Chip Emulation

OnCE ix

P

PCB ix
Phase Locked Loop

PLL ix
PLL ix
Printed Circuit Board

PCB ix
Program memory 4
Pulse Width Modulation

PWM ix
PWM ix

Group Interface and LEDs 14

group signals 14

LEDs 14

outputs 14

signals 14
PWM-compatible peripheral 1

Q

Quad Encoder 17
Quadrature Encoder/Hall-Effect 17

L

Logic

motor bus over-current 1
motor bus over-voltage 1
motor zero crossing 1

Low-Profile Quad Flat Pack

LQFP ix

LQFP ix

Index - 2 Freescale Semiconductor

DSP56F803EVM User Manual, Rev. 5

R

Z

RAM ix
Random Access Memory

RAM ix

Read Only Memory

ROM ix
real-time debugging 7
ROM ix
RS-232

cable connection 4

interface 5

Schematic Diagram 5
RS-232 interface 1

S

SCI ix

Serial Communications Port 23
SCI-compatible peripheral 1
Serial Communications Interface

SCI ix
Serial Peripheral Interface Port

SPI ix
SPI ix

Serial Peripheral Interface 24
SPI-compatible peripheral 1
SRAM ix

external data 1

external program 1
Static Random Access Memory

SRAM ix

Zero-Crossing

circuits 17

T

test points 25
Timer Channel 21
Timer compatible peripheral 1

U

UART ix
UNI-3

interface connector 14

Motor interface 2
UNI-3 connector/interface 12
Universal Asynchronous Receiver/Transmitter

UART ix

Freescale Semiconductor Index - 3

,

16

Index, Rev. 5

Index - 4 Freescale Semiconductor

DSP56F803EVM User Manual, Rev. 5

How to Reach Us:

Home Page:

www.freescale.com

E-mail:

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© Freescale Semiconductor, Inc. 2005. All rights reserved.

DSP56F803EVMUM
Rev. 5
07/2005