NXP Semiconductors 56F803, 56F800 User Manual

56F803

Evaluation Module User Manual

56F800
16-bit Digital Signal Controllers

DSP56F803EVMUM
Rev. 5
07/2005

freescale.com

TABLE OF CONTENTS

Preface vii

Audience . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vii

Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vii

Suggested Reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vii

Notation Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . viii

Definitions, Acronyms, and Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ix

References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . x

Chapter 1

Introduction

1.1 56F803EVM Architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2

1.2 56F803EVM Configuration Jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3

1.3 56F803EVM Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4

Chapter 2

Technical Summary

2.1 56F803. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2

2.2 Program and Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4

2.3 RS-232 Serial Communications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5

2.4 Clock Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6

2.5 Operating Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6

2.6 Debug LED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7

2.7 Debug Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7

2.7.1 JTAG Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7

2.7.2 Parallel JTAG Interface Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8

2.8 External Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10

2.9 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11

2.10 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11

2.11 UNI-3 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12

2.12 Run/Stop Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13

2.13 Motor Control PWM Signals and LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14

2.14 Motor Protection Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14

2.14.1 UNI-3 Motor Protection Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15

2.15 Back-EMF and Motor Phase Current Sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16

Freescale Semiconductor i

Table of Contents, Rev. 5

2.16 Quadrature Encoder/Hall-Effect Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17

2.17 Zero-Crossing Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17

2.18 CAN Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18

2.19 Peripheral Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19

2.19.1 External Memory Control Signal Expansion Connector . . . . . . . . . . . . . . . . . . . . . 2-20

2.19.2 Encoder/Timer Channel Expansion Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20

2.19.3 Timer Channel Expansion Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21

2.19.4 Address Bus Expansion Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21

2.19.5 Data Bus Expansion Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22

2.19.6 A/D Port Expansion Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-23

2.19.7 Serial Communications Port Expansion Connector . . . . . . . . . . . . . . . . . . . . . . . . 2-23

2.19.8 Serial Peripheral Interface Expansion Connector . . . . . . . . . . . . . . . . . . . . . . . . . . 2-24

2.19.9 CAN Expansion Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-24

2.19.10 PWM Port Expansion Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-25

2.20 Test Points. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-25

Appendix A

56F803EVM Schematics

Appendix B

56F803EVM Bill of Material

ii Freescale Semiconductor

DSP56F803EVM User Manual, Rev. 5

LIST OF FIGURES

1-1 Block Diagram of the 56F803EVM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2

1-2 56F803EVM Jumper Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3

1-3 Connecting the 56F803EVM Cables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4

2-1 Schematic Diagram of the External Memory Interface. . . . . . . . . . . . . . . . . . . . . . . 2-4

2-2 Schematic Diagram of the RS-232 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5

2-3 Schematic Diagram of the Clock Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6

2-4 Schematic Diagram of the Debug LED Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7

2-5 Block Diagram of the Parallel JTAG Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9

2-6 Schematic Diagram of the User Interrupt Interface. . . . . . . . . . . . . . . . . . . . . . . . . 2-10

2-7 Schematic Diagram of the RESET Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11

2-8 Schematic Diagram of the Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11

2-9 Run/Stop Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13

2-10 PWM Group Interface and LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14

2-11 DC Bus Over-Voltage and Over-Current Detection Schematic Diagram . . . . . . . . 2-15

2-12 Primary Back-EMF or Motor Phase Current Sense Signals . . . . . . . . . . . . . . . . . . 2-16

2-13 Zero-Crossing Encoder Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17

2-14 CAN Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18

A-1 56F803 Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-2

A-2 Reset, Mode, Clock & IRQsL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-3

A-3 Program & Data SRAM Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-4

A-4 RS-232 and SCI Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-5

A-5 56F803 PWM LEDs and User LED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-6

A-6 UNI-3 Over-Voltage and Current Sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-7

A-7 Zero-Crossing/ Encoder or Hall-Effect Selection . . . . . . . . . . . . . . . . . . . . . . . . A-8

A-8 High Speed CAN Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-9

A-9 Port Timer D, Address, Data, A/D and Control Line Connectors . . . . . . . . . . . A-10

A-10 UNI-3 Interface and General Purpose Switches . . . . . . . . . . . . . . . . . . . . . . . . A-11

Freescale Semiconductor iii

List of Figures, Rev. 5

A-11 Back-EMF and Phase Current Sense Analog Input Selectors . . . . . . . . . . . . . . A-12

A-12 Parallel JTAG Host/Target Interface and JTAG Connector . . . . . . . . . . . . . . . A-13

A-13 Power Supplies 3.3V and 5.0V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-14

A-14 Bypass Capacitors and Spare Gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-15

iv Freescale Semiconductor

DSP56F803EVM User Manual, Rev. 5

LIST OF TABLES

1-1 56F803EVM Default Jumper Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3

2-1 RS-232 Serial Connector Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5

2-2 Operating Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6

2-3 JTAG Connector Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8

2-4 Parallel JTAG Interface Disable Jumper Selection . . . . . . . . . . . . . . . . . . . . . . . 2-8

2-5 Parallel JTAG Interface Connector Description . . . . . . . . . . . . . . . . . . . . . . . . . 2-9

2-6 On-Board Host Target Interface Power Source Jumper Selection . . . . . . . . . . 2-10

2-7 UNI-3 Connector Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12

2-8 CAN Header Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19

2-9 External Memory Control Signal Connector Description . . . . . . . . . . . . . . . . . 2-20

2-10 Timer Connector Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20

2-11 Timer D Connector Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21

2-12 External Memory Address Bus Connector Description. . . . . . . . . . . . . . . . . . . 2-21

2-13 External Memory Address Bus Connector Description. . . . . . . . . . . . . . . . . . . 2-22

2-14 A/D Connector Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-23

2-15 SCI Connector Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-23

2-16 SPI Connector Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-24

2-17 CAN Connector Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-24

2-18 PWM Port Connector Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-25

Freescale Semiconductor v

List of Tables, Rev. 5

vi Freescale Semiconductor

DSP56F803EVM User Manual, Rev. 5

Preface

This reference manual describes in detail the hardware on the 56F803 Evaluation Module.

Audience

This document is intended for application developers who are creating software for
devices using the Freescale 56F803 part.

Organization

This manual is organized into two chapters and two appendixes.

• Chapter 1, Introduction - provides an overview of the 56F803EVM and its
features.

• Chapter 2, Technical Summary - describes in detail the 56F803EVM hardware.

• Appendix A, 56F803EVM Schematics - contains the schematics of the
56F803EVM.

• Appendix B, 56F803EVM Bill of Material - provides a list of the materials used
on the 56F803EVM board.

Suggested Reading

More documentation on the 56F803 and the 56F803EVM kit may be found at the URL:

Freescale Semiconductor vii

http://www.freescale.com

Preface, Rev. 5

Notation Conventions

This document uses the following conventions:

Term or Value Symbol Examples Exceptions

Active High Signals
(Logic One)

Active Low Signals
(Logic Zero)

Hexadecimal Values Begin with a “$”

Decimal Values No special symbol

Binary Values Begin with the letter

Numbers Considered positive

Bold Reference sources,

No special symbol
attached to the sig­nal name

Noted with an
overbar in text and in
most figures

symbol

attached to the
number

“b” attached to the
number

unless specifically
noted as a negative
value

paths, emphasis

A0
CLKO

WE
OE

$0FF0
$80

10
34

b1010
b0011

5

-10

...see:

www.freescale.com

In schematic drawings,
Active Low Signals may
be noted by a backslash:
/WE

Voltage is often shown
as positive: +3.3V

...

viii Freescale Semiconductor

DSP56F801EVM User Manual, Rev. 5

Definitions, Acronyms, and Abbreviations

Definitions, acronyms and abbreviations for terms used in this document are defined below for
reference.

A/D

CAN

CiA

EVM

GPIO

IC

JTAG

LQFP

MPIO

OnCE

PCB

PLL

TM

Analog-to-Digital

Controller Area Network; serial communications peripheral and method

CAN in Automation, an international CAN user’s group that coordinates
standards for CAN communications protocols

Evaluation Module

General Purpose Input and Output Port

Integrated Circuit

Joint Test Action Group, a bus protocol/interface used for test and debug

Low-profile Quad Flat Pack

Multi Purpose Input and Output Port; shares package pins with other
peripherals on the chip and can function as a GPIO

On-Chip Emulation, a debug bus and port created by Freescale to enable
designers to create a low-cost hardware interface for a professional
quality debug environment

Printed Circuit Board

Phase Locked Loop

PWM

RAM

ROM

SCI

SPI

Pulse Width Modulation

Random Access Memory

Read Only Memory

Serial Communications Interface

Serial Peripheral Interface Port

SRAM Static Random Access Memory

UART

Freescale Semiconductor ix

Universal Asynchronous Receiver/Transmitter

Preface, Rev. 5

References

The following sources were referenced to produce this manual:

[1] DSP56800 Family Manual, Freescale Semiconductor, DSP56800FM

[2] DSP56F801/803/805/807 User’s Manual, Freescale Semiconductor,

DSP56F801-7UM

[3] 56F803 Technical Data, Freescale Semiconductor, DSP56F803

[4] CiA Draft Recommendation DR-303-1, Cabling and Connector Pin Assignment,

Version 1.0, CAN in Automation

[5] CAN Specification 2.0B, BOSCH or CAN in Automation

x Freescale Semiconductor

DSP56F801EVM User Manual, Rev. 5

Chapter 1
Introduction

The 56F803EVM is used to demonstrate the abilities of the 56F803 and to provide a hardware
tool allowing the development of applications that use the 56F803.

The 56F803EVM is an evaluation module board that includes a 56F803 part, peripheral
expansion connectors, external memory, RS-232 interface and a CAN interface. The expansion
connectors are for signal monitoring and user feature expandability.

The 56F803EVM is designed for the following purposes:

• Allowing new users to become familiar with the features of the 56800 architecture. The
tools and examples provided with the 56F803EVM facilitate evaluation of the feature set
and the benefits of the family.

• Serving as a platform for real-time software development. The tool suite enables the user
to develop and simulate routines, download the software to on-chip or on-board RAM, run

TM

it, and debug it using a debugger via the JTAG/OnCE
the OnCE port enable the user to easily specify complex break conditions and to execute
user-developed software at full-speed, until the break conditions are satisfied. The ability
to examine and modify all user accessible registers, memory and peripherals through the
OnCE port greatly facilitates the task of the developer.

port. The breakpoint features of

• Serving as a platform for hardware development. The hardware platform enables the user
to connect external hardware peripherals. The on-board peripherals can be disabled,
providing the user with the ability to reassign any and all of the controller’s peripherals.
The OnCE port's unobtrusive design means that all of the memory on the board and on the
chip are available to the user.

Freescale Semiconductor 1-1

Introduction, Rev. 5

1.1 56F803EVM Architecture

The 56F803EVM facilitates the evaluation of various features present in the 56F803 part. The
56F803EVM can be used to develop real-time software and hardware products based on the
56F803. The 56F803EVM provides the features necessary for a user to write and debug
software, demonstrate the functionality of that software and interface with the customer's
application-specific device(s). The 56F803EVM is flexible enough to allow a user to fully
exploit the 56F803's features to optimize the performance of their product, as shown in

Figure 1-1.

56F803

Low Freq

Crystal

RESET

LOGIC

XTAL/EXTAL

RESET

DSub

25-Pin

MODE / IRQ

LOGIC

Program

Memory

64Kx16-bit

Data Memory

64Kx16-bit

Memory

Expansion

Connector(s)

JTAG

Connector

Parallel

JTAG Interface

RS-232

Interface

Peripheral
Expansion

Connector(s)

UNI-3

Power Supply

3.3V, 5V &

3.3VA

MODE / IRQ

Address,
Data &
Control

JTAG / OnCE

SCI

SPI

CAN

TIMER

GPIO

PWM

A / D

3.3 V & GND

Figure 1-1. Block Diagram of the 56F803EVM

DSub
9-Pin

CAN Interface

Debug LEDs

PWM LEDs

Over V Sense

Over I Sense

Zero Crossing

Detect

1-2 Freescale Semiconductor 

DSP56F803EVM User Manual, Rev. 5

56F803EVM Configuration Jumpers

1.2 56F803EVM Configuration Jumpers

Ten jumper groups, (JG1-JG10), shown in Figure 1-2, are used to configure various
features on the 56F803EVM board. Table 1-1 describes the default jumper group settings.

7

8

9

1

J9

JG9

JG2

U6

J4

DSP56F803EVM

1

JG4

JTAG

JG8

J1

U7

3

JG9

P3

JG6

2

1

3

3

12

JG6

P1

1

738

USER LED

789

2

9

PWM LEDs

LED3

9

7

8

JG1

1

2

7

8

JG7

JG7

132

JG5

P4

JG10

JG3

J3

J2

JG10

JG1

1

S2

J8

J10

Y1

1

JG3

1

U1

U15

S/N

S1

JG4

RUN/STOP

S4

S3

P2

IRQBIRQA

RESET

JG5

JG4

JG2

JG8

Figure 1-2. 56F803EVM Jumper Reference

Table 1-1. 56F803EVM Default Jumper Options

Jumper

Group

Comment

JG1 UNI-3 serial selected 1–2, 3–4, 5–6 & 7–8

JG2 Enable on-board Parallel JTAG Command Converter Interface NC

JG3 Use on-board crystal for oscillator input 1–2

JG4 Selects device’s Mode 0, BOOT From FLASH, operation upon exit from

reset

JG5 Enable external SRAM 1–2

JG6 UNI-3 3-Phase Current Source Selected 2–3, 5–6 & 8–9

Jumpers

Connections

1–2

JG7 Encoder Input Selected 2–3, 5–6 & 8–9

JG8 On-board Parallel JTAG Command Converter powered by Host System 1-2

JG9 Use on-board crystal for oscillator input 1–2

JG10 Leave CAN bus un-terminated NC

Freescale Semiconductor 1-3

Introduction, Rev. 5

1.3 56F803EVM Connections

An interconnection diagram is shown in Figure 1-3 for connecting the PC and the external +12V
DC power supply to the 56F803EVM board.

Parallel Extension

Cable

56F803EVM
PC-compatible
Computer

P2

Connect cable

to Parallel/Printer port

External

+12V

Power

P3

with 2.1mm,
receptacle
connector

Figure 1-3. Connecting the 56F803EVM Cables

Perform the following steps to connect the 56F803EVM cables:

1. Connect the parallel extension cable to the Parallel port of the host computer.

2. Connect the other end of the parallel extension cable to P2, shown in Figure 1-3, on the
56F803EVM board. This provides the connection which allows the host computer to
control the board.

3. Make sure that the external +12V DC, 4.0A power supply is not plugged into a +120V AC
power source.

4. Connect the 2.1mm output power plug from the external power supply into P3, shown in

Figure 1-3, on the 56F803EVM board.

5. Apply power to the external power supply. The green Power-On LED will illuminate
when power is correctly applied.

1-4 Freescale Semiconductor 

DSP56F803EVM User Manual, Rev. 5

Chapter 2
Technical Summary

The 56F803EVM is designed as a versatile controller development card for developing real-time
software and hardware products to support a new generation of applications in digital and
wireless messaging, servo and motor control, digital answering machines, feature phones,
modems, and digital cameras. The power of the 16-bit 56F803 controller, combined with the
on-board 64K u16-bit external program Static RAM (SRAM), 64K u16-bit external data
SRAM, CAN interface, Hall-Effect/Quadrature Encoder interface, motor zero crossing logic,
motor bus over-current logic, motor bus over-voltage logic and parallel JTAG interface, makes
the 56F803EVM ideal for developing and implementing many motor controlling algorithms, as
well as for learning the architecture and instruction set of the 56F803 processor.

The main features of the 56F803EVM include:

• 56F803 16-bit +3.3V controller operating at 80MHz [U1]

• External fast Static RAM (FSRAM) memory [U2], configured as:

— 64Ku16-bit of Program memory with 0 wait states at 70MHz

— 64Ku16-bit of Data memory with 0 wait states at 70MHz

• 8.00MHz crystal oscillator for device frequency generation [Y1]

• Optional external oscillator frequency input connector [JG3 and JG9]

• Joint Test Action Group (JTAG) port interface connector for an external debug Host
Target Interface [J1]

• On-board Parallel JTAG Host Target Interface, with a connector for a PC printer port
cable [P2]

• RS-232 interface for easy connection to a host processor [U3 and P4]

• CAN interface for high speed, 1.0Mbps, communications [U15 and J3]

• CAN bypass and bus termination [J13 and JG10]

• Connector to allow the user to connect his own SCI / GPIO-compatible peripheral [J12]

• Connector to allow the user to connect his own SPI / MPIO-compatible peripheral [J6]

• Connector to allow the user to connect his own PWM / GPIO-compatible peripheral [J4]

• Connector to allow the user to connect his own CAN physical layer peripheral [J5]

• Connector to allow the user to connect his own Timer / MPIO-compatible peripheral [J10]

Freescale Semiconductor 2-1

Technical Summary, Rev. 5

• Connector to allow the user to connect to the device’s A/D Port [J9]

• 56F803’s external memory expansion connectors [J7, J8 and J11]

• On-board power regulation from an external +12V DC-supplied power input [P3]

• Light Emitting Diode (LED) power indicator [LED1]

• Six on-board PWM monitoring LEDs [LED2-LED7]

• On-board real-time user debugging LED [LED8]

• UNI-3 Motor interface [P1]

— Encoder/Hall-Effect interface

— Over-Voltage sensing [U14]

— Over-Current sensing [U14]

— DC Bus Voltage sensing [U13]

— DC Bus Current sensing [U13]

— Back-EMF sensing

— Temperature sensing

— Zero Crossing detection

— Pulse Width Modulation

— Power Factor Correction (PFC) sensing

• Manual RESET push-button [S4]

• Manual interrupt push-button for IRQA

• Manual interrupt push-button for IRQB

[S2]

[S3]

• General purpose toggle switch for RUN/STOP control(AN7) [S1]

2.1 56F803

The 56F803EVM uses a Freescale DSP56F803BU80 part, designated as U1 on the board and in
the schematics. This part will operate at a maximum speed of 80MHz. A full description of the
56F803, including functionality and user information, is provided in the following documents:

• 56F803 Technical Data, (DSP56F803): Provides features list and specifications including
signal descriptions, DC power requirements, AC timing requirements and available
packaging.

2-2 Freescale Semiconductor 

DSP56F803EVM User Manual, Rev. 5

56F803

• DSP56F801/803/805/807 User’s Manual, (DSP56F801-7UM): Provides an overview
description of the controller and detailed information about the on-chip components
including the memory and I/O maps, peripheral functionality, and control/status register
descriptions for each subsystem.

• DSP56800 Family Manual, (DSP56800FM): Provides a detailed description of the core
processor including internal status and control registers and a detailed description of the
family instruction set.

These manuals contain detailed information about chip functionality and operation and can be
found at this URL:

http://www.freescale.com

Freescale Semiconductor 2-3

Technical Summary, Rev. 5

2.2 Program and Data Memory

The 56F803EVM uses one bank of 128Ku16-bit Fast Static RAM (GSI GS72116, labeled U2)
for external memory expansion; see the FSRAM schematic diagram in Figure 2-1. This physical
memory bank is split into two logical memory banks of 64Kx16-bits: one for Program memory
and the other for Data memory. By using the device’s program strobe, PS
the memory chip’s A0 signal line, half of the memory chip is selected when Program memory
accesses are requested and the other half of the memory chip is selected when Data memory
accesses are requested. This memory bank will operate with zero wait-state accesses while the
56F803 is running at 70MHz. However, when running at 80MHz, the memory bank operates
with four wait-state accesses. This memory bank can be disabled by removing the jumper at JG5.

, signal line along with

56F803

A0-A15

PS

D0-D15

RD

WR

Connect Pin 1-2:
Enable SRAM

Jumper Removed:
Disable SRAM

JG5

+3.3V

1

2

GS72116

A1-A16

A0

D0-D15

RD

WR

CS

Figure 2-1. Schematic Diagram of the External Memory Interface

2-4 Freescale Semiconductor 

DSP56F803EVM User Manual, Rev. 5

RS-232 Serial Communications

2.3 RS-232 Serial Communications

The 56F803EVM provides an RS-232 interface by the use of an RS-232 level converter,
(Analog Devices ADM3311EARS, designated as U3); refer to the RS-232 schematic
diagram in Figure 2-2. The RS-232 level converter transitions the SCI UART’s +3.3V
signal levels to RS-232 compatible signal levels and connects to the host’s serial port via
connector P4. Flow control is not provided, but could be implemented using uncommitted
GPIO signals. The pin-out of connector P4 is listed in Table 2-1.

RS-232

56F803

TXD0

RXD0 R1in

Level Interface

R1out

RS-232 DB9

1

6

T1outT1in

2

7

3
8

4
9

x

5

P4

Figure 2-2. Schematic Diagram of the RS-232 Interface

Table 2-1. RS-232 Serial Connector Description

P4

Pin # Signal Pin # Signal

1 Jumper to 6 & 4 6 Jumper to 1 & 4

2 TXD 7 Jumper to 8

3 RXD 8 Jumper to 7

4 Jumper to 1 & 6 9 N/C

5GND

Freescale Semiconductor 2-5

Technical Summary, Rev. 5