NXP Laboratories UK JN5148M4, JN5148M3, JN5148M0 chip manual

Data Sheet: JN5148-001 Preliminary

IEEE802.15.4 Wireless Microcontroller

Overview

The JN5148-001 is an ultra low power, high performance wireless microcontroller targeted at ZigBee PRO networking applications. The device features an enhanced 32-bit RISC processor offering high coding efficiency through variable width instructions, a multi-stage instruction pipeline and low power operation with programmable clock speeds. It also includes a 2.4GHz IEEE802.15.4 compliant transceiver, 128kB of ROM, 128kB of RAM, and a rich mix of analogue and digital peripherals. The large memory footprint allows the device to run both a network stack, e.g. ZigBee PRO, and an embedded application or in a co-processor mode. The operating current is below 18mA, allowing operation direct from a coin cell.

Enhanced peripherals include low power pulse counters running in sleep mode designed for pulse counting in AMR applications and a unique Time of Flight ranging engine, allowing accurate location services to be implemented on wireless sensor networks. It also includes a 4-wire I audio interface, to interface directly to mainstream audio CODECs, as well as conventional MCU peripherals.

Block Diagram

RAM

Time of Flight

Engine

2.4GHz Radio

XTAL

Watchdog

Timer

Power

Management

O-QPSK

Modem

IEEE802.15.4

MAC

Acceler ator

128-bi t AES Encryption Acceler ator

Benefits

• Single chip integrates

transceiver and microcontroller for wireless sensor networks

• Large memory footprint to

run ZigBee PRO together with an application

• Very low current solution for

long battery life

• Highly featured 32-bit RISC

CPU for high performance and low power

• System BOM is low in

component count and cost

• Extensive user peripherals

128kB

32-bit

RISC CPU

32-byte

OTP eFuse

ROM 128kB

SPI

2-Wir e Serial

Timer s UARTs

4-Wire Audio

Sleep Counters

12-bit ADC,

Comparators 12-bit DACs,

Temp Se n s or

Applications

• Robust and secure low power

wireless applications

• ZigBee PRO networks

• Smart metering

(e.g. AMR)

• Home and commercial building

automation

• Location Aware services – e.g.

Asset Tracking

• Industrial systems

• Telemetry

• Remote Control

• Toys and gaming peripherals

Features: Transceiver

• 2.4GHz IEEE802.15.4 compliant

• Time of Flight ranging engine

• 128-bit AES security processor

• MAC accelerator with packet

• 500 & 667kbps data rate modes

• Integrated sleep oscillator for low

• On chip power regulation for 2.0V

• Deep sleep current 100nA

• Sleep current with active sleep

• <$0.50 external component cost

• Rx current 17.5mA

• Tx current 15.0mA

• Receiver sensitivity -95dBm

• Transmit power 2.5dBm

Features: Microcontroller

• Low power 32-bit RISC CPU, 4 to

• Variable instruction width for high

• Multi-stage instruction pipeline

• 128kB ROM and 128kB RAM for

• JTAG debug interface

• 4-input 12-bit ADC, 2 12-bit

• 3 application timer/counters,

• 2 UARTs

• SPI port with 5 selects

• 2-wire serial interface

• 4-wire digital audio interface

• Watchdog timer

• Low power pulse counters

• Up to 21 DIO

Industrial temp (-40°C to +85°C) 8x8mm 56-lead Punched QFN

Lead-free and RoHS compliant

formatting, CRCs, address check, auto-acks, timers

power

to 3.6V battery operation

timer 1.25µA

32MHz clock speed

coding efficiency

bootloaded program code & data

DACs, 2 comparators

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Contents

1 Introduction 6

1.1 Wireless Transceiver 6

1.2 RISC CPU and Memory 6

1.3 Peripherals 7

1.4 Block Diagram 8

2 Pin Configurations 9

2.1 Pin Assignment 10

2.2 Pin Descriptions 12

2.2.1 Power Supplies 12

2.2.2 Reset 12

2.2.3 32MHz Oscillator 12

2.2.4 Radio 12

2.2.5 Analogue Peripherals 13

2.2.6 Digital Input/Output 13

3 CPU 15 4 Memory Organisation 16

4.1 ROM 16

4.2 RAM 17

4.3 OTP eFuse Memory 17

4.4 External Memory 17

4.4.1 External Memory Encryption 18

4.5 Peripherals 18

4.6 Unused Memory Addresses 18

5 System Clocks 19

5.1 16MHz System Clock 19

5.1.1 32MHz Oscillator 19

5.1.2 24MHz RC Oscillator 19

5.2 32kHz System Clock 20

5.2.1 32kHz RC Oscillator 20

5.2.2 32kHz Crystal Oscillator 20

5.2.3 32kHz External Clock 20

6 Reset 21

6.1 Internal Power-on Reset 21

6.2 External Reset 22

6.3 Software Reset 22

6.4 Brown-out Detect 23

6.5 Watchdog Timer 23

7 Interrupt System 24

7.1 System Calls 24

7.2 Processor Exceptions 24

7.2.1 Bus Error 24

7.2.2 Alignment 24

7.2.3 Illegal Instruction 24

7.2.4 Stack Overflow 24

7.3 Hardware Interrupts 25

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8 Wireless Transceiver 26

8.1 Radio 26

8.1.1 Radio External Components 27

8.1.2 . Antenna Diversity 27

8.2 Modem 29

8.3 Baseband Processor 29

8.3.1 Transmit 29

8.3.2 Reception 30

8.3.3 Auto Acknowledge 30

8.3.4 Beacon Generation 30

8.3.5 Security 30

8.4 Security Coprocessor 30

8.5 Location Awareness 31

8.6 Higher Data Rates 31

9 Digital Input/Output 32 10 Serial Peripheral Interface 33 11 Timers 36

11.1 Peripheral Timer/Counters 36

11.1.1 Pulse Width Modulation Mode 37

11.1.2 Capture Mode 37

11.1.3 Counter/Timer Mode 38

11.1.4 Delta-Sigma Mode 38

11.1.5 Example Timer / Counter Application 39

11.2 Tick Timer 39

11.3 Wakeup Timers 40

11.3.1 RC Oscillator Calibration 41

12 Pulse Counters 42 13 Serial Communications 43

13.1 Interrupts 44

13.2 UART Application 44

14 JTAG Debug Interface 45 15 Two-Wire Serial Interface 46

15.1 Connecting Devices 46

15.2 Clock Stretching 47

15.3 Master Two-wire Serial Interface 47

15.4 Slave Two-wire Serial Interface 48

16 Four-Wire Digital Audio Interface 49 17 Random Number Generator 51 18 Sample FIFO 52 19 Intelligent Peripheral Interface 53

19.1 Data Transfer Format 53

19.2 JN5148 (Slave) Initiated Data Transfer 54

19.3 Remote (Master) Processor Initiated Data Transfer 54

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20 Analogue Peripherals 56

20.1 Analogue to Digital Converter 57

20.1.1 Operation 57

20.1.2 Supply Monitor 58

20.1.3 Temperature Sensor 58

20.2 Digital to Analogue Converter 58

20.2.1 Operation 58

20.3 Comparators 59

21 Power Management and Sleep Modes 60

21.1 Operating Modes 60

21.1.1 Power Domains 60

21.2 Active Processing Mode 60

21.2.1 CPU Doze 60

21.3 Sleep Mode 60

21.3.1 Wakeup Timer Event 61

21.3.2 DIO Event 61

21.3.3 Comparator Event 61

21.3.4 Pulse Counter 61

21.4 Deep Sleep Mode 61

22 Electrical Characteristics 62

22.1 Maximum Ratings 62

22.2 DC Electrical Characteristics 62

22.2.1 Operating Conditions 62

22.2.2 DC Current Consumption 63

22.2.3 I/O Characteristics 64

22.3 AC Characteristics 64

22.3.1 Reset and Voltage Brown-Out 64

22.3.2 SPI MasterTiming 66

22.3.3 Intelligent Peripheral (SPI Slave) Timing 66

22.3.4 Two-wire Serial Interface 67

22.3.5 Four-Wire Digital Audio Interface 68

22.3.6 Wakeup and Boot Load Timings 68

22.3.7 Bandgap Reference 69

22.3.8 Analogue to Digital Converters 69

22.3.9 Digital to Analogue Converters 70

22.3.10 Comparators 71

22.3.11 32kHz RC Oscillator 71

22.3.12 32kHz Crystal Oscillator 72

22.3.13 32MHz Crystal Oscillator 72

22.3.14 24MHz RC Oscillator 73

22.3.15 Temperature Sensor 73

22.3.16 Radio Transceiver 74

Appendix A Mechanical and Ordering Information 79

A.1 56-pin QFN Package Drawing 79 A.2 PCB Decal 80 A.3 Ordering Information 81 A.4 Device Package Marking 82 A.5 Tape and Reel Information 83 A.5.1 Tape Orientation and Dimensions 83

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A.5.2 Reel Information: 180mm Reel 84 A.5.3 Reel Information: 330mm Reel 85 A.5.4 Dry Pack Requirement for Moisture Sensitive Material 85

Appendix B Development Support 86

B.1 Crystal Oscillators 86 B.1.1 Crystal Equivalent Circuit 86 B.1.2 Crystal Load Capacitance 86 B.1.3 Crystal ESR and Required Transconductance 87 B.2 32MHz Oscillator 88 B.3 32kHz Oscillator 90 B.4 JN5148 Module Reference Designs 92 B.4.1 Schematic Diagram 92 B.4.2 PCB Design and Reflow Profile 94 Related Documents 95 RoHS Compliance 95 Status Information 95 Disclaimers 96 Version Control 96 Contact Details 97

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1 Introduction

The JN5148-001 is an IEEE802.15.4 wireless microcontroller that provides a fully integrated solution for applications using the IEEE802.15.4 standard in the 2.4 - 2.5GHz ISM frequency band of the functionality required to meet the IEEE802.15.4 and ZigBee PRO specifications and has additional processor capability to run a wide range of applications including, but not limited to Smart Energy, Automatic Meter Reading, Remote Control, Home and Building Automation, Toys and Gaming.

Applications that transfer data wirelessly tend to be more complex than wired ones. Wireless protocols make stringent demands on frequencies, data formats, timing of data transfers, security and other issues. Application development must consider the requirements of the wireless network in addition to the product functionality and user interfaces. To minimise this complexity, Jennic provides a series of software libraries and interfaces that control the transceiver and peripherals of the JN5148. These libraries and interfaces remove the need for the developer to understand wireless protocols and greatly simplifies the programming complexities of power modes, interrupts and hardware functionality.

In view of the above, the register details of the JN5148 are not provided in the datasheet.

The device includes a Wireless Transceiver, RISC CPU, on chip memory and an extensive range of peripherals.

Hereafter, the JN5148-001 will be referred to as JN5148.

1.1 Wireless Transceiver

The Wireless Transceiver comprises a 2.45GHz radio, a modem, a baseband controller and a security coprocessor. In addition, the radio also provides an output to control transmit-receive switching of external devices such as power amplifiers allowing applications that require increased transmit power to be realised very easily. Appendix B.4, describes a complete reference design including Printed Circuit Board (PCB) design and Bill Of Materials (BOM).

The security coprocessor provides hardware-based 128-bit AES-CCM, CBC specified by the IEEE802.15.4 standard. It does this in-band on packets during transmission and reception, requiring minimal intervention from the CPU. It is also available for off-line use under software control for encrypting and decrypting packets generated by software layers such as ZigBee and user applications. This means that these algorithms can be off-loaded by the CPU, increasing the processor bandwidth available for user applications.

The transceiver elements (radio, modem and baseband) work together to provide IEEE802.15.4 Medium Access Control (MAC) under the control of a protocol stack. Applications incorporating IEEE802.15.4 functionality can be rapidly developed by combining user-developed application software with a protocol stack library.

(1) AES-CBC processing is only available off-line for use under software control.

[1], including ZigBee PRO. It includes all

(1)

, CTR and CCM* processing as

1.2 RISC CPU and Memory

A 32-bit RISC CPU allows software to be run on chip, its processing power being shared between the IEEE802.15.4 MAC protocol, other higher layer protocols and the user application. The JN5148 has a unified memory architecture, code memory, data memory, peripheral devices and I/O ports are organised within the same linear address space. The device contains 128kbytes of ROM, 128kbytes of RAM and a 32-byte One Time Programmable (OTP) eFuse memory.

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1.3 Peripherals

The following peripherals are available on chip:

• Master SPI port with five select outputs

• Two UARTs with support for hardware or software flow control

• Three programmable Timer/Counters – all three support Pulse Width Modulation (PWM) capability, two have

capture/compare facility

• Two programmable Sleep Timers and a Tick Timer

• Two-wire serial interface (compatible with SMbus and I

• Four-wire digital audio interface (compatible with I²S)

• Slave SPI port for Intelligent peripheral mode (shared with digital I/O)

• Twenty-one digital I/O lines (multiplexed with peripherals such as timers and UARTs)

• Four channel, 12-bit, Analogue to Digital converter

• Two 12-bit Digital to Analogue converters

• Two programmable analogue comparators

• Internal temperature sensor and battery monitor

• Time Of Flight ranging engine

• Two low power pulse counters

• Random number generator

• Watchdog Timer and Voltage Brown-out

• Sample FIFO for digital audio interface or ADC/DAC

• JTAG hardware debug port

User applications access the peripherals using the Integrated Peripherals API. This allows applications to use a tested and easily understood view of the peripherals allowing rapid system development.

C) supporting master and slave operation

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1.4 Block Diagram

VB_XX

VDD1 VDD2

RE SET N

XT A L_IN

XT A L_O UT

Tic k Tim e r

Programm able

Interrupt

Controller

From Pe r i p he r al s

RAM

128kB

32kHz

Os c

Supply Monitor

32-bit RISC CPU

ROM

128kB

Voltage

Regulators

Reset

Wakeup

Tim er0

Wakeup

Tim er1

32kHz Clock

Select

32kHz

Clock

Gen

32MHz Clock

Generator

OTP

eFuse

Cl oc k Divi de r

1.8V

Brow n-out

Detect

Wat chdog

Timer

32KIN

32KXTALIN 32KXTALOUT

Multiplier

Sample

FIFO

CPU and 16MHz

System Clock

24MHz

RC Osc

SPICLK SPIMOSI

SPI

Mas ter

UART0

UART1

Tim er0

Tim er1

Tim er2

2-wire

Interface

Intelligent Peripheral

Pulse

Counters

JTAG

Debug

Antenna

Diversity

4-wire Digital Audio

Interface

SPISEL1 SPISEL2 SPISEL3 SPISEL4

TXD0

RXD0 RTS0 CTS0

TXD1

RXD1 RTS1 CTS1

TIM0CK_GT

TIM0OUT TIM0CAP

TIM1CK_GT

TIM1OUT TIM1CAP

TIM2OUT

SIF_D SIF_CLK

IP_DO IP_DI

IP_INT IP_CLK IP_SEL

PC0 PC1

JTAG_TDI

JTAG_TMS JTAG_TCK JTAG_TDO

ADO

ADE

I2S_OUT

I2S_DIN I2S_CLK

I2S_SYNC

MUX

SPIMISO SPISEL0

DI O0/ S PISE L 1 DI O1/ S PISE L 2/P C0 DI O2/ S PISE L 3/ RFRX DI O3/ S PISE L 4/ RFTX

DIO4/CTS0/JT AG_TCK DIO5/RTS0/JT AG_TMS DIO6/TXD0/JTAG_TDO

DIO7/RXD0/JTAG_TDI DIO8/TIM0CK_GT/P C1

DIO9/TIM0CAP/32KXTALIN/32KIN

DI O1 0/T IM0 OU T /32 KXT ALOU T

DIO11/TIM1CK_GT/T IM2OUT DIO12/TIM1CAP/ADO/DAI_WS

DI O 1 3 /T IM 1 OU T /A D E/ D A I_ S D IN

DIO14/SIF_CLK/IP_CLK DIO15/SIF_D/IP_DO DIO16/RX D1/IP_DI/JTAG_TDI

DI O17 / CTS1 /I P_ SEL /DA I_S CK /

DIO18/RTS1/IP_INT/DAI_SDOUT/

DIO19/TXD1/JTAG_TDO DIO20/RX D1/JTAG_TDI

JTAG_TCK

JTAG_TMS

ADC1 ADC2 ADC3 ADC4

DAC1

DAC2

COMP 1M/

EXT_PA_B

COMP 1P/

EXT_PA_C

COMP2M

COMP2P

M U X

ADC

Temperature

Sensor

Wireless

Transceiver

Security

Coproces sor

DAC1

Time

Digital

DAC2

Comparator1

Comparator2

Baseband

Flight

Radio

RF_IN VCOT UNE

IBAIS

Figure 1: JN5148 Block Diagram

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2 Pin Configurations

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DIO16/RXD 1/IP_DI/JTA G_T DI

DIO17/C TS1/I P_S EL/DAI _SC K/JT AG_TCK

VSS3

DIO18/RTS 1/IP_INT/DAI_SDOUT/JT AG_TMS

DIO19/T XD1/JTA G_TDO

VSS2

VSSS

XTAL_ OUT

XTAL_ IN

VB_SY NTH

VCOTUNE

VB_VCO

VDD1

IBIAS

1 2 3 4 5 6

7 8

9 10 11 12 13 14

DIO15/SIF_D/IP_DO

DIO14/ SIF_C LK/I P_CLK

DIO13/T IM 1OUT/AD E/DA I_SDIN

DIO12/TIM1CAP/ADO/DAI_WS

DIO10/T IM 0OUT/3 2KXTALOU T

DIO11/TIM1CK_GT/TIM2OUT

DIO9/TIM 0C AP/32KXT ALIN/32K IN

VSSA

(Paddl e)

VDD2

DIO8/TIM 0C K_GT/PC 1

DIO 7/RXD 0/JT AG_TD I

DIO5/RTS0/JTAG_TMS

DIO6/TXD0/JTAG_TDO

DIO3/S PISE L4/RF TX

DIO4/CTS0/JTAG_TCK

DIO2/SPISEL3/RFRX

DIO1/S PISE L2/PC0

VB_DIG

RESET N

DIO0/S PISE L1

SPISE L0

SPIMOSI

VB_RAM

SPIMISO

SPICLK

VSS1

DIO20/RXD1/JTAG_TDI

31 30

DAC2

DAC1

VREF

RF_IN

VB_RF2

VB_RF

COMP1M

ADC1

ADC2

ADC3

ADC4

COMP1P

COMP2M

VB_A

COMP2P

Figure 2: 56-pin QFN Configuration (top view)

 Note: Please refer to Appendix B.4 JN5148 Module Reference

Design for important applications information regarding the connection of the PADDLE to the PCB.

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2.1 Pin Assignment

Pin No Power supplies Signal

10, 12, 16, 18, 27, 35, 40

13, 49 VDD1, VDD2 3.3V Supplies: VDD1 for analogue,

32, 6, 3, 7, Paddle VSS1, VSS2, VSS3, VSSS, VSSA 0V Grounds (see appendix A.2 for

28 NC No connect General

39 RESETN CMOS Reset input

8, 9 XTAL_OUT, XTAL_IN 1.8V System crystal oscillator Radio

11 VCOTUNE 1.8V VCO tuning RC network

14 IBIAS 1.8V Bias current control

17 RF_IN 1.8V RF antenna

21, 22, 23, 24 ADC1, ADC2, ADC3, ADC4 3.3V ADC inputs

15 VREF 1.8V Analogue peripheral reference

29, 30 DAC1, DAC2 3.3V DAC outputs

19, 20 COMP1M/EXT_PA_B, COMP1P/EXT_PA_C 3.3V Comparator 1 inputs and

25, 26 COMP2M, COMP2P 3.3V Comparator 2 inputs Digital Peripheral I/O

33 SPICLK CMOS SPI Clock Output

36 SPIMOSI CMOS SPI Master Out Slave In Output

34 SPIMISO CMOS SPI Master In Slave Out Input

37 SPISEL0 CMOS SPI Slave Select Output 0

38 DIO0 SPISEL1 CMOS DIO0 or SPI Slave Select Output

41 DIO1 SPISEL2 PC0 CMOS DIO1, SPI Slave Select Output 2

42 DIO2 SPISEL3 RFRX CMOS DIO2, SPI Slave Select Output 3

43 DIO3 SPISEL4 RFTX CMOS DIO3, SPI Slave Select Output 4

44 DIO4 CTS0 JTAG_TCK CMOS DIO4, UART 0 Clear To Send

45 DIO5 RTS0 JTAG_TMS CMOS DIO5, UART 0 Request To Send

46 DIO6 TXD0 JTAG_TDO CMOS DIO6, UART 0 Transmit Data

47 DIO7 RXD0 JTAG_TDI CMOS DIO7, UART 0 Receive Data

48 DIO8 TIM0CK_GT PC1 CMOS DIO8, Timer0 Clock/Gate Input

50 DIO9 TIM0CAP 32KXTALIN 32KIN CMOS DIO9, Timer0 Capture Input, 32K

VB_SYNTH, VB_VCO, VB_RF2, VB_RF, VB_A, VB_RAM, VB_DIG

Analogue Peripheral I/O

Primary Alternate Functions

Type

1.8V Regulated supply voltage

Description

VDD2 for digital

paddle details)

voltage

external PA control

or Pulse Counter0 Input

or Radio Receive Control Output

or Radio Transmit Control Output

Input or JTAG CLK

Output or JTAG Mode Select

Output or JTAG Data Output

Input or JTAG Data Input

or Pulse Counter1 Input

External Crystal Input or 32K Clock Input

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Primary Alternate Functions

51 DIO10 TIM0OUT 32KXTALOUT CMOS DIO10, Timer0 PWM Output or

52 DIO11 TIM1CK_GT TIM2OUT CMOS DIO11, Timer1 Clock/Gate

53 DIO12 TIM1CAP ADO DAI_WS CMOS DIO12, Timer1 Capture Input,

54 DIO13 TIM1OUT ADE DAI_SDIN CMOS DIO13, Timer1 PWM Output,

55 DIO14 SIF_CLK IP_CLK CMOS DIO14, Serial Interface Clock

56 DIO15 SIF_D IP_DO CMOS DIO15, Serial Interface Data or

1 DIO16 RXD1

(optional)

2 DIO17 CTS1 IP_SEL DAI_SCK JTAG_TCK CMOS DIO17, UART 1 Clear To Send

4 DIO18 RTS1 IP_INT DAI_SDOUT JTAG_TMS CMOS DIO18, UART 1 Request To

5 DIO19 TXD1 JTAG_TDO CMOS DIO19 or UART 1 Transmit

31 DIO 20 RXD1

(default)

Digital Peripheral I/O Pin

IP_DI JTAG_TDI

(optional)

JTAG_TDI

(default)

Signal

Type

32K External Crystal Output

Input or Timer2 PWM Output

Antenna Diversity or Digital Audio Word Select

Antenna Diversity or Digital Audio Data Input

or Intelligent Peripheral Clock Input

Intelligent Peripheral Data Out

CMOS DIO16, UART 1 Receive Data

Input or Intelligent Peripheral Data In or JTAG data In (optional)

Input, Intelligent Peripheral Device Select Input or Digital Audio Clock or JTAG CLK

Send Output, Intelligent Peripheral Interrupt Output or Digital Audio Data Output or JTAG Mode Select

Data Output or JTAG Data Out

CMOS DIO 20, UART 1 Receive Data

Input or JTAG data In (default)

Description

 The PCB schematic and layout rules detailed in Appendix B.4

must be followed. Failure to do so will likely result in the JN5148 failing to meet the performance specification detailed herein and worst case may result in device not functioning in the end application.

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2.2 Pin Descriptions

2.2.1 Power Supplies

The device is powered from the VDD1 and VDD2 pins, each being decoupled with a 100nF ceramic capacitor. VDD1 is the power supply to the analogue circuitry; it should be decoupled to ground. VDD2 is the power supply for the digital circuitry; and should also be decoupled to ground. A 10uF tantalum capacitor is required. Decoupling pins for the internal 1.8V regulators are provided which require a 100nF capacitor located as close to the device as practical. VB_VCO, VB_RF, VB_A and VB_SYNTH should be decoupled with an additional 47pF capacitor, while VB_RAM and VB_DIG require only 100nF. VB_RF and VB_RF2 should be connected together as close to the device as practical, and only require one 100nF capacitor and one 47pF capacitor. Refer to

VSSA, VSSS, VSS1, VSS2, VSS3 are the ground pins.

2.2.2 Reset

RESETN is a bi-directional active low reset pin that is connected to a 40kΩ internal pull-up resistor. It may be pulled low by an external circuit, or can be driven low by the JN5148 if an internal reset is generated. Typically, it will be used to provide a system reset signal. Refer to section 6.2, External Reset, for more details.

2.2.3 32MHz Oscillator

A crystal is connected between XTALIN and XTALOUT to form the reference oscillator, which drives the system clock. A capacitor to analogue ground is required on each of these pins. Refer to section for more details. The 32MHz reference frequency is divided down to 16MHz and this is used as the system clock throughout the device.

B.4.1 for schematic diagram.

5.1 16MHz System Clock

2.2.4 Radio

The radio is a single ended design, requiring a capacitor and just two inductors to match to 50Ω microstrip line to the RF_IN pin.

An external resistor (43kΩ) is required between IBIAS and analogue ground to set various bias currents and references within the radio.

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2.2.5 Analogue Peripherals

Several of the analogue peripherals require a reference voltage to use as part of their operations. They can use either an internal reference voltage or an external reference connected to VREF. This voltage is referenced to analogue ground and the performance of the analogue peripherals is dependant on the quality of this reference.

There are four ADC inputs, two pairs of comparator inputs and two DAC outputs. The analogue I/O pins on the JN5148 can have signals applied up to 0.3v higher than VDD1. A schematic view of the analogue I/O cell is shown in Figure 3: Analogue I/O Cell

In reset and deep sleep, the analogue peripherals are all off and the DAC outputs are in a high impedance state.

In sleep, the ADC and DACs are off, with the DAC outputs in high impedance state. The comparators may optionally be used as a wakeup source.

Unused ADC and comparator inputs should be left unconnected.

VDD1

Analogue

Peripheral

I/O Pin

VSSA

Figure 3: Analogue I/O Cell

2.2.6 Digital Input/Output

Digital I/O pins on the JN5148 can have signals applied up to 2V higher than VDD2 (with the exception of pins DIO9 and DIO10 that are 3V tolerant) and are therefore TTL-compatible with VDD2 > 3V. For other DC properties of these pins see section 22.2.3 I/O Characteristics.

When used in their primary function all Digital Input/Output pins are bi-directional and are connected to weak internal pull up resistors (40kΩ nominal) that can be disabled. When used in their secondary function (selected when the appropriate peripheral block is enabled through software library calls) then their direction is fixed by the function. The pull up resistor is enabled or disabled independently of the function and direction; the default state from reset is enabled.

A schematic view of the digital I/O cell is in

Figure 4: DIO Pin Equivalent Schematic.

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VDD2

PROT

DIO[x] Pin

VSS

Figure 4: DIO Pin Equivalent Schematic

In reset, the digital peripherals are all off and the DIO pins are set as high-impedance inputs. During sleep and deep sleep, the DIO pins retain both their input/output state and output level that was set as sleep commences. If the DIO pins were enabled as inputs and the interrupts were enabled then these pins may be used to wake up the JN5148 from sleep.

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3 CPU

The CPU of the JN5148 is a 32-bit load and store RISC processor. It has been architected for three key requirements:

• Low power consumption for battery powered applications

• High performance to implement a wireless protocol at the same time as complex applications

• Efficient coding of high-level languages such as C provided with the Jennic Software Developers Kit

It features a linear 32-bit logical address space with unified memory architecture, accessing both code and data in the same address space. Registers for peripheral units, such as the timers, UARTs and the baseband processor are also mapped into this space.

The CPU has access to a block of 15 32-bit General-Purpose (GP) registers together with a small number of special purpose registers which are used to store processor state and control interrupt handling. The contents of any GP register can be loaded from or stored to memory, while arithmetic and logical operations, shift and rotate operations, and signed and unsigned comparisons can be performed either between two registers and stored in a third, or between registers and a constant carried in the instruction. Operations between general or special-purpose registers execute in one cycle while those that access memory require a further cycle to allow the memory to respond.

The instruction set manipulates 8, 16 and 32-bit data; this means that programs can use objects of these sizes very efficiently. Manipulation of 32-bit quantities is particularly useful for protocols and high-end applications allowing algorithms to be implemented in fewer instructions than on smaller word-size processors, and to execute in fewer clock cycles. In addition, the CPU supports hardware Multiply that can be used to efficiently implement algorithms needed by Digital Signal Processing applications.

The instruction set is designed for the efficient implementation of high-level languages such as C. Access to fields in complex data structures is very efficient due to the provision of several addressing modes, together with the ability to be able to use any of the GP registers to contain the address of objects. Subroutine parameter passing is also made more efficient by using GP registers rather than pushing objects onto the stack. The recommended programming method for the JN5148 is by using C, which is supported by a software developer kit comprising a C compiler, linker and debugger.

The CPU architecture also contains features that make the processor suitable for embedded, real-time applications. In some applications, it may be necessary to use a real-time operating system to allow multiple tasks to run on the processor. To provide protection for device-wide resources being altered by one task and affecting another, the processor can run in either supervisor or user mode, the former allowing access to all processor registers, while the latter only allows the GP registers to be manipulated. Supervisor mode is entered on reset or interrupt; tasks starting up would normally run in user mode in a RTOS environment.

Embedded applications require efficient handling of external hardware events. Exception processing (including reset and interrupt handling) is enhanced by the inclusion of a number of special-purpose registers into which the PC and status register contents are copied as part of the operation of the exception hardware. This means that the essential registers for exception handling are stored in one cycle, rather than the slower method of pushing them onto the processor stack. The PC is also loaded with the vector address for the exception that occurred, allowing the handler to start executing in the next cycle.

To improve power consumption a number of power-saving modes are implemented in the JN5148, described more fully in section software control, the processor can be shut down and on an interrupt it will wake up to service the request. Additionally, it is possible under software control, to set the speed of the CPU to 4, 8, 16 or 32MHz. This feature can be used to trade-off processing power against current consumption.

21 - Power Management and Sleep Modes. One of these modes is the CPU doze mode; under

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4 Memory Organisation

This section describes the different memories found within the JN5148. The device contains ROM, RAM, OTP eFuse memory, the wireless transceiver and peripherals all within the same linear address space.

0xFFFFFFFF

0xF0020000

RAM

(128kB)

0xF0000000

Unpopulated

0x04000000

0x02000000 0x00020000

0x00000000

RAM Ec ho

Peripherals

ROM

(128kB)

Figure 5: JN5148 Memory Map

4.1 ROM

The ROM is 128k bytes in size, and can be accessed by the processor in a single CPU clock cycle. The ROM contents include bootloader to allow external Flash memory contents to be bootloaded into RAM at runtime, a default interrupt vector table, an interrupt manager, IEEE802.15.4 MAC and APIs for interfacing on-chip peripherals. The operation of the boot loader is described in detail in Application Note to the application’s soft interrupt vector table contained within RAM. Section the handling of interrupts. ROM contents are shown in

0x00020000

Figure 6.

[8]. The interrupt manager routes interrupt calls

7 contains further information regarding

Spare

APIs

IEEE802.15.4

Stack

Boot Loader

Interrupt Manager

0x00000000

Interrupt Vectors

Figure 6: Typical ROM contents

16 JN-DS-JN5148-001 1v2 © Jennic 2009

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4.2 RAM

The JN5148 contains 128kBytes of high speed RAM. It can be used for both code and data storage and is accessed by the CPU in a single clock cycle. At reset, a boot loader controls the loading of segments of code and data from an external memory connected to the SPI port, into RAM. Software can control the power supply to the RAM allowing the contents to be maintained during a sleep period when other parts of the device are un-powered. Typical RAM contents are shown in Figure 7.

0x04020000

CPU Stack

(Grows D own)

Application

MAC Address

MAC Data

Interrupt Vector Table

0x04000000

Figure 7: Typical RAM Contents

4.3 OTP eFuse Memory

The JN5148 contains a total of 32bytes of eFuse memory; this is a One Time Programmable (OTP) memory that is used to support on chip 64-bit MAC ID and a 128-bit AES security key. A limited number of bits are available for customer use for storage of configuration information; configuration of these is made through use of software APIs.

For full details on how to program and use the eFuse memory, please refer to application note OTP efuse Memory

Alternatively, Jennic can provide an eFuse programming service for customers that wish to use the eFuse but do not wish to undertake this for themselves. For further details of this service, please contact your local Jennic sales office.

[2]

JN-AN-1062 Using

4.4 External Memory

An external memory with an SPI interface may be used to provide storage for program code and data for the device when external power is removed. The memory is connected to the SPI interface using select line SPISEL0; this select line is dedicated to the external memory interface and is not available for use with other external devices. See Figure 8 for connection details.

JN5148

SPIS EL0 SPIMISO SPIMOSI

SPICLK

Figure 8: Connecting External Serial Memory

Serial

Me mo ry

SS SDO SDI CLK

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At reset, the contents of this memory are copied into RAM by the software boot loader. The Flash memory devices that are supported as standard through the JN5148 bootloader are given in Table 1. Jennic recommends that where possible one of these devices should be selected.

Manufacturer Device Number

SST (Silicon Storage Technology) 25VF010A (1Mbyte device)

Numonyx M25P10-A (1Mbyte device),

M25P40 (4Mbyte device)

Table 1: Supported Flash Memories

Applications wishing to use an alternate Flash memory device should refer to application note [3] JN-AN-1038 Programming Flash devices not supported by the JN51xx ROM-based bootloader. This application note provides guidance on developing an interface to an alternate device.

4.4.1 External Memory Encryption

The contents of the external serial memory may be encrypted. The AES security processor combined with a user programmable 128-bit encryption key is used to encrypt the contents of the external memory. The encryption key is stored in eFuse.

When bootloading program code from external serial memory, the JN5148 automatically accesses the encryption key to execute the decryption process. User program code does not need to handle any of the decryption process; it is transparent.

With encryption enabled, the time taken to boot code from external flash is increased.

4.5 Peripherals

All peripherals have their registers mapped into the memory space. Access to these registers requires 3 clock cycles. Applications have access to the peripherals through the software libraries that present a high-level view of the peripheral’s functions through a series of dedicated software routines. These routines provide both a tested method for using the peripherals and allow bug-free application code to be developed more rapidly. For details, see the Integrated Peripherals API Reference Manual (JN-RM-2001).[6]

4.6 Unused Memory Addresses

Any attempt to access an unpopulated memory area will result in a bus error exception (interrupt) being generated.

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5 System Clocks

Two system clocks are used to provide timing references into the on-chip subsystems of the JN5148. A 16MHz clock, generated by a crystal-controlled 32MHz oscillator, is used by the transceiver, processor, memory and digital and analogue peripherals. A 32kHz clock is used by the sleep timer and during the startup phase of the chip.

5.1 16MHz System Clock

The 16MHz system clock is used by the digital and analogue peripherals and the transceiver. A scaled version (4,8,16 or 32MHz) of this clock is also used by the processor and memories. For most operations it is necessary to source this clock from the 32MHz oscillator.

Crystal oscillators are generally slow to start. Hence to provide a faster start-up following a sleep cycle a fast RC oscillator is provided that can be used as the source for the 16MHz system clock. The oscillator starts very quickly and is typically 24MHz causing the system clock to run at 12MHz. Using a clock of this speed scales down the speed of the processor and any peripherals in use. For the SPI interface this causes no functional issues as the generated SPI clock is slightly slower and is used to clock the external SPI slave. Use of the radio is not possible when using the 24MHz RC oscillator. Additionally, timers and UARTs should not be used as the exact frequency will not be known.

The JN5148 device can be configured to wake up from sleep using the fast RC oscillator and automatically switch over to use the 32MHz xtal as the clock source, when it has started up. This could allow application code to be downloaded from the flash before the xtal is ready, typically improving start-up time by 550usec. Alternatively, the switch over can be controlled by software, or the system could always use the 32MHz oscillator as the clock source.

5.1.1 32MHz Oscillator

The JN5148 contains the necessary on chip components to build a 32MHz reference oscillator with the addition of an external crystal resonator and two tuning capacitors. The schematic of these components are shown in The two capacitors, C1 and C2, should typically be 15pF and use a COG dielectric. Due to the small size of these capacitors, it is important to keep the traces to the external components as short as possible. The on chip transconductance amplifier is compensated for temperature variation, and is self-biasing by means of the internal resistor R1. The electrical specification of the oscillator can be found in section 22.3.13. Please refer to Appendix B for development support with the crystal oscillator circuit.

Figure 9.

JN5148

XTALIN

Figure 9: 32MHz Crystal Oscillator Connections

XTALOUT

C2 C1

5.1.2 24MHz RC Oscillator

An on-chip 24MHz RC oscillator is provided. No external components are required for this oscillator. The electrical specification of the oscillator can be found in section

22.3.14.

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5.2 32kHz System Clock

The 32kHz system clock is used for timing the length of a sleep period (see section 21 Power Management and Sleep Modes) and also to generate the system clock used internally during reset. The clock can be selected from one of three sources through the application software:

32kHz RC Oscillator

•

32kHz Crystal Oscillator

•

• 32kHz External Clock

Upon a chip reset or power-up the JN5148 defaults to using the internal 32kHz RC Oscillator. If another clock source is selected then it will remain in use for all 32kHz timing until a chip reset is performed.

5.2.1 32kHz RC Oscillator

The internal 32kHz RC oscillator requires no external components. The internal timing components of the oscillator have a wide tolerance due to manufacturing process variation and so the oscillator runs nominally at 32kHz ±30%. To make this useful as a timing source for accurate wakeup from sleep, a frequency calibration factor derived from the more accurate 16MHz clock may be applied. The calibration factor is derived through software, details can be found in section 11.3.1. For detailed electrical specifications, see section 22.3.11.

5.2.2 32kHz Crystal Oscillator

In order to obtain more accurate sleep periods, the JN5148 contains the necessary on-chip components to build a 32kHz oscillator with the addition of an external 32.768kHz crystal and two tuning capacitors. The crystal should be connected between 32KXTALIN and 32KXTALOUT (DIO9 and DIO10), with two equal capacitors to ground, one on each pin. Due to the small size of the capacitors, it is important to keep the traces to the external components as short as possible.

The electrical specification of the oscillator can be found in section 22.3.12. The oscillator cell is flexible and can operate with a range of commonly available 32.768kHz crystals with load capacitances from 6 to 12.5pF. However, the maximum ESR of the crystal and the supply current are both functions of the actual crystal used, see appendix B.1 for more details.

JN5148

32KXTALOUT 32KXTALIN

Figure 10: 32kHz crystal oscillator connections

5.2.3 32kHz External Clock

An externally supplied 32kHz reference clock on the 32KIN input (DIO9) may be provided to the JN5148. This would allow the 32kHz system clock to be sourced from a very stable external oscillator module, allowing more accurate sleep cycle timings compared to the internal RC oscillator. (See section tolerant input)

Preliminary

22.2.3 I/O Characteristics, DIO9 is a 3V

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6 Reset

A system reset initialises the device to a pre-defined state and forces the CPU to start program execution from the reset vector. The reset process that the JN5148 goes through is as follows.

When power is applied, the 32kHz RC oscillator starts up and stabilises, which takes approximately 100μsec. At this point, the 32MHz crystal oscillator is enabled and power is applied to the processor and peripheral logic. The logic blocks are held in reset until the 32MHz crystal oscillator stabilises, typically this takes 0.75ms. Then the internal reset is removed from the CPU and peripheral logic and the CPU starts to run code beginning at the reset vector, consisting of initialisation code and the resident boot loader. [8] Section 22.3.1 provides detailed electrical data and timing.

The JN5148 has five sources of reset:

• Internal Power-on Reset

• External Reset

• Software Reset

• Watchdog timer

• Brown-out detect

 Note: When the device exits a reset condition, device operating

parameters (voltage, frequency, temperature, etc.) must be met to ensure operation. If these conditions are not met, then the device must be held in reset until the operating conditions are met. (See section 22.3)

6.1 Internal Power-on Reset

For the majority of applications the internal power-on reset is capable of generating the required reset signal. When power is applied to the device, the power-on reset circuit monitors the rise of the VDD supply. When the VDD reaches the specified threshold, the reset signal is generated and can be observed as a rising edge on the RESETN pin. This signal is held internally until the power supply and oscillator stabilisation time has elapsed, when the internal reset signal is then removed and the CPU is allowed to run.

VDD

Internal RESET

RESETN Pin

Figure 11: Internal Power-on Reset

When the supply drops below the power on reset ‘falling’ threshold, it will re-trigger the reset. Use of the external reset circuit show in

Figure 12 is suggested.

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VDD

JN5148

18k

RESETN

Figure 12: External Reset Generation

The external resistor and capacitor provide a simple reset operation when connected to the RESETN pin.

470nF

6.2 External Reset

An external reset is generated by a low level on the RESETN pin. Reset pulses longer than the minimum pulse width will generate a reset during active or sleep modes. Shorter pulses are not guaranteed to generate a reset. The JN5148 is held in reset while the RESETN pin is low. When the applied signal reaches the Reset Threshold Voltage

) on its positive edge, the internal reset process starts.

RST

Multiple devices may connect to the RESETN pin in an open-collector mode. The JN5148 has an internal pull-up resistor connect to the RESETN pin. The pin is an input for an external reset, an output during the power-on reset and may optionally be an output during a software reset. No devices should drive the RESETN pin high.

RESETN pin

Reset

Internal Reset

Figure 13: External Reset

6.3 Software Reset

A system reset can be triggered at any time through software control, causing a full chip reset and invalidating the RAM contents. For example this can be executed within a user’s application upon detection of a system failure. When performing the reset, the RESETN pin is driven low for 1µsec; depending on the external components this may or may not be visible on the pin.

In addition, the RESETN line can be driven low by the JN5148 to provide a reset to other devices in the system (e.g. external sensors) without resetting itself. When the RESETN line is not driven it will pull back high through either the internal pull-up resistor or any external circuitry. It is essential to ensure that the RESETN line pulls back high within 100µsec after the JN5148 stops driving the line; otherwise a system reset will occur. Due to this, careful consideration should be taken of any capacitance on this line. For instance, the RC values recommended in section to be replaced with a suitable reset IC

Preliminary

6.1 may need

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6.4 Brown-out Detect

An internal brown-out detect module is used to monitor the supply voltage to the JN5148; this can be used whilst the device is awake or is in CPU doze mode. Dips in the supply voltage below a variable threshold can be detected and can be used to cause the JN5148 to perform a chip reset. Equally, dips in the supply voltage can be detected and used to cause an interrupt to the processor, when the voltage either drops below the threshold or rises above it.

The brown-out detect is enabled by default from power-up and can extend the reset during power-up. This will keep the CPU in reset until the voltage exceeds the brown-out threshold voltage. The threshold voltage is configurable to

2.0V, 2.3V, 2.7V and 3.0V and is controllable by software. From power-up the threshold is set by eFuse settings and the default chip configuration is for the 2.3V threshold. It is recommended that the threshold is set so that, as a minimum, the chip is held in reset until the voltage reaches the level required by the external memory device on the SPI interface.

6.5 Watchdog Timer

A watchdog timer is provided to guard against software lockups. It operates by counting cycles of the 32kHz system clock. A pre-scaler is provided to allow the expiry period to be set between typically 8ms and 16.4 seconds. Failure to restart the watchdog timer within the pre-configured timer period will cause a chip reset to be performed. A status bit is set if the watchdog was triggered so that the software can differentiate watchdog initiated resets from other resets, and can perform any required recovery once it restarts. If the source of the 32kHz system clock is the 32kHz RC oscillator then the watchdog expiry periods are subject to the variation in period of the RC oscillator.

After power up, reset, start from deep sleep or start from sleep, the watchdog is always enabled with the largest timeout period and will commence counting as if it had just been restarted. Under software control the watchdog can be disabled. If it is enabled, the user must regularly restart the watchdog timer to stop it from expiring and causing a reset. The watchdog runs continuously, even during doze, however the watchdog does not operate during sleep or deep sleep, or when the hardware debugger has taken control of the CPU. It will recommence automatically if enabled once the debugger un-stalls the CPU.

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7 Interrupt System

The interrupt system on the JN5148 is a hardware-vectored interrupt system. The JN5148 provides several interrupt sources, some associated with CPU operations (CPU exceptions) and others which are used by hardware in the device. When an interrupt occurs, the CPU stops executing the current program and loads its program counter with a fixed hardware address specific to that interrupt. The interrupt handler or interrupt service routine is stored at this location and is run on the next CPU cycle. Execution of interrupt service routines is always performed in supervisor mode. Interrupt sources and their vector locations are listed in

Interrupt Source Vector Location Interrupt Definition

Bus error 0x08 Typically cause by an attempt to access an invalid address or a

disabled peripheral Tick timer 0x0e Tick timer interrupt asserted Alignment error 0x14 Load/store address to non-naturally-aligned location Illegal instruction 0x1a Attempt to execute an unrecognised instruction Hardware interrupt 0x20 interrupt asserted System call 0x26 Trap 0x2c caused by the b.trap instruction or the debug unit Reset 0x38 Caused by software or hardware reset. Stack Overflow 0x3e Stack overflow

System call initiated by b.sys instruction

Table 2: Interrupt Vectors

Table 2 below:

7.1 System Calls

The b.trap and b.sys instructions allow processor exceptions to be generated by software.

A system call exception will be generated when the b.sys instruction is executed. This exception can, for example, be used to enable a task to switch the processor into supervisor mode when a real time operating system is in use. (See section 3 for further details.)

The b.trap instruction is commonly used for trapping errors and for debugging.

7.2 Processor Exceptions

7.2.1 Bus Error

A bus error exception is generated when software attempts to access a memory address that does not exist, or is not populated with memory or peripheral registers or when writing to ROM.

7.2.2 Alignment

Alignment exceptions are generated when software attempts to access objects that are not aligned to natural word boundaries. 16-bit objects must be stored on even byte boundaries, while 32-bit objects must be stored on quad byte boundaries. For instance, attempting to read a 16-bit object from address 0xFFF1 will trigger an alignment exception as will a read of a 32-bit object from 0xFFF1, 0xFFF2 or 0xFFF3. Examples of legal 32-bit object addresses are 0xFFF0, 0xFFF4, 0xFFF8 etc.

7.2.3 Illegal Instruction

If the CPU reads an unrecognised instruction from memory as part of its instruction fetch, it will cause an illegal instruction exception.

7.2.4 Stack Overflow

When enabled, a stack overflow exception occurs if the stack pointer reaches a programmable location.

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7.3 Hardware Interrupts

Hardware interrupts generated from the transceiver, analogue or digital peripherals and DIO pins are individually masked using the Programmable Interrupt Controller (PIC). Management of interrupts is provided in the peripherals

[6]. For details of the interrupts generated from each peripheral see the respective section in this datasheet.

library

Interrupts can be used to wake the JN5148 from sleep. The peripherals, baseband controller, security coprocessor and PIC are powered down during sleep but the DIO interrupts and optionally the pulse counters, wake-up timers and analogue comparator interrupts remain powered to bring the JN5148 out of sleep.

Prioritised external interrupt handling (i.e., interrupts from hardware peripherals) is provided to enable an application to control an events priority to provide for deterministic program execution.

The priority Interrupt controller provides 15 levels of prioritised interrupts. The priority level of all interrupts can be set, with value 0 being used to indicate that the source can never produce an external interrupt, 1 for the lowest priority source(s) and 15 for the highest priority source(s). Note that multiple interrupt sources can be assigned the same priority level if desired.

If while processing an interrupt, a new event occurs at the same or lower priority level, a new external interrupt will not be triggered. However, if a new higher priority event occurs, the external interrupt will again be asserted, interrupting the current interrupt service routine.

Once the interrupt service routine is complete, lower priority events can be serviced.

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8 Wireless Transceiver

The wireless transceiver comprises a 2.45GHz radio, modem, a baseband processor, a security coprocessor and PHY controller. These blocks, with protocol software provided as a library, implement an IEEE802.15.4 standardsbased wireless transceiver that transmits and receives data over the air in the unlicensed 2.4GHz band.

8.1 Radio

Figure 14 shows the single ended radio architecture.

Radio

LNA

Lim1

Lim2

Lim3

Lim4

D-Type

Switch

Calibration

Reference

& Bias

ADC

sigma

synth

Figure 14: Radio Architecture

The radio comprises a low-IF receive path and a direct modulation transmit path, which converge at the TX/RX switch. The switch connects to the external single ended matching network, which consists of two inductors and a capacitor, this arrangement creates a 50Ω port and removes the need for a balun. A 50Ω single ended antenna can be connected directly to this port.

The 32MHz crystal oscillator feeds a divider, which provides the frequency synthesiser with a reference frequency. The synthesiser contains programmable feedback dividers, phase detector, charge pump and internal Voltage Controlled Oscillator (VCO). The VCO has no external components, and includes calibration circuitry to compensate for differences in internal component values due to process and temperature variations. The VCO is controlled by a Phase Locked Loop (PLL) that has an internal loop filter. A programmable charge pump is also used to tune the loop characteristic.

The receiver chain starts with the low noise amplifier / mixer combination whose outputs are passed to a lowpass filter, which provides the channel definition. The signal is then passed to a series of amplifier blocks forming a limiting strip. The signal is converted to a digital signal before being passed to the Modem. The gain control for the RX path is derived in the automatic gain control (AGC) block within the Modem, which samples the signal level at various points down the RX chain. To improve the performance and reduce current consumption, automatic calibration is applied to various blocks in the RX path.

In the transmit direction, the digital stream from the Modem is passed to a digital sigma-delta modulator which controls the feedback dividers in the synthesiser, (dual point modulation). The VCO frequency now tracks the applied modulation. The 2.4 GHz signal from the VCO is then passed to the RF Power Amplifier (PA), whose power control can be selected from one of three settings. The output of the PA drives the antenna via the RX/TX switch

delta

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8.1.1 Radio External Components

In order to realise the full performance of the radio it is essential that the reference PCB layout and BOM are carefully followed. See Appendix

The radio is powered from a number of internal 1.8V regulators fed from the analogue supply VDD1, in order to provide good noise isolation between the digital logic of the JN5148 and the analogue blocks. These regulators are also controlled by the baseband controller and protocol software to minimise power consumption. Decoupling for internal regulators is required as described in section

For single ended antennas or connectors, a balun is not required, however a matching network is needed.

The RF matching network requires three external components and the IBIAS pin requires one external component as shown in schematic in B.4.1. These components are critical and should be placed close to the JN5148 pins and analogue ground as defined in Constraints

8.1.2 . Antenna Diversity

Support is provided for antenna diversity. Antenna diversity is a technique that maximises the performance of an antenna system. It allows the radio to switch between two antennas that have very low correlation between their received signals. Typically, this is achieved by spacing two antennas around 0.25 wavelengths apart or by using two orthogonal polarisations. So, if a packet is transmitted and no acknowledgement is received, the radio system can switch to the other antenna for the retry, with a different probability of success.

The JN5148 provides an output (ADO) on DIO12 that is asserted on odd numbered retries that can be used to control an antenna switch; this enables antenna diversity to be implemented easily (see

B.4.

2.2.1, Power Supplies

Table 8: JN5148 Printed Antenna Reference Module Components and PCB Layout

Figure 15 and Figure 16).

ADO (DIO[12])

Antenna A

SEL

SELB

Antenna B

RF Switch: Single-Pole, Double-Throw (SPDT)

COM

Device RF Port

Figure 15 Simple Antenna Diversity Implementation using External RF Switch

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ADO (DIO[12])

TX Active

RX Active

1stTX-RX Cycle 2ndTX-RX Cycle (1stRetry)

Figure 16 Antenna Diversity ADO Signal for TX with Acknowledgement

DIO13 can be configured to be ADE, the inverse of ADO. In this configuration, an antenna diversity scheme can be implemented without the need for the inverter shown in

Figure 15.

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8.2 Modem

The modem performs all the necessary modulation and spreading functions required for digital transmission and reception of data at 250kbps in the 2450MHz radio frequency band in compliance with the IEEE802.15.4 standard. It also provides a high data rate modes at 500 and 667kbps.

Features provided to support network channel selection algorithms include Energy Detection (ED), Link Quality Indication (LQI) and fully programmable Clear Channel Assessment (CCA).

The Modem provides a digital Receive Signal Strength Indication (RSSI) that facilitates the implementation of the IEEE 802.15.4 ED function.

The LQI is defined in the IEEE 802.15.4 standard as a characterisation of the strength and/or data quality of a received packet. The Modem produces a signal quality metric based upon correlation magnitudes, which may be used in conjunction with the ED value to formulate the LQI.

The CCA capability of the Modem supports all modes of operation defined in the IEEE 802.15.4 standard, namely Energy above ED threshold, Carrier Sense and Carrier Sense and/or energy above ED threshold.

8.3 Baseband Processor

The baseband processor provides all time-critical functions of the IEEE802.15.4 MAC layer. Dedicated hardware guarantees air interface timing is precise. The MAC layer hardware/software partitioning, enables software to implement the sequencing of events required by the protocol and to schedule timed events with millisecond resolution, and the hardware to implement specific events with microsecond timing resolution. The protocol software layer performs the higher-layer aspects of the protocol, sending management and data messages between endpoint and coordinator nodes, using the services provided by the baseband processor.

Bitstream

Append

Checksum

Supervisor

Serialiser

Status

Encrypt

Port

AES AES

Codec Codec

Tx/Rx

Frame

Buffer

Radio

Bitstream

Protocol Timing Engine

CSMA CCA

Verify

Checksum

Backoff Control

Control

Deserialiser

Inline

Security

Decrypt

Port

Protocol

Timers

Processor

Bus

Figure 17: Baseband Processor

8.3.1 Transmit

A transmission is performed by software writing the data to be transferred into the Tx/Rx Frame Buffer, together with parameters such as the destination address and the number of retries allowed, and programming one of the protocol timers to indicate the time at which the frame is to be sent. This time will be determined by the software tracking the higher-layer aspects of the protocol such as superframe timing and slot boundaries. Once the packet is prepared and protocol timer set, the supervisor block controls the transmission. When the scheduled time arrives, the supervisor controls the sequencing of the radio and modem to perform the type of transmission required. It can perform all the algorithms required by IEEE802.15.4 such as CSMA/CA, GTS without processor intervention including retries and random backoffs.

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When the transmission begins, the header of the frame is constructed from the parameters programmed by the software and sent with the frame data through the serialiser to the Modem. At the same time, the radio is prepared for transmission. During the passage of the bitstream to the modem, it passes through a CRC checksum generator that calculates the checksum on-the-fly, and appends it to the end of the frame.

If using slotted access, it is possible for a transmission to overrun the time in its allocated slot; the Baseband Processor handles this situation autonomously and notifies the protocol software via interrupt, rather than requiring it to handle the overrun explicitly.

8.3.2 Reception

During reception, the radio is set to receive on a particular channel. On receipt of data from the modem, the frame is directed into the Tx/Rx Frame Buffer where both header and frame data can be read by the protocol software. An interrupt may be provided on receipt of the frame header. As the frame data is being received from the modem it is passed through a checksum generator; at the end of the reception the checksum result is compared with the checksum at the end of the message to ensure that the data has been received correctly. An interrupt may be provided to indicate successful packet reception.

During reception, the modem determines the Link Quality, which is made available at the end of the reception as part of the requirements of IEEE802.15.4.

8.3.3 Auto Acknowledge

Part of the protocol allows for transmitted frames to be acknowledged by the destination sending an acknowledge packet within a very short window after the transmitted frame has been received. The JN5148 baseband processor can automatically construct and send the acknowledgement packet without processor intervention and hence avoid the protocol software being involved in time-critical processing within the acknowledge sequence. The JN5148 baseband processor can also request an acknowledge for packets being transmitted and handle the reception of acknowledged packets without processor intervention.

8.3.4 Beacon Generation

In beaconing networks, the baseband processor can automatically generate and send beacon frames; the repetition rate of the beacons is programmed by the CPU, and the baseband then constructs the beacon contents from data delivered by the CPU. The baseband processor schedules the beacons and transmits them without CPU intervention.

8.3.5 Security

The baseband processor supports the transmission and reception of secured frames using the Advanced Encryption Standard (AES) algorithm transparently to the CPU. This is done by passing incoming and outgoing data through an in-line security engine that is able to perform encryption and decryption operations on-the-fly, resulting in minimal processor intervention. The CPU must provide the appropriate encrypt/decrypt keys for the transmission or reception. On transmission, the key can be programmed at the same time as the rest of the frame data and setup information.

During reception, the CPU must look up the key and provide it from information held in the header of the incoming frame. However, the hardware of the security engine can process data much faster than the incoming frame data rate. This means that it is possible to allow the CPU to receive the interrupt from the header of an incoming packet, read where the frame originated, look up the key and program it to the security hardware before the end of the frame has arrived. By providing a small amount of buffering to store incoming data while the lookup process is taking place, the security engine can catch up processing the frame so that when the frame arrives in the receive frame buffer it is fully decrypted.

8.4 Security Coprocessor

As well as being used during in-line encryption/decryption operations over a streaming interface and in external memory encryption, it is also possible to use the AES core as a coprocessor to the CPU of the JN5148. To allow the hardware to be shared between the two interfaces an arbiter ensures that the streaming interface to the AES core always has priority, to ensure that in-line processing can take place at any time.

Preliminary

+ 67 hidden pages

NXP Laboratories UK JN5148M4, JN5148M3, JN5148M0 chip manual

Specifications and Main Features

Frequently Asked Questions

User Manual

1 Introduction

1.1 Wireless Transceiver

1.2 RISC CPU and Memory

1.3 Peripherals

1.4 Block Diagram

2 Pin Configurations

2.1 Pin Assignment

2.2 Pin Descriptions

2.2.1 Power Supplies

2.2.2 Reset

2.2.3 32MHz Oscillator

2.2.4 Radio

2.2.5 Analogue Peripherals

2.2.6 Digital Input/Output

3 CPU

4 Memory Organisation

4.1 ROM

4.2 RAM

4.3 OTP eFuse Memory

4.4 External Memory

4.4.1 External Memory Encryption

4.5 Peripherals

4.6 Unused Memory Addresses

5 System Clocks

5.1 16MHz System Clock

5.1.1 32MHz Oscillator

5.1.2 24MHz RC Oscillator

5.2 32kHz System Clock

5.2.1 32kHz RC Oscillator

5.2.2 32kHz Crystal Oscillator

5.2.3 32kHz External Clock

6 Reset

6.1 Internal Power-on Reset

6.2 External Reset

6.3 Software Reset

6.4 Brown-out Detect

6.5 Watchdog Timer

7 Interrupt System

7.1 System Calls

7.2 Processor Exceptions

7.2.1 Bus Error

7.2.2 Alignment

7.2.3 Illegal Instruction

7.2.4 Stack Overflow

7.3 Hardware Interrupts

8 Wireless Transceiver

8.1 Radio

8.1.1 Radio External Components

8.2 Modem

8.3 Baseband Processor

8.3.1 Transmit

8.3.2 Reception

8.3.3 Auto Acknowledge

8.3.4 Beacon Generation

8.3.5 Security

8.4 Security Coprocessor