NXP Laboratories UK JN5139M0 User Manual

Advanced Data Sheet – JN513x

Sleep current with active beacon

Lead

h JN5121 for

IEEE802.15.4 and ZigBee Wireless Microcontrollers

Overview

The JN513x are a family of low power, low cost wireless microcontrollers suitable for IEEE802.15.4 and ZigBee applications. Each device integrates a 32-bit RISC processor, with a fully compliant 2.4GHz IEEE802.15.4 transceiver, 192kB of ROM, a selection of RAM sizes from 8kB to 96kB, and a rich mixture of analogue and digital peripherals.

The cost sensitive ROM/RAM architecture supports the storage of system software, including protocol stacks, routing tables and application code/data. Each device has hardware MAC and AES encryption accelerators, power saving and timed sleep modes, and mechanisms for security key and program code encryption. These features all make for a highly efficient, low power, single chip wireless microcontroller for battery-powered applications.

Block Diagram

RAM

XTAL

2.4GHz Radio

Power

Management

O-QPSK

Modem

IEEE802.15.4

MAC

Accelerator

128-bit AES

Encryption

Accelerator

Benefits

•

Single chip integrates transceiver and microcontroller for wireless sensor networks

•

Cost sensitive ROM/RAM architecture, meets needs for volume application

•

System BOM is low in component count and cost

• Hardware MAC ensures low power consumption and low processor overhead

• Extensive user peripherals

•

Pin compatible wit easy migration

8kB - 96kB

RISC CPU

48-byte

OTP eFuse

32-bit

ROM

192kB

SPI

2-wire serial

Timers

UARTs

12-bit ADC,

comparators

11-bit DACs, temp sensor

Applications

•

Robust and secure low power wireless applications

• Wireless sensor networks, particularly IEEE802.15.4 and ZigBee systems

• Home and commercial building automation

• Remote Control

• Toys and gaming

peripherals

• Industrial systems

•

Telemetry and utilities (e.g. AMR)

Bootloader

Flash

Optional

Features: Transceiver

• 2.4GHz IEEE802.15.4 compliant

• 128-bit AES security processor

•

MAC accelerator with packet formatting, CRCs, address check, auto-acks, timers

•

Integrated power management and sleep oscillator for low power

• On-chip power regulation for

2.2V to 3.6V battery operation

• Deep sleep current <0.4µA

•

timer <1.5µA

• Needs minimum of external components (< US$1 cost)

•

Rx current 39mA

• Tx current 39mA

•

Receiver sensitivity -97dBm

• Transmit power +3dBm

Features: Microcontroller

•

32-bit RISC processor sustains 32MIPs with low power

• 192kB ROM stores system code, including protocol stack

• 8kB, 16kB, 32kB or 96kB RAM stores system data and optionally bootloaded program code

• 48-byte OTP eFuse, stores MAC ID on-chip, offers AES based code encryption feature

• 4-input 12-bit ADC, 2 11-bit DACs, 2 comparators

•

2 Application timer/counters, 3 system timers

•

2 UARTs (one for debug)

•

SPI port with 5 selects

• 2-wire serial interface

•

Up to 21 GPIO

Industrial temperature range (-40°C to +85°C)

8x8mm 56-lead QFN – pin compatible with JN5121

-free and RoHS compliant

i JN-DS-JN513x v1.1 © Jennic 2007

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Contents

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1 Introduction 1

1.1 Wireless Microcontroller 1

1.2 Wireless Transceiver 1

1.3 RISC CPU and Memory 1

1.4 Peripherals 2

1.5 Block Diagram 3

2 Pin Configurations 4

2.1 Pin Assignment 5

2.2 Pin Descriptions 6

2.2.1 Power Supplies 6

2.2.2 Reset 6

2.2.3 16MHz System Clock 6

2.2.4 Radio 6

2.2.5 Analogue Peripherals 6

2.2.6 Digital Input/Output 7

3 CPU 8

4 Memory Organisation 9

4.1 ROM 10

4.2 RAM 10

4.3 OTP eFuse Memory 10

4.4 External Memory 11

4.4.1 Secure External Memory Encryption 11

4.5 Peripherals 11

4.6 Unused Memory Addresses 11

5 System Clocks 12

5.1 16MHz Oscillator 12

5.2 32kHz Oscillator 12

6 Reset 13

6.1 Power-on Reset 13

6.2 External Reset 13

6.3 Software Reset 14

6.4 Brown-out Detect 14

7 Interrupt System 15

7.1 System Calls 15

7.2 Processor Exceptions 15

7.2.1 Bus Error 15

7.2.2 Alignment 15

7.2.3 Illegal Instruction 15

7.3 Hardware Interrupts 16

8 Wireless Transceiver 17

8.1 Radio 17

8.1.1 Radio External components 18

8.1.2 Antenna Diversity 18

8.2 Modem 19

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8.3 Baseband Processor 20

8.3.1 Transmit 20

8.3.2 Reception 20

8.3.3 Auto Acknowledge 21

8.3.4 Beacon Generation 21

8.3.5 Security 21

8.4 Security Coprocessor 21

9 Digital Input/Output 22

10 Serial Peripheral Interface 23

10.1 Programming Example 25

11 Intelligent Peripheral Interface 27

11.1 Data Transfer Format 27

11.2 JN513x Initiated Data Transfer 28

11.3 Remote Processor Initiated Data Transfer 28

12 Timers 29

12.1 Peripheral Timer / Counters 29

12.1.1 Pulse Width Modulation Mode 30

12.1.2 Capture Mode 30

12.1.3 Counter / Timer Mode 31

12.1.4 Delta-Sigma Mode 31

12.1.5 Timer / Counter Application 32

12.2 Tick Timer 33

12.3 Wakeup Timers 34

12.3.1 RC Oscillator Calibration 34

12.3.2 External 32kHz Clock Source 35

13 Serial Communications 36

13.1 Interrupts 37

13.2 UART Application 37

13.3 Programming Example 38

14 Two-Wire Serial interface 39

14.1 Connecting Devices 40

14.2 Multi-Master Operation 40

14.3 Clock Stretching 41

14.4 Programming Example 41

15 Analogue Peripherals 43

15.1 Analogue to Digital Converter 44

15.1.1 Operation 44

15.1.2 Supply Monitor 44

15.1.3 Temperature Sensor 45

15.1.4 Programming Example 45

15.2 Digital to Analogue Converter 45

15.2.1 Operation 45

15.2.2 Programming Example 46

15.3 Comparators 46

16 Power Management and Sleep Modes 48

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16.1 Operating Modes 48

16.1.1 Power Domains 48

16.2 Active Processing Mode 48

16.2.1 CPU Doze 48

16.3 Sleep Mode 48

16.3.1 Wakeup Timer Event 49

16.3.2 DIO Event 49

16.3.3 Comparator Event 49

16.4 Deep Sleep Mode 49

17 Electrical Characteristics 50

17.1 Maximum ratings 50

17.2 DC Electrical Characteristics 50

17.2.1 Operating Conditions 50

17.2.2 DC Current Consumption 51

17.2.3 I/O Characteristics 52

17.3 AC Characteristics 52

17.3.1 Reset 52

17.3.2 Brown-out Detect 53

17.3.3 SPI Timing 54

17.3.4 Two-wire serial interface 54

17.3.5 Power Down and Wake-Up timings 55

17.3.6 32kHz Oscillator 56

17.3.7 16MHz Crystal Oscillator 56

17.3.8 Analogue to Digital Converters 56

17.3.9 Digital to Analogue Converters 57

17.3.10 Comparators 58

17.3.11 Temperature Sensor 59

17.3.12 Radio Transceiver 59

Appendix A Mechanical and Ordering Information 63

A.1 56pin QFN Package Drawing 63 A.2 Ordering Information 64 A.3 Device Package Marking 65 A.4 Tape and Reel Information 66 A.4.1 Tape Orientation and Dimensions 66 A.4.2 Reel Information: 7” Reel 67 A.4.3 Reel Information: 13” Reel 68 A.4.4 Dry Pack Requirement for Moisture Sensitive Material 68 A.5 PCB Design and Reflow Profile 69

Appendix B Development Support 70

B.1 Crystal Oscillator 70 B.1.1 Crystal Equivalent Circuit 70 B.1.2 Crystal Load Capacitance 71 B.1.3 Crystal ESR and Required Transconductance 71 B.2 16MHz Oscillator 73 B.3 Applications Schematic 74

Appendix C 75

Related Documents 75 RoHS Compliance 75

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Status Information 75 Disclaimers 76 Version Control 76 Contact Details 77

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1 Introduction

The JN513x is an IEEE802.15.4 wireless microcontroller that provides a fully integrated solution for applications using the IEEE802.15.4 standard in the 2.4 - 2.5GHz ISM frequency band [1], including ZigBee. It includes all of the functionality required to meet the IEEE802.15.4 specification and has additional processor capability to run a wide range of applications including but not limited to Remote Control, Home and Building Automation, Toys and Gaming.

The device includes a Wireless Transceiver, RISC CPU, on-chip memory and an extensive range of peripherals.

1.1 Wireless Microcontroller

Applications that transfer data wirelessly tend to be more complex than wired ones. Wireless protocols make stringent demands on frequencies, data formats, timing of data transfers, security and other issues. Application development must consider the requirements of the wireless network in addition to the product functionality and user interfaces. To minimise this complexity, Jennic provides a series of software libraries that control the transceiver and peripherals of the JN513x. These libraries, with functions called by an Application Programming Interface (API) remove the need for the developer to understand wireless protocols and greatly simplify the programming complexities of power modes, interrupts and hardware functionality. In addition, the JN513x is expected to be programmed in the C high-level language and debugged using the JN5 series software developer kit.

In view of the above, the register details of the JN513x are not provided in the datasheet and access to all peripherals is gained using API calls to the peripheral library. Extensive reference to such calls is made throughout the datasheet and the convention used is to format the function call in the courier font e.g. function calls can be found in the JN-RM-2001 Integrated Peripherals API [2].

An IEEE802.15.4 compliant wireless network can be developed using the IEEE802.15.4 MAC library described in JNRM-2002 802.15.4 Stack [3]. Applications over simple (point-point, star or tree) wireless networks can use this library directly or more complex wireless mesh networks such as ZigBee or IPv6 can be built on top of the IEEE802.15.4 library.

vAHI_Init()

. Full details of these

1.2 Wireless Transceiver

The Wireless Transceiver is highly integrated and, together with the IEEE802.15.4 MAC library requires little knowledge of RF or wireless design.

The Wireless Transceiver comprises a low-IF 2.45GHz radio, an O-QPSK modem, a baseband controller and a security coprocessor. The radio has a 200Ω resistive differential antenna port that includes all the required matching components on-chip, allowing a differential antenna to be connected directly to the port, minimising the system BOM costs. Connection to a single ported antenna can be achieved using a 200/50Ω 2.45GHz balun. In addition, the radio also provides an output to control transmit-receive switching of external devices such as power amplifiers allowing applications that require increased transmit power to be realised very easily.

The Security coprocessor provides hardware-based 128-bit AES-CCM, CBC specified by the 802.15.4b standard. It does this in-band on packets during transmission and reception, requiring minimal intervention from the CPU. It is also available for off-line use under software control for encrypting and decrypting packets generated by software layers such as Zigbee and user applications. This means that these algorithms can be off-loaded by the CPU, increasing the processor bandwidth available for user applications.

The transceiver elements (radio, modem and baseband) work together to provide 802.15.4 Medium Access Control under the control of a protocol stack supplied with the device as a software library. Applications incorporating IEEE802.15.4 functionality can be rapidly developed by combining user-developed application software with this library. The facilities provided by this library to applications together with examples of their use are described in more detail in [3].

(1) AES-CBC processing is only available off-line for use under software control.

(1)

, CTR and CCM* processing as

1.3 RISC CPU and Memory

A 32-bit RISC CPU allows software to be run on-chip, its processing power being shared between the IEEE802.15.4 MAC protocol, other higher layer protocols and the user application. The JN513x has a unified memory architecture, code memory, data memory, peripheral devices and I/O ports are organized within the same linear address space.

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The device contains 192kBytes of ROM, a choice of 8k, 16k, 32k or 96kBytes of RAM and a 48-byte OTP eFuse memory.

1.4 Peripherals

The following peripherals are available on-chip:

Master SPI port with five select outputs

•

Two UARTs

•

Two programmable Timer/Counters with capture/compare facility

•

Two programmable Sleep Timers and a Tick Timer

•

Two-wire serial interface (compatible with SMbus and I2C)

•

Slave SPI port (shared with digital I/O)

•

Twenty-one digital I/O lines (multiplexed with UARTs, timers and SPI selects)

•

Four-channel, 12-bit, 100ksps Analogue-to-Digital converter

•

Two 11-bit Digital-to-Analogue converters

•

Two programmable analogue comparators

•

Internal temperature sensor and battery monitor

•

User applications access the peripherals using the Hardware Peripheral Library with a simple API. This allows applications to use a tested and easily understood view of the peripherals allowing rapid system development. The JN-RM-2001 Integrated Peripherals API [2] describes this interface in more detail.

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1.5 Block Diagram

VB_xx

VDD1

VDD2

RESETN

XTALIN

XTALOUT

COMP1M

COMP1P

COMP2M

COMP2P

Tick Timer

Programmable

Interrupt

Controller

From Peripherals

RAM

8k - 96kB

ROM

192kB

Voltage

Regulators

Reset

Wakeup

WT1

WT0

Clock

Generator

Comparator1

Comparator2

32-bit RISC CPU

OTP

eFuse

48-byte

1.8V

32kHz

Osc

2 x

Clock

SPI

UART0

UART1

Timer0

Timer1

2-wire

interface

Intelligent

Peripheral

Wireless

Transceiver

Security

Coprocessor

SPICLK SPIMOSI SPIMISO SPISEL0

DIO0/SPISEL1 DIO1/SPISEL2 DIO2/SPISEL3/RFRX DIO3/SPISEL4/RFTX

DIO4/CTS0 DIO5/RTS0 DIO6/TXD0 DIO7/RXD0

DIO17/CTS1/IP_SEL DIO18/RTS1/IP_INT DIO19/TXD1

M U X

DIO20/RXD1

DIO8/TIM0CK_GT DIO9/TIM0CAP/CLK32K DIO10/TIM0OUT

DIO11/TIM1CK_GT DIO12/TIM1CAP DIO13/TIM1OUT

DIO14/SIF_CLK/IP_CLK DIO15/SIF_D/IP_DO

DIO16/IP_DI

DAC1

DAC2

ADC1 ADC2 ADC3 ADC4

M U X

DAC1

DAC2

Supply

Monitor

ADC

Temperature

Sensor

Baseband Controller

Modem

Radio

RFM RFP

VCOTUNE IBAIS

Figure 1: JN513x Block Diagram

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2 Pin Configurations

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DIO16/IP_DI 1

DIO17/CTS1/IP_SEL

VB_DIG2

DIO18/RTS1/IP_INT

DIO19/TXD1

DIO20/RXD1

VSS2

RESETN

VSS3

VSSS

XTALOUT

XTALIN

VB_SYN

VCOTUNE

DIO15/SIF_D/IP_DO

DIO13/TIM1OUT

DIO14/SIF_CLK/IP_CLK

DIO11/TIM1CK_GT

DIO12/TIM1CAP

DIO9/TIM0CAP/CLK32K

DIO10/TIM0OUT

JN513x

(pin compatible with JN5121)

DIO6/TXD0

DIO7/RXD0

DIO8/TIM0CK_GT

VDD2

DIO5/RTS0

DIO3/SPISEL4/RFTX

DIO4/CTS0

DIO2/SPISEL3/RFRX

DIO1/SPISEL2

VB_MEM

VSS1

DIO0/SPISEL1

SPISEL0

SPIMOSI

VB_DIG1

SPIMISO

SPICLK

COMP2M

COMP2P

DAC2

DAC1

RFP

VDD1

VB_VCO

COMP1M

IBIAS

COMP1P

RFM

ADC1

ADC2

VB_RF

VREF

ADC3

VB_A

ADC4

Figure 2: 56-pin QFN Configuration (top view)

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2.1 Pin Assignment

Pin No Power supplies Description

3, 13, 15, 21 28, 35, 40

16, 49 VDD1, VDD2 Device supplies: VDD1 for analog, VDD2 for digital

7, 9, 10, 39 Paddle VSS2, VSS3, VSSS, VSS1, VSSA Device grounds (see appendix A.1 for paddle details)

8 RESETN Reset input

11, 12 XTALOUT, XTALIN System crystal oscillator

14 VCOTUNE VCO tuning RC network

19 IBIAS Bias current control

20, 22 RFP, RFM Differential antenna port

24, 25, 26, 27 ADC1, ADC2, ADC3, ADC4 ADC inputs

23 VREF Analogue peripheral reference voltage

29, 30 DAC1, DAC2 DAC outputs

17, 18, 31, 32 COMP1M, COMP1P, COMP2P, COMP2M Comparator inputs

33 SPICLK SPI Clock

36 SPIMOSI SPI Master Out Slave In

34 SPIMISO SPI Master In Slave Out

37 SPISEL0 SPI Slave Select Input/Output 0

38 DIO0 SPISEL1 DIO0 or SPI Slave Select Output 1

41 DIO1 SPISEL2 DIO1 or SPI Slave Select Output 2

42 DIO2 SPISEL3, RFRX DIO2 or SPI Slave Select Output 3 or

43 DIO3 SPISEL4, RFTX

44 DIO4 CTS0 DIO4 or UART 0 Clear To Send Input

45 DIO5 RTS0 DIO5 or UART 0 Request To Send Output

46 DIO6 TXD0 DIO6 or UART 0 Transmit Data Output

47 DIO7 RXD0 DIO7 or UART 0 Receive Data Input

48 DIO8 TIM0CK_GT DIO8 or Timer0 Clock/Gate Input

50 DIO9 TIM0CAP,CLK32K DIO9 or Timer0 Capture Input or CLK32K

51 DIO10 TIM0OUT DIO10 or Timer0 PWM Output

52 DIO11 TIM1CK_GT DIO11 or Timer1 Clock/Gate Input

53 DIO12 TIM1CAP DIO12 or Timer1 Capture Input or Antenna Diversity

54 DIO13 TIM1OUT DIO13 or Timer1 PWM Output or Antenna Diversity

55 DIO14 SIF_CLK, IP_CLK

56 DIO15 SIF_D, IP_DO

1 DIO16 IP_DI DIO16 or Intelligent Peripheral Data In

2 DIO17 CTS1, IP_SEL

4 DIO18 RTS1, IP_INT

5 DIO19 TXD1 DIO19 or UART 1 Transmit Data Output

6 DIO20 RXD1 DIO20 or UART 1 Receive Data Input

VB_DIG2, VB_SYN, VB_VCO, VB_RF, VB_A, VB_DIG1, VB_MEM

General

Radio

Analogue Peripheral I/O

Digital I/O

Primary Function Alternate Function

Regulated supply voltage

Radio Receive Control Output

DIO3 or SPI Slave Select Output 4 or Radio Transmit Control Output

DIO14 or Serial Interface Clock or Intelligent Peripheral Clock Input

DIO15 or Serial Interface Data or Intelligent Peripheral Data Out

DIO17 or UART 1 Clear To Send Input or Intelligent Peripheral Device Select Input

DIO18 or UART 1 Request To Send Output or Intelligent Peripheral Interrupt Output

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2.2 Pin Descriptions

2.2.1 Power Supplies

The device is powered from the VDD1 and VDD2 pins, each being decoupled with a 100nF ceramic capacitor. VDD1 is the power supply to the analogue circuitry; it should be decoupled to analogue ground. VDD2 is the power supply for the digital circuitry; it should be decoupled to digital ground. A 10uF tantalum capacitor is required at the common ground star point of analogue and digital supplies. Decoupling pins for the internal 1.8V regulators are provided which require a 100nF capacitor located as close to the device as practical. VB_VCO, VB_RF, VB_A and VB_SYN should be decoupled to analogue ground, while VB_MEM, VB_DIG1 and VB_DIG2 should be decoupled to digital ground. See also Appendix B for connection details.

VSSA is the analogue ground, connected to the paddle of the device, while VSSS, VSS1, VSS2, VSS3 are digital ground pins.

2.2.2 Reset

RESETN is a bi-directional active low reset pin that is connected to a 45kΩ internal pull-up resistor. It may be pulled low by an external circuit, or can be driven low by the JN513x if an internal reset is generated. Typically, it will be used to provide a system reset signal. Refer to section 6.2, External Reset, for more details.

2.2.3 16MHz System Clock

A crystal connected between XTALIN and XTALOUT drives the system clock. A capacitor to analogue ground is required on each of these pins. Refer to section 5.1 16MHz Oscillator for more details.

2.2.4 Radio

A 200Ω balanced antenna (such as a printed circuit antenna) can be connected directly to the radio interface pins RFM and RFP.

A single-ended 50Ω antenna such as a ceramic type or SMA connector for an external antenna requires the addition of a 200/50Ω 2.45GHz balun transformer connected to the antenna pins. The balun differential port should be connected to the antenna port with 200Ω balanced controlled impedance track. A 50Ω controlled impedance track should be used to connect the unbalanced port of the balun to the antenna to ensure good impedance matching and reduce losses and reflections.

A simple external loop filter circuit consisting of two capacitors and a resistor is connected to VCOTUNE. Refer to section 8.1 Radio for more details.

An external resistor (43kΩ) is required between IBIAS and analogue ground to set various bias currents and references within the radio.

2.2.5 Analogue Peripherals

Several of the analogue peripherals require a reference voltage to use as part of their operations. They can use either an internal reference voltage or an external reference connected to VREF. This voltage is referenced to analogue ground and the performance of the analogue peripherals is dependant on the quality of this reference.

There are four ADC inputs, two comparator inputs and two DAC outputs. The analogue I/O pins on the JN513x can have signals applied up to 0.3v higher than VDD1. A schematic view of the analogue I/O cell is shown in Figure 3 Analogue I/O Cell.

In reset and deep sleep the analogue peripherals are all off and the DAC outputs are in a high impedance state. During sleep the ADC and DAC’s are off, with the DAC outputs in a high impedance state and the comparator may optionally be used as a wakeup.

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VDD1

Analogue

I/O Pin

Analogue

Peripheral

VSSA

Figure 3 Analogue I/O Cell

2.2.6 Digital Input/Output

Digital I/O pins on the JN513x can have signals applied up to 2V higher than VDD2 and are therefore TTL-compatible with VDD2 > 3V. For other DC properties of these pins see section 17.2.3 I/O Characteristics.

When used in their primary function all Digital Input/Output pins are bi-directional and are connected to weak internal pull up resistors (45kΩ nominal) that can be disabled. When used in their secondary function (selected when the appropriate peripheral block is enabled) their direction is fixed by the function.

A schematic view of the digital I/O cell is in Figure 4: DIO Pin Equivalent Schematic.

VDD2

PROT

DIO[x] Pin

VSS

Figure 4: DIO Pin Equivalent Schematic

Each DIO pin configuration is programmed by functions in Hardware Peripheral Library. The pin direction is set by calling the which uses the cell as part of its I/O. The use of the pull-up resistor Rpu for each pin is controlled through the

vAHI_DioSetPullup()

In reset, the digital peripherals are all off and the DIO pins are set as high-impedance inputs. During sleep and deep sleep, the DIO pins retain both their input/output state and output level that was set as sleep commences. If the DIO pins were enabled as inputs and the interrupts were enabled these pins may be used to wake up the JN513x from sleep.

vAHI_DioSetDirection()

routine in the peripheral library.

function that enables OE and IE as required, or by enabling a peripheral

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3 CPU

The CPU of the JN513x is a 32-bit load and store RISC processor. It has been architected for three key requirements:

Low power consumption for battery powered applications

•

High performance to implement a wireless protocol at the same time as complex applications

•

Efficient coding of high-level languages such as C/C++ provided with the Jennic Software Developers Kit

•

It features a linear 32-bit logical address space with unified memory architecture, accessing both code and data in the same address space. Registers for peripheral units, such as the timers, UARTs and the baseband processor are also mapped into this space.

The CPU contains a block of 32 32-bit General-Purpose (GP) registers together with a small number of special purpose registers which are used to store processor state and control interrupt handling. The contents of any GP register can be loaded from or stored to memory, while arithmetic and logical operations, shift and rotate operations, and signed and unsigned comparisons can be performed either between two registers and stored in a third, or between registers and a constant carried in the instruction. Operations between general or special-purpose registers execute in one cycle (16/32MHz) while those that access memory require a further cycle to allow the memory to respond.

The instruction set manipulates 8, 16 and 32-bit data; this means that programs can use objects of these sizes very efficiently. Manipulation of 32-bit quantities is particularly useful for protocols and high-end applications allowing algorithms to be implemented in fewer instructions than on smaller word-size processors, and to execute in fewer clock cycles. In addition, the CPU supports hardware Multiply that can be used to efficiently implement algorithms needed by Digital Signal Processing applications.

The instruction set is designed for the efficient implementation of high-level languages such as C. Access to fields in complex data structures is very efficient due to the provision of several addressing modes, together with the ability to be able to use any of the GP registers to contain the address of objects. Subroutine parameter passing is also made more efficient by using GP registers rather than pushing objects on the stack. The recommended programming method for the JN513x is by using C, which is supported by a software developer kit comprising a C compiler, linker and debugger.

The CPU architecture also contains features that make the processor suitable for embedded, real-time applications. In some applications, it may be necessary to use a real-time operating system to allow multiple tasks to run on the processor. To provide protection for device-wide resources being altered by one task and affecting another, the processor can run in either supervisor or user mode, the former allowing access to all processor registers, while the latter only allows the GP registers to be manipulated. Supervisor mode is entered on reset or interrupt; tasks starting up would normally run in user mode in a RTOS environment.

Embedded applications require efficient handling of external hardware events. Exception processing (including reset and interrupt handling) is enhanced by the inclusion of a number of special-purpose registers into which the PC and status register contents are copied as part of the operation of the exception hardware. This means that the essential registers for exception handling are stored in one cycle, rather than the slower method of pushing them onto the processor stack. The PC is also loaded with the vector address for the exception that occurred, allowing the handler to start executing in the next cycle.

To improve power consumption a number of power-saving modes are implemented in the JN513x, described more fully in section 16 - Power Management and Sleep Modes. One of these modes is the CPU doze mode, under software control, the processor can be shut down and on an interrupt it will wake up to service the request.

The CPU clock may be optionally doubled using a 2x clock input. Using the 2x clock mode enables the CPU to clocked at 32MHz and therefore able to sustain 32 MIPs.

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4 Memory Organisation

This section describes the different memories found within the JN513x. The device contains ROM, RAM, OTP memory, the wireless transceiver and peripherals all within the same linear address space.

0xEFFFFFFF0xFFFFFFFF 0x980001FF

0x98000000

0x90000013

0x90000000

0x80000017

0x80000000

0x70000013

0x70000000

0x6000001B

0x60000000

0x5000001B

0x50000000

0x4000007F

0x40000000

0x3000007F

0x30000000

0x2000000B

0x20000000

0x10000F23

0x10000F00

0x10000E57

0x10000E00 0x10000DFF

0x10000C00

0x100009FF

0x10000400

0x100000FF

0x10000000

0xF0018000

0xF0008000

0xF0004000

0xF0002000

0xF0000000

0x10000000

0x04000000

0x00030000

0x00000000

RAM

(96kB)

(32kB)

(16kB)

(8kB)

PeripheralsUnpopulated

RAM Echo

ROM

(192kB)

Intelligent Peripheral

Memory Block

Intelligent Peripheral

SPI

2-Wire Interface

Timer1

Timer0

UART1

UART0

GPIO

Analogue Peripherals

PHY Controller

Security Coprocessor

Baseband Controller

System Controller

Figure 5: JN513x Memory Map

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4.1 ROM

The ROM is 192K bytes in size, organized as 48k x 32-bit words and can be accessed by the CPU in a single clock cycle. The ROM contents change for different versions of the device to support differing protocol stacks and applications, all versions carry a default interrupt vector table and interrupt manager. Variants that can be used for application or protocol development carry a boot loader, to allow code from external Flash memory to be bootloaded into RAM at runtime. The operation of the boot loader is described in detail in Application Note JN-AN-1003 Boot Loader Operation [4]. For development variants the interrupt manager routes interrupt calls to the application’s soft interrupt vector table contained within RAM. Section 7 contains further information regarding the handling of interrupts. Typical ROM contents for a development variant containing a ZigBee protocol stack is shown in Figure 6.

0x0002FFFF

0x00000F00

0x00000000

Figure 6: Typical ROM contents

Unused

ZigBee Stack

IEEE802.15.4

Stack

Boot Loader

Interrupt Manager

Interrupt Vectors

4.2 RAM

The JN513x contains 8k, 16k, 32k or 96k bytes of high speed RAM organized as 2k, 4k, 8k or 24k x 32-bit words respectively. It can be used for both code and data storage and is accessed by the CPU in a single clock cycle. At reset, a boot loader controls the loading of segments of code and data from an external memory connected to the SPI port, into RAM. Software can control the power supply to the RAM allowing the contents to be maintained during a sleep period when other parts of the device are un-powered.

4.3 OTP eFuse Memory

The JN513x contains 48-bytes of eFuse memory; this is one time programmable memory that is organised as 12 x 32-bit words, 4 words are reserved by Jennic, 2 of which support on-chip MAC ID. The remaining 8 words are fully user programmable, designed to allow the storage of configuration and product information. If secure external memory encryption is enabled then 4 words of the user eFuse are used for this (see section 4.4.1)

At a low level, programming of the eFuse requires for a sequence of carefully controlled steps, therefore to simplify the procedure, a simple API function call through software is provided that handles the various sequences required, this is described in JN-RM-2001 Integrated Peripherals API [2]. For reliable programming operation, a minimum system supply voltage VDD2 of 3.3V must be provided. If this condition is not satisfied, then programming reliability cannot be guaranteed.

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4.4 External Memory

An external memory with an SPI interface may be used to provide storage for program code and data for the device when external power is removed. The memory is connected to the SPI interface using select line SPISEL0; this select line is dedicated to the external memory interface and is not available for use with other external devices. See Figure 7 for connection details.

JN513x

SPISEL0

SPIMISO

SPIMOSI

SPICLK

Figure 7: Connecting External Serial Memory

At reset, the contents of this memory are copied into RAM by the software boot loader. A number of types of memory device may be used with the JN513x boot loader so long as they conform to the format of read instructions issued by the boot loader over the SPI interface. See application note [4] JN-AN-1003 Boot Loader Operation for details on the format of the read command and other details of the boot loader.

Serial

Memory

SDO

SDI

CLK

4.4.1 Secure External Memory Encryption

The contents of the external serial memory may be securely encrypted to protect against system cloning or intrusion. The AES security processor combined with a user programmable 128-bit encryption key is used to encrypt the contents of the external memory. The encryption key is stored in eFuse and is programmed through software control. Initially after programming, the encryption feature is not active; this allows the system to continue to operate in an unsecured mode. Enabling of the encryption feature is through software control, once enabled all programming operations require authentication. Full details of the eFuse software functions may be found in JN-RM-2001 Integrated Peripherals API [2].

When bootloading program code from external serial memory, the JN513x automatically accesses the encryption key to execute the decryption process. User program code, does not need to handle any of the decryption process, it is a transparent process.

4.5 Peripherals

All peripherals have their registers mapped into the memory space. Access to these registers requires 3 clock cycles. Applications have access to the peripherals through the peripherals library, which presents a high-level view of the peripheral’s functions through a series of dedicated software routines. These routines provide both a tested method for using the peripherals and operation of power and interrupts with the IEEE802.15.4 software protocol stack allowing bug-free application code to be developed more rapidly. See JN-RM-2001 Integrated Peripherals API [2] for more details.

4.6 Unused Memory Addresses

Any attempt to access an unpopulated memory area will result in a bus error exception (interrupt) being generated.

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5 System Clocks

Two separate oscillators are used to provide system clocks: a crystal controlled 16MHz oscillator, using an external crystal and an internal, RC based 32kHz oscillator.

5.1 16MHz Oscillator

The JN513x contains the necessary on-chip components to build a 16 MHz reference oscillator with the addition of an external crystal resonator and two tuning capacitors. The schematic and layout of these components are shown in Figure 8. The two capacitors, C1 and C2, should be 15pF ±5% and use a COG dielectric. Due to the small size of these capacitors, it is important to keep the traces to the external components as short as possible. The on-chip transconductance amplifier is compensated for temperature variation, and is self-biasing by means of the internal resistor R1. The electrical specification of the oscillator can be found in section 17.3.6. For detailed application support and specification of the crystal required see Appendix B.1.

JN513x

XTALIN

Figure 8: Crystal oscillator connections

The clock generated by this oscillator provides the reference for most of the JN513x subsystems, including the transceiver, processor, memory and digital and analogue peripherals. The clock for the processor, RAM and ROM may be optionally driven by a 2x clock that effectively clocks these at 32MHz.

XTALOUT

5.2 32kHz Oscillator

The internal 32kHz RC oscillator requires no external components. It provides a low speed clock for use in sleep mode. The clock is used for timing the length of a sleep period (see section 16 Power Management and Sleep Modes) and also to generate the system clock used internally during reset. The internal timing components of the oscillator have a wide tolerance due to manufacturing process variation and so the oscillator runs nominally at 32kHz ±30%. To make this useful as a timing source for accurate wakeup from sleep, a frequency calibration factor derived from the more accurate 16MHz oscillator may be applied. The calibration factor is derived through software, details can be found in section 12.3.1. For detailed electrical specifications, see section 17.3.5.

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6 Reset

A system reset initialises the device to a predefined state and forces the CPU to start program execution from the reset vector. The reset process that the JN513x goes through is as follows.

When power is applied, the 32kHz oscillator starts up and stabilises, which takes approximately 100µsec. At this point, the 16MHz crystal oscillator is enabled and power is applied to processor and peripheral logic. The logic blocks are held in reset until the 16MHz crystal oscillator stabilises, typically this takes 2.5ms.

Once the oscillator is up and running the internal reset is removed from the CPU and peripheral logic and the CPU starts to run code beginning at the reset vector, consisting of initialisation code and then optionally the resident Boot Loader (described in reference [4]).

Section 17.3.1 provides detailed electrical data and timing. Appendix B describes the JN513x pin states during and after reset.

The JN513x has four sources of reset:

Power-on Reset

•

External Reset

•

Software Reset

•

Brown-Out-Detect

•

Note: When the device exits a reset condition, device operating parameters (voltage, frequency, temperature,

etc.) must be met to ensure operation. If these conditions are not met, then the device must be held in reset until the operating conditions are met.

6.1 Power-on Reset

A power-on reset is generated by an on-chip detection circuit eliminating the need for an external reset circuit. The power-on reset is activated whenever VDD is below the detection level, and causes the JN513x to be held in reset. Once VDD has risen above this level, and the power supply and oscillator stabilization time t reset is removed and the CPU is allowed to run. During the time that the internal reset is active the RESETN pin is driven low to provide a reset signal to any other devices in the system.

VDD

Internal RESET

RESETN Pin

Figure 9: Power-on Reset

has elapsed, the

STAB

6.2 External Reset

An external reset is generated by a low level on the RESETN pin. Reset pulses longer than the minimum pulse width will generate a reset during active or sleep modes. Shorter pulses are not guaranteed to generate a reset. The JN513x is held in reset while the RESETN pin is low and when the applied signal reaches the Reset Threshold Voltage (V

) on its positive edge, the internal reset process starts.

RST

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Multiple devices may connect to the RESETN pin in an open-collector mode. The JN513x has an internal pull-up resistor although an external pull-up resistor is recommended when multiple devices connect to the RESETN pin. The pin is an input for an external reset, an output during the power-on reset and may optionally be an output during a software reset. No devices should drive the RESETN pin high.

RESETN pin

Reset

Figure 10: External Reset

Internal Reset

6.3 Software Reset

A system reset can be triggered at any time by calling the Software Reset function, peripheral library. This function can be executed within a users application, upon detection of a system failure for example. The RESETN line can be driven low by the JN513x to provide a reset to other devices in the system (e.g. external sensors). The reset output feature can be enabled or disabled for the software generated reset using the function

vAHI_DriveResetOut()

within the peripheral library (the default state is disabled).

vAHI_SwReset()

from the

6.4 Brown-out Detect

A brown-out detect module is used to monitor the supply voltage to the JN513x; this can be used whilst the device is awake or is in CPU doze mode. Dips in the supply voltage below a variable threshold can be detected and can be used to cause the JN513x to perform a chip reset. Equally, dips in the supply voltage can be detected and used to cause an interrupt to the processor, when the voltage either drops below the threshold or rises above it. Hysteresis is built into the brown out detect module this is nominally 100mV.

The threshold voltage is selectable at levels of 2.1V, 2.4V, 2.5V or 2.6V through software control, this is described in JN-RM-2001 Integrated Peripherals API [2].

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7 Interrupt System

The interrupt system on JN513x is a hardware-vectored interrupt system. The JN513x provides several interrupt sources, some associated with CPU operations (CPU exceptions) and others which are used by hardware in the device. When an interrupt occurs the CPU stops executing the current program and loads its program counter with a fixed hardware address specific to that interrupt. The interrupt handler or interrupt service routine is stored at this location and is run on the next CPU cycle. Execution of interrupt service routines is always performed in supervisor mode. Interrupt sources and their vector locations are listed in Table 1 below:

Interrupt Source Vector Location Interrupt Definition

Reset 0x100 Software or hardware reset

Bus Error 0x200 Bus error or attempt to access invalid physical address Tick Timer 0x500 Tick Timer expiry Alignment 0x600 Load/Store to naturally not aligned location

Illegal Instruction 0x700 Illegal instruction in instruction stream Hardware Interrupts 0x800 Hardware Interrupt

System Call 0xC00 System Call Initiated by software (l.sys instruction) Trap 0xE00 Caused by l.trap instruction

Table 1: Interrupt Vectors

7.1 System Calls

Executing the allow a task to switch into supervisor mode when a real time operating system is in use, see section 3 for further details. It also allows a software interrupt to be issued, as does execution of the

instruction causes a system call interrupt to be generated. The purpose of this interrupt is to

l.sys

l.trap

instruction.

7.2 Processor Exceptions

7.2.1 Bus Error

A bus error exception is generated when software attempts to access a memory address that does not exist, or is not populated with memory or peripheral registers.

7.2.2 Alignment

Alignment exceptions are generated when software attempts to access objects that are not aligned to natural word boundaries. 16-bit objects must be stored on even byte boundaries, while 32-bit objects must be stored on quad byte boundaries. For instance, attempting to read a 16-bit object from address 0xFFF1 will trigger an alignment exception as will a read of a 32-bit object from 0xFFF1, 0xFFF2 or 0xFFF3. Examples of legal 32-bit object addresses are 0xFFF0, 0xFFF4, 0xFFF8 etc.

7.2.3 Illegal Instruction

If the CPU reads an unrecognised instruction from memory as part of its instruction fetch, it will cause an illegal instruction exception.

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7.3 Hardware Interrupts

Hardware interrupts generated from the transceiver, analogue or digital peripherals and DIO pins are individually masked using the Programmable Interrupt Controller (PIC). Management of interrupts is provided in the peripherals library. Further details of interrupts are provided for the functions in their respective sections in this datasheet.

Interrupts are used to wake the JN513x from sleep. The peripherals, baseband controller, security coprocessor and PIC are powered down during sleep but the DIO interrupts and optionally the wake-up timers and analogue comparator interrupts remain powered to bring the JN513x out of sleep.

Wake-up

Timers

Baseband

Controller

Security

Coprocessor

DIO Pins

UART0

Programmable

Interrupt

Controller

UART1

Timer0

Timer1

2-wire Serial

Interface

SPI Controller

Intelligent

Peripheral

Analogue

Peripheral

Hardware

Interrupt

Figure 11: Programmable Interrupt Controller

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8 Wireless Transceiver

The wireless transceiver comprises a 2.45GHz radio, an O-QPSK modem, a baseband processor, a security coprocessor and PHY controller. These blocks, with protocol software provided as a library, implement an IEEE802.15.4 standards-based wireless transceiver that transmits and receives data over the air in the unlicensed

2.4GHz band. IEEE802.15.4 wireless functionality is provided with the transceiver and the protocol software described in JN-RM-2002 802.15.4 Stack [3]. Applications interface to the protocol software via an API interface that corresponds to the SAP interfaces defined in the IEEE Std 802.15.4-2006 [1]

8.1 Radio

IDATA

QDATA

IF DATA

AGC

Power

LNA

LOQ

LOI

VGA

LOI

LOQ

Calibration

LOI

LOQ

PLL

VGA1

VCO

PA (I)

Trim

VGA

PA (Q)

Trim

VGA2

Calibration

DAC

ADC

Reference

& BIAS

Figure 12: Radio Architecture

The radio comprises a low-IF receive path and a direct up-conversion transmit path, which converge at the TX/RX switch. This switch includes the necessary matching components such that a 200Ω differential antenna may be directly connected without external components. Alternatively, a balun can be used for single ended antennas.

The 16MHz crystal oscillator feeds a divider, which provides the frequency synthesiser with a reference frequency. The synthesiser contains programmable feedback dividers, phase detector, charge pump and internal Voltage Controlled Oscillator (VCO). The VCO has no external components, and includes calibration circuitry to compensate for differences in internal component values due to process and temperature variations. The VCO is controlled by a Phase Lock Loop (PLL) that has a loop filter comprising 3 external components. A programmable charge pump is also used to tune the loop characteristic. Finally, quadrature (I and Q) local oscillator signals for the mixer drives are derived.

The receiver chain starts with the low noise amplifier / mixer combination whose outputs are passed to the polyphase bandpass filter. This filter provides the channel definition as well as image frequency rejection. The signal is then passed to two variable gain amplifier blocks. The gain control for these stages, and the bandpass filter, is derived in the automatic gain control (AGC) block within the Modem. The signal is conditioned with the anti-alias low pass filter, before being converted to a digital signal with a flash ADC.

In the transmit direction, the digital I and Q streams from the Modem are passed to I and Q quadrature DAC blocks which are buffered and low-pass filtered, before being applied to the modulator mixers. The summed 2.4 GHz signal is then passed to the RF Power Amplifier (PA), whose power control can be selected from one of six settings. The output of the PA drives the antenna via the RX/TX switch.

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8.1.1 Radio External components

The VCO loop filter requires three external components and the IBIAS pin requires one external component as shown in Figure 13. These components should be placed close to the JN513x pins and analogue ground.

VCOTUNE

3n3F

VB_VCO

100nF

VSSA

4k7

330pF

Figure 13: VCO Loop Filter and IBIAS

The radio is powered from a number of internal 1.8V regulators fed from the analogue supply VDD1, in order to provide good noise isolation between the digital logic of the JN513x and the analogue blocks. These regulators are also controlled by the baseband controller and protocol software to minimise power consumption. Decoupling for internal regulators is required as described in section 2.2.1, Power Supplies.

IBIAS

43k 1%

VSSA

8.1.2 Antenna Diversity

Support is provided for antenna diversity. Antenna diversity is a technique that maximises the performance of an antenna system. It allows the radio to switch between two antennas that have very low correlation between their received signals. Typically, this is achieved by spacing two antennas around 0.25 wavelengths apart or by using two orthogonal polarisations. So, if a packet is transmitted and no acknowledgement is received, the radio system can switch to the other antenna for the retry, with a different probability of success.

The JN513x provides two outputs that can be used to control an antenna switch; this enables antenna diversity to be implemented easily. DIO12 is asserted on odd numbered retires and DIO13 is asserted on the first transmit and even numbered retries.

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8.2 Modem

The Modem performs all the necessary modulation and spreading functions required for digital transmission and reception of data at 250kbps in the 2450MHz radio frequency band in compliance with the IEEE802.15.4 standard.

Gain

IF Signal

AGC

O-QPSK

Demodulation

Symbol

Detection

(Despreading)

RX Data Interface

Pulse Shaping

O-QPSK

Modulation

Spreading

TX Data Interface

Figure 14: Modem Architecture

The transmitter receives symbols from the baseband processor and uses the spreading function to map each unique 4-bit symbol to a 32-chip Pseudo-random Noise (PN) sequence. Offset-QPSK modulation and half-sine pulse shaping is applied to the resultant spreading sequence to produce two independent quadrature phase signals (I and Q), which are subsequently converted to analogue voltages in the radio transmit path.

The Automatic Gain Control (AGC) monitors the received signal level and adjusts the gain of the amplifiers in the radio receiver to ensure that the optimum signal amplitude is maintained during reception.

The demodulator performs digital IF down-conversion and matched filtering and is extremely tolerant to carrier frequency offsets in excess of ±80ppm without suffering any significant degradation in performance.

Symbol detection and synchronization is performed using direct sequence correlation techniques in conjunction with searches for the Preamble and Start-of-Frame Delimiter (SFD) fields contained in the transmitted IEEE 802.15.4 Synchronization Header (SHR).

Features are provided to support network channel selection algorithms include Energy Detection (ED), Link Quality Indication (LQI) and fully programmable Clear Channel Assessment (CCA).

The Modem provides a digital Receive Signal Strength Indication (RSSI) that facilitates the implementation of the IEEE 802.15.4 ED function.

The LQI is defined in the IEEE 802.15.4 standard as a characterization of the strength and/or data quality of a received packet. The Modem produces a signal quality metric based upon correlation magnitudes, which may be used in conjunction with the ED value to formulate the LQI.

The CCA capability of the Modem supports all modes of operation defined in the IEEE 802.15.4 standard, namely Energy above ED threshold, Carrier Sense and Carrier Sense and/or energy above ED threshold.

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