NXP UM11423 User Manual
UM11423
LPCXpresso55S16 Development Boards
Rev. 1.3 — 20 October 2020 User manual
Document information
Info Content
Keywords LPC55S16, LPC55S1x, LPCXpresso55S16, LPC55S16-EVK
Abstract LPCXpresso55S16 development board user manual
NXP Semiconductors
UM11423
LPCXpresso55S16 Development Boards
Revision history
Rev Date Description
1.3 20201019 Updated description of JP12 to include an explanation of establishing an external USART
1.2 20200619 Added Section 10.2 “Proper termination resistors required between the MCU and the USB
1.1 20200306 Updated information about crystals.
1.0 20201002 Initial internal release.
connection using JP3. Corrected miscellaneous typos.
connector”.
Updated information about 1.8V operation.
Added clarifications about labeling of external serial connector.
Added section 10 to Errata.
Added information about regulator errata.
Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
UM11423
User manual Rev. 1.3 — 20 October 2020 2 of 20
All information provided in this document is subject to legal disclaimers. © NXP B.V. 2020. All rights reserved.
NXP Semiconductors
1. Introduction
The LPCXpresso™ family of boards provides a powerful and flexible development system
for NXP's LPC Cortex®-M family of MCUs. They can be used with a wide range of
development tools, including NXP's MCUXpresso IDE, Keil uVISION and IAR Embedded
Workbench. The LPCXpresso55S06 board (order code LPC55S06-EVK) is the evaluation
and development platform for the LPC55S1x families of MCUs.
See https://www.nxp.com/demoboard/LPC55S06-EVK for more information on these
boards, including tutorial videos, development software and board hardware design files.
The abbreviation LPC55S1x is used to collectively refer to the LPC55S16 family device on
the board.
UM11423
LPCXpresso55S16 Development Boards
Fig 1. LPCXpresso55S16
The LPCXpresso55S16 board includes the following features:
• LPC55S16 Cortex-M33 processor
• Onboard, high-speed USB, Link2 debug probe with CMSIS-DAP and SEGGER J-Link
protocol options
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User manual Rev. 1.3 — 20 October 2020 3 of 20
NXP Semiconductors
• UART and SPI port bridging from LPC55Sxx target to USB via the onboard debug
probe
• Optional external debug probes with trace option (10 or 20 pin Cortex-M connectors)
• External crystal oscillators
• RGB user LED
• Reset, ISP, User/Wakeup and user buttons
• Multiple Expansion options, including Arduino UNO, Mikroe Click and PMod
• CAN-FD controller and onboard CAN transceiver
• NXP FXOS8700 accelerometer
• Stereo audio codec with line in/out
• High / full speed USB port with micro A/B connector for the host or device functionality
2. Board layout and Settings
UM11423
LPCXpresso55S16 Development Boards
Figure 2 shows the layout of the board (top side), indicating the default location of the
jumpers, while Figure 3 shows locations of the connectors and headers. Table 1 provides
a description of connectors, jumpers, LEDs and buttons.
JP2: USB Host power enable
(1-2 closed, USB0)
JP 15, JP16, J P17: Link2 SWD
(closed)
JS2: USB host selection
(1-2 closed USB0)
JP1: Power Selection
(1-2 closed, 3.3V)
JP6: DFU mode on-board
debugger (open)
JS4: PM OD I2C enable
(closed)
JS5: PM OD I2C enable
(closed)
JP12: UART (closed)
JP9: PMOD SPI/Flexcomm0
UART (open)
JP3: E xternal UART
(1 RXD 2 TXD, 3 GND)
JP21: VDDA power (closed)
JP 18, JP19: C odec (closed)
JP8: Buer power (1-2 closed)
JP7: O n-board debug
target (open)
JP13: Link2 SWD (closed)
JP14: Link2 SWD (closed)
JP20: VDD power (closed)
JS3: Force target M CU
into ISP mode (open)
JP22: VBAT power (closed)
J11: Analog comparator
Input/O utput (open)
Fig. Default jumper locations
Fig 2. Default jumper positions
UM11423 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2020. All rights reserved.
User manual Rev. 1.3 — 20 October 2020 4 of 20
NXP Semiconductors
UM11423
LPCXpresso55S16 Development Boards
J4
J3
J2
J1
U16
D8
J17
J18
J10, J13
J19
J5D4J6
D5
U27
SW4
SW2
SW3
SW1
J8, J7
J9, J12
Fig 3. Board connectors and headers
Table 1. Indicators, buttons, connectors and LEDs
Circuit
Description Default Reference
reference
D5 Target power indicator LED n/a n/a
D8 Link2 boot LED n/a
Section 4.1
D4 RGB User LED (Tri-color Red/Green/Blue) n/a Section 7.5
J5 Audio codec line input jack. n/a Section 7.5
J6 Audio codec line output jack. n/a Section 7.5
JP8 Buffer Power Selection
For On-board Target place in position 1-2 (default)
1-2
Section 3.1,
Section 4.4
For Off-board Target place in position 2-3
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User manual Rev. 1.3 — 20 October 2020 5 of 20
NXP Semiconductors
LPCXpresso55S16 Development Boards
Table 1. Indicators, buttons, connectors and LEDs
Circuit
reference
JP6 Link2 (LPC43xx) force DFU boot.
JP7 Target processor selection for the on-board Debug Probe.
JP2 USB host Vbus selection
JS2 USB host power control selection
JP9 When open (default), the "Bridge" UART and SPI connections from the
JP1 Target VDD power selection. An external supply voltage to the
Description Default Reference
Leave this jumper open (default) for Link2 to follow the normal boot
sequence. The Link2 will boot from internal flash if image is found
there. With the internal flash erased the Link2 normal boot sequence
will fall through to DFU boot.
Install this jumper to force the Link2 to DFU boot mode. Use this setting
to reprogram the Link2 internal flash with a new image (using the
LPCScrypt utility) or to use the MCUXpresso IDE with CMSIS-DAP
protocol.
Note that the Link2 flash is pre-programmed with a version of
CMSIS-DAP firmware by default.
Jumper open (default) the LPC55Sxx Target SWD interface enabled.
Normal operating mode where the Target SWD is connected to either
the on-board Link2 Debug Probe or an external Debug Probe.
Jumper shunted, the LPC55Sxx Target SWD interface is disabled. Use
this setting only when the on-board Link2 Debug Probe is used to
debug an off-board target MCU.
Note that only one of USB0 or USB1 can be configured as a USB host
port at any given time (this is a board restriction, not a limitation of the
LPC55Sxx.)
Install jumper in position 1-2 for USB0 (Full Speed) to provide Vbus (i.e.
enable USB host capability) (Default)
Install jumper in position 2-3 for USB1 (High Speed) to provide Vbus
(i.e. enable USB host capability)
This jumper selects routing of USB port power and overcurrent detect
from either the USB0 or USB1 ports of the LPC55Sxx. Note that only
one of USB0 or USB1 can be configured as a USB host port at any
given time (this is a board restriction, not a limitation of the LPC55Sxx.)
Leave open when using USB1 (High Speed) as a USB host (Default)
Install jumper for USB0 (Full Speed) to provide Vbus (i.e. enable USB
host capability).
Link2 probe are driven to the LPC55Sxx target. Install JP9 when using
the SPI interface at connector J18 and/or FC0 UART at JP3. Note that
this disables the Link2 SPI and UART (bridge) connections.
LPC55Sxx can also be applied through pin 2 of this header.
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Open
Open Section 4.
1-2 (USB0)
Installed
(USB1)
Open
1-2 (3.3V)
2-3 (1.8V)
Section 3.,
Section 4.
Section 6.1
Section 6.1
Section 4.
Section 5.
J2 External +5V power
Micro USB connection for power to the LPC55Sxx target and peripheral
circuitry (excluding Link2 Debug Probe). Must be installed for the USB
host to work.
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User manual Rev. 1.3 — 20 October 2020 6 of 20
n/a Section 5.
Section 6.1
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