UM10540
NVT2001GM and NVT2002DP demo boards
Rev. 1 — 7 March 2012 User manual
Document information
Info Content
Keywords NVT, voltage translator, level translator, level shift, passive voltage
translator, passive level translator, passive level shift, I2C-bus, SMBus,
SPI, NVT2001, NVT2002
Abstract NXP Voltage Translators (NVT) are used in bidirectional signaling voltage
level translation applications for I/O buses with incompatible logic levels.
The NVT2001 and NVT2002 are single- and dual-channel voltage
translators, operational from 1.0 V to 3.6 V at V
1.8 V to 5.5 V at V
open-drain or push-pull I/O devices.
(high voltage side) without direction control for
CC(B)
(low voltage side) and
CC(A)
NXP Semiconductors
UM10540
NVT2001GM and NVT2002DP demo boards
Revision history
Rev Date Description
v.1 20120307 user manual; initial release
Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
UM10540 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
User manual Rev. 1 — 7 March 2012 2 of 7
NXP Semiconductors
019aac711
019aac712
1. Introduction
The NVT2001GM (OM13315) and NVT2002DP (OM 13318) demo boards are designed to
evaluate the NXP 1-channel or 2-channel bidirectional voltage level translators. The demo
boards interface between device I/Os operating at different voltage levels. Since the
NVT2001GM and NVT2002DP devices are passive devices, pull-up resistors may be
needed depending on the I/O interface type (totem pole or open-drain), difference in
translation voltage, and the translation direction (high to low voltage, low to high voltage,
or bidirectional). The NVT2001GM and NVT2002DP devices allow translations between
any voltages from 1.0 V to 5.5 V.
UM10540
NVT2001GM and NVT2002DP demo boards
Please refer to NVT2001/NVT2002 data sheet (Ref. 1
(Ref. 2
) for more detailed information.
a. NVT2001GM (OM13315) b. NVT2002DP (OM13318)
Fig 1. Bidirectional voltage level translators demo boards
) and application note AN11127
UM10540 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
User manual Rev. 1 — 7 March 2012 3 of 7
NXP Semiconductors
2. Hardware description
2.1 Schematic
The demo boards contain footprint s for the NVT2001GM and NVT2002DP devices, where
the jumpers, headers, and passive components are shared. The NVT2001GM and
NVT2002DP demo board schematic is shown in Figure 2
shorted to enable the part. Pins 4 and 1 on J3 are power and GND for the low voltage
side. Pins 4 and 1 on J4 are power and GND for the high voltage side. All Bn I/O pins on
the right side have 10 kΩ pull-up resistors to VREFB and all An I/O pins on the left side
have 10 kΩ pull-up resistors to VREFA through jumper J2. A shunt needs to be installed
at J2 if VREFB − VREFA < 1 V. If VREFB − VREFA ≥ 1 V, then J2 should be open and
resistors R2 and R3 must be removed. If they are not removed, then a resistive path
exists between the A-side I/Os that can impact the efficiency and signal integrity of the
solution.
UM10540
NVT2001GM and NVT2002DP demo boards
. Pins 2 and 3 on J1 must be
Jumper:
ON: if VREFB − VREFA < 1 V
(populated 10 kΩ pull-up resistors)
OFF: if VREFB − VREFA ≥ 1 V
low voltage
J3
4
3
2
1
header 1 × 4
A-side
VREFA
A1
A2
GND
(do not populate 10 kΩ pull-up resistors)
J2
JP
21
10 kΩ
10 kΩ
R3
R2
VREFA
A1
A2
NVT2002DP
2
3
4
1
U1
GND
NVT2001GL
EN
VREFA
A1
2
3
U2
1
6
5
4
GND
EN_Vb
VREFB
B1
Fig 2. NVT2001GM and NVT2002DP demo board schematic
8
7
6
5
EN
VREFB
B1
B2
EN_Vb
C1
0.1 μF
J1
231
R1
200 kΩ
2-3: switch enable
1-2: switch disable
10 kΩ
10 kΩ
R5
R4
high voltage
B-side
VREFB
B1
B2
GND
header 1
002aag940
J4
4
3
2
1
×
4
UM10540 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
User manual Rev. 1 — 7 March 2012 4 of 7
NXP Semiconductors
UM10540
NVT2001GM and NVT2002DP demo boards
2.2 Jumper and header functions
The functions of the jumpers and headers on these demo boards are shown in Table 1.
Table 1. Header descriptions for NVT2001GM (OM13315) and NVT2002DP (OM13318) demo boards
Jumper/header Function Notes
J1 (3-pin) Device switch enable or disable
J2 (2-pin) Connects 10 kΩ pull-up resistors to
J3 (4-pin) Low voltage VREFA, GND and
J4 (4-pin) High voltage VREFB, GND and
control
VREFA on low voltage side for
VREFB − VREFA < 1 V
An I/O signal connect pins
Bn I/O signal connect pins
Short pins 2 and 3 to enable the NVT2001GM or NVT2002DP
device (default). When pins 1 and 2 are shorted, the device is
disabled.
Short pins 1 and 2 to connect 10 kΩ pull-up resistors to VREFA
on low voltage side (default).
Remark: Pins 1 and 2 must be open and 10 kΩ pull-up resistors
must be removed when VREFB − VREFA ≥ 1V.
Pin 1 = VREFA: low voltage power.
Pin 4 = GND: low voltage ground.
A1 is low voltage signal for NVT2001GM.
A[1:2] are low voltage signals for NVT2002DP.
Pin 1 = VREFB: high voltage power.
Pin 4 = GND: high voltage ground.
B1 is high voltage signal for NVT2001GM.
B[1:2] are high voltage signals for NVT2002DP.
3. Abbreviations
Table 2. Abbreviations
Acronym Description
2
C-bus Inter-Integrated Circuit bus
I
I/O Input/Output
SMBus System Management Bus
SPI Serial Peripheral Interface
4. References
[1] NVT2001; NVT2002, “Bidirectional voltage level translator for open-drain and
[2] AN11127, “Bidirectional voltage level translators NVT20xx, PCA9306,
push-pull applications” — Product data sheet; NXP Semiconductors;
www.nxp.com/documents/data_sheet/NVT2001_NVT2002.pdf
GTL2000, GTL2002, GTL2003, GTL2010” — application note;
NXP Semiconductors; www.nxp.com/documents/application_note/AN11127.pdf
UM10540 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
User manual Rev. 1 — 7 March 2012 5 of 7
NXP Semiconductors
5. Legal information
UM10540
NVT2001GM and NVT2002DP demo boards
5.1 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
5.2 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semi conductors’ aggregat e and cumulative liabil ity towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the cu stomer’s own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconduct ors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors product s, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default ,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third part y
customer(s). NXP does not accept any liability in this respect.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Evaluation products — This product is provided on an “as is” and “with all
faults” basis for evaluation purposes only. NXP Semiconductors, its affiliates
and their suppliers expressly disclaim all warranties, whet her express, implied
or statutory, including but not limited to the implied warranties of
non-infringement, merchantability and fitness for a particular purpose. The
entire risk as to the quality, or arising out of the use or performance, of this
product remains with customer.
In no event shall NXP Semiconductors, its affiliates or their su ppliers be liable
to customer for any special, indirect, consequential, punitive or incidental
damages (including without limitation damages for l oss of bu siness, busi ness
interruption, loss of use, loss of data or information, and the like) arising out
the use of or inability to use the product, whether or not based on tort
(including negligence), strict liability, breach of contract, breach of warranty or
any other theory , even if advised of the possibility of such damages.
Notwithstanding any damages that customer might incur for any reason
whatsoever (including without limitation, all damages referenced above and
all direct or general damages), the entire liability of NXP Semiconductors, its
affiliates and their suppliers and customer’s exclusive remedy for all of the
foregoing shall be limited to actual damages incurred by customer based on
reasonable reliance up to the greater of the amount actually paid by customer
for the product or five dollars (US$5.00). The foregoin g limita tions, exclusions
and disclaimers shall apply to the maximum extent permitted by applicable
law, even if any remedy fails of its essential purpose.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
5.3 Trademarks
Notice: All referenced brands, prod uct names, service names and trademarks
are the property of their respective owners.
UM10540 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
User manual Rev. 1 — 7 March 2012 6 of 7
NXP Semiconductors
6. Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2 Hardware description . . . . . . . . . . . . . . . . . . . . 4
2.1 Schematic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.2 Jumper and header functions . . . . . . . . . . . . . . 5
3 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . . 5
4 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
5 Legal information. . . . . . . . . . . . . . . . . . . . . . . . 6
5.1 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
5.2 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
5.3 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
6 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
UM10540
NVT2001GM and NVT2002DP demo boards
Please be aware that important notices concerning th is document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2012. All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 7 March 2012
Document identifier: UM10540
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