NXP UM10375 User Manual

UM10375

LPC1311/13/42/43 User manual

Rev. 5 — 21 June 2012 User manual

Document information

Info Content Keywords ARM Cortex-M3, microcontroller, USB, LPC1311, LPC1313, LPC1342,

LPC1343, LPC1311/01, LPC1313/01

Abstract LPC1311/13/42/43 user manual

NXP Semiconductors

UM10375

LPC13xx User manual

Revision history

Rev Date Description

5 20120621 LPC1311/13/42/43 user manual

Modifications:

• Description of the IP_xxx bits in the interrupt priority registers updated (Table 78 to

Table 92

• Description of the FUNC bits in register IOCON_PIO2_11 updated (Table 123).

• ISP Go command description updated (ARM mode not allowed). See Table 325.

• Description of interrupt use with IAP calls updated (Section 21.8.7).

• Figure 4 updated (RESET updated by internal reset).

• Frequency values for FREQSEL bits in the WDTOSCCTRL register corrected (see

Table 15

• SYSRESSTAT register access changed to R/W (Table 7).

• SRAM use by the bootloader explained in Section 21.2.

• Figure 9 “Standard I/O pin configuration” updated.

4 20110928 LPC1311/13/42/43 user manual

Modifications:

• PDSLEEPCFG register settings updated for parts LPC1311/01 and LPC1313/01 (see

Section 3.5.45.

• Figure 6 up dated and power profile entry address updated in Section 5.4.

• Figure 19 updated.

• Description of UART modem interrupt added in Section 12.6.5.

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Revision history …continued

Rev Date Description

3 20110614 LPC1311/13/42/43 user manual

Modifications:

• Parts LPC1311/01 and LPC1313/01 added.

• Modifications to the user manual applicable to parts LPC1311/01 and LPC1313/01 only:

– SSP1 added for part LPC1313FBD48/01 in Chapter 3 “LPC13xx System

configuration” and Chapter 14 “LPC13xx SSP0/1”.

– UART functions for part LPC1313FBD48/01 added in Table 128, Table 129, , and

Table 138.

– Use of IRC for entering deep power-down updated in Section 3.9.4.2. – Enable sequence for UART clock updated in Section 12.1. – Chapter 5 “LPC13xx Power profiles” added. – Register IOCON_DSR_LOC (Table 140), IOCON_DCD_LOC (Table 141),

IOCON_RI_LOC (Table 142) added.

– Programmable bit OD for pseudo open-drain mode added to IOCON registers in

Chapter 7.

– Chapter 19 “LPC13xx Windowed WatchDog Timer (WWDT)” added.

• Editorial and formatting updates throughout the user manual.

• Pull-up level for internal pull-ups specified in Section 7.3.2 and Section 8.4.1 and

Section 8.4.2.

• Description WDEN bit updated in Tabl e 290 and Table 296 (WDMOD registers).

• Section 3.7 “Start-up behavior” added.

• NVIC priority register bit description updated in Section 6.6.

• Description of GPIO data register updated in Section 9.4.1.

• LPC1342FBD48 package added.

2 20100707 LPC1311/13/42/43 user manual

UM10375

LPC13xx User manual

1 20091106 LPC1311/13/42/43 user manual

Contact information

For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com

User manual Rev. 5 — 21 June 2012 3 of 370

1.1 Introduction

UM10375

Chapter 1: LPC13xx Introductory information

Rev. 5 — 21 June 2012 User manual

The LPC13xx are ARM Cortex-M3 based microcontrollers for embedded applications featuring a high level of integration and low power consumption. The ARM Cortex-M3 is a next generation core that offers system enhancements such as enhanced debug features and a higher level of support block integration.

The LPC13xx operate at CPU frequencies of up to 72 MHz. The ARM Cortex-M3 CPU incorporates a 3-stage pipeline and uses a Harvard arc hit ec tu re with separat e local instruction and data buses as well as a third bus for peripherals. The ARM Cortex-M3 CPU also includes an internal prefetch unit that supports speculative branching.

The peripheral complement of the LPC13xx series includes up to 32 kB of flash memory, up to 8 kB of data memory, USB Device, one Fast-mode Plus (FM+) I UART, four general purpose timers, and up to 42 general purpose I/O pins.

1.2 How to read this manual

This user manual describes parts LPC1311, LPC1313, LPC1342, LPC1343. Part-specific features and registers are listed at the beginning of each chapter.

Remark: The LPC13xx series consists of the LPC1300 series (parts LPC1311/13/42/43) and the LPC1300L series (parts LPC1311/01 and LPC1313/01). The LPC1300L series features the following enhancements over the LPC1300 series:

• Power profiles with lower power consumption in Active and Sleep modes.

• Four levels for BOD forced reset.

• Second SSP controller (LPC1313FBD48/01 only).

• Windowed Watchdog Timer (WWDT).

• Internal pull-up resistors pull up pins to full V

• Programmable pseudo open-drain mode for GPIO pins.

1.3 Features

level.

C interface, one

• ARM Cortex-M3 processor, running at frequencies of up to 72 MHz.

• ARM Cortex-M3 built-in Nested Vectored Interrupt Controller (NVIC).

• 32 kB (LPC1343/13)/16 kB (LPC1342)/8 kB (LPC1311) on-chip flash programming

memory.

• 8 kB (LPC1343/13)/4 kB (LPC1342/11) SRAM.

• In-System Programming (ISP) and In-Application Programming (IAP) via on-chip

bootloader software.

• Selectable boot-up: UART or USB (USB on LPC134x only).

• On LPC134x: USB MSC and HID on-chip drivers.

• Serial interfaces:

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• Other peripherals:

• Serial Wire Debug and Serial Wire Trace port.

• High-current output driver (20 mA) on one pin.

• High-current sink drivers (20 mA) on two I

• Integrated PMU (Power Management Unit) to minimize power consumption during

• Power profiles residing in boot ROM allowing to optimize performance and minimize

• Three reduced power modes: Sleep, Deep-sleep, and Deep power-d own.

• Single power supply (2.0 V to 3.6 V).

• 10-bit ADC with input multiplexing among 8 pins.

• GPIO pins can be used as edge and level sensitive interrupt sources.

• Clock output function with divider that can reflect the system oscillator clock, IRC

• Processor wake-up from Deep-sleep mode via a dedicated start logic using up to 40

• Brownout detect with four separate thresholds for interrupt and one threshold for

• Power-On Reset (POR).

• Integrated oscillator with an operating range of 1 MHz to 25 MHz.

• 12 MHz internal RC oscillator trimmed to 1 % accuracy over the entire temperature

• Programmable watchdog oscillator with a frequency range of 7.8 kHz to 1.8 MHz.

UM10375

Chapter 1: LPC13xx Introductory information

– USB 2.0 full-speed device controller with on-chip PHY for device (LPC1342/43

only).

– UART with fractional baud rate generation, modem, internal FIFO, and

RS-485/EIA-485 support.

– SSP controller with FIFO and multi-protocol capabilities. – Additional SSP controller on LPC1313FBD48/01.

C-bus interface supporting full I2C-bus specification and Fast-mode Plus with a

– I

data rate of 1 Mbit/s with multiple address recognition and monitor mode.

– Up to 42 General Purpose I/O (GPIO) pins with configurable pull-up/pull-down

resistors.

– Four general purpose counter/timers with a total of four capture inputs and 13

match outputs.

– Programmable WatchDog Timer (WDT). – Programmable Windowed Watchdog Timer (WWDT) on LPC1311/01 and

LPC1313/01.

– System tick timer.

C-bus pins in Fast-mode Plus.

Sleep, Deep-sleep, and Deep power-down modes.

power consumption for any given application through one simple fun ction call. (LPC1300L series, on LPC1311/01 and LPC1313/01 only.)

clock, CPU clock, or the watchdog clock.

of the functional pins.

forced reset (four thresholds for forced reset on the LPC1311/01 and LPC1313/01 parts).

and voltage range that can optionally be used as a system clock.

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• System PLL allows CPU operation up to the maximum CPU rate without the need for

a high-frequency crystal. May be run from the system oscillator or the internal RC oscillator.

• For USB (LPC1342/43), a second, dedicated PLL is provided.

• Code Read Protection (CRP) with different security levels.

• Unique device serial number for identification.

• Available as 48-pin LQFP package and 33-pin HVQFN package.

1.4 Ordering options

UM10375

Chapter 1: LPC13xx Introductory information

Table 1. Ordering information

Type number Package

LPC1311FHN33 HVQFN33 HVQFN33: plastic thermal enhanced very thin quad flat package; no

LPC1311FHN33/01 HVQFN33 HVQFN33: plastic thermal enhanced very thin quad flat package; no

LPC1313FHN33 HVQFN33 HVQFN33: plastic thermal enhanced very thin quad flat package; no

LPC1313FHN33/01 HVQFN33 HVQFN33: plastic thermal enhanced very thin quad flat package; no

LPC1313FBD48 LQFP48 LQFP48: plastic low profile quad flat package; 48 leads; body 7  7 

LPC1313FBD48/01 LQFP48 LQFP48: plastic low profile quad flat package; 48 leads; body 7  7 

LPC1342FHN33 HVQFN33 HVQFN33: plastic thermal enhanced very thin quad flat package; no

LPC1342FBD48 LQFP48 LQFP48: plastic low profile quad flat package; 48 leads; body 7  7 

LPC1343FHN33 HVQFN33 HVQFN33: plastic thermal enhanced very thin quad flat package; no

LPC1343FBD48 LQFP48 LQFP48: plastic low profile quad flat package; 48 leads; body 7  7 

Name Description Version

leads; 33 terminals; body 7  7  0.85 mm

1.4 mm

leads; 33 terminals; body 7  7  0.85 mm

1.4 mm

leads; 33 terminals; body 7  7  0.85 mm

1.4 mm

n/a

SOT313-2

n/a

SOT313-2

n/a

SOT313-2

Table 2. Ordering options for LPC13xx

Type number Flash Total

LPC1311FHN33 8 kB 4 kB - no 1 1 1 8 33 HVQFN33 LPC1311FHN33/01 8 kB 4 kB - yes 1 1 1 8 33 HVQFN33 LPC1313FHN33 32 kB 8 kB - no 1 1 1 8 33 HVQFN33 LPC1313FHN33/01 32 kB 8 kB - yes 1 1 1 8 33 HVQFN33 LPC1313FBD48 32 kB 8 kB - no 1 1 1 8 48 LQFP48 LPC1313FBD48/01 32 kB 8 kB - yes 1 1 2 8 48 LQFP48 LPC1342FHN33 16 kB 4 kB Device no 1 1 1 8 33 HVQFN33

User manual Rev. 5 — 21 June 2012 6 of 370

SRAM

USB Power

profiles

UART RS-485

I2C/ Fast+

SSP ADC

channels

Pins Package

NXP Semiconductors

UM10375

Chapter 1: LPC13xx Introductory information

Table 2. Ordering options for LPC13xx

Type number Flash Total

SRAM

LPC1342FBD48 16 kB 4 kB Device no 1 1 1 8 48 LQFP48 LPC1343FHN33 32 kB 8 kB Device no 1 1 1 8 33 HVQFN33 LPC1343FBD48 32 kB 8 kB Device no 1 1 1 8 48 LQFP48

USB Power

profiles

UART RS-485

I2C/ Fast+

SSP ADC

channels

Pins Package

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1.5 Block diagram

UM10375

Chapter 1: LPC13xx Introductory information

GPIO ports

PIO0/1/2/3

RXD

TXD

DTR, DSR

DCD

CT32B0_MAT[3:0]

CT32B1_MAT[3:0]

CT16B0_MAT[2:0]

CT16B1_MAT[1:0]

(2)

, CTS,

(2)

, RI

, RTS

CT32B0_CAP0

CT32B1_CAP0

CT16B0_CAP0

CT16B1_CAP0

SWD

TEST/DEBUG

INTERFACE

ARM

CORTEX-M3

I-code bus

HIGH-SPEED

GPIO

32-bit COUNTER/TIMER 0

32-bit COUNTER/TIMER 1

16-bit COUNTER/TIMER 0

16-bit COUNTER/TIMER 1

D-code bus

UART

USB DEVICE

CONTROLLER

system bus

AHB-LITE BUS

AHB TO

BRIDGE

USB pins

USB PHY

slaveslave

APB

LPC1311/13/42/43

(1)

WDO

POR

(1)

slave

WDT/WWDT

IRC

FLASH

8/16/32 kB

10-bit ADC

SSP0

SSP1

I2C-BUS

IOCONFIG

XTALIN

XTALOUT

CLOCK

GENERATION,

POWER CONTROL,

SYSTEM

FUNCTIONS

clocks and

controls

slave

(3)

(4)

RESET

CLKOUT

ROM

SRAM 4/8 kB

AD[7:0]

SCK0,SSEL0 MISO0, MOSI0

SCK1,SSEL1 MISO1, MOSI0

SCL SDA

SYSTEM CONTROL

002aae722

(1) LPC1342/43 only. (2) LQFP48 package only. (3) On LPC1313FBD48/01 only. (4) Windowed WatchDog Timer (WWDT) on LPC1311/01 and LPC1313/01 only.

Fig 1. LPC13xx block diagram

User manual Rev. 5 — 21 June 2012 8 of 370

UM10375

Chapter 2: LPC13xx Memory mapping

Rev. 5 — 21 June 2012 User manual

2.1 How to read this chapter

See Table 3 for LPC13xx memory configurations:

Table 3. LPC13xx memory configuration

Part Flash Address range SRAM Address rang e

LPC1311 8 kB 0x0000 0000 - 0x0000 1FFF 4 kB 0x1000 0000 - 0x1000 0FFF LPC1311/01 8 kB 0x0000 0000 - 0x0000 1FFF 4 kB 0x1000 0000 - 0x1000 0FFF LPC1313 32 kB 0x0000 0000 - 0x0000 7FFF 8 kB 0x1000 0000 - 0x1000 1FFF LPC1313/01 32 kB 0x0000 0000 - 0x0000 7FFF 8 kB 0x1000 0000 - 0x1000 1FFF LPC1342 16 kB 0x0000 0000 - 0x0000 3FFF 4 kB 0x1000 0000 - 0x1000 0FFF LPC1343 32 kB 0x0000 0000 - 0x0000 7FFF 8 kB 0x1000 0000 - 0x1000 1FFF

2.2 Memory map

Figure 2 shows the memory and peripheral address space of the LPC13xx.

The AHB peripheral area is 2 MB in size and is divided to allow for up to 128 peripherals. On the LPC13xx, the GPIO ports are the only AHB peripherals. The APB peripheral area is 512 kB in size and is divided to allow for up to 32 peripherals. Each peripheral of either type is allocated 16 kB of space. This allows simplifying the address decoding for each peripheral.

All peripheral register addresses are 32-bit word aligned regardless of their size. An implication of this is that word and half-word registers must be accessed all at once. For example, it is not possible to read or write the upper byte of a word register separately.

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0x5000 0000

0x5001 0000

0x5002 0000

0x5020 0000

AHB peripherals

16 - 127 reserved

GPIO PIO1

4-7

0x5003 0000

0x5004 0000

GPIO PIO2

GPIO PIO3

8-11

12-15

GPIO PIO0

0-3

APB peripherals

0x4000 4000

0x4000 8000

0x4000 C000

0x4001 0000

0x4001 8000

0x4002 0000

0x4002 8000

0x4003 8000

0x4003 C000

0x4004 0000

0x4004 4000

0x4004 8000

0x4004 C000

0x4008 0000

0x4002 4000

0x4001 C000

0x4001 4000

0x4000 0000

WDT/WWDT

32-bit counter/timer 0

32-bit counter/timer 1

ADC

UART

PMU

C-bus

10 - 13 reserved

reserved

19 - 21 reserved

23 - 31 reserved

16 15

reserved

0x0000 0000

0 GB

0.5 GB

4 GB

1 GB

0x0000 4000

0x0000 2000

0x1000 2000

0x1000 1000

0x1FFF 0000

0x1FFF 4000

0x2000 0000

0x4000 0000

0x4008 0000

0x5000 0000

0x5020 0000

0xFFFF FFFF

reserved

APB peripherals

AHB peripherals

8 kB SRAM (LPC1313/1343)

0x1000 0000

4 kB SRAM (LPC1311/1342)

LPC1311/13/42/43

16 kB on-chip flash (LPC1342)

8 kB on-chip flash (LPC1311)

0x0000 8000

32 kB on-chip flash (LPC1313/43)

16 kB boot ROM

0x0000 0000

0x0000 0400

active interrupt vectors

+ 256 words

I-code/D-code memory space

002aae723

reserved

SSP0

0x4005 8000

0x4005 C000

SSP1 (LPC1313FBD48/01)

16-bit counter/timer 1

16-bit counter/timer 0

USB (LPC1342/43 only)

IOCONFIG

system control

flash controller

0xE000 0000

0xE010 0000

private peripheral bus

UM10375

Chapter 2: LPC13xx Memory mapping

Fig 2. LPC13xx memory map

2.3 Memory remapping

User manual Rev. 5 — 21 June 2012 10 of 370

For details, see Table 8.

UM10375

Chapter 3: LPC13xx System configuration

Rev. 5 — 21 June 2012 User manual

3.1 How to read this chapter

The system configuration registers apply to all LPC13xx parts with the following exceptions:

USB clocking and power control

Since the USB block is available on the LPC1342 and LPC1343 only, the registers and register bits listed in Table 4

Table 4. USB related registers and register bits reserved for LPC1311/13

Name Access Address

USBPLLCTRL R/W 0x010 USB PLL control all USBPLLSTAT R 0x014 USB PLL status all USBPLLCLKSEL R/W 0x048 USB PLL clock source select all USBPLLCLKUEN R/W 0x04C USB PLL clock source update enable all SYSAHBCLKCTRL R/W 0 x080 System AHB clock control bit 14 USBCLKSEL R/W 0x0C0 USB clock source select all USBCLKUEN R/W 0x0C4 USB clock source update enable all USBCLKDIV R/W 0x0C8 USB clock source divider all PDSLEEPCFG R/W 0x230 Power-down states in Deep-sleep

PDAWAKECFG R/W 0x234 Power-down st ates after wake-up from

PDRUNCFG R/W 0x238 Power-down configuration register bits 8 and 10

are reserved for parts LPC1311 and LPC1313:

Description Register bits

offset

mode

Deep-sleep mode

reserved for LPC1311/13

bits 8 and 10

SSP1

The SSP1 block is available on the LPC1313FBD48/01 only. SSP1 related registers and register bits are reserved for the following parts: LPC1311/13/42/43 and LPC1311FHN33/01 and LPC1313FHN33/01.

BOD control

The number of programmable BOD levels for forced reset is different for the LPC1300 and the LPC1300L series. See Table 5

. The BOD trip levels for the LPC1300 and LPC1300L

series are listed in the LPC1311/13/42/43 data sheet.

Table 5. BOD interrupt and reset levels

Series Type number Interrupt levels Reset levels

LPC1300 LPC1311FHN33 4 (programmable) 1 (fixed) LPC1300 LPC1313FBD48 4 (programmable) 1 (fixed) LPC1300 LPC1313FHN33 4 (programmable) 1 (fixed) LPC1300 LPC1342FHN33 4 (programmable) 1 (fixed) LPC1300 LPC1343FBD48 4 (programmable) 1 (fixed)

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Table 5. BOD interrupt and reset levels

Series Type number Interrupt levels Reset levels

LPC1300 LPC1343FHN33 4 (programmable) 1 (fixed) LPC1300L LPC1311FHN33/01 4 (programmable) 4 (programmable) LPC1300L LPC1313FHN33/01 4 (programmable) 4 (programmable) LPC1300L LPC1313FBD48/01 4 (programmable) 4 (programmable)

Input pins to the start logic

UM10375

Chapter 3: LPC13xx System configuration

For HVQFN packages, the start logic control bits (see Table 44 for port pins PIO2_1 to PIO2_11 and PIO3_0, PIO3_1, and PIO3_3.

PIO reset status registers

For HVQFN packages, the reset status bits (see Table 40 port pins PIO2_1 to PIO2_11 and PIO3_0 and PIO3_1, and PIO3_3.

Entering Deep power-down mode

Status of the IRC before entering Deep power-down mode (see Section 3 .9.4.2

to Table 51) are reserved

and Table 41) are reserved for

• IRC must be enabled for parts LPC1311/13/42/43.

• IRC status has no effect for parts LPC1311/01 and LPC1313/01.

Enabling sequence for UART cloc k

Requirements for enabling the UART pe ripheral clock:

• The UART pins must be configured in the IOCON block before the UART clock can be enabled

in the SYSAHBCLKCTRL register (Table 25) for parts LPC1311/13/42/43.

in the

• The sequence of configuring the UART pins and the UART clock has no effect for

parts LPC1311/01 and LPC1313/01.

Deep-sleep mode configuration

Register values configuring the Deep-sleep mode are different for the LPC1300 (parts LPC1311/13/42/43) and LPC1300L (parts LPC1311/01 and LPC1313/01) series (see

Section 3.5.45

, the PDSLEEPCFG register).

3.2 Introduction

The system configuration block controls oscillators, the power management unit, and clock generation of the LPC13xx. Also included in this block are registers for setting the priority for AHB access and a register for remapping flash, SRAM, and ROM memory areas.

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3.3 Pin description

Table 6 shows pins that are associated with system control block functions .

Table 6. Pin summary

Pin name Pin

CLKOUT O Clockout pin PIO0_0 to PIO0_11 I Wake-up pins port 0 PIO1_0 to PIO1_11 I Wake-up pins port 1 PIO2_0 to PIO2_11 PIO3_0 to PIO3_3

[1] For HVQFN packages, applies to P2_0, P3_2, and P3_3 only.

UM10375

Chapter 3: LPC13xx System configuration

Pin description

direction

[1]

I Wake-up pins port 2 I Wake-up pins port 3

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3.4 Clocking and power control

See Figure 3 for an overview of the LPC13xx Clock Generation Unit (CGU). The LPC131x include three independent oscillators. These are the system oscillator, the

Internal RC oscillator (IRC), and the Watchdog oscillator. Each oscillator can be used for more than one purpose as required in a particular application.

Following reset, the LPC131x will operate from the Internal RC oscillator until switched by software. This allows systems to operate without any external crystal and the bootloader code to operate at a known frequency.

The SYSAHBCLKCTRL register gates the system clock to the various peripherals and memories. UART, SSP0/1, the SysTick timer, and the ARM trace clock have individual clock dividers to derive peripheral clocks from the main clock.

The USB clock, if available, and the watchdog clock, can be derived from the oscillator output or the main clock.

The main clock, and the clock outputs from the IRC, the system oscillator, and the watchdog oscillator can be observed directly on the CLKOUT pin.

UM10375

Chapter 3: LPC13xx System configuration

User manual Rev. 5 — 21 June 2012 14 of 370

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SYS PLL

irc_osc_clk

sys_osc_clk

wdt_osc_clk

irc_osc_clk

wdt_osc_clk

USB PLL

MAINCLKSEL

SYSPLLCLKSEL

USBPLLCLKSEL

CLOCK

DIVIDER

SYSAHBCLKCTRL (ROM enable)

SYSAHBCLKCTRL (SSP1 enable)

CLOCK

DIVIDER

SSP0/1_PCLK

CLOCK

DIVIDER

UART_PCLK

CLOCK

DIVIDER

CLOCK

DIVIDER

SYSTICK timer

CLOCK

DIVIDER

ARM trace clock

WDCLK

WDTUEN

CLOCK

DIVIDER

usb_clk

USBUEN

wdt_osc_clk

irc_osc_clk

sys_osc_clk

CLOCK

DIVIDER

CLKOUT

CLKOUTUEN

main clock system clock

sys_pllclkin

usb_pllclkin

sys_pllclkout

usb_pllclkout

ARM

CORTEX-M3

ROM

SSP1

SYSAHBCLKDIV

UM10375

Chapter 3: LPC13xx System configuration

USB is available in parts LPC134x only. SSP1 is available on part LPC1313FBD48 only.

Fig 3. LPC13xx CGU block diagram

3.5 Register description

All registers, regardless of size, are on word address boundaries. Details of the registers

User manual Rev. 5 — 21 June 2012 15 of 370

appear in the description of each function. See Section 3.12

for the flash access timing register, which can be re-configured as part

the system setup. This register is not part of the system configuration block.

NXP Semiconductors

UM10375

Chapter 3: LPC13xx System configuration

Table 7. Register o verview: system control block (base address 0x4004 8000)

Name Access Address offset Description Reset value Reference

SYSMEMREMAP R/W 0x000 System memory remap 0x0000 0002 Table 8 PRESETCTRL R/W 0x004 Peripheral reset control 0x0000 0000 Table 9 SYSPLLCTRL R/W 0x008 System PLL control 0x0000 0000 Table 10 SYSPLLSTAT R 0x00C System PLL status 0x0000 0000 Table 11 USBPLLCTRL R/W 0x010 USB PLL control 0x0000 0000 Table 12 USBPLLSTAT R 0x014 USB PLL status 0x0000 0000 Table 13

- - 0x018 - 0x01C Reserved - - SYSOSCCTRL R/W 0x020 System oscillator control 0x0000 0000 Table 14 WDTOSCCTRL R/W 0x024 Watchdog oscillator control 0x0000 0000 Table 15 IRCCTRL R/W 0x028 IRC control 0x0000 0080 Table 16

- - 0x02C Reserved - - SYSRESSTAT R/W 0x030 System reset status register 0x0000 0000 Table 17

- - 0x034 - 0x03C Reserved - - SYSPLLCLKSEL R/W 0x040 System PLL clock source select 0x0000 0000 Table 18 SYSPLLCLKUEN R/W 0x044 System PLL clock source update enable 0x0000 0000 Table 19 USBPLLCLKSEL R/W 0x048 USB PLL clock source select 0x0000 0000 Table 20 USBPLLCLKUEN R/W 0x04C USB PLL clock source update enable 0x0000 0000 Table 21

- - 0x050 - 0x06C Reserved - - MAINCLKSEL R/W 0x070 Main clock source select 0x0000 0000 Table 22 MAINCLKUEN R/W 0x074 Main clock source update enable 0x0000 0000 Table 23 SYSAHBCLKDIV R/W 0x078 System AHB clock divider 0x0000 0001 Table 24

- - 0x07C Reserved - - SYSAHBCLKCTRL R/W 0x080 System AHB clock control 0x0000 485F Table 25

- - 0x084 - 0x090 Reserved - - SSP0CLKDIV R/W 0x094 SSP0 clock divider 0x0000 0000 Table 26 UARTCLKDIV R/W 0x098 UART clock divder 0x0000 0000 T able27 SSP1CLKDIV R/W 0x09C SSP1 clock divider 0x000 Table 28

- - 0x0A0 - 0x0A8 Reserved - - TRACECLKDIV R/W 0x0AC ARM trace clock divider 0x0000 0000 Table 29 SYSTICKCLKDIV R/W 0x0B0 SYSTICK clock divder 0x0000 0000 Table 30

- - 0x0B4 - 0x0BC Reserved - - USBCLKSEL R/W 0x0C0 USB clock source select 0x0000 0000 Table 31 USBCLKUEN R/W 0x0C4 USB clock source update enable 0x0000 0000 Table 32 USBCLKDIV R/W 0x0C8 USB clock source divider 0x0000 0000 T able33

- - 0x0CC Reserved - - WDTCLKSEL R/W 0x0D0 WDT clock source select 0x0000 0000 Table 34 WDTCLKUEN R/W 0x0D4 WDT clock source update enable 0x0000 0000 Table 35 WDTCLKDIV R/W 0x0D8 WDT clock divider 0x0000 0000 Table 36

- - 0x0DC Reserved - - CLKOUTCLKSEL R/W 0x0E0 CLKOUT clock source select 0x0000 0000 Table 37 CLKOUTUEN R/W 0x0E4 CLKOUT clock source update enable 0x0000 0000 Table 38

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Table 7. Register o verview: system control block (base address 0x4004 8000) …continued

Name Access Address offset Description Reset value Reference

CLKOUTDIV R/W 0x0E8 CLKOUT clock divider 0x0000 0000 Table 39

- - 0x0EC - 0x0FC Reserved - - PIOPORCAP0 R 0x100 POR captured PIO status 0 - Table 40 PIOPORCAP1 R 0x104 POR captured PIO status 1 - Table 40

- - 0x108 - 0x14C Reserved 0x0000 0000 - BODCTRL R/W 0x150 BOD control 0x0000 0000 Table 42 SYSTCKCAL R/W 0x154 System tick counter calibration 0x0000 0004 Table 43

- - 0x158 - 0x1FC Reserved - - STAR TAPRP0 R/W 0x200 Start logic edge control register 0; bottom

32 interrupts

STARTERP0 R/W 0x204 Start logic signal enable register 0;

bottom 32 interrupts

STARTRSRP0CLR W 0x208 Start logic reset register 0; bottom 32

interrupts

START SRP0 R 0x20C Start logic status register 0; bottom 32

interrupts

START APRP1 R/W 0x210 Start logic edge control register 1; top 8

interrupts

STARTERP1 R/W 0x214 Start logic signal enable register 1; top 8

interrupts

STARTRSRP1CLR W 0x218 Start logic reset register 1; top 8

interrupts

STARTSRP1 R 0x21C Start logic status register 1; top 8

interrupts

- - 0x220 - 0x22C Reserved - PDSLEEPCFG R/W 0x230 Power-down states in Deep-sleep mode 0x0000 0000 Table 53 PDAWAKECFG R/W 0x234 Power-down states after wake-up from

Deep-sleep mode

PDRUNCFG R/W 0x238 Power-down configuration register 0x0000 FDF0 Table 55

- - 0x23C - 0x3F0 Reserved - - DEVICE_ID R 0x3F4 Device ID part

- Table 44

- Table 45

- Table 46

- Table 47

- Table 48

- Table 49

- Table 50

- Table 51

0x0000 FDF0 Table 54

Table 56

dependent

3.5.1 System memory remap register

The system memory remap register selects whether the ARM interrupt vectors are read from the boot ROM, the flash, or the SRAM.

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Table 8. System memory remap register (SYSMEMREMAP, address 0x4004 8000) bit

Bit Symbol Value Description Reset

1:0 MAP System memory remap 10

31:2 - - Reserved 0x00

3.5.2 Peripheral reset control register

This register allows software to reset the SSP0/1 and I2C peripherals. Writing a 0 to the SSP0/1_RST_N or I2C_RST_N bits resets the SSP0/1 or I2C peripherals. Writing a 1 de-asserts the reset.

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description

value

0x0 Boot Loader Mode. Interrupt vectors are re-mapped to Boot

ROM.

0x1 User RAM Mode. Interrupt vectors are re-mapped to Static

RAM.

0x2 User Flash Mode. Interrupt vectors are not re-mapped and

reside in Flash.

Remark: Before accessing the SSP0/1 and I2C peripherals, write a 1 to this register to ensure that the reset signals to the SSP0/1 and I2C are de-asserted.

Table 9. Peripher al reset control register (PRESETCTRL, address 0x4004 8004) bit

description

Bit Symbol Value Description Reset

0 SSP0_RST_N SSP0 reset control 0

0 Reset SSP0. 1 De-assert SSP0 reset.

1 I2C_RST_N I2C reset control 0

0 Reset I2C. 1 De-asset I2C reset.

2 SSP1_RST_N SSP1 reset control 0

0 Reset the SSP1. 1 De-assert SSP1 reset.

31:3 - - Reserved 0x00

3.5.3 System PLL control register

This register connects and enables the system PLL a nd configur es the PLL multiplie r and divider values. The PLL accepts an input frequency from 10 MHz to 25 MHz from various clock sources. The input frequency is multiplied up to a high frequency, then divided down to provide the actual clock used by the CPU, peripherals, and optionally the USB subsystem. Note that the USB subsystem has its own dedicated PLL. The PLL can produce a clock up to the maximum allowed for the CPU, which is 72 MHz.

value

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Table 10. System PLL control register (SYSPLLCTRL, address 0x4004 8008) bit description

Bit Symbol Value Description Reset

4:0 MSEL Feedback divider value. The division value M is the

6:5 PSEL Post divider ratio P. The division ratio is 2  P. 0x00

31:7 - - Reserved. Do not write ones to reserved bits. 0x00

3.5.4 System PLL status register

This register is a Read-only register and supplies the PLL lock status (see Section 3.11.1).

Table 11. System PLL status register (SYSPLLSTAT, address 0x4004 800C) bit description

Bit Symbol Value Description Reset

0 LOCK PLL lock status 0x0

31:1 - - Reserved 0x00

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value

0x000 programmed MSEL value + 1. 00000: Division ratio M = 1 to 11111: Division ratio M = 32.

0x0 P = 1 0x1 P = 2 0x2 P = 4 0x3 P = 8

value

0 PLL not locked 1 PLL locked

3.5.5 USB PLL control register

The USB PLL is identical to the system PLL and is used to provide a dedicated clock to the USB block if available (see Section 3.1

This register connects and enables the USB PLL and configures the PLL multiplier and divider values. The PLL accepts an input frequency from 10 MHz to 25 MHz from various clock sources. The input frequency is multiplied up to a high frequency, then divided down to provide the actual clock 48 MHz clock used by the USB subsystem.

Remark: The USB PLL must be connected to the system oscillator for correct USB operation (see Table 20

Table 12. USB PLL control register (USBPLLCTRL, address 0x4004 8010) bit description

Bit Symbol Value Description Reset

4:0 MSEL Feedback divider value. The division value M is the

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programmed MSEL value + 1. 00000: Division ratio M = 1 to 11111: Division ratio M = 32.

value

0x000

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Table 12. USB PLL control register (USBPLLCTRL, address 0x4004 8010) bit description

Bit Symbol Value Description Reset

6:5 PSEL Post divider ratio P. The division ratio is 2  P. 0x00

31:7 - - Reserved. Do not write ones to reserved bits. 0x00

3.5.6 USB PLL status register

This register is a Read-only register and supplies the PLL lock status (see Section 3.11.1).

Table 13. USB PLL status register (USBPLLSTAT, address 0x4004 8014) bit description

Bit Symbol Value Description Reset

0 LOCK PLL lock status 0x0

31:1 - - Reserved 0x00

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value

0x0 P = 1 0x1 P = 2 0x2 P = 4 0x3 P = 8

value

0 PLL not locked 1 PLL locked

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3.5.7 System oscillator control register

This register configures the frequency range for the system oscillator.

Table 14. System oscillator control register (SYSOSCCTRL, address 0x4004 8020) bit

Bit Symbol Value Description Reset

0 BYPASS Bypass system oscillator 0x0

1 FREQRANGE Determines frequency range for Low-power

31:2 - - Reserved 0x00

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description

value

0 Oscillator is not bypassed. 1 Bypass enabled. PLL input (sys_osc_clk) is fed

directly from the XTALIN and XTALOUT pins.

0x0

oscillator. 0 1 - 20 MHz frequency range. 1 15 - 25 MHz frequency range

3.5.8 Watchdog oscillator control register

This register configures the watchdog oscillator. The oscillator consists of an analog and a digital part. The analog part contains the oscillator function and generates an analog clock (Fclkana). With the digital part, the analog output clock (Fclkana) can be divided to the required output clock frequency wdt_osc_clk. The analog output frequency (Fclkan a) can be adjusted with the FREQSEL bits between 500 kHz and 3.4 MHz. With the digital part Fclkana will be divided (divider ratios = 2, 4,...,64) to wdt_osc_clk using the DIVSEL bits.

The output clock frequency of the watchdog oscillator can be calculated as wdt_osc_clk = Fclkana/(2  (1 + DIVSEL)) = 7.8 kHz to 1.7 MHz (nominal values).

Remark: Any setting of the FREQSEL bits will yield a Fclkana value within  40% of the listed frequency value. The watchdog oscillator is the clock source with the lowest power consumption. If accurate timing is required, use the IRC or system clock.

Remark: The frequency of the watchdog oscillator is undefined after reset. The watchdog oscillator frequency must be programmed by writing to the WDTOSCCTRL register before using the watchdog oscillator.

Table 15. Watchdog oscillator control register (WDTOSCCTRL, address 0x4004 8024) bit

description

Bit Symbol Value Description Reset

4:0 DIVSEL Select divider for Fclkana.

wdt_osc_clk = Fclkana/(2  (1 + DIVSEL)).

value

0x0

00000: 2  (1 + DIVSEL) = 2 00001: 2  (1 + DIVSEL) = 4 to 11111: 2  (1 + DIVSEL) = 64

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Table 15. Watchdog oscillator control register (WDTOSCCTRL, address 0x4004 8024) bit

Bit Symbol Value Description Reset

8:5 FREQSEL Select watchdog oscillator analog output frequency

31:9 - - Reserved 0x00

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description

value

0x00

(Fclkana).

0x1 0.6 MHz 0x2 1.05 MHz 0x3 1.4 MHz 0x4 1.75 MHz 0x5 2.1 MHz 0x6 2.4 MHz 0x7 2.7 MHz 0x8 3.0 MHz 0x9 3.25 MHz 0xA 3.5 MHz 0xB 3.75 MHz 0xC 4.0 MHz 0xD 4.2 MHz 0xE 4.4 MHz 0xF 4.6 MHz

3.5.9 Internal resonant crystal control register

This register is used to trim the on-chip 12 MHz oscillator. The trim value is factory-preset and written by the boot code on start-up.

Table 16. Internal resona nt crystal control register (IRCCTRL, address 0x4004 8028) bit

description

Bit Symbol Description Reset value

7:0 TRIM Trim value 0x1000 0000, then flash will reprogram 31:8 - Reserved 0x00

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3.5.10 System reset status register

The SYSRSTSTAT register shows the source of the latest reset event. The bits are cleared by writing a one to any of the bits. The POR event clears all other bits in this register, but if an othe r re se t signal ( e.g., EXTRST) remains asserted after the POR signal is negated, then its bit is set to detected.

Table 17. System reset status register (SYSRESSTAT, address 0x4004 8030) bit description

Bit Symbol Value Description Reset

0 POR POR reset status 0x0

1 EXTRST 0x0

2 WDT Status of the Watchdog reset 0x0

3 BOD Status of the Brown-out detect reset 0x0

4 SYSRST Status of the software system reset. The ARM software

31:5 - - Reserved 0x00

Chapter 3: LPC13xx System configuration

0 No POR detected 1 POR detected

0 No RESET 1 RESET

0 No WDT reset detected 1 WDT reset detected

0 No BOD reset detected 1 BOD reset detected

reset has the same effect as the hardware reset using the

RESET 0 No System reset detected 1 System reset detected

event detected

detected

pin.

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value

0x0

3.5.11 System PLL clock source select register

This register selects the clock source for the system PLL. The SYSPLLCLKUEN register (see Section 3.5.12

Remark: The system oscillator must be selected if the system PLL is used to generate a 48 MHz clock to the USB block.

Remark: When switching clock sources, both clocks must be running before the clock source is updated.

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) must be toggled from LOW to HIGH for the update to take effect.

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T able 18. System PLL clock source select register (SYSPLLCLKSEL, address 0x4004 8040)

Bit Symbol Value Description Reset

1:0 SEL System PLL clock source 0x00

31:2 - - Reserved 0x00

3.5.12 System PLL clock source update enable register

This register updates the clock source of the system PLL with the new input clock after the SYSPLLCLKSEL register has been written to. In order for the update to take effect, first write a zero to the SYSPLLUEN register and then write a one to SYSPLLUEN.

Remark: When switching clock sources, both clocks must be running before the clock source is updated.

Table 19. System PLL clock source update enable register (SYSPLLCLKUEN, address

Bit Symbol Value Description Reset value

0 ENA Enable system PLL clock source update 0x0

31:1 - - Reserved 0x00

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bit description

value

0x0 IRC oscillator 0x1 System oscillator 0x2 Reserved 0x3 Reserved

0x4004 8044) bit description

0 No change 1 Update clock source

3.5.13 USB PLL clock source select register

This register selects the clock source for the dedicated USB PLL. The USBPLLCLKUEN register (see Section 3.5.14 effect.

Remark: When switching clock sources, both clocks must be running before the clock source is updated in the USBPLLCLKUEN register. For USB operation, the clock source must be switched from IRC to system oscillator with both the IRC and the system oscillator running. After the switch, the IRC can be turned off.

T able 20. USB PLL clock source select register (USBPLLCLKSEL, address 0x4004 8048) bit

description

Bit Symbol Value Description Reset

1:0 SEL USB PLL clock source 0x00

0x0 IRC. The USB PLL clock source must be switched to system

0x1 System oscillator 0x2 Reserved 0x3 Reserved

31:2 - - Reserved 0x00

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) must be toggled from LOW to HIGH for the update to take

value

oscillator for correct USB operation.

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3.5.14 USB PLL clock source update enable register

This register updates the clock source of the USB PLL with the new input clock after the USBPLLCLKSEL register has been written to. In order for the update to take effect at the USB PLL input, first write a zero to the USBPLLUEN register and then write a one to USBPLLUEN.

Remark: The system oscillator must be selected in the USBPLLCLKSEL register in order to use the USB PLL, and this register must be toggled to update the USB PLL clock with the system oscillator.

Remark: When switching clock sources, both clocks must be running before the clock source is updated.

T able 21. USB PLL clock source update enable register (USBPLLCLKUEN, address 0x4004

Bit Symbol Value Description Reset value

0 ENA Enable USB PLL clock source update 0x0

31:1 - - Reserved 0x00

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804C) bit description

0 No change 1 Update clock source

3.5.15 Main clock source select register

This register selects the main system clock which can be either any input to the system PLL, the output from the system PLL (sys_pllclkout), or the watchdog or IRC oscillators directly. The main system clock clocks the core, the peripherals and memories, and optionally the USB block.

The MAINCLKUEN register (see Section 3.5.16 the update to take effect.

Remark: When switching clock sources, both clocks must be running before the clock source is updated.

Table 22. Main clock source select register (MAINCLKSEL, address 0x4004 8070) bit

description

Bit Symbol Value Description Reset value

1:0 SEL Clock source for main clock 0x00

0x0 IRC oscillator 0x1 Input clock to system PLL 0x2 WDT oscillator 0x3 System PLL clock out

31:2 - - Reserved 0x00

) must be toggled from LOW to HIGH for

3.5.16 Main clock source update enable register

This register updates the clock source of the main clock with the new input clock after the MAINCLKSEL register has been written to. In order for the update to take effect, first write a zero to the MAINCLKUEN register and then write a one to MAINCLKUEN.

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Remark: When switching clock sources, both clocks must be running before the clock

source is updated.

Table 23. Main clock source update enable register (MAINCLKUEN, address 0x4004 8074)

Bit Symbol Value Description Reset value

0 ENA Enable main clock source update 0x0

31:1 - - Reserved 0x00

3.5.17 System AHB clock divider register

This register divides the main clock to provide the system clock to the core, memories, and the peripherals. The system clock can be shut down completely by setting the DIV bits to 0x0.

Table 24. System AHB clock divider register (SYSAHBCLKDIV, address 0x4004 8078) bit

Bit Symbol Description Reset value

7:0 DIV System AHB clock divider values

31:8 - Reserved 0x00

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bit description

0 No change 1 Update clock source

description

0x01 0: System clock disabled. 1: Divide by 1. to 255: Divide by 255.

3.5.18 System AHB clock control register

The SYSAHBCLKCTRL register enables the clocks to individual system and peripheral blocks. The system clock (sys_ahb_clk[0], bit 0 in the SYSAHBCLKCTRL register) provides the clock for the AHB to APB bridge, the AHB matrix, the ARM Cortex-M3, the Syscon block, and the PMU. This clock cannot be disabled.

Table 25. System AHB clock control register (SYSAHBCLKCTRL, address 0x4004 8080) bit

description

Bit Symbol Value Description Reset

0 SYS Enables clock for AHB to APB bridge, to the AHB

matrix, to the Cortex-M3 FCLK and HCLK, to the

SysCon, and to the PMU. This bit is read only. 0 Reserved 1 Enabled

1 ROM Enables clock for ROM. 1

0 Disabled 1 Enabled

2 RAM Enables clock for RAM. 1

0 Disabled 1 Enabled

value

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Table 25. System AHB clock control register (SYSAHBCLKCTRL, address 0x4004 8080) bit

Bit Symbol Value Description Reset

3 FLASHREG Enables clock for flash register interface. 1

4 FLASHARRAY Enables clock for flash array access. 1

5 I2C Enables clock for I2C. 0

6 GPIO Enables clock for GPIO. 1

7 CT16B0 Enables clock for 16-bit counter/timer 0. 0

8 CT16B1 Enables clock for 16-bit counter/timer 1. 0

9 CT32B0 Enables clock for 32-bit counter/timer 0. 0

10 CT32B1 Enables clock for 32-bit counter/timer 1. 0

11 SSP Enables clock for SSP. 1

12 UART Enables clock for UART. Note that for the

13 ADC Enables clock for ADC. 0

14 USB_REG Enables clock for USB_REG. 1

description

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Chapter 3: LPC13xx System configuration

…continued

value

0 Disabled 1 Enabled

0 LPC1311/13/42/43, the UAR T pins must be configured in the IOCON block before the UART clock can be enabled. For the LPC1311/01 and LPC1313/01 no special enabling sequence is required.

0 Disabled 1 Enabled

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Table 25. System AHB clock control register (SYSAHBCLKCTRL, address 0x4004 8080) bit

Bit Symbol Value Description Reset

15 WDT Enables clock for WDT. 0

16 IOCON Enables clock for IO configuration block. 0

17 - - Reserved 0x00 18 SSP1 Enables clock for SSP1. 0

31:19 - - Reserved 0x00

3.5.19 SSP0 clock divider register

description

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…continued

value

0 Disabled 1 Enabled

0 Disable 1 Enable

This register configures the SSP0 peripheral clock SSP0_PCLK. The SSP0_PCLK can be shut down by setting the DIV bits to 0x0.

Table 26. SSP0 clock divider register (SSP0CLKDIV, address 0x4004 8094) bit description

Bit Symbol Description Reset value

7:0 DIV SSP_PCLK clock divider values.

0: Disable SSP0_PCLK. 1: Divide by 1. to 255: Divide by 255.

31:8 - Reserved 0x00

3.5.20 UART clock divider register

This register configures the UART peripheral clock UART_PCLK. The UART_PCLK can be shut down by setting the DIV bits to 0x0.

Remark: Note that for the LPC1311/13/42/43, the UART pins must be configured in the IOCON block before the UART clock can be enabled. For the LPC1311/01 and LPC1313/01 no special enabling sequence is required.

Table 27. UART clock divider register (UARTCLKDIV, address 0x4004 8098) bit description

Bit Symbol Description Reset value

7:0 DIV UART_PCLK clock divider values

0: Disable UART_PCLK. 1: Divide by 1. to 255: Divide by 255.

31:8 - Reserved 0x00

0x00

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3.5.21 SSP1 clock divider register

This register configures the SSP1 peripheral clock SSP1_PCLK. The SSP1_PCLK can be shut down by setting the DIV bits to 0x0.

Table 28. SSP1 clock divider register (SSP1CLKDIV, address 0x4004 809C) bit description

Bit Symbol Description Reset

7:0 DIV SSP1_PCLK clock divider values

31:8 - Reserved 0x00

3.5.22 Trace clock divider register

This register configures the ARM trace clock. The trace clock can be shut down by setting the DIV bits to 0x0.

Table 29. TRACECLKDIV clock divider register (TRACECLKDIV, address 0x4004 80AC) bit

Bit Symbol Description Reset value

7:0 DIV ARM trace clock divider values.

31:8 - Reserved 0x00

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value

0x00 0: Disable SSP1_PCLK. 1: Divide by 1. to 255: Divide by 255.

description

0x00 0: Disable TRACE_CLK. 1: Divide by 1. to 255: Divide by 255.

3.5.23 SYSTICK clock divider register

This register configures the SYSTICK peripheral clock. The SYSTICK timer clock can be shut down by setting the DIV bits to 0x0.

Table 30. SYSTICK clock divider register (SYSTICKCLKDIV, address 0x4004 80B0) bit

description

Bit Symbol Description Reset value

7:0 DIV SYSTICK clock divider values.

0: Disable SYSTICK timer clock. 1: Divide by 1. to 255: Divide by 255.

31:8 - Reserved 0x00

0x00

3.5.24 USB clock source select register

This register selects the clock source for the USB usb_clk. The clock source can be either the USB PLL output or the main clock, and the clock can be further divided by the USBCLKDIV register (see Table 33

The USBCLKUEN register (see Section 3.5.25 the update to take effect.

User manual Rev. 5 — 21 June 2012 29 of 370

) to obtain a 48 MHz clock.

) must be toggled from LOW to HIGH for

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Remark: When switching clock sources, both clocks must be running before the clock

source is updated. The default clock source for the USB controller is the USB PLL output. For switching the clock source to the main clock, ensure that the system PLL and the USB PLL are running to make both clock sources available for switching. The main clock must be set to 48 MHz and configured with the main PLL and the system oscillator. After the switch, the USB PLL can be turned off.

Table 31. USB clock source select register (USBCLKSEL, address 0x4004 80C0) bit

Bit Symbol Value Description Reset

1:0 SEL USB clock source 0x00

31:2 - - Reserved 0x00

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description

value

0x0 USB PLL out 0x1 Main clock 0x2 Reserved 0x3 Reserved

3.5.25 USB clock source update enable register

This register updates the clock source of the USB with the new input clock after the USBCLKSEL register has been written to. In order for the update to take effect, first write a zero to the USBCLKUEN register and then write a one to USBCLKUEN.

Remark: When switching clock sources, both clocks must be running before the clock source is updated.

T able 32. USB clock source update enable register (USBCLKUEN, address 0x4004 80C4) bit

description

Bit Symbol Value Description Reset value

0 ENA Enable USB clock source update 0x0

0 No change 1 Update clock source

31:1 - - Reserved 0x00

3.5.26 USB clock divider register

This register allows the USB clock usb_clk to be divided to 48 MHz. The usb_clk can be shut down by setting the DIV bits to 0x0.

Table 33. USB clock divider re gister (USBCLKDIV, address 0x4004 80C8) bit description

Bit Symbol Description Reset value

7:0 DIV USB clock divider values.

0: Disable USB clock. 1: Divide by 1. to 255: Divide by 255.

31:8 - Reserved 0x00

0x00

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