LPC23xx series are ARM-based microcontrollers for applications requiring serial
communications for a variety of purposes. These microcontrollers typica lly incorporate a
10/100 Ethernet MAC, USB 2.0 Full Speed interface, four UARTs, two CAN channels, an
SPI interface, two Synchronous Serial Ports (SSP), thr ee I2C interfaces, an I
and a MiniBus (8-bit data/16-bit address parallel bus).
2.How to read this manual
The term “LPC23xx“ in the following text will be used as a generic name for all parts
covered in this user manual:
• LPC2361/62
• LPC2364/65/66/67/68
• LPC2377/78
• LPC2387
• LPC2388
2
S interface,
3.Features
3.1General features
Only when needed, a specific device name will be used to distinguish the part. See
• Up to 512 kB on-chip Flash Program Memory with In-System Prog ramming (ISP) a nd
In-Application Programming (IAP) capabilities. Single Flash sector or full-chip erase in
400 ms and 256 bytes programming in 1 ms. Flash program memory is on the ARM
local bus for high performance CPU access.
• Up to 64 kB of SRAM on the ARM local bus for high performance CPU access.
• 16 kB St atic RAM for Ethernet inter face. Can also be used as general purpo se SRAM.
• 8 kB Static RAM for general purpose or USB interface.
• Dual AHB system that provides for simultaneous Ethernet DMA, USB DMA, and
• Advanced Vector ed Interrupt Controller, supporting up to 32 vectored interrupts.
• General Purpose DMA controller (GPDMA) on AHB that can be used with the SSP
• Serial Interfaces:
• Other APB Peripherals:
UM10211
Chapter 1: LPC23XX Introductory information
program execution from on-chip flash with no contention between those functions. A
bus bridge allows the Ethernet DMA to access the other AHB subsystem.
serial interfaces, the I
memory-to-memory transfers.
– Ethernet MAC with associated DMA controller. These functions reside on an
independent AHB bus.
– On LPC2364/66/68, LPC2378, LPC2387, LPC2388: USB 2.0 device controller
with on-chip PHY and associated DMA controller.
– On LPC2388: USB Host/OTG controller.
– Four UARTs with fractional baud rate generation, one with modem control I/O, one
with IrDA support, all with FIFO. These reside on the APB bus.
– SPI controller, residing on the APB bus.
– Two SSP controllers with FIFO and multi-protocol capabilities. One is an alternate
for the SPI port, sharing its interrupt. The SSP controllers can be used with the
GPDMA controller and reside on the APB bus.
2
– Three I
are expansion I
2
I
2
– I
bus. The I
– On LPC2364/66/68, LPC2378, LPC2387, LPC2388: Two CAN channels with
Acceptance Filter/FullCAN mode residing on the APB bus.
– On LPC2367/68, LPC2377/78, LPC2387, LPC2388: Secure Digital (SD) /
MultiMediaCard (MMC) memory card interface.
– Up to 70 (100 pin packages) or 104 (144 pin packages) general purpose I/O pins.
– 10 bit A/D converter with input multiplexing among 6 pins (100 pin packages) or 8
pins (144 pin packages).
– 10 bit D/A converter.
– Four general purpose timers with two capture inputs each and up to four compare
output pins each. Each timer block has an external count input.
– One PWM/Timer block with support for three-phase motor control. The PWM has
two external count inputs.
– Real-Time Clock (RTC) with separate power pin; clock source can be the RTC
oscillator or the APB clock.
– 2 kB Static RAM powered from the RTC power pin , allowing data to be stored
when the rest of the chip is powered off.
C interfaces reside on the APB bus. The second and third I2C interfaces
C pins.
S (Inter-IC Sound) interface for digital audio input or output, residing on the APB
2
S interface can be used with the GPDMA.
2
S port, and the SD/MMC card port, as well as for
2
C interfaces with standard port pins rather than specia l open-drain
The LPC2300 consists of an ARM7TDMI-S CPU with emulation support, the ARM7 Local
Bus for closely coupled, high speed access to the majority of on-chip memory, the AMBA
Advanced High-performance Bus (AHB) interfacing to high speed on-chip peripherals an d
external memory, and the AMBA Advanced Peripheral Bus (APB) for connection to other
on-chip peripheral functions. The microcontroller permanently configures the
ARM7TDMI-S processor for little-endian byte order.
The microcontroller implements two AHB buses in order to allow the Etherne t block to
operate without interference caused by other system activity. The primary AHB, referred
to as AHB1, includes the V ectored Interrupt Controller, General Purpose DMA Controller,
External Memory Controller, USB interface, and 8/16 kB SRAM primarily intended for use
by the USB.
The second AHB, referred to as AHB2, includes only the Ethernet block and an
associated 16 kB SRAM. In addition, a bus bridge is provided that allows the secondary
AHB to be a bus master on AHB1, allowing expansion of Ethernet buffer space into
off-chip memory or unused space in memory resid ing on AHB1.
In summary, bus masters with access to AHB1 are the ARM7 itself, the USB block, the
General Purpose DMA function, and the Ethernet block (via the bus bridge from AHB2).
Bus masters with access to AHB2 are the ARM7 and the Ethernet block.
AHB peripherals are allocated a 2 MB range of addresses at the very top of the 4 GB
ARM memory space. Each AHB peripheral is allocated a 16 kB address space within the
AHB address space. Lower speed peripheral functions are connected to the APB bus.
The AHB to APB bridge interfaces the APB bus to the AHB bus. APB peripherals are also
allocated a 2 MB range of addresses, beginning at the 3.5 GB address point. Each APB
peripheral is allocated a 16 kB address space within the APB address space.
7.ARM7TDMI-S processor
The ARM7TDMI-S is a general purpose 32 bit microprocessor, which offers high
performance and very low power consumption. The ARM architecture is based on
Reduced Instruction Set Computer (RISC) principles, and the instruction set and related
decode mechanism are much simpler than those of microprogrammed Complex
Instruction Set Computers. This simplicity results in a high instruction throughput and
impressive real-time interrupt response from a small and cost-effective processor core.
UM10211
Chapter 1: LPC23XX Introductory information
Pipeline techniques are employed so that all pa rts of the p rocessing and memory systems
can operate continuously. Typically, while one instruction is being executed, its successor
is being decoded, and a third instruction is being fetched from memory.
The ARM7TDMI-S processor also employs a unique architectural strategy known as
THUMB, which makes it ideally suited to high-volume applications with memory
restrictions, or applications where code density is an issue.
The key idea behind THUMB is that of a super-reduced instruction set. Essentially, the
ARM7TDMI-S processor has two instruction sets:
• The standard 32 bit ARM instruction set.
• A 16 bit THUMB instruction set.
The THUMB set’s 16 bit instruction length allows it to approach twice the density of
standard ARM code while retaining most of the ARM’s performance advantage over a
traditional 16 bit processor using 16 bit registers. This is possible because THUMB code
operates on the same 32 bit register set as ARM code.
THUMB code is able to provide up to 65% of the code size of ARM, and 160% of the
performance of an equivalent ARM processor connected to a 16 bit memory system.
The ARM7TDMI-S processor is described in detail in the ARM7TDMI-S Datasheet that
can be found on official ARM website.
The LPC2300 includes a Flash memory system with up to 512 kB. This memory may be
used for both code and data storage. Programming of the Flash memory may be
accomplished in several ways. It may be programmed In System via the serial port. The
application program may also erase and/or program the Flash while the application is
running, allowing a great degree of flexibility for data storage field firmware upgrades, etc.
The Flash is 128 bits wide and includes pre -fetching and buf fering techniques to allow it to
operate at SRAM speeds.
9.On-chip Static RAM
The LPC2300 includes a static RAM memory up to 64 kB in size, that may be used for
code and/or data storage.
The SRAM controller incorporates a write-back buffer in order to prevent CPU stalls
during back-to-back writes. The write-back buffer always holds the last data sent by
software to the SRAM. The data is only written to the SRAM when software does another
write. After a "warm" chip reset, the SRAM does not reflect the last write operation. Two
identical writes to a location guarantee that the data will be present after a Reset.
Alternatively, a dummy write operation before entering idle or power-down mode will
similarly guarantee that the last data written will be present after a subsequent Reset.
ARM processors have a single 4 GB address space. The following table shows how this
space is used on NXP embedded ARM devices. For memory option det ails see Table 1–2
Table 9.LPC2300 memory usage
Address range General useAddress range details and description
0x0000 0000 to
0x3FFF FFFF
0x4000 0000 to
0x7FFF FFFF
0x8000 0000 to
0xDFFF FFFF
0xE000 0000 to
0xEFFF FFFF
0xF000 0000 to
0xFFFF FFFF
on-chip
NV memory
and fast I/O
on-chip RAM0x4000 0000 - 0x4000 7FFFRAM (up to 32 kB)
off-chip memoryTwo static memory banks, 64 KB each (LPC2377/78 and LPC2388 only):
The LPC2300 incorporates several distinct memory regions, shown in the following
figures. Figure 2–7
address space from the user program viewpoint following reset. Th e interrupt vector area
supports address remapping, which is described later in this section.
Figure 12 and Table 2–10 show different views of the peripheral address space. Both the
AHB and APB peripheral areas are 2 megabyte spaces which are divided up into 128
peripherals. Each peripheral space is 16 kilobytes in size. This allows simplifying the
address decoding for each peripheral.
All peripheral register addresses are word aligned (to 32 bit boundaries) regardless of
their size. This eliminates the need for byte lane mapping hardware that would be required
to allow byte (8 bit) or half-word (16 bit) accesses to occur at smaller boundaries. An
implication of this is that word and half-word registers must be accessed all at once. For
example, it is not possible to read or write the upper byte of a word register separately.
The following table shows the APB address map. No APB peripheral uses all of the 16 kB
space allocated to it. T ypically each device’ s registers are "aliased" or re peated at multiple
locations within each 16 kB range.
Table 10.APB peripherals and base addresses
APB PeripheralBase AddressPeripheral Name
00xE000 0000Watchdog Timer
10xE000 4000Timer 0
20xE000 8000Timer 1
30xE000 C000UART0
40xE001 0000UART1
50xE001 4000Not used
60xE001 8000PWM1
70xE001 C000I
80xE002 0000SPI
90xE002 4000RTC
100xE002 8000GPIO
1 10xE002 C000Pin Connect Block
120xE003 0000SSP1
130xE003 4000ADC
140xE003 8000CAN Acceptance Filter RAM
150xE003 C000CAN Acceptance Filter Registers
160xE004 0000CAN Common Registers
170xE004 4000CAN Controller 1
180xE004 8000CAN Controller 2
19 to 220xE004 C000 to 0xE005 8000Not used
230xE005 C000I
240xE006 0000Not used
250xE006 4000Not used
260xE006 8000SSP0
270xE006 C000DAC
280xE007 0000Timer 2
290xE007 4000Timer 3
300xE007 8000UART2
310xE007 C000UART3
320xE008 0000I
330xE008 4000Battery RAM
340xE008 8000I2S
350xE008 C000SD/MMC Card Interface
36 to 1260xE009 0000 to 0xE01F BFFFNot used
1270xE01F C000System Control Block
UM10211
Chapter 2: LPC23XX memory addressing
2
C0
[1]
[1]
[1]
[1]
[1]
2
C1
2
C2
[2]
[1] CAN interface is available in LPC2364/66/68, LPC2378, LPC2387, and LPC2388.
[2] The SD/MMC card interface is available in LPC2365/66, LPC2377/78, LPC2387, and LPC2388.
4.LPC2300 memory re-mapping and boot ROM
4.1Memory map concepts and operating modes
The basic concept on the LPC2300 is that each memory area has a "natural" location in
the memory map. This is the address range for which code residing in that area is written.
The bulk of each memory space remains permanently fixed in the same location,
eliminating the need to have portions of the code designed to run in different address
ranges.
Because of the location of the interrupt vectors on the ARM7 processor (at addresses
0x0000 0000 through 0x0000 001C, as shown in Table 2–11
Boot ROM and SRAM spaces need to be re-mapped in order to allow alternative uses of
interrupts in the differen t operating modes described in Table 2–12
interrupts is accomplished via the Memory Mapping Contro l feature (Section 2–5 “
The Boot Loader always executes after any reset. The Boot ROM
interrupt vectors are mapped to the bottom of memory to allow
handling exceptions and using interrupts during the Boot Loading
process. A sector of the Flash memory (the Boot Flash) is available to
hold part of the Boot Code.
.
NXP Semiconductors
Table 12. LPC2300 Memory mapping modes
ModeActivationUsage
User
Flash
mode
User RAM
mode
User
External
Memory
mode
[1] See EMCControl register address mirror bit in Table5–60 for address of external memory bank 0.
4.2Memory re-mapping
In order to allow for compatibility with future derivatives, the entire Boot ROM is mapped
to the top of the on-chip memory space. In this manner, the use of larger or smaller flash
modules will not require changing the location of the Boot ROM (which would require
changing the Boot Loader code itself) or changing the mapping of the Boot ROM interru pt
vectors. Memory spaces other than the interrupt vectors remain in fixed locations.
Figure 2–13
UM10211
Chapter 2: LPC23XX memory addressing
Software
activation by
boot code
Software
activation by
user program
Software
activation by
user code
shows the on-chip memory mapping in the modes defined above.
Activated by the Boot Loader when a valid User Program Signature is
recognized in memory and Boot Loader operation is not forced.
Interrupt vectors are not re-mapped and are found in the bottom of the
Flash memory.
Activated by a User Program as desired. Interrupt vectors are
re-mapped to the bottom of the Static RAM.
Activated by a User Program as desired. Interrupt vectors are
re-mapped to external memory bank 0
[1]
.
The portion of memory that is re-mapped to allow interrupt processing in different modes
includes the interrupt vector area (32 bytes) and an additional 32 bytes for a total of
64 bytes, that facilitates branching to interrupt handlers at distant physical addresses. The
remapped code locations overlay addresses 0x0000 0000 through 0x0000 003F. A typical
user program in the Flash memory can place the entire FIQ handler at address
0x0000 001C without any need to consider mem or y bo un d ar ies. The vector contained in
the SRAM, external memory , and Boot ROM must cont ain branches to the actual interrupt
handlers, or to other instructions that accomplish the branch to the interrupt hand lers.
There are three reasons this configuration was chosen:
1. To give the FIQ handler in the Flash memory the advantage of not having to take a
memory boundary caused by the remapping into account.
2. Minimize the need to for the SRAM and Boot ROM vectors to deal with arbitrary
boundaries in the middle of code space.
3. To provide space to store constants for jumping beyond the range of single word
branch instructions.
Re-mapped memory areas, including the Boot ROM and interrupt vectors, continue to
appear in their original location in addition to the re-mapped address.
Details on re-mapping and examples can be found in Section 2–5 “
The Memory Mapping Control alters the mapping of the interrupt vectors that appear
beginning at address 0x0000 0000. This allows code running in different memory spaces
to have control of the interrupts.
5.1Memory Mapping Control Register (MEMMAP - 0xE01F C040)
Whenever an exception handling is necessary, microcontroller will fetch an instruction
residing on exception corresponding address as described in Table 2–11 “
vector locations” on page 25. The MEMMAP register determines the source of data that
will fill this table.
Table 13.Memory mapping control registers
NameDescriptionAccessReset
MEMMAP Memory mapping control. Selects whether the
ARM interrupt vectors are read from the Boot
ROM, User Flash, or RAM.
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Chapter 2: LPC23XX memory addressing
ARM exception
Address
value
R/W0x000xE01F C040
Table 14.Memory Mapping control register (MEMMAP - address 0xE01F C040) bit
description
BitSymbol Value DescriptionReset
1:0MAP00Boot Loader Mode. Interrupt vectors are re-mapped to Boot ROM. 00
01User Flash Mode. Interrupt vectors are not re-mapped and reside
in Flash.
10User RAM Mode. Interrupt vectors are re-mapped to Static RAM.
11User External Memory Mode (available on LPC2377/78 and
LPC2388 only).
Warning: Improper setting of this value may result in incorrect operation of
the device.
7:2--Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
5.2Memory mapping control usage notes
Memory Mapping Control simply selects one out of three available sources of data (set s of
64 bytes each) necessary for handling ARM exceptions (interrupts).
For example, whenever a Software Interrupt request is generated, ARM core will always
fetch 32 bit data "residing" on 0x0000 0008 see Table 2–11 “
locations” on page 25. This means that when MEMMAP[1:0] = 10 (User RAM Mode),
read/fetch from 0x0000 0008 will provide data stored in 0x4000 0008. In case of
MEMMAP[1:0] = 00 (Boot Loader Mode), read/fetch from 0x0000 0008 will provide data
available also at 0x7FFF E008 (Boot ROM remapped from on-chip Bootloader).
The LPC2300 generates the appropriate bus cycle abort exception if an access is
attempted for an address that is in a reserved or unassigned address region. The regions
are:
• Areas of the memory map that are not implemented for a specific ARM derivative. Fo r
the LPC2300, this is:
– Address space between On-Chip Non-Volatile Memory and the Special Register
space. Labelled "Reserved for On-Chip Memory" in Figure 2–7
Figure 2–9
– Address space between On-Chip Static RAM and the Boot ROM. Labelled
"Reserved Address Space" in Figure 2–7
– External Memory
– Reserved regions of the AHB and APB spaces. See Figure 2–11
• Unassigned AHB peripheral spaces. See Figure 2–12.
• Unassigned APB peripheral spaces. See Table 2–10.
.
UM10211
Chapter 2: LPC23XX memory addressing
, Figure 2–8, and
, Figure 2–8, and Figure 2–9.
.
For these areas, both attempted data acce ss and in struction fetch genera te an exception.
In addition, a Prefetch Abort exception is generated for an y instruction fetch that maps to
an AHB or APB peripheral address, or to the Special Register space located just below
the SRAM at addresses 0x3FFF8000 through 0x3FFFFFFF.
Within the address space of an existing APB peripheral, a data abort exception is not
generated in response to an access to an undefined address. Address decoding within
each peripheral is limited to that needed to distinguish defined registers within the
peripheral itself. For example, an access to address 0xE000 D000 (an undefined addre ss
within the UART0 space) may result in an access to the register defined at address
0xE000 C000. Details of such address aliasing within a peripheral space are not defined
in the LPC2300 documentation and are not a supporte d feature.
If software executes a write directly to the Flash memory, the MAM generates a data abort
exception. Flash programming must be accomplished using the specified Flash
programming interface provided by the Boot Code.
Note that the ARM core stores the Prefetch Abort flag along with the associated
instruction (which will be meaningless) in the pipeline and processes the abort only if an
attempt is made to execute the instruction fetched from the illegal address. This prevents
accidental aborts that could be caused by prefetches that occur when code is executed
very near a memory boundary.
The system control block includes several system features and control registers for a
number of functions that are not related to specific peripheral devices. These include:
• Reset
• Brown-Out Detection
• External Interrupt Input s
• Miscellaneous System Controls and Status
• Code Security vs. Debugging
Each type of function has its own register(s) if any are required and unneeded bit s are
defined as reserved in order to allow future expansion. Unrelated functions never share
the same register addresses
2.Pin description
Table 3–15 shows pins that are associated with System Control block functions.
Table 15.Pin summary
Pin namePin
EINT0InputExternal Interrupt Input 0 - An active low/high level or
EINT1InputExternal Interrupt Input 1 - See the EINT0 description ab ove.
EINT2InputExternal Interrupt Input 2 - See the EINT0 description ab ove.
EINT3InputExternal Interrupt Input 3 - See the EINT0 description ab ove.
RESET
3.Register description
All registers, regardless of size, are on word address boundaries. Details of the registers
appear in the description of each function.
Reset has four sources on the LPC2300: the RESET pin, the Watchdog Reset, Power On
Reset (POR) and the Brown Out Detection circuit (BOD). The RESET
trigger input pin. Assertion of chip Reset by any source, once the operating volt age attains
a usable level, starts the W akeup Timer (see description in Section 4–9 “
this chapter), causing reset to remain asserted until the external Reset is de-asserted, the
oscillator is running, a fixed number of clocks have passed, and the Flash controller has
completed its initialization. The reset logic is shown in the following block diagram (see
Fig 14. Reset block diagram including the wakeup timer
On the assertion of any of reset sources (POR, BOD reset, External reset and Watchdog
reset), the IRC starts up. Af ter the IRC-start-up time (maximum of 60 μs on power-up) and
after the IRC provides stable clock output, the reset signal is latched and synchronized on
the IRC clock. Then the following two sequences start simultaneously :
1. The 2-bit IRC wakeup timer starts counting when the synchronized reset is
de-asserted. The boot code in the ROM start s when the 2-bit IRC wakeup timer times
out. The boot code performs the boot tasks an d m ay jump to th e F lash. If th e Flash is
not ready to access, the MAM will insert wait cycles until the Flash is ready.
2. The Flash wakeup-timer (9-bit) starts counting when the synchronized reset is
de-asserted. The Flash wakeup-timer generates the 100 μs Flash start-up time. Once
it times out, the Flash initialization sequence is started, which takes about 250 cycles.
When it’s done, the MAM will be granted access to the Flash.
When the internal Reset is removed, the processor begins executing at address 0, which
is initially the Reset vector mapped from the Boot Block. At that point, all of the processor
and peripheral registers have been initialized to predetermined values.
Figure 3–15
processor status when the LPC2300 starts up after reset. See Section 4–4.2 “
shows an example of the relationship between the RESET, the IRC, and the
oscillator” for start-up of the main oscillator if selected by the user code.
Main
NXP Semiconductors
valid threshold
processor status
V
DD(3V3)
IRC status
RESET
GND
002aad482
30 μs
1 μs; IRC stability count
8 μs
170 μs
160 μs
boot timeuser code
boot code
execution
finishes;
user code starts
flash read
finishes
flash read
starts
supply ramp-up
time
UM10211
Chapter 3: LPC23XX System control block
Fig 15. E xample of start-up after reset
The various Resets have some small dif ferences. For example, a Power On Reset causes
the value of certain pins to be latched to configure the part.
For more details on Reset, PLL and startup/boot code inte ra ction se e Section 4– 6.2 “
This register contains one bit for each source of Reset. Writing a 1 to any of these bits
clears the corresponding read-side bit to 0. The interactions among the four sources are
described below.
2WDTRThis bit is set when the Watchdog Timer times out and the WDTRESET
3BODRThis bit is set when the 3.3 V power reaches a level below 2.6 V.
7:4-Reserved, user software should not write ones to reserved bits. The
UM10211
Chapter 3: LPC23XX System control block
bit in the Watchdog Mode Register is 1. It is cleared by any of the other
sources of Reset.
If the V
will be set to 1.
If the V
to the level at which POR is asserted (nominally 1 V), the BODR bit is
cleared.
if the V
2.6 V, the BODR will be set to 1.
This bit is not affected by External Reset nor Watchdog Reset.
Note: Only in case when a reset occurs and the POR = 0, the BODR bit
indicates if the V
value read from a reserved bit is not defined.
voltage dips from 3.3 V to 2.5 V and backs up, the BODR bit
DD
voltage dips from 3.3 V to 2.5 V and continues to decline
DD(3V3)
voltage rises continuously from below 1 V to a level above
DD(3V3)
voltage was below 2.6 V or not.
DD(3V3)
value
See text
See text
NA
5.Brown-out detection
The LPC2300 includes 2-stage monitoring of the voltage on the V
voltage falls below 2.95 V, the Brown-Out Detector (BOD) asserts an interrupt signal to
the Vectored Interrupt Controller. This signal can be enabled for interrupt in the Interrupt
Enable Register in the VIC (see Section 6–5.4 “
0xFFFF F010)”) in order to cause a CPU interrupt; if not, software can monitor the signal
by reading the Raw Interrupt Status Register (see Section 6–5.3 “
Register (VICRawIntr - 0xFFFF F008)”).
The second stage of low-voltage detection asserts Reset to inactivate the LPC2300 when
the voltage on the V
Flash as operation of the various elements of the chip would othe rwise become unrelia ble
due to low voltage. The BOD circuit maintains this reset down below 1 V, at which point
the Power-On Reset circuitry maintains the overall Reset.
Both the 2.95 V and 2.65 V thresholds include some hysteresis. In normal operation, this
hysteresis allows the 2.95 V detection to reliably interrupt, or a regularly-executed event
loop to sense the condition.
But when Brown-Out Detection is enabled to bring the LPC2300 out of Power-Down mode
(which is itself not a guaranteed operation -- see Section 4–8.6 “
register (PCON - 0xE01F C0C0)”), the supply volt age may recover from a transient be fore
the Wakeup Timer has completed its delay. In this case, the net result of the transient
BOD is that the part wakes up and continues operation after the instructions that set
Power-Down Mode, without any interrupt occurring and with the BOD bit in the RSID
being 0. Since all other wakeup conditions have latching flags (see Section 3–6.2
“External Interrupt flag register (EXTINT - 0xE01F C140)” and Section 26–6.2), a wakeup
of this type, without any apparent cause, can be assumed to be a Brown-Out that has
gone away.
pins. If this
DD(3V3)
Interrupt Enable Register (VICIntEnable -
Raw Interrupt Status
pins falls below 2.65 V. This Reset prevents alteration of the
The LPC2300 includes four External Interrupt Inputs as selectable pin functions. In
addition, external interrupts have the ability to wake up the CPU from Power-down mode.
This is controlled by the register INTWAKE, which is described in the Clocking and Power
Control chapter under the Power Control heading
6.1Register description
The external interrupt function has four registers associated with it. The EXTINT register
contains the interrupt flags. The EXTMODE and EXTPOLAR registers specify the level
and edge sensitivity parameters.
Table 18.External Interrupt registers
NameDescriptionAccess Reset
EXTINTThe External Interrupt Flag Register contains
interrupt flags for EINT0, EINT1, EINT2 and
EINT3. See Table 3–19
whether each pin is edge- or level-sensitive.
See Table 3–20
EXTPOLAR The External Interrupt Polarity Register controls
which level or edge on each pin will cause an
interrupt. See Table 3–21
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Chapter 3: LPC23XX System control block
Address
[1]
value
R/W0x000xE01F C140
.
R/W0x000xE01F C148
.
R/W0x000xE01F C14C
.
[1] Reset Value reflects the data stored in used bits only. It does not include reserved bits content.
6.2External Interrupt flag register (EXTINT - 0xE01F C140)
When a pin is selected for its external interrupt function, the level or edge on that pin
(selected by its bits in the EXTPOLAR a nd EXTMODE registers) will set its interrup t flag in
this register. This asserts the corresponding interrupt request to the VIC, which will cause
an interrupt if interrupts from the pin are enabled.
Writing ones to bits EINT0 through EINT3 in EXTINT register clears the corresponding
bits. In level-sensitive mode the interrupt is cleared only when the pin is in its inactive
state.
Once a bit from EINT0 to EINT3 is set and an appropriate code st arts to execute (hand ling
wakeup and/or external interrupt), this bit in EXTINT register must be cleared. Otherwise
event that was just triggered by activity on the EINT pin will not be recognized in future.
Important: whenever a change of external interrupt operating mode (i.e. active
level/edge) is performed (including the initialization of an external interrupt), the
corresponding bit in the EXTINT register must be cleared! For details see Section
For example, if a system wakes up from power-down using low level on external interrupt
0 pin, its post-wakeup code must reset EINT0 bit in order to allow future entry into the
power-down mode. If EINT0 bit is left set to 1, subsequent attempt(s) to invoke
power-down mode will fail. The same goes for external interrupt handling.
More details on Power-down mode will be discussed in the following chapters.
Table 19.External Interrupt Flag regist er (EXTINT - address 0xE01F C140) bit description
Bit Symbol DescriptionReset
0EINT0In level-sensitive mode, this bit is set if the EINT0 function is selected for its
1EINT1In level-sensitive mode, this bit is set if the EINT1 function is selected for its
2EINT2In level-sensitive mode, this bit is set if the EINT2 function is selected for its
3EINT3In level-sensitive mode, this bit is set if the EINT3 function is selected for its
7:4 -Reserved, user software should not write ones to reserved bits. The value
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Chapter 3: LPC23XX System control block
pin, and the pin is in its active state. In edge-sensitive mode, this bit is set if
the EINT0 function is selected for its pin, and the selected edge occurs on
the pin.
This bit is cleared by writing a one to it, except in level sensitive mode when
the pin is in its active state.
pin, and the pin is in its active state. In edge-sensitive mode, this bit is set if
the EINT1 function is selected for its pin, and the selected edge occurs on
the pin.
This bit is cleared by writing a one to it, except in level sensitive mode when
the pin is in its active state.
pin, and the pin is in its active state. In edge-sensitive mode, this bit is set if
the EINT2 function is selected for its pin, and the selected edge occurs on
the pin.
This bit is cleared by writing a one to it, except in level sensitive mode when
the pin is in its active state.
pin, and the pin is in its active state. In edge-sensitive mode, this bit is set if
the EINT3 function is selected for its pin, and the selected edge occurs on
the pin.
This bit is cleared by writing a one to it, except in level sensitive mode when
the pin is in its active state.
read from a reserved bit is not defined.
[1]
[1]
[1]
[1]
value
0
0
0
0
NA
[1] Example: e.g. if the EINTx is selected to be low level sensitive and low level is present on
corresponding pin, this bit can not be cleared; this bit can be cleared only when signal on the
pin becomes high.
The bits in this register select whether ea ch EINT pin is le vel- or edge- sensitive. Only pins
that are selected for the EINT function (see Section 9–5
register (Section 6–5.4 “
Interrupt Enable Register (VICIntEnable - 0xFFFF F010)”) can
cause interrupts from the External Interrupt function (though of course pins selected for
other functions may cause interrupts from those functions).
Note: Software should only change a bit in this register when its interrupt is
disabled in VICIntEnable, and should write the corresponding 1 to EXTINT before
enabling (initializing) or re-enabling the interrupt. An extraneous interrupt(s) could
be set by changing the mode and not having the EXTINT cleared.
In level-sensitive mode, the bits in this register select whether the corresponding pin is
high- or low-active. In edge-sensitive mode, they select whether the pin is rising- or
falling-edge sensitive. Only pins that are selected for the EINT function (see Section 9–5
and enabled in the VICIntEnable register (Section 6–5.4 “
(VICIntEnable - 0xFFFF F010)”) can cause interrupts from the External Interrupt function
(though of course pins selected for other functions may cause interrupts from those
functions).
description
1EINT0
1EINT1
1EINT2
1EINT3
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Chapter 3: LPC23XX System control block
value
.0
is edge sensitive.
.0
is edge sensitive.
.0
is edge sensitive.
.0
is edge sensitive.
NA
bits. The value read from a reserved bit is not defined.
)
Interrupt Enable Register
Note: Software should only change a bit in this register when its interrupt is
disabled in VICIntEnable, and should write the corresponding 1 to EXTINT before
enabling (initializing) or re-enabling the interrupt. An extraneous interrupt(s) could
be set by changing the polarity and not having the EXTINT cleared.
By default, the AHB1 access is scheduled round-robin (bit 0 = 1). For round-robin
scheduling, the default priority sequence will be CPU, DMA, AHB1, and USB.
The AHB1 access priority can be configured as priority scheduling (bit 0 = 0) and priority
of the each of the AHB1 bus masters can be set by writing the priority value (highest
priority = 4, lowest priority = 1).
Masters with the same priority value are scheduled on a round-robin basis.
2:1break_burst00Break all defined length bursts (the CPU does not create
defined bursts).
01Break all defin ed length bursts greater than four-beat.
10Break all defin ed length bursts greater than eight-beat.
11Never break defined length bursts.
By default, the AHB2 access is scheduled round-robin (bit 0 = 1). For round-robin
scheduling, the default priority sequence will be Ethernet and CPU.
The AHB2 access priority can be configured as priority scheduling (bit 0 = 0) and priority
of the each of the AHB2 bus masters can be set by writing the priority value (highest
priority = 2, lowest priority = 1).
Masters with the same priority value are scheduled on a round-robin basis.
2:1break_burst00Break all defined length bursts (the CPU does not create
defined bursts).
01Break all defin ed length bursts greater than four-beat.
10Break all defin ed length bursts greater than eight-beat.
11Never break defined length bursts.
7:4quantum_sizeControls the type of arbitration and the number of quanta
9:8default_masternnMaster 2 (Eth ernet) is the default master.01
11:10 --Reserved.13:12 EP1nnExternal priority for master 1 (CPU).00
15:14 --Reserved.17:16 EP2nnExtern al priority for master 2 (Ethernet).00
31:18 --Reserved. User software should not write ones to
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Chapter 3: LPC23XX System control block
description
value
0100
before re-arbiration occurs.
0000Preemptive, re-arbitrate after 1 AHB quantum.
0001Preemptive, re-arbitrate after 2 AHB quanta.
0010Preemptive, re-arbitrate after 4 AHB quanta.
001 1Preemptive, re-arbitrate after 8 AHB quanta.
0100Preemptive, re-arbitrate after 16 AHB quanta.
0101Preemptive, re-arbitrate after 32 AHB quanta.
0110Preemptive, re-arbitrate after 64 AHB quanta.
0111Preemptive, re-arbitrate after 128 AHB quanta.
1000Preemptive, re-arbitrate after 256 AHB quanta.
1001Preemptive, re-arbitrate after 512 AHB quanta.
1010Preemptive, re-arbitrate after 1024 AHB quanta.
1011Preemptive, re-arbitrate after 2048 AHB quanta.
1100Preemptive, re-arbitrate after 4096 AHB quanta.
1101Preemptive, re-arbitrate after 8192 AHB quanta.
1110Preemptive, re-arbitrate after 16384 AHB quanta.
1111Non- preemptive, infinite AHB quanta.
NA
reserved bits. The value read from a reserved bit is not
defined.
[1] Allowed values for nn are: 10 (high priority) and 01 (low priority).
7.1.2.1Examples of AHB2 settings
Table 29.Priority sequence (bit 0 = 0): Ethernet, CPU
BitSymbolDescription Priority value nnPriority sequence
13:12EP1CPU10 (2)1
17:16EP2Ethernet01 (1)2
Table 30.Priority sequence (bit 0 = 0): Ethernet, CPU
BitSymbolDescription Priority value nnPriority sequence
7.2System Controls and Status register (SCS - 0xE01F C1A0)
Remark: The EMC is available in LPC2377/78 and LPC2388 only. The SD/MMC is
available in LPC2365/66, LPC2377/78, LPC2387, and LPC2388. Bits are reser ved when
the peripheral is not present.
Table 31. System Contro ls and Status register (SCS - address 0xE01F C1A0) bit description
BitSymbolValue DescriptionAccess Reset
0GPIOMGPIO access mode selection.R/W0
1EMC Reset
2--Reserved. User software should not write ones to reserved bits. The value
3MCIPWR
4OSCRANGEMain oscillator range select.R/W0
5OSCENMain oscillator enable.R/W0
6OSCSTATMain oscillator status.RO0
31:7 --Reserved. User software should not write ones to reserved bits. The value
Disable
Active
Level
[1]
[1]
value
0GPIO ports 0 and 1 are accessed via APB addresses in a fashion
compatible with previous LPC2000 devices.
1High speed GPIO is enabled on ports 0 and 1, accessed via addresses in
the on-chip memory range. This mode includes the port masking feature
described in the GPIO chapter.
External Memory Controller Reset Disable.R/W0
0Both EMC resets are asserted when any type of reset event occurs. In this
mode, all registers and functions of the EMC are initialized upon any reset
condition.
1Many portions of the EMC are only reset by a power-on or brown-out event,
in order to allow the EMC to retain its state through a warm reset (external
reset or watchdog reset). If the EMC is configured correctly, auto-refresh can
be maintained through a warm reset.
NANA
read from a reserved bit is not defined.
MCIPWR pin control.R/W0
0The MCIPWR pin is low.
1The MCIPWR pin is high.
0The frequency range of the main oscillator is 1 MHz to 20 MHz.
1The frequency range of the main oscillator is 15 MHz to 24 MHz.
0The main oscillator is disabled.
1The main oscillator is enabled, and will start up if the correct external
circuitry is connected to the XTAL1 and XTAL2 pins.
0The main oscillator is not ready to be used as a clock source.
1The main oscillator is ready to be used as a clock source . The main
oscillator must be enabled via the OSCEN bit.
-NA
read from a reserved bit is not defined.
[1] The state of this bit is preserved through a software reset, and only a POR or a BOD event will reset it to its default value.
Applications in development typically need the debugging and tracing facilities in the
LPC2300. Later in the life cycle of an application, it may be more important to protect the
application code from observation by hostile or competitive eyes. The following feature of
the LPC2300 allows an application to control whether it can be debugged or protected
from observation.
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Chapter 3: LPC23XX System control block
Details about Code Read Protection can be found in Section 29–6
This chapter describes the clocking and power co nt ro l fea ture s for all LPC 23xx parts.
Note that the CAN1/2 block and the USB block are available on LPC2364/66/68,
LPC2378, LPC2387, and LPC2388 (not available on LPC2365 and LPC2377). The MCI
is available on LPC2367/68, LPC2377/78, LPC2387, and LPC2388. The Ethernet
controller is not available on the LPC3161. All corresponding bits and register settings for
not implemented peripherals are reserved.
2.Introduction
This chapter describes the generation of the various clocks needed by the LPC2300 and
options of clock source selection, as well as power control and wakeup from reduced
power modes. Functions described in the following subsections include:
• Oscillators
• Clock Source Selection
• PLL
• Clock Dividers
• Power Control
• Wakeup Timer
Figure 4–16
are generated.
shows how the clocks for different blocks and peripherals on the LPC23xx
PCONPower Control RegisterR/W00xE01F C0C0
INTWAKEInterrupt Wakeup RegisterR/W00xE01F C144
PCONPPower Control for Peripherals RegisterR/W0x03BE0xE01F C0C4
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Chapter 4: LPC23XX Clocking and power control
4.Oscillators
The LPC2300 includes three independent oscillators. These are the Main Oscillator, the
Internal RC Oscillator, and the RTC oscillator. Each oscillator can be used for more than
one purpose as required in a particular application.
Following Reset, the LPC2300 will operate from the Internal RC Oscillator until switched
by software. This allows systems to operate without any external crystal, and allows the
Boot Loader code to operate at a known frequency . When Boot Block will branch to a user
program, there could be an option to activate the main oscillator prior to entering user
code.
4.1Internal RC oscillator
The Internal RC Oscillator (IRC) may be used as the clock source for the watchdog timer,
and/or as the clock that drives the PLL and subsequently the CPU. The precision of the
IRC does not allow for use with the USB interface, which requires a much more precise
time base. Also, do not use the IRC for the CAN1/2 block if the CAN baud rate is higher
than 100 kbit/s. The nominal IRC frequency is 4 MHz.
Upon power up or any chip reset, the LPC2300 uses the IRC as the clock source.
Software may later switch to one of the other available clock sources.
The main oscillator can be used as the clock source for the CPU, with or without using the
PLL. The main oscillator operates at frequencies of 1 MHz to 24 MHz. This frequency can
be boosted to a higher frequency, up to the maximum CPU operating frequency, by the
PLL. The oscillator output is called OSCCLK. The clock selected as the PLL input is
PLLCLKIN and the ARM processor clock frequency is referred to as CCLK for purposes of
rate equations, etc. elsewhere in this document. The frequencies of PLLCLKIN and CCLK
are the same value unless the PLL is active and connected. Refer to the PLL description
in this chapter for details.
The on-board oscillator in the LPC23xx can operate in one of two modes: slave mode and
oscillation mode.
In slave mode the input clock signal should be coupled by means of a capacitor of 100 pF
(C
C
in this configuration can be left not connected.
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Chapter 4: LPC23XX Clocking and power control
in Figure 4–17, drawing a), with an amplitude of at least 200 mVrms. The XTAL2 pin
External components and models used in oscillation mode are shown in Figure 4–17
drawings b and c, and in Table 4–33
integrated on chip, only a crysta l and the cap acit ances C
and Table 4–34. Since the feedback resistance is
and CX2 need to be connected
X1
externally in case of fundamental mode oscillation (the fundamental frequency is
represented by L, C
parallel package capacitance and should not be larger than 7 pF. Parameters F
and C
are supplied by the crystal manufacturer.
P
and RS). Capacitance CP in Figure 4–17, drawing c, represents the
L
, CL, RS
C
,
Fig 17. Oscillator modes and models: a) slave mode of operation, b) oscillation mode of operation, c) external
components parameters) low frequency mode (OSCRANGE = 0, see Table 3–31)
Crystal load
capacitance C
20 pF< 300 Ω39 pF, 39 pF
30 pF< 300 Ω57 pF, 57 pF
20 pF< 200 Ω39 pF, 39 pF
30 pF< 100 Ω57 pF, 57 pF
20 pF< 60 Ω39 pF, 39 pF
T able 34. Recommended values for C
in oscillation mode (crystal and external
X1/X2
components parameters) high frequency mode (OSCRANGE = 1, see Table 3–31
Fundamental
oscillation frequency
F
OSC
Crystal load
capacitance C
Maximum crystal
L
series resistance R
External load
capacitors CX1,
S
15 MHz - 20 MHz10 pF< 180 Ω18 pF, 18 pF
20 pF< 100 Ω39 pF, 39 pF
20 MHz - 25 MHz10 pF< 160 Ω18 pF, 18 pF
20 pF< 80 Ω39 pF, 39 pF
Since chip operation always begins using the Internal RC Oscillator, and the main
oscillator may never be used in some applications, it will only be started by software
request. This is accomplished by setting the OSCEN bit in the SCS register, as described
in Table 3–31
. The main oscillator provides a status flag (the OSCSTAT bit in the SCS
register) so that software can determine when the oscillator is running and stable. At that
point, software can control switching to the main oscillator as a clock source. Prior to
starting the main oscillator, a frequency range must be selected by configuring the
OSCRANGE bit in the SCS register.
4.3RTC oscillator
The RTC oscillator can be used as the clock source for the RTC, and/or the watchdog
timer. The RTC oscillator can also be used to drive the PLL and the CPU.
)
CX2
5.Clock source selection multiplexer
Several clock sources may be chosen to drive the PLL and ultimately the CPU and
on-chip peripheral devices. The clock sources available are the main oscillator, the RTC
oscillator, and the Internal RC oscillator.
The clock source selection can only be changed safely when the PLL is not connected.
For a detailed description of how to change the clock source in a system using the PLL
see Section 4–6.14 “
Note the following restrictions regarding the choice of clock sources:
1:0 CLKSRCSelects the clock source for the PLL as follows:0
7:2 -0Unused, always 0.0
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Chapter 4: LPC23XX Clocking and power control
baud rate is larger than 100 kbit/s.
description
value
00Selects the Internal RC oscillator as the PLL clock source
(default).
01Selects the main oscillator as the PLL clock source.
10Selects the RTC oscillator as the PLL clock source.
1 1Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
Warning: Improper setting of this value, or an incorrect sequence of
changing this value may result in incorrect operation of the device.
6.PLL (Phase Locked Loop)
The PLL accepts an input clock frequency in the range of 32 kHz to 25 MHz . The input
frequency is multiplied up to a high frequency, then divided down to provide the actual
clock used by the CPU and the USB block.
6.1PLL operation
The PLL input, in the range of 32 kHZ to 25 MHz, may initially be divided down by a value
"N", which may be in the range of 1 to 256. This input division provides a greater number
of possibilities in providing a wide range of output frequencies from the same input
frequency.
Following the PLL input divider is the PLL multiplier. This can multiply the input divider
output through the use of a Current Controlled Oscillator (CCO) by a value "M", in the
range of 1 through 32768. The resulting frequency must be in the range of 275 MHz to
550 MHz. The multiplier works by dividing the CCO output by the value of M, then using a
phase-frequency detector to compare the divided CCO output to the multiplier input. The
error value is used to adjust the CCO frequency.
There are additional dividers at the PLL output to bring the frequency down to what is
needed for the CPU, USB, and other peripherals. The PLL output dividers ar e described
in the Clock Dividers section following the PLL description. A block diagram of the PLL is
shown in Figure 4–18
PLL activation is controlled via the PLLCON register. The PLL multiplier and divider
values are controlled by the PLLCFG register. These two registers are protected in order
to prevent accidental alteration of PLL para meters or deactivation of the PLL. Since all
chip operations, including the Watchdog Timer, could be dependent on the PLL if so
configured (for example when it is providing the chip clock), a ccidental changes to the PLL
setup could result in unexpected or fatal behavior of the microc ontroller. The pr otection is
accomplished by a feed sequence similar to that of the Watchdog Timer. Details are
provided in the description of the PLLFEED regis ter.
The PLL is turned off and bypassed following a chip Reset and by entering Power-down
mode. PLL is enabled by software only.
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Chapter 4: LPC23XX Clocking and power control
It is important that the setup procedur e described in Section 4–6.14 “
PLL setup sequence”
is followed as is or the PLL might not operate at all!.
6.2PLL and startup/boot code interaction
The boot code for the LPC2300 is a little dif ferent from those for the previous NXP ARM7
LPC2000 chips. When there's no valid code (determined by the checksum word) in the
user flash or the ISP enable pin (P2.10) is pulled low on startup, the ISP mode will be
entered and the boot code will setup the PLL with the IRC. Therefore it can not be
assumed that the PLL is disabled when the user opens a debug session to debug the
application code. The user startup code must follow the steps described in this chapter to
disconnect the PLL.
The boot code may also change the values for some registers when the chip enters ISP
mode. For example, the GPIOM bit in the SCS register is set in the ISP mode. If the user
doesn't notice it and clears the GPIOM bit in the application code, the application code will
not be able to operate with the traditional GPIO function on PORT0 and PORT1.
6.3Register description
The PLL is controlled by the registers shown in Table 4–36. More detailed descriptions
follow. Writes to any unused bits are ignored. A read of any unused bits will return a logic
zero.
Warning: Improper setting of PLL values may result in incorrect operation of the
device!
Table 36.PLL registers
NameDescriptionAccess Reset
value
PLLCONPLL Control Register. Holding register for
updating PLL control bits. Values written to this
register do not take effec t unti l a valid PLL feed
sequence has taken place.
PLLCFGPLL Confi guration Register. Holding register for
PLLSTATPLL Status Register. Read-back register for
PLLFEEDPLL Feed Register. This register enables
Chapter 4: LPC23XX Clocking and power control
updating PLL configuration values. Values
written to this register do not take effect until a
valid PLL feed sequence has taken place.
PLL control and configuration information. If
PLLCON or PLLCFG have been written to, but
a PLL feed sequence has not yet occurred, they
will not reflect the current PLL state. Reading
this register provides the actual values
controlling the PLL, as well as the PLL status.
loading of the PLL control and configuration
information from the PLLCON and PLLCFG
registers into the shadow registers that actually
affect PLL operation.
UM10211
Address
[1]
value
R/W00xE01F C084
RO00xE01F C088
WONA0xE01F C08C
[1] Reset Value reflects the data stored in used bits only. It does not include reserved bits content.
The PLLCON register contains the bits that enable and connect the PLL. Enabling the
PLL allows it to attempt to lock to the current settings of the multiplier and divider values.
Connecting the PLL causes the processor and all chip functions to run from the PLL
output clock. Changes to the PLLCON register do not take effect until a correct PLL feed
sequence has been given (see Section 4–6.9 “
Table 37.PLL Control register (PLLCON - address 0xE01F C080) bit description
BitSymbolDescriptionReset
0PLLEPLL Enable. When one, and after a valid PLL feed, this bit will
1PLLCPLL Connect. Having both PLLC and PLLE set to one followed by a
7:2-Reserved, user software should not write ones to reserved bits. The
The PLL must be set up, enabled, and Lock established before it may be used as a clock
source. When switching from the oscillator clock to the PLL output or vice versa, internal
circuitry synchronizes the operation in order to ensure that glitches are not generated.
Hardware does not insure that the PLL is locked before it is connected or automatically
disconnect the PLL if lock is lost during operation. In the event of loss of PLL lock, it is
likely that the oscillator clock has become unstable and disconnecting the PLL will not
remedy the situation.
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Chapter 4: LPC23XX Clocking and power control
activate the PLL and allow it to lock to the requested frequency. See
PLLSTAT register, Table 4–40
valid PLL feed sequence, the PLL becomes the clock source for the
CPU, as well as the USB subsystem and. Otherwise, the clock
selected by the Clock Source Selection Multiplexer is used directly
by the LPC2300. See PLLSTAT register, Table 4–40.
The PLLCFG register contains the PLL multiplier and divider values. Changes to the
PLLCFG register do not take ef fect until a corre ct PLL feed sequence has been given (see
Section 4–6.9 “
frequency, and multiplier and divider values are found in the Section 4–6.11 “
The read-only PLLSTAT register provides the actual PLL parameters that are in effect at
the time it is read, as well as the PLL status. PLLSTAT may disa gree with values found in
PLLCON and PLLCFG because changes to those registers do not take effect until a
proper PLL feed has occurred (see Section 4–6.9 “
T able 40. PLL Status register (PLLSTAT - address 0xE01F C088) bit description
BitSymbolDescriptionReset
14:0MSELRead-back for the PLL Multiplier value. This is the value currently
15-Reserved, user software should not write ones to reserved bits. The
23:16 NSELRead-back for the PLL Pre-Divider value. This is the value currently
24PLLERead-back for the PL L Enable bit. When one, the PLL is currently
25PLLCRead-back for the PLL Connect bit. When PLLC and PLLE are both
26PLOCKReflects the PLL Lock status. When zero, the PLL is not locked.
31:27 -Reserved, user software should not write ones to reserved bits. The
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Chapter 4: LPC23XX Clocking and power control
value
0
used by the PLL, and is one less than the actual multiplier.
NA
value read from a reserved bit is not defined.
0
used by the PLL, and is one less than the actual divider.
0
activated. When zero, the PLL is turned off. This bit is automatically
cleared when Power-down mode is activated.
0
one, the PLL is connected as the clock source for the LPC2300.
When either PLLC or PLLE is zero, the PLL is bypassed. This bit is
automatically cleared when Power-down mode is activated.
0
When one, the PLL is locked onto the requested frequency. See
text for details.
NA
value read from a reserved bit is not defined.
6.7PLL Interrupt: PLOCK
The PLOCK bit in the PLLSTAT register reflects th e lock status of the PLL. When the PLL
is enabled, or parameters are changed, the PLL requires some time to establish lock
under the new conditions. PLOCK can be monitored to determine when the PLL may be
connected for use. The value of PLOCK may not be stable when the PLL reference
frequency (F
, the frequency of REFCLK, which is equal to the PLL input frequency
REF
divided by the pre-divider value) is less than 100 kHz or greater than 20 MHz. In these
cases, the PLL may be assumed to be stable after a start-up time has passed. This time is
500 μs when FREF is greater than 400 kHz and 200 / FREF seconds when FREF is less
than 400 kHz
PLOCK is connected to the interrupt controller. This allows for software to turn on the PLL
and continue with other functions without having to wait for the PLL to achieve lock. When
the interrupt occurs, the PLL may be connected, and the interrupt disabled.
6.8PLL Modes
The combinations of PLLE and PLLC are shown in Table 4–41.
Table 41.PLL control bit combinations
PLLCPLLEPLL Function
00PLL is turned off and disconnected. The PLL outputs the unmodified clock
input.
01The PLL is active, but not yet connected. The PLL can be connected after
PLOCK is asserted.
10Same as 00 combination. This prevents the possibility of the PLL being
connected without also being enabled.
11The PLL is active and has been connected as the system clock source.
A correct feed sequence must be written to the PLLFEED register in order for changes to
the PLLCON and PLLCFG registers to take effect. The feed sequence is:
1. Write the value 0xAA to PLLFEED.
2. Write the value 0x55 to PLLFEED.
The two writes must be in the correct sequence, and must be consecutive APB bus
cycles. The latter requirement implies that interrupts must be disabled for the duration of
the PLL feed operation. If either of the feed values is incorrect, or one of the previously
mentioned conditions is not met, any changes to the PLLCON or PLLCFG register will not
become effective.
7:0PLLFEED The PLL feed sequence must be written to this register in order for
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Chapter 4: LPC23XX Clocking and power control
value
0x00
PLL configuration and control register changes to take effect.
6.10PLL and Power-down mode
Power-down mode automatically turns off and disconnects the PLL. Wakeup from
Power-down mode does not automatically restore the PLL settings, this must be done in
software. Typically, a routine to activate the PLL, wait for lock, and then connect the PLL
can be called at the beginning of any interrupt service routine that might be called due to
the wakeup. It is important not to attempt to restart the PLL by simply feeding it when
execution resumes after a wakeup from Power-down mode. This would enable and
connect the PLL at the same time, before PLL lock is established.
6.11PLL frequency calculation
The PLL equations use the following parameters:
Table 43.PLL frequency parameter
ParameterDescription
F
IN
F
CCO
NPLL Pre-divider value from the NSEL bits in the PLLCFG register (PLLCFG
MPLL Multiplier value from the MSEL bits in the PLLCFG register (PLLCFG
F
REF
the frequency of PLLCLKIN from the Clock Source Selection Multiplexer.
the frequency of the SYSCLK (output of the PLL Current Controlled Oscillator)
NSEL field + 1). N is an integer from 1 through 32.
MSEL field + 1). Not all potential values are supported. See below.
PLL internal reference frequency, FIN divided by N.
The PLL output frequency (when the PLL is both active and connected) is given by:
= (2 × M × FIN) / N
F
CCO
The PLL inputs and settings must meet the following:
The PLL equation can be solved for other PLL parameters:
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Chapter 4: LPC23XX Clocking and power control
M = (F
N = (2 × M × F
FIN = (F
× N) / (2 × FIN)
CCO
) / F
IN
× N) / (2 × M)
CCO
CCO
Allowed values for M:
At higher oscillator frequencies, in the MHz range, values of M from 6 through 512 are
allowed. This supports the entire useful range of both the main oscillator and the IRC.
For lower frequencies, specifically when the RTC is used to clock the PLL, a set of 65
additional M values have been selected for supporting baud rate generation, CAN/USB
operation, and attaining even MHz frequencies. These values are shown in Table 4–44
Table 44.Additional Multiplier Values for use with a Low Frequency Clock Input
PLL parameter determination can be simplified by using a spreadsheet availab le from
NXP. To determine PLL parameters by hand, the following general procedure may be
used:
1. Determine if the application requires use of the USB interface. The USB requires a
50% duty cycle clock of 48 MHz within a very small tolerance, which means that F
must be an even integer multiple of 48 MHz (i.e. an in teger multiple of 9 6 MHz), within
a very small tolerance.
2. Choose the desired processor operating frequency (CCLK). This may be based on
processor throughput requirements, need to support a specific set of UART baud
rates, etc. Bear in mind that peripheral devices may be running from a lower clock
frequency than that of the processor (see Section 4–7 “
and Section 4–8 “
Power control” on page 63). Find a value for F
Clock dividers” on page 60
that is close to a
CCO
multiple of the desired CCLK frequency, bearing in mind the requirement for USB
support in [1] above, and that lower values of F
3. Choose a value for the PLL input frequency (FIN). This can be a clock obtained from
4. Calculate values for M and N to produce a sufficiently accurate F
In general, it is better to use a smaller value for N, to reduce the level of multiplication that
must be accomplished by the CCO. Due to the difficulty in finding the best values in some
cases, it is recommended to use a spreadsheet or similar method to show many
possibilities at once, from which an overall best choice may be selected. A spreadsheet is
available from NXP for this purpose.
6.13Examples of PLL settings
The following examples illustrate selecting PLL values based on different system
requirements.
Example 1)
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Chapter 4: LPC23XX Clocking and power control
the main oscillator, the RTC oscillator, or the on-chip RC oscillator. For USB support,
the main oscillator should be used.
frequency. The
CCO
desired M value -1 will be written to the MSEL field in PLLCFG. The desired N value -1
will be written to the NSEL field in PLLCFG.
Assumptions:
• The USB interface will be used in the application. The lowest integer multiple of
96 MHz that falls within the PLL operating range (288 MHz) will be targeted.
• The desired CPU rate = 60 MHz.
• An external 4 MHz crystal or clock source will be used as the system clock source.
Calculations:
M = (F
Start by assuming N = 1, since this produces the smallest multiplier needed for the PLL.
So, M = 288 × 10
look further for a good set of PLL configuration values. The value written to PLLCFG
would be 0x23 (N - 1 = 0; M - 1 = 35 = 0x23).
The potential CPU clock rate can be determined by dividing F
frequency: 288 × 10
Divider is then 5, giving us 57.6 MHz as the nearest value to the desired CPU clock rate.
If it is important to obtain exactly 60 MHz, an F
down to both 48 MHz and 60 MHz. The only possibility is 480 MHz. Divided by 10, this
gives the 48 MHz with a 50% duty cycle needed by the USB block. Divided by 8, it gives
60 MHz for the CPU clock. PLL settings for 480 MHz are N = 1 and M = 60.
× N) / (2 × FIN)
CCO
6
/(2× 4 × 106) = 36. Since the result is an integer, there is no need to
by the desired CPU
6
/60× 106= 4.8. The nearest integer value for the CPU Clock
rate must be found that can be divided
CCO
CCO
Example 2)
Assumptions:
• The USB interface will not be used in the application.
• The desired CPU rate = 72 MHz
• The 32.768 kHz RTC clock source will be used as the system clock source
that can produce our desired CPU clock rate and is
CCO
within the PLL operating range is 288 MHz (4 × 72 MHz). Start by assuming N = 1, since
this produces the smallest multiplier needed for the PLL.
6
So, M = 288 × 10
/(2× 32,768) = 4,394.53125. This is not an integer, so the CPU
frequency will not be exactly 288 MHz with this setting. Since this case is less obvious, it
may be useful to make a table of possibilities for different values of N (see Table 4–45
Beyond N = 7, the value of M is out of range or not supported, so the table stops there. In
the table, the calculated M value is rounded to the nearest integer. If this results in CCLK
being above the maximum operating frequency (72 MHz), it is allowed if it is not more than
½% above the maximum frequency.
In general, larger values of F
frequency. Even the first table entry shows a very small error of just over 1 hundredth of a
percent, or 107 parts per million (ppm). If that is not accurate enough in the application,
the second case gives a much smaller error of 7 ppm.
Remember that when a frequency below about 1 MHz is used as the PLL clock source,
not all multiplier values are available. As it turns out, all of the rounded M values found in
Table 4–45
of this example are supported, as may be confirmed in Table 4–44.
If PLL calculations suggest use of unsupported multiplier values, those values must be
disregarded and other values examined to find the best fit. Multiplier values one count off
from calculated values may also be good possibilities..
The value written to PLLCFG for the second table entry would be 0x12254
(N - 1 = 1 = 0x1; M - 1 = 8788 = 0x2254).
6.14PLL setup sequence
The following sequence must be followed step by step in order to have the PLL initialized
an running:
1. Disconnect the PLL with one feed sequence if PLL is already connected.
2. Disable the PLL with one feed sequence.
3. Change the CPU Clock Divider setting to speed up operation without the PLL, if
desired.
4. Write to the Clock Source Selection Control register to change the clock source.
result in a more stable PLL when the input clock is a low
5. Write to the PLLCFG and make it effective with one feed sequen ce. The PLLCFG can
6. Enable the PLL with one feed sequence.
7. Change the CPU Clock Divider setting for the operation with the PLL. It's critical to do
8. Wait for the PLL to achieve lock by monito ring the PLOCK bit in the PLLSTA T register,
9. Connect the PLL with one feed sequence.
It's very important not to merge any steps above. For example, don't update the PLLCFG
and enable the PLL simultaneously with the same feed sequence.
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Chapter 4: LPC23XX Clocking and power control
only be updated when the PLL is disabled.
this before connecting the PLL.
or using the PLOCK interrupt, or wait for a fixed time when the input clock to PLL is
slow (i.e. 32 kHz). The value of PLOCK may not be stable when the PLL reference
frequency (FREF, the frequency of REFCLK, which is equal to the PLL input
frequency divided by the pre-divider value) is less than 100 kHz or greater than
20 MHz. In these cases, the PLL may be assumed to be stable after a start-up time
has passed. This time is 500 µs when FREF is greater than 400 kHz and 200 / FREF
seconds when FREF is less than 400 kHz.
7.Clock dividers
The output of the PLL must be divided down for use by the CPU and the USB block.
Separate dividers are provided such that the CPU frequency can be determined
independently from the USB block, which always requires 48 MHz with a 50% duty cycle
for proper operation.
The CCLKCFG register controls the division of the PLL output before it is used by the
CPU. When the PLL is bypassed, the division may be by 1. When the PLL is running, the
output must be divided in order to bring the CPU clock frequency (CCLK) within operating
limits. An 8 bit divider allows a range of options, including slowing CPU operation to a low
rate for temporary power savings without turning off the PLL.
Note: when the USB interface is used in an application, CCLK must be at least 18 MHz in
order to support internal operations of the USB block.
7:0 CCLKSELSelects the divide value for creating the CPU clock (CCLK) from the
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Chapter 4: LPC23XX Clocking and power control
description
value
0x00
PLL output.
Only 0 and odd values (1, 3, 5, ..., 255) are supported and can be
used when programming the CCLKSEL bits.
Warning: Using an even value (2, 4, 6, ..., 254) when setting the
CCLKSEL bits may result in incorrect operation of the device.
The CCLK is derived from the PLL output signal, divided by CCLKSEL + 1. Having
CCLKSEL = 1 results in CCLK being one half the PLL output, CCLKSEL = 3 results in
CCLK being one quarter of the PLL output, etc..
The USBCLKCFG register controls the division of the PLL output before it is used by the
USB block. If the PLL is bypassed, the division may be by 1. In that case, the PLL input
frequency must be 48 MHz, with a 500 ppm tolerance. When the PLL is running, the
output must be divided in order to bring the USB clock frequency to 48 MHz with a 50%
duty cycle. A 4-bit divider allows obtaining the correct USB clock from any even multiple of
48 MHz (i.e. any multiple of 96 MHz) within the PLL operating range.
Remark: The Internal RC clock can not be used as a clock source for USB because a
more precise clock is needed (see Table 4–35
T able 48. IRC Trim register (IRCTRIM - address 0xE01F C1A4) bit description
BitSymbolDescriptionReset
7:0IRCtrimIRC trim value. It controls the on-chip 4 MHz IRC frequency.0xA0
15:8-Reserved. Software must write 0 into these bits.NA
[1] Actual reset value depends on IRC factory trimming.
7.4Peripheral Clock Selection registers 0 and 1 (PCLKSEL0 0xE01F C1A8 and PCLKSEL1 - 0xE01F C1AC)
A pair of bits in a Peripheral Clock Selection register controls the rate of the clock signal
that will be supplied to the corresponding peripheral as specified in Table 4–49
1:0PCLK_WDTPeripheral clock selection for WDT.00
3:2PCLK_TIMER0Peripheral clock selection for TIMER0.00
5:4PCLK_TIMER1Peripheral clock selection for TIMER1.00
7:6PCLK_UART0Peripheral clock selection for UART0.00
9:8PCLK_UART1Peripheral clock selection for UART1.00
11:10-Unused, always read as 0.00
13:12PCLK_PWM1Peripheral clock selection for PWM1.00
15:14PCLK_I2C0Peripheral clock selection for I2C0.00
17:16PCLK_SPIPeripheral clock selection for SPI.00
19:18PCLK_RTC
21:20PCLK_SSP1Peripheral clock selection for SSP1.00
23:22PCLK_DACPeripheral clock selection for DAC.00
25:24PCLK_ADCPeripheral clock selection for ADC.00
27:26PCLK_CAN1Peripheral clock selection for CAN1.00
29:28PCLK_CAN2Peripheral clock selection for CAN2.00
31:30PCLK_ACFPeripheral clock selection for CAN filtering.00
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Chapter 4: LPC23XX Clocking and power control
and Table 4–51. For details on the CCLK clock see Figure 4–19.
description
[1]
Peripheral clock selection for RTC.00
value
[1]
,
value
[1] For PCLK_RTC only, the value ’01’ is illegal. Do not write ’01’ to the PCLK_RTC. Attempting to write ’01’
1:0PCLK_BAT_RAMPeripheral clock selection for the battery supported RAM.00
3:2PCLK_GPIOPeripheral clock selection for GPIOs.00
5:4PCLK_PCBPeripheral clock selection for the Pin Connect block.00
7:6PCLK_I2C1Peripheral clock selection for I2C1.00
9:8-Unused, always read as 0.00
11:10PCLK_SSP0Peripheral clock selection for SSP0.00
13:12PCLK_TIMER2Peripheral clock selection for TIMER2.00
15:14PCLK_TIMER3Peripheral clock selection for TIMER3.00
17:16PCLK_UART2Peripheral clock selection for UART2.00
19:18PCLK_UART3Peripheral clock selection for UART3.00
21:20PCLK_I2C2Peripheral clock selection for I2C2.00
23:22PCLK_I2SPeripheral clock selection for I2S.00
25:24PCLK_MCIPeripheral clock selection for MCI.00
27:26-Unused, always read as 0.00
29:28PCLK_SYSCONPeripheral clock selection for the System Control block.00
31:30-Unused, always read as 0.00
Table 51.Peripheral Clock Selection register bit values
PCLKSEL0 and PCLKSEL1
individual peripheral’ s clock
select options
00PCLK_xyz = CCLK/400
01PCLK_xyz = CCLK
10PCLK_xyz = CCLK/2
11Peripheral’s clock is selected to PCLK_xyz = CCLK/8
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Chapter 4: LPC23XX Clocking and power control
description
value
FunctionReset
value
[1]
except for CAN1, CAN2, and CAN filtering when ’11’
selects PCLK_xyz = CCLK/6.
[1] For PCLK_RTC only, the value ’01’ is illegal. Do not write ’01’ to the PCLK_RTC. Attempting to write ’01’
results in the previous value being unchanged.
8.Power control
The LPC2300 supports a variety of power control features. Ther e are three special modes
of processor power reduction: Idle mode, Sleep mode, and Power-down mode. The CPU
clock rate may also be controlled as needed by changing clock sources, re-configuring
PLL values, and/or altering the CPU clock divider value. This allows a trade-off of power
versus processing speed based on application requirements. In addition, Peripheral
Power Control allows shutting down the clocks to individual on-chip peripherals, allowing
fine tuning of power consumption by eliminating all dynamic power use in any peripher als
that are not required for the application.
The LPC2300 also implements a separate power domain in order to allow turning off
power to the bulk of the device while maintaining operation of the Real Time Clock and a
small static RAM, referred to as the Battery RAM. This feature is described in more detail
in Section 4–8.10
When Idle mode is entered, the clock to the core is stopped. Resumption from the Id le
mode does not need any special sequence but re-enabling the clock to the ARM core.
In Idle mode, execution of instructions is suspended until either a Reset or interrupt
occurs. Peripheral functions continue operation du ring Idle mode and may generate
interrupts to cause the processor to resume execution. Idle mode eliminates dynamic
power used by the processor itself, memory systems and related controllers, and internal
buses.
8.2Sleep mode
When the chip enters the Sleep mode, the main oscillator is powered down and all clocks
are stopped. The output of the IRC is disabled but the IRC is not powered down for a fast
wakeup later. The 32 kHz RTC oscillator is not stopped because the RTC interrupts may
be used as the wakeup source. The Flash is le ft in the st andby mode allowing a very q uick
wakeup. The PLL is automatically turned off and disconnected. The CCLK and USBCLK
clock dividers automatically get reset to zero.
The processor state and registers, peripheral registers, and internal SRAM values are
preserved throughout Sleep mode and the logic levels of chip pins remain static. The
Sleep mode can be terminated and normal operation resumed by eith er a Reset or certain
specific interrupts that are able to function without clocks. Since all dynamic operation of
the chip is suspended, Sleep mode reduces chip power consumption to a very low value.
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Chapter 4: LPC23XX Clocking and power control
On the wakeup of sleep mode, if the IRC was used before entering sleep mode, the 2-bit
IRC timer starts counting and the code execution and peripherals activities will resume
after the timer expires (4 cycles). If the main external oscillator was used, the 12-bit main
oscillator timer starts counting and the code execution will resume when the timer expires
(4096 cycles). The PLL and the clock dividers must be reconfigured after wakeup.
8.3Power-down mode
Power-down mode does everything that Sleep mode does, but also turns off the Flash
memory. This saves more power, but requires waiting for resumption of Flash operation
before execution of code or data access in the Flash memory can be accomplished.
When the chip enters Power-down mode, the IRC, the main oscillator, and all clocks are
stopped. The 32kHz RTC oscillator is not stopped because the RTC interrupts may be
used as the wakeup source. The flash is forced into Power-down mode. The PLL is
automatically turned off and disconnected. The CCLK and USBCLK clock dividers
automatically get reset to zero.
On the wakeup from Power-down m ode, if the IRC was used before enter ing power -down
mode, after IRC-start-up time (60 μs), the 2-bit IRC timer starts counting and expires in 4
cycles. The code execution can then be resumed immediately upon the expiration of the
IRC timer if the code was running from SRAM. In the meantime, the Flash wakeup-timer
generates Flash start-up time 100 μs. When it times out, access to the Flash is enabled.
The PLL and clock dividers must be reconfigured after wakeup.
A Power Control for Peripherals feature allows individual peripherals to be turned off if
they are not needed in the application, resulting in additional power savings. This is
detailed in the description of the PCONP register.
8.5Register description
The Power Control function uses registers shown in Table 4–52. More detailed
descriptions follow.
Table 52.Power Control registers
NameDescriptionAccess Reset
PCONPower Contro l Register. This register
INTWAKE Interrupt Wakeup Register. Controls which
PCONPPower Control for Peripherals Register. This
Chapter 4: LPC23XX Clocking and power control
contains control bits that enable the two
reduced power operating modes of the
LPC2300. See Table 4–53
interrupts will wake the LPC2300 from
power-down mode. See Table 4–55
register contains control bits that enable and
disable individual peripheral functions,
allowing elimination of power consumption by
peripherals that are not needed.
.
UM10211
[1]
value
R/W0x000xE01F C0C0
R/W0x000xE01F C144
R/W0xE01F C0C4
Address
[1]Reset Value reflects the data stored in used bits only. It does not include reserved bits content.
8.6Power Mode Control register (PCON - 0xE01F C0C0)
Reduced power modes are controlled via the PCON register, as described in Table 4–53.
Table 53.Power Mode Control register (PCON - address 0xE01F C0C0) bit description
BitSymbolDescriptionReset
0PM0 (IDL) Power mode control bit 0. See text and table below for details.0
1PM1 (PD)Power mode control bit 1. See text and table below for details.0
2BODPDMBrown-Out Power-down mode. When BODPDM is 1, the Brown-Out
Detect circuitry will turn off when chip Power-down mode is entered,
resulting in a further reduction in power usage. Howeve r, the possibility
of using Brown-Out Detect as a wakeup source from Power-down mode
will be lost.
When 0, the Brown-Out Detect function remains active during
Power-down mode.
See the System Control Block chapter for details of Brown-Out
detection.
3BOGDBrown-Out Global Disabl e. When BOGD is 1, the Brown-Out Detect
circuitry is fully disabled at all times, and does not consume power.
When 0, the Brown-Out Detect circuitry is enabled.
See the System Control Block chapter for details of Brown-Out
Table 53.Power Mode Control register (PCON - address 0xE01F C0C0) bit description
BitSymbolDescriptionReset
4BORDBrown-Out Reset Disable. When BORD is 1, the second stage of low
6:3-Reserved, user software should not write ones to reserved bits. The
7PM2Power mode control bit 2. See text and table below for details.0
Encoding of Reduced Power Modes
The PM2, PM1, and PM0 bits in PCON allow entering reduced power modes as needed.
The encoding of these bits allows backward compatibility with devices that previously only
supported Idle and Power-down modes. Table 4–54
three reduced power modes supported by the LPC2300.
Table 54.Encoding of reduced power modes
PM2, PM1, PM0 Description
000Normal operation
001Idle mode. Causes the processor clock to be stopped, while on-chip peripherals
101Sleep mode. This mode is similar to Power-down mode (the oscillator and all
010Power-down mode. Causes the oscillator and all on-chip clocks to be stopped.
1 10Reserved.
OthersReserved, not currently used.
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Chapter 4: LPC23XX Clocking and power control
value
0
voltage detection (2.6 V) will not cause a chip reset.
When BORD is 0, the reset is enabled. The first stage of low voltage
detection (2.9 V) Brown-Out interrupt is not affected.
See the System Control Block chapter for details of Brown-Out
detection.
NA
value read from a reserved bit is not defined.
below shows the encoding for the
remain active. Any enabled interrupt from a peripheral or an external interrupt
source will cause the processor to resume execution. See text for details.
on-chip clocks are stopped), but the Flash memory is left in Standby mode. This
allows a more rapid wakeup than Power-down mode because the Flash
reference voltage regulator start-up time is not needed. See text for details.
A wakeup condition from an external interrupt can cause the oscillator to
re-start, the PD bit to be cleared, and the processor to resume execution. See
text for details.
Enable bits in the INTWAKE register allow the external interrupts to wake up the
processor if it is in Power-down mode. The related EINTn function must be mapped to the
pin in order for the wakeup process to take place. It is not necessary for the interrupt to be
enabled in the V ectored Interr upt Controller for a wake up to t ake place. T his arra ngemen t
allows additional capabilities, such as having an external interrupt input wake up the
processor from Power-down mode without causing an interrupt (simply resuming
operation), or allowing an interrupt to be enabled during Power Down with out waking the
processor up if it is asserted (eliminating the need to disable the interrupt if the wakeup
feature is not desirable in the application). Details of the wakeup operations are shown in
For an external interrupt pin to be a source that would wake up the micro controller from
Power-down mode, it is also necessary to clear the corresponding interrupt flag (see
4ETHWAKEWhen one, assertion of the Wake-up on LAN interrupt
5USBWAKEWhen one, activity on the USB bus will wake up the processor
6CANWAKEWhen one, activity of the CAN bus will wake up the processor
7GPIO0WAKEWhen one, specified activity on GPIO pins (port 0) enabled for
8GPIO2WAKEWhen one, specified activity on GPIO pins (port 2) enabled for
13:9-Reserved, user software should not write ones to reserved bits.
14BODWAKEWhen one, Brown-Out Detect interrupt will wake up the
15RTCWAKEWhen one, assertion of an RTC interrupt will wake up the
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Chapter 4: LPC23XX Clocking and power control
External Interrupt flag register (EXTINT - 0xE01F C140)”).
will wake up the processor from
Power-down mode.
will wake up the processor from
Power-down mode.
will wake up the processor from
Power-down mode.
will wake up the processor from
Power-down mode.
(WakeupInt) of the Ethernet block will wake up the processor
from Power-down mode.
from Power-down mode. Any change of state on the USB data
pins will cause a wakeup when this bit is set. For details on the
relationship of USB to Power-down mode and wakeup, see the
relevant USB chapter(s).
from Power-down mode. Any change of state on the CAN
receive pins will cause a wakeup when this bit is set.
wakeup will wake up the processor from Power-down mode.
See the GPIO chapter for details.
wakeup will wake up the processor from Power-down mode.
See the GPIO chapter for details.
The value read from a reserved bit is not defined.
processor from Power-down mode.
Note: since there is a delay before execution begins, there is
no guarantee that execution will resume before V
fallen below the lower BOD threshold, which prevents
execution. If execution does resume, there is no guarantee of
how long the processor will continue execution before the lower
BOD threshold terminates execution. These issues depend on
the slope of the decline of V
capacitance (between V
DD(3V3)
. High decoupling
DD(3V3)
and ground) in the vicinity of the
LPC2300 will improve the likelihood that software will be able to
do what needs to be done when power is in the process of
being lost.
8.8Power Control for Peripherals register (PCONP - 0xE01F C0C4)
The PCONP register allows turning off selected peripheral functions for the purpose of
saving power. This is accomplished by gating off the clock source to the specified
peripheral blocks. A few peripheral functions cannot be turned off (i.e. the Watchdog timer,
GPIO, the Pin Connect block, and the System Control block).
Some peripherals, particularly those that include analog functions, may consume power
that is not clock dependent. These peripherals may cont ain a separate d isable control that
turns off additional circuitry to reduce power. Information on peripheral specific power
saving features may be found in the chapter describing that peri pheral.
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Chapter 4: LPC23XX Clocking and power control
Each bit in PCONP controls one peripheral as shown in Table 4–56
. The bit numbers
correspond to the related peripheral number as shown in the APB peripheral map Table
2–10 “APB peripherals and base addresses”.
If a peripheral control bit is 1, that peripheral is enabled. If a perip h er al bit is 0, that
peripheral’s clock is disabled (gated off) to conserve power. For example if bit 19 is 1, the
2
C1 interface is enabled. If bit 19 is 0, the I2C1 interface is disabled.
I
Important: valid read from a peripheral register and valid write to a peripheral
register is possible only if that peripheral is enabled in the PCONP register!
Table 56.Power Control for Peripherals register (PCONP - address 0xE01F C0C4) bit
description
BitSymbolDescriptionReset
value
0-Unused, always 0.0
1PCTIM0Timer/Counter 0 power/clock co ntrol bit.1
2PCTIM1Timer/Counter 1 power/clock co ntrol bit.1
3PCUART0UART0 power/clock control bit.1
4PCUART1UART1 power/clock control bit.1
5-Unused, always 0.1
6PCPWM1PWM1 power/clock control bit.1
2
7PCI2C0The I
8PCSPIThe SPI interface power/clock control bit.1
9PCRTCThe RTC power/clock control bit.1
10PCSSP1The SSP1 interface power/clock control bit.1
11PCEMCExternal Memory Controller1
12PCADA/D converter (ADC) power/clock control bit.
13PCAN1CAN Controller 1 power/clock control bit.0
14PCAN2CAN Controller 2 power/clock control bit.0
18:15 -Reserved, user software should not write ones to reserved bits. The
19PCI2C1The I
20-Unused, always 00
21PCSSP0The SSP0 interface power/clock control bit.1
C0 interface power/clock control bit.1
Note: Clear the PDN bit in the AD0CR (see Section 27–6.1
clearing this bit, and set this bit before setting PDN.
Table 56.Power Control for Peripherals register (PCONP - address 0xE01F C0C4) bit
BitSymbolDescriptionReset
22PCTIM2Timer 2 power/clock control bit.0
23PCTIM3Timer 3 power/clock control bit.0
24PCUART2UART 2 power/clock control bit.0
25PCUART3UART 3 power/clock control bit.0
26PCI2C2I
27PCI2SI
28PCSDCSD card interface power/clock control bit.0
29PCGPDMA GP DMA function power/clock control bit.0
30PCENETEth ernet blo ck power/clock control bit.0
31PCUSBUSB interface power/clock control bit.0
8.9Power control usage notes
description
2
2
UM10211
Chapter 4: LPC23XX Clocking and power control
value
C interface 2 power/clock control bit.1
S interface power/clock control bit.0
After every reset, the PCONP register contains the valu e that e nab les sele cted interfaces
and peripherals controlled by the PCONP to be enabled. Therefore, apart from proper
configuring via peripheral dedicated registers, the user’s application might have to access
the PCONP in order to start using some of the on-board peripherals.
Power saving oriented systems should have 1s in the PCONP register only in positions
that match peripherals really used in the application. All other bits, declared to be
"Reserved" or dedicated to the peripherals not used in the current application, must be
cleared to 0.
8.10Power domains
The LPC2300 provides two independent power domains that allow the bulk of the device
to have power removed while maintaining operation of the Real Time Clock and the
Battery RAM.
The VBAT pin supplies power only to the RTC and the Battery RAM. These two functions
require a minimum of power to operate, which can be supplied by an external battery.
When the CPU and the rest of chip functions are stopped and power removed, the RTC
can supply an alarm output that may be used by external hardware to restore chip power
and resume operation. Details may be found in Section 26–2
Note: The RTC and the battery RAM operate independently from each other. Therefore,
the battery RAM can be accessed at any time, regardless of whether the RTC is enabled
or disabled via a dedicated bit in the PCONP register.
.
9.Wakeup timer
The LPC2300 begins operation at power-up and when awakened from Power-down mod e
by using the 4 MHz IRC oscillator as the clock source (see Section 3–4
operation quickly in these cases. If the main oscillator or the PLL is needed by the
application, software will need to enable these features and wait for them to stabilize
before they are used as a clock source.
When the main oscillator is initially activated, the wakeup timer allows software to ensure
that the main oscillator is fully functional before the processor uses it as a clock source
and starts to execute instructions. This is important at power on, all types of Reset, and
whenever any of the aforementioned functions are turned off for any reason. Since the
oscillator and other functions are turned off during Power-down mode, any wakeup of the
processor from Power-down mode makes use of the Wakeup Timer.
The Wakeup T i mer monitors the crystal oscillator as the means of checking whether it is
safe to begin code execution. When power is applied to the chip, or some event caused
the chip to exit Power-down mode, some time is required for the oscillator to produce a
signal of sufficient amplitude to drive the clock logic. The amount of time depends on
many factors, including the rate of V
crystal and its electrical characteristics (if a quartz crystal is used), as well as any other
external circuitry (e.g. capacitors), and the characteristics of the oscillator itself under the
existing ambient conditions.
Once a clock is detected, the Wakeup Timer counts a fixed number of clocks (4096), then
sets the flag (OSCSTAT bit in the SCS register) that indicates that the main oscillator is
ready for use. Software can then switch to the main oscillator and, if needed, start the
PLL. See Section 4–4.2
This chapter describes the EMC controller for the following parts:
• LPC2377/78
• LPC2388
LPC2361/62, LPC2364/65/66/67/68, and LPC2387 do not have an EMC controller.
2.Basic configuration
The EMC is configured using the following registers:
3.Introduction
4.Features
1. Power: In the PCONP register (Table 4–56Remark: The EMC is enabled on reset (PCEMC = 1). On POR and warm reset, the
EMC is enabled as well, see Section 5–11.1
2. Clock: see Section 4–7.1
3. Pins: Select data, address, and control pins and their modes in PINSEL6/8/9 and
PINMODE6/8/9 (see Section 9–5
4. Configuration: see Table 5–62
The External Memory Controller (EMC) is an ARM PrimeCell™ MultiPort Memory
Controller peripheral offering support for asynchronous static memory devices such as
RAM, ROM and Flash. The EMC is an Advanced Microcontroller Bus Architecture
(AMBA) compliant peripheral.
.
).
and Table 5–64.
), set bit PCEMC.
.
• Asynchronous static memory device support including RAM, ROM, and Flash, with or
without asynchronous page mode.
• Low transaction latency.
• Read and write buffers to reduce latency and to impr ove performance.
• 8-bit wide static memory support.
• Can be used as an interface to some external I/O devices.
• Two chip selects for static memory devices.
5.Functional overview
This chapter describes the major functional blocks of the EMC.
The functions of the EMC blocks are described in the following sections:
• AHB slave register interface.
• AHB slave memory interfaces.
• Data buffers.
• Memory controller state machine.
• Pad interface.
7.AHB Slave register interface
The AHB slave register interface block enables the registers of the EMC to be
programmed. This module also contains most of the registers and performs the majority of
the register address decoding.
To eliminate the possibility of endianness problems, all data transfers to and from the
registers of the EMC must be 32 bits wide.
Note: If an access is attempted with a size other than a word (32 bits), it causes an
ERROR response to the AHB bus and the transfer is terminated.
The AHB slave memory interface allows access to external memories.
7.1.1Memory transaction endianness
The endianness of the data transfers to a nd from the exter nal memorie s is de te rm ined b y
the Endian mode (N) bit in the EMCConfig Register.
Note: The memory controller must be idle (see the busy field of the EMCStatus Register)
before endianness is changed, so that the data is transferred correctly.
7.1.2Memory transaction size
For the LPC23xx, memory transactions must be 8 bits wide. Any access attempted with a
size greater than 8 bits causes an ERROR response to the AHB bus and the transfer is
terminated.
7.1.3Write protected memory areas
Write transactions to write-protected memory areas genera te an ERROR resp onse to the
AHB bus and the transfer is terminated.
The AHB interface reads and writes via buffers to improve memory bandwid th and re duce
transaction latency. The EMC contains four 16-word buffers. The buffers can be used as
read buffers, write buffers, or a combination of both. The buffers are allocated
automatically.
They can be enabled or disabled for static memory using the EMCStaticConfig Registers.
7.2.1Write buffers
Write buffers are used to:
• Merge write transactions so that the number of external transactions are minimized.
Buffer data until the EMC can complete the write transaction, improving AHB write
latency.
• Reduce external memory traffic. This improves memory bandwidth and reduces
power consumption.
Write buffer operation:
• If the buffers are enabled, an AHB write operation writes into the Least Recently Used
(LRU) buffer, if empty.
If the LRU buffer is not empty, the contents of the buffer are flushed to memory to
make space for the AHB write data.
• If a buffer contains write data it is marked as dirty, and its contents are written to
memory before the buffer can be reallocated.
The write buffers are flushed whenever:
• The memory controller state machine is not busy performing accesses to external
The memory controller state machine is not busy performing accesses to external
memory, and an AHB interface is writing to a different buffer.
data from the buffer rather than memory, reducing transaction latency.
power consumption.
data is provided directly from the buffer.
dirty (contains write data), the write data is flushed to memory. When an empty buffer
is available the read command is posted to the memory.
A buffer filled by performing a read from memory is marked as not-dirty (not containing
write data) and its contents are not flushed back to the memory controller unless a
subsequent AHB transfer performs a write that hits the buffer.
7.3Memory controller state machine
The memory controller state machine comprises a static memory controller.
7.4Pad interface
The pad interface block provides the interface to the pads.
8.Memory bank select
Two independently-configurable memory chip selects are supported. Pins CS1 and CS0
are used to select static memory devices.
Static memory chip select ranges are each 64 kilobytes in size. Table 5–57
address ranges of the chip selects.
Table 57.Memory bank selection
Chip Select Pin Address RangeMemory Type Size of Range
The EMC receives two reset signals. One is Power-On Reset (POR), asserted when chip
power is applied, and when a brown-out condition is detected (see Section 3–5
“Brown-out detection” for details). The other reset is from the external Reset pin and the
Watchdog Timer.
A configuration bit in the SCS register, called EMC_Reset_Disable, allows control of how
the EMC is reset. The default configuration (EMC_Reset_Disable = 0) is that both EMC
resets are asserted when any type of reset event occurs. In this mode, all registers and
functions of the EMC are initialized upon any reset condition.
If EMC_Reset_Disable is set to 1, many portions of the EMC are only reset by a power-on
or brown-out event, in order to allow the EMC to retain its state through a warm reset
(external reset or watchdog reset). If the EMC is configured correctly, auto-refresh can be
maintained through a warm reset.
[1:0]Output 0x3Static memory chip selects. Default active LOW.
CS
Output 1Low active output enable for static memory devices.
Output 1Low active Byte Lane select signal 0.
Data outputs =
0x0000 0000
Description
External memory data lines. These are inputs when
data is read from external memory and outputs when
data is written to external memory.
Used for static memory devices.
11. Register description
This chapter describes the EMC registers and provides details required when
programming the microcontroller. The EMC registers are shown in Table 5–59
Table 59. EMC register summary
AddressRegister NameDescriptionWarm
0xFFE0 8000 EMCControlControls operation of the memory controller.0x10x3R/W
0xFFE0 8004EMCStatusProvides EMC status information.-0x5RO
0xFFE0 8008EMCConfigConfigures operation of the memory controller-0 x0R/W
0xFFE0 8080EMCStaticExtendedWait Time long static memory read and write transfers.-0x0R/W
0xFFE0 8200EMCStaticConfig0Selects the memory configuration for static chip select 0.-0x0R/W
0xFFE0 8204 EMCStaticWaitWen0Selects the delay from chip select 0 to write enable.-0x0R/W
0xFFE0 8208EMCStaticWaitOen0Selects the delay from chip select 0 or address change,
whichever is later, to output enable.
0xFFE0 820C EMCStaticWaitRd0Selects the delay from chip select 0 to a read access.-0x1FR/W
0xFFE0 8210EMCStaticWaitPage0Selects the delay for asynchronous page mode
sequential accesses for chip select 0.
0xFFE0 8214 EMCStaticWaitWr0Selects the delay from chip select 0 to a write access.-0x1FR/W
0xFFE0 8218 EMCStaticWaitTurn0Selects the number of bus turnaround cycles for chip
select 0.
0xFFE0 8220EMCStaticConfig1Selects the memory configuration for static chip select 1.-0x0R/W
0xFFE0 8224EMCStatic\WaitWen1Selects the delay from chip select 1 to write enable.-0x0R/W
0xFFE0 8228EMCStaticWaitOen1Selects the delay from chip select 1 or address change,
whichever is later, to output enable.
0xFFE0 822C EMCStaticWaitRd1Selects the delay from chip select 1 to a read access.-0x1FR/W
0xFFE0 8230EMCStaticWaitPage1Selects the delay for asynchronous page mode
sequential accesses for chip select 1.
0xFFE0 8234 EMCStaticWaitWr1Selects the delay from chip select 1 to a write access.-0x1FR/W
0xFFE0 8238 EMCStaticWaitTurn1Selects the number of bus turnaround cycles for chip
select 1.
-0x0R/W
-0x1FR/W
-0xFR/W
-0x0R/W
-0x1FR/W
-0xFR/W
POR
Reset
Value
Type
11.1EMC Control Register (EMCControl - 0xFFE0 8000)
The EMCControl Register is a read/write register that controls operation of the memory
controller. The control bits can be altered during normal operation. Table 5–60
bit assignments for the EMCControl Register.
Table 60. EMC Control register (EMCControl - address 0xFFE0 8000) bit description
BitSymbolValue DescriptionPOR
0EEMC Enable control. Indicates if the EMC is enabled or disabled:1
1MAddress mirror control. Indicates normal or reset memory map:1
0Disabled
1Enabled (POR and warm reset value).
Note: Disabling the EMC reduces power consumption. When the memory controller is
disabled the memory is not refreshed. The memory controller is enabled by setting the
enable bit or by reset.
This bit must only be modified when the EMC is in idle state.
Table 60. EMC Control register (EMCControl - address 0xFFE0 8000) bit description
BitSymbolValue DescriptionPOR
Reset
Value
2LLow-power mode control. Indicates normal, or low-power mode:0
0Normal mode (warm reset value).
1Low-power mode.
Note: Entering low-power mode reduces memory controller power consumption. The
memory controller returns to normal functional mode by clearing the low-power mode bit
(L), or by POR.
This bit must only be modified when the EMC is in idle state.
31:3--Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
[1] The external memory cannot be accessed in low-power or disabled state. If a memory access is performed an AHB error response is
generated. The EMC registers can be programmed in low-power and/or disabled state.
[1]
NA
11.2EMC Status Register (EMCStatus - 0xFFE0 8004)
The read-only EMCStatus Register provides EMC status information. Table 5–61 shows
the bit assignments for the EMCStatus Register.
Table 61. EMC Status register (EMCStatus - address 0xFFE0 8008) bit description
BitSymbolValueDescriptionPOR
0BBusy . This bit is used to ensure that the memory controller enters the low-power or
1SWrite buffer status. This bit enables the EMC to enter low-power mode or disabled
2SASelf-refresh acknowledge. This bit indicates the operating mode of the EMC:1
31:3 --Reserved, user software should not write ones to reserved bits. The value read
Reset
Value
1
disabled mode cleanly by determining if the memory controller is busy or not:
0EMC is idle (warm reset value).
1EMC is busy performing memory transactions, commands, auto-refresh cycles, or
The EMCConfig Register configures the operation of the memory controller. It is
recommended that this register is modified during system initialization, or when there are
no current or outstanding transactions. This can be ensured by waiting until the EMC is
idle, and then entering low-power or disabled mode. This register is accessed with one
wait state. Table 5–62
The EMCStaticExtendedWait register times long static memory read and write transfers
(which are longer that can be supported by the EMCStaticWaitRd[n] or
EMCStaticW aitW r[n] registers) when the EW bit of one of the EMCSt aticConfig registers is
enabled. There is only a single EMCStaticExtendedWait Register. This is used by the
relevant static memory chip select if the appropriate ExtendedWait (EW) bit in the
EMCStaticConfig Register is set. It is recommended that this register is modified during
system initialization, or when there are no current or outstanding transactio ns. However, if
necessary, these control bits can be altered during normal operation. This register is
accessed with one wait state.
9:0EXTENDEDWAITExternal wait time out in terms of the CCLK clock
31:10 --Reserved, user software should not write ones to
shows the bit assignments for the EMCStaticExtendedWait register.
0xFFE0 8080) bit description
cycles. The delay is (EXTENDWAIT + 1) x 16 x t
0x016 CCLK clock cycles (POR reset value).
n(n+1) x 16 CCLK clock cycles.
0x3F(0x3F+1) x 16 CCLK clock cycles.
reserved bits. The value read from a reserved bit is
not defined.
CCLK
Value
0x000
NA
For example, for a static memory read/write transfer time of 16 µs, and a CCLK frequency
of 50 MHz, the following value must be programmed into this register:
The EMCStaticConfig0-1 Registers configure the static memory configuration. It is
recommended that these registers are modified during system initialization, or when there
are no current or outstanding transactions. This can be ensured by waiting until the EMC
is idle, and then entering low-power, or disabled mode. These registers are accessed with
one wait state.
2--Reserved, user software should not write ones to reserved bits. The value read from
3PMPage mode. In page mode the EMC can burst up to four external accesses.
5:4--Reserved, user software should not write ones to reserved bits. The value read from
6PCChip select polarity. The value of the chip select polarity on power-on reset is 0.0
7--Reserved, user software should not write ones to reserved bits. The value read from
8EWExtended wait. Extended wait (EW) uses the EMCStaticExtendedWait Register to
18:9--Reserved, user software should not write ones to reserved bits. The value read from
19B
[2]
008 bit (POR reset value).
01Reserved.
10Reserved.
1 1Reserved.
a reserved bit is not defined.
Therefore devices with asynchronous page mode burst four or higher devices are
supported. Asynchronous page mode burst two devices are not supported and must
The EMCStaticWaitWen0-1 Registers enable you to program the delay from the chip
select to the write enable. It is recommended that these registers are modified during
system initialization, or when there are no current or outstanding tr ansactions. This can be
ensured by waiting until the EMC is idle, and then entering low-power, or disabled mode.
These registers are accessed with one wait state.
The EMCStaticWaitOen0-1 Registers enable you to program the delay from the chip
select or address change, whichever is later, to the output enable. It is recommended that
these registers are modified during system initialization, or when there are no current or
outstanding transactions. This can be ensured by waiting until the EMC is idle, and then
entering low-power, or disabled mode. These registers are accessed with one wait state.
The EMCSt aticWaitRd0-1 Registers enable you to program the delay from the chip select
to the read access. It is recommended that these registers are modified during system
initialization, or when there are no current or outstanding transactions. This can be
ensured by waiting until the EMC is idle, and then entering low-power , or disabled mo de. It
is not used if the extended wait bit is enabled in the EMCStaticConfig0-1 Registers. These
registers are accessed with one wait state.
4:0WAITRDNon-page mode read wait states or asynchronous page
31:5--Reserved, user software should not write ones to
shows the bit assignments for the EMCStaticWaitRd0-1 Registers.
0xFFE0 820C, 0xFFE0 822C) bit description
mode readfirst access wait state expressed in terms of
the CCLK clock cycles. Non-page mode read or
asynchronous page mode read, first read only wait state
time is: (WAITRD + 1) x t
0x01 CCLK clock cycle for read accesses.
n(n + 1) CCLK cycles for read accesses.
0x1F32 CCLK cycles for read accesses (POR reset value).
reserved bits. The value read from a reserved bit is not
The EMCSt aticWaitPage0-1 Registers enable you to program the delay for asynchronous
page mode sequential accesses. It is recommended that these registers are modified
during system initialization, or when there are no current or outst anding transa ctions. This
can be ensured by waiting until the EMC is idle, and then entering low-power, or disabled
mode. This register is accessed with one wait state.
The EMCSt aticWaitWr0-1 Registers enable you to program the delay from the chip select
to the write access. It is recommended that these registers are modified during system
initialization, or when there are no current or outstanding transactions. This can be
ensured by waiting until the EMC is idle, and then entering low-power, or disabled
mode.These registers are not used if the extended wait (EW) bit is enabled in the
EMCStaticConfig Register. These registers are accessed with one wait state.
The EMCStaticExtendedWait register times long static memory read and write transfers
(which are longer that can be supported by the EMCStaticWaitRd[n] or
EMCStaticW aitW r[n] registers) when the EW bit of one of the EMCSt aticConfig registers is
enabled. There is only a single EMCStaticExtendedWait Register. This is used by the
relevant static memory chip select if the appropriate ExtendedWait (EW) bit in the
EMCStaticConfig Register is set. It is recommended that this register is modified during
system initialization, or when there are no current or outstanding transactio ns. However, if
necessary, these control bits can be altered during normal operation. This register is
accessed with one wait state.
9:0EXTENDEDWAITExternal wait time out in terms of the CCLK clock
31:10 --Reserved, user software should not write ones to
shows the bit assignments for the EMCStaticExtendedWait register.
0xFFE0 8080) bit description
cycles. The delay is (EXTENDWAIT + 1) x 16 x t
0x016 CCLK clock cycles (POR reset value).
n(n+1) x 16 CCLK clock cycles.
0x3F(0x3F+1) x 16 CCLK clock cycles.
reserved bits. The value read from a reserved bit is
not defined.
CCLK
Value
0x000
NA
For example, for a static memory read/write transfer time of 16 µs, and a CCLK frequency
of 50 MHz, the following value must be programmed into this register:
The EMCStaticWaitTurn0-1 Registers enable you to program the number of bus
turnaround cycles. It is recommended that these registers are modified during system
initialization, or when there are no current or outstanding transactions. This can be
ensured by waiting until the EMC is idle, and then entering low-power, or disabled mode.
These registers are accessed with one wait state.
shows the bit assignments for the EMCStaticWaitTurn0-1 Registers.
0xFFE0 8218, 0xFFE0 8238) bit description
Bus turnaround time is (WAITTURN + 1) x t
01 CCLK clock cycle turnaround cycles
n(n + 1) CCLK clock cycles turnaround cycle.0xF
0xF16 CCLK turnaround cycles (POR reset value).
reserved bits. The value read from a reserved bit is not
defined.
CCLK
.
Value
NA
NXP Semiconductors
OE
CS
BLS[0]
D[7:0]
CE
OE
WE
IO[7:0]
A[a_m:0]
A[a_b:0]
To prevent bus contention on the external memory data bus, the WAITTURN field controls
the number of bus turnaround cycles added between static me mory read and write
accesses. The WAITTURN field also controls the number of turnaround cycles between
static memory accesses.
12. External memory interface
Shown in Figure 5–21 is the external memory interfacing for an 8-bit bank width.
8 bit wide memory banks do require all address lines down to A0. See Section 9–5.9
configuring pins for address lines.
Symbol "a_b" in the following figures refers to the highest order address line in the data
bus. Symbol "a_m" refers to the highest order address line of the me mory chip used in the
external memory interface.
See Table 1–2 for peripherals that are not implemented in all LPC23XX parts. The
corresponding interrupt signals are rese rve d .
2.Features
• ARM PrimeCell Vectored Interrupt Controller
• Mapped to AHB address space for fast access
• Supports 32 vectored IRQ interrupts
• 16 programmable interrupt priority levels
• Fixed hardware priority within each programmable priority level
• Hardware priority level masking
• Any input can be assigned as an FIQ interrupt
• Software interrupt generation
3.Description
The ARM processor core has two interrupt inputs called Interrupt Request (IRQ) an d Fast
Interrupt reQuest (FIQ). The Vectored Interrupt Controller (VIC) takes 32 interrupt request
inputs and programmably assigns them as FIQ or vectored IRQ types. The programmable
assignment scheme means that priorities of interrupt s from the va rious peripherals can be
dynamically assigned and adjusted.
Fast Interrupt reQuest (FIQ) requests have the high est priority. If more than one request is
assigned to FIQ, the VIC ORs the requests to produce the FIQ signal to the ARM
processor. The fastest possible FIQ latency is achieved when only one request is
classified as FIQ, because then the FIQ service routine can simply start dealing with that
device. But if more than one request is assigned to the FIQ class, the FIQ service routine
can read a word from the VIC that identifies which FIQ source(s) is (are) requesting an
interrupt.
Vectored IRQ’s, which include all interrupt request s that are not classified as FIQs, ha ve a
programmable interrupt priority. When more than one interrupt is assigned the same
priority and occur simultaneously, the one connected to the lowest numbered VIC channel
(see Table 6–86 on page 92
The VIC ORs the requests from all of the vectored IRQs to produce the IRQ signal to the
ARM processor. The IRQ service routine can start by reading a register from the VIC and
jumping to the address supplied by that register.
) will be serviced first.
4.Register description
The VIC implements the registers shown in Table 6–72. More detailed descriptions follow.
Vector Address Register holds the address of the currently
active interrupt.
[1] Reset Value reflects the data stored in used bits only. It does not include reserved bits content.
R/W00xFFFF FF00
Address
[1]
5.VIC registers
The following section describes the VIC registers in the order in which they are used in the
VIC logic, from those closest to the interrupt request inputs to those most abstracted for
use by software. For most people, this is also the best order to read about the registers
when learning the VIC.
The VICSoftInt register is used to generate soft ware interrupts. The contents of this
register are ORed with the 32 interrupt requests from the various peripherals, before any
other logic is applied.
The VICSoftIntClear register is a ’Write Only’ register. This register allows software to
clear one or more bits in the Software Interrupt register, without having to first read it.
5.3Raw Interrupt Status Register (VICRawIntr - 0xFFFF F008)
This is a read only register. This register reads out the state of the 32 interrupt requests
and software interrupts, regardless of enabling or classification.
Table 75.Raw Interrupt Status register (VICRawIntr - address 0xFFFF F008) bit description
This is a read/write accessible register. This register controls which of the 32 combined
hardware and software interrupt requests are enabled to contribute to FIQ or IRQ.
T able 76. Interrupt Enable register (VICIntEnable - address 0xFFFF F010) bit description
0Neither the hardware nor software interrupt request wi th this
bit number are asserted.
1The hardware or software interrupt request with this bit
number is asserted.
When this register is read, 1s indicate interrupt requests or software
interrupts that are enabled to contribute to FIQ or IRQ.
When this register is written, ones enable interrupt requests or
software interrupts to contribute to FIQ or IRQ, zeroes have no
effect. See Section 6–5.5 “
(VICIntEnClear - 0xFFFF F014)” on page 89 and Table 6–77 below
0The interrupt request with this bit number is assigned to the
IRQ category.
1The interrupt request with this bit number is assigned to the
FIQ category.
A bit read as 1 indicates a corresponding interrupt request being
enabled, classified as IRQ, and asserted
value
0
value
0
5.8FIQ Status Register (VICFIQStatus - 0xFFFF F004)
This is a read only register. This register reads out the state of those interrupt requests
that are enabled and classified as FIQ. If more than one request is classified as FIQ, the
FIQ service routine can read this register to see which request(s) is (are) active.
Table 80.FIQ Status register (VICFIQStatus - address 0xFFFF F004) bit description
BitSymbolDescriptionReset
value
31:0 See Table
6–87
“Interrupt
sources bit
allocation
table”.
A bit read as 1 indicates a corresponding interrupt request being
enabled, classified as IRQ, and asserted
0
5.9Vector Address Registers 0-31 (VICVectAddr0-31 - 0xFFFF F100 to
17C)
These are read/write accessible registers. These registers hold the addresses of the
Interrupt Service routines (ISRs) for the 32 vectored IRQ slots.
T able 81. Vector Address registers 0-31 (VICVectAddr0-31 - addresses 0xFFFF F100 to
BitSymbolDescriptionReset value
31:0 VICVectAddr T he VIC provides the contents of one of these registers in
5.10Vector Priority Registers 0-31 (VICVectPriority0-31 - 0xFFFF F200 to
27C)
These registers select a priority level for the 32 vectored IRQs. There are 16 priority
levels, corresponding to the values 0 through 15 decimal, of which 15 is the lowest priority.
The reset value of these registers defaults all interrupt to the lowest priority, allowing a
single write to elevate the priority of an individual interrupt.
response to a read of the Vector Address register (VICAddress
see Section 6–5.9
register (one of the 32 VICVectAddr registers) that
corresponds to the interrupt that is to be serviced is read from
VICAddress whenever an interrupt occurs.
When an IRQ interrupt occurs, the address of the Interrupt Service Routine (ISR) for the
interrupt that is to be serviced can be read from this register . The addre ss supplied is from
one of the Vector Address Registers (VICVectAddr0-31).
31:0 VICAddress Contains the address of the ISR for the currently active interrupt. This
register must be written (with any value) at the end of an ISR, to
update the VIC priority hardware. Writing to the register at any other
time can cause incorrect operation.
This is a read/write accessible register. This one bit register controls access to the VIC
registers by software running in User mode. The VICProtection register itself can only be
accessed in privileged mode.
NA
reserved bits. The value read from a reserved bit is
not defined.
value
1The VIC registers can only be accessed in privileged mode.
NA
bits. The value read from a reserved bit is not defined.
6.Interrupt sources
Table 6–86 lists the interrupt sources for each peripheral function. Each periphe ral device
may have one or more interrupt lines to the Vectored Interrupt Controller. Each line may
represent more than one interrupt source. There is no significance or priority about what
line is connected where, except for certain standards from ARM.
Table 86.Connection of interrupt sources to the Vectored Interrupt Controller
BlockFlag(s)VIC Channel # and
WDTWatchdog Interrupt (WDINT)00x0000 0001
-Reserved for Software Interrupts only10x0000 0002
ARM CoreEmbedded ICE, DbgCommRx20x0000 0004
ARM CoreEmbedded ICE, DbgCommTX30x0000 0008
TIMER0Match 0 - 1 (MR0, MR1)
TIMER1Match 0 - 2 (MR0, MR1, MR2)
UART0Rx Line Status (RLS)
Hex Mask
40x0000 0010
Capture 0 - 1 (CR0, CR1)
50x0000 0020
Capture 0 - 1 (CR0, CR1)
60x0000 0040
Transmit Holding Register Empty (THRE)
Rx Data Available (RDA)
Character Time-out Indicator (CTI)
End of Auto-Baud (ABEO)
Auto-Baud Time-Out (ABTO)
70x0000 0080
Transmit Holding Register Empty (THRE)
Rx Data Available (RDA)
Character Time-out Indicator (CTI)
Modem Control Change
End of Auto-Baud (ABEO)
Auto-Baud Time-Out (ABTO)
80x0000 0100
Capture 0-1 of PWM1
100x0000 0400
Mode Fault of SPI0 (MODF)
Tx FIFO half empty of SSP0
Rx FIFO half full of SSP0
Rx Timeout of SSP0
Rx Overrun of SSP0
110x0000 0800
Rx FIFO half full
Rx Timeout
Rx Overrun
The MAM block in the LPC23XX maximizes the performance of the ARM processor when
it is running code in Flash memory using a single Flash bank.
Simply put, the Memory Accelerator Module (MAM) attempts to have the next ARM
instruction that will be needed in its latches in time to prevent CPU fetch stalls. The
LPC2300 uses one bank of Flash memory, compared to the two banks used on
predecessor devices. It includes three 128 bit buffers called the Prefetch buffer, the
Branch Trail Buf fer and the data b uffer. When an Instruction Fetch is not satisfied by either
the Prefetch or Branch Trail buf fe r, nor has a prefetch been initiated for that line, the ARM
is stalled while a fetch is initiated for the 128 bit line. If a prefetch has been initiated but not
yet completed, the ARM is stalled for a shorter time. Unless aborted by a data access, a
prefetch is initiated as soon as the Flash has completed the previous access. The
prefetched line is latched by the Flash module, but the MAM does not capture the line in
its prefetch buffer until the ARM core present s the address from which the prefetch has
been made. If the core presents a different address from the one from which the prefetch
has been made, the prefetched line is discarded.
The prefetch and Branch Trail buffers each include four 32 bit ARM instructions or eight
16 bit Thumb instructions. During sequential code execution, typically the prefetch buffer
contains the current instruction and the entire Flash line that contains it.
The MAM uses the LPROT[0] line to differentiate between instructio n an d data accesses.
Code and data accesses use separate 128 bit buffers. 3 of every 4 sequential 32 bit code
or data accesses "hit" in the buffer without requiring a Flash access (7 of 8 sequential
16 bit accesses, 15 of every 16 sequential byte accesses). The fourth (eighth, 16th)
sequential data access must access Flash, aborting any prefetch in progress. When a
Flash data access is concluded, any prefetch that had been in progress is re-initiated.
Timing of Flash read operations is programmable and is described later in this section.
In this manner , there is no code fetch penalty for sequential instruction execution when the
CPU clock period is greater than or equal to one fourth of the Flash access time. The
average amount of time spent doing program bra nches is relatively small (less than 25%)
and may be minimized in ARM (rather than Thumb) code through the use of the
conditional execution feature present in all ARM instructions. This conditional execution
may often be used to avoid small forward branches that would otherwise be necessary.
Branches and other program flow changes cause a break in the sequential flow of
instruction fetches described above. The Branch Trail buffer captures the line to which
such a non-sequential break occurs. If the same branch is taken again, the next
instruction is taken from the Branch T rail buff er . When a branch out side the contents of the
prefetch and Branch Trail buf fer is taken, a stall of several clocks is needed to load the
Branch Trail buffer. Subsequently, there will typically be no further instruction fetch delays
until a new and different branch occurs.
If an attempt is made to write directly to the Flash memory, without using the normal Flash
programming interface, the MAM ge ne r ate s a da ta abort.
3.Memory Acceleration Module blocks
The Memory Accelerator Module is divided into several functional blocks:
• A Flash Address Latch and an incrementor function to form prefetch addresses
• A 128 bit prefetch buffer and an associated Address latch and comparator
• A 128 bit Branch Trail buffer and an associated Address latch and comparator
• A 128 bit Data buffer and an associated Address latch and comparator
• Control logic
• Wait logic
UM10211
Figure 7–23
shows a simplified block diagram of the Memory Accelerator Module data
paths.
In the following descriptions, the term “fetch” applies to an explicit Flash read request from
the ARM. “Pre-fetch” is used to denote a Flash read of instructions beyond the current
processor fetch address.
3.1Flash memory bank
There is one bank of Flash memory with the LPC2300 MAM.
Flash programming operations are not controlled by the MAM, but are handled as a
separate function. A “boot block” sector contains Flash programming algorithms that may
be called as part of the application program, and a loader that may be run to allow serial
programming of the Flash memory.
Fig 23. Simplified block diagram of the Memory Accelerator Module
NXP Semiconductors
3.2Instruction latches and data latches
Code and Data accesses are treated separately by the Memory Accelerator Module.
There is a 128 bit Latch, a 15 bit Address Latch, and a 15 bit comparator associated with
each buffer (prefetch, branch trail, and data). Each 128 bit latch holds 4 words (4 ARM
instructions, or 8 Thumb instructions).
Also associated with each buffer are 32 4:1 Multiplexers that select the requested word
from the 128 bit line.
3.3Flash programming Issues
Since the Flash memory does not allow accesses during programming and erase
operations, it is necessary for the MAM to force the CPU to wait if a memory access to a
Flash address is requested while the Flash module is busy. (This is accomplished by
asserting the ARM7TDMI-S local bus signal CLKEN.) Under some conditions, this delay
could result in a Watchdog time-out. The user will need to be aware of this possibility and
take steps to insure that an unwanted Watchdog reset does not cause a system failure
while programming or erasing the Flash memory.
In order to preclude the possibility of stale data being read from the Flash memory, the
LPC2300 MAM holding latches are automatically invalidated at the beginning of any Flash
programming or erase operation. Any subsequent read from a Flash address will cause a
new fetch to be initiated after the Flash operation has completed.
Three modes of operation are defined for the MAM, trading off performance for ease of
predictability:
Mode 0: MAM off. All memory requests result in a Flash read operation (see note 2
below). There are no instruction prefetches.
Mode 1: MAM partially enabled. Sequential instruction accesses are fulfilled from the
holding latches if the data is present. Instruction prefetch is enabled. Non-sequential
instruction accesses initiate Flash read operations (see Table note 7–2
that all branches cause memory fetches. All data operations cause a Flash read
because buffered data access timing is hard to predict and is very situation dependent.
Mode 2: MAM fully enabled. Any memory request (code or data) for a value that is
contained in one of the corresponding holding latches is fulfilled from the latch.
Instruction prefetch is enabled. Flash read operations are initiated for instruction
prefetch and code or data values not available in the corresponding holding latches.
T able 88. MAM responses to program accesses of various types
T able 88. MAM responses to program accesses of various types
Program Memory Request TypeMAM Mode
Sequential access, data not in latchesInitiate FetchInitiate Fetch
Non-sequential access, data in latchesInitiate Fetch
Non-sequential access, data not in
latches
[1] Instruction prefetch is enabled in modes 1 and 2.
[2] The MAM actually uses latched data if it is available, but mimics the timing of a Flash read operation. This
T able 89. MAM responses to data and DMA accesses of various types
Data Memory Request T ypeMAM Mode
Sequential access, data in latchesInitiate Fetch
Sequential access, data not in latchesInitiate FetchInitiate FetchInitiate Fetch
Non-sequential access, data in latchesInitiate Fetch
Non-sequential access, data not in latches Initiate FetchInitiate FetchInitiate Fetch
saves power while resulting in the same execution timing. The MAM can truly be turned off by setting the
fetch timing value in MAMTIM to one clock.
[1][2]
[1]
Use Latched
[1]
Data
Initiate Fetch
012
[1]
Initiate Fetch
[1]
Use Latched
Data
[1]
Initiate Fetch
[1]
Use Latched
Data
[1]
[1]
[1] The MAM actually uses latched data if it is available, but mimics the timing of a Flash read operation. This
saves power while resulting in the same execution timing. The MAM can truly be turned off by setting the
fetch timing value in MAMTIM to one clock.
5.MAM configuration
After reset the MAM defaults to the disabled state. Software can turn memory access
acceleration on or off at any time. This allows most of an application to be run at the
highest possible performance, while certain functions can be run at a somewhat slower
but more predictable rate if more precise timing is required.
6.Register description
The MAM is controlled by the registers shown in Table 7–90. More detailed descriptions
follow. Writes to any unused bits are ignored. A read of any unused bits will return a logic
zero.
T able 90. Summary of Memory Acceleration Module registers
NameDescriptionAccess Reset
MAMCR Memory Accelerator Module Control Register.
Determines the MAM functional mode, that is, to
what extent the MAM performance enhancements
are enabled. See Table 7–91
MAMTIM Memory Accelerator Module Timing control.
Determines the number of clocks used for Flash
memory fetches (1 to 7 processor clocks).
[1] Reset Value reflects the data stored in used bits only. It does not include reserved bits content.
.
7.MAM Control Register (MAMCR - 0xE01F C000)
Two configuration bits select the three MAM operating modes, as shown in Table 7–91.
Following any reset, MAM functions are disabled. Software can turn memory access
acceleration on or off at any time allowing most of an application to be run at the highest
possible performance, while certain functions can be run a t a somewhat slower but more
predictable rate if more precise timing is required.
UM10211
Address
[1]
value
R/W0x00xE01F C000
R/W0x070xE01F C004
Changing the MAM operating mode causes th e MAM to inv alid at e all of the ho ld ing
latches, resulting in new reads of Flash informatio n as required. This guarantees
synchronization of the MAM to CPU operation.
T able 91. MAM Control Register (MAMCR - address 0xE01F C000) bit description
BitSymbolValueDescriptionReset
1:0MAM_mode
_control
7:2--Unused, always 0.0
00MAM functions disabled
01MAM functions partially enabled
10MAM functions fully enabled
11Reserved. Not to be used in the application.
These bits determine the operating mode of the MAM.0
8.MAM Timing Register (MAMTIM - 0xE01F C004)
The MAM Timing register determines how many CCLK cycles are used to access the
Flash memory. This allows tuning MAM timing to match the processor operating
frequency. Flash access times from 1 clock to 7 clocks are possible. Sing le cloc k Fla sh
accesses would essentially remove the MAM from timing calculations. In this case the
MAM mode may be selected to optimize power usage.