NXP UM10211 User Manual
UM10211
LPC23XX User manual
Rev. 02 — 11 February 2009 User manual
Document information
Info Content
Keywords LPC2300, LPC2361, LPC2362, LPC2364, LPC2365, LPC2366, LPC2367,
LPC2368, LPC2377, LPC2378, LPC2387, LPC2388, ARM, ARM7, 32-bit,
USB, Ethernet, CAN, I2S, Microcontroller
Abstract LPC23xx User manual revision
NXP Semiconductors
UM10211
LPC23XX User manual
Revision history
Rev Date Description
02 20090211 LPC23XX User manual
Modifications:
• Parts LPC2361 and LPC2362 added.
• Numerous editorial updates.
• AHB configuration registers AHBCFG1 and AHBCFG2 added.
• UARTs: minimum setting for DLL value updated.
01 20080311 LPC2364/65/66/67/68/77/78/87/88 User manual
Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
UM10211_2 © NXP B.V. 2009. All rights reserved.
User manual Rev. 02 — 11 February 2009 2 of 706
UM10211
Chapter 1: LPC23XX Introductory information
Rev. 02 — 11 February 2009 User manual
1. Introduction
LPC23xx series are ARM-based microcontrollers for applications requiring serial
communications for a variety of purposes. These microcontrollers typica lly incorporate a
10/100 Ethernet MAC, USB 2.0 Full Speed interface, four UARTs, two CAN channels, an
SPI interface, two Synchronous Serial Ports (SSP), thr ee I2C interfaces, an I
and a MiniBus (8-bit data/16-bit address parallel bus).
2. How to read this manual
The term “LPC23xx“ in the following text will be used as a generic name for all parts
covered in this user manual:
• LPC2361/62
• LPC2364/65/66/67/68
• LPC2377/78
• LPC2387
• LPC2388
2
S interface,
3. Features
3.1 General features
Only when needed, a specific device name will be used to distinguish the part. See
Table 1–1
Table 1. LPC23xx overview
Part Features Ordering info Ordering options Block diagram
LPC2361/62 Section 1–3.1
LPC2364/65/66/67/68 Section 1–3.1 Table 1–3 Table 1–5 Figure 1–2
LPC2377/78 Section 1–3.1,
LPC2387 Section 1–3.1,
LPC2388 Section 1–3.1,
•
to find information about a particular part.
,
Table 1–3 Table 1–4 Figure 1–1
Section 1–3.2
Table 1–3 Table 1–6 Figure 1–3
Section 1–3.3
Table 1–3 Table 1–7 Figure 1–4
Section 1–3.4
Table 1–3 Table 1–8 Figure 1–5
Section 1–3.4
ARM7TDMI-S processor, running at up to 72 MHz.
• Up to 512 kB on-chip Flash Program Memory with In-System Prog ramming (ISP) a nd
In-Application Programming (IAP) capabilities. Single Flash sector or full-chip erase in
400 ms and 256 bytes programming in 1 ms. Flash program memory is on the ARM
local bus for high performance CPU access.
• Up to 64 kB of SRAM on the ARM local bus for high performance CPU access.
UM10211_1 © NXP B.V. 2009. All rights reserved.
User manual Rev. 02 — 11 February 2009 3 of 706
NXP Semiconductors
• 16 kB St atic RAM for Ethernet inter face. Can also be used as general purpo se SRAM.
• 8 kB Static RAM for general purpose or USB interface.
• Dual AHB system that provides for simultaneous Ethernet DMA, USB DMA, and
• Advanced Vector ed Interrupt Controller, supporting up to 32 vectored interrupts.
• General Purpose DMA controller (GPDMA) on AHB that can be used with the SSP
• Serial Interfaces:
• Other APB Peripherals:
UM10211
Chapter 1: LPC23XX Introductory information
program execution from on-chip flash with no contention between those functions. A
bus bridge allows the Ethernet DMA to access the other AHB subsystem.
serial interfaces, the I
memory-to-memory transfers.
– Ethernet MAC with associated DMA controller. These functions reside on an
independent AHB bus.
– On LPC2364/66/68, LPC2378, LPC2387, LPC2388: USB 2.0 device controller
with on-chip PHY and associated DMA controller.
– On LPC2388: USB Host/OTG controller.
– Four UARTs with fractional baud rate generation, one with modem control I/O, one
with IrDA support, all with FIFO. These reside on the APB bus.
– SPI controller, residing on the APB bus.
– Two SSP controllers with FIFO and multi-protocol capabilities. One is an alternate
for the SPI port, sharing its interrupt. The SSP controllers can be used with the
GPDMA controller and reside on the APB bus.
2
– Three I
are expansion I
2
I
2
– I
bus. The I
– On LPC2364/66/68, LPC2378, LPC2387, LPC2388: Two CAN channels with
Acceptance Filter/FullCAN mode residing on the APB bus.
– On LPC2367/68, LPC2377/78, LPC2387, LPC2388: Secure Digital (SD) /
MultiMediaCard (MMC) memory card interface.
– Up to 70 (100 pin packages) or 104 (144 pin packages) general purpose I/O pins.
– 10 bit A/D converter with input multiplexing among 6 pins (100 pin packages) or 8
pins (144 pin packages).
– 10 bit D/A converter.
– Four general purpose timers with two capture inputs each and up to four compare
output pins each. Each timer block has an external count input.
– One PWM/Timer block with support for three-phase motor control. The PWM has
two external count inputs.
– Real-Time Clock (RTC) with separate power pin; clock source can be the RTC
oscillator or the APB clock.
– 2 kB Static RAM powered from the RTC power pin , allowing data to be stored
when the rest of the chip is powered off.
C interfaces reside on the APB bus. The second and third I2C interfaces
C pins.
S (Inter-IC Sound) interface for digital audio input or output, residing on the APB
2
S interface can be used with the GPDMA.
2
S port, and the SD/MMC card port, as well as for
2
C interfaces with standard port pins rather than specia l open-drain
UM10211_1 © NXP B.V. 2009. All rights reserved.
User manual Rev. 02 — 11 February 2009 4 of 706
NXP Semiconductors
• Standard ARM Test/Debug interface for compatibility with existing tools.
• Emulation Trace Module.
• Support for real-time trace.
• Single 3.3 V power supply (3.0 V to 3.6 V).
• Three reduced power modes: Idle, Sleep, and Power-down.
• Four external interrupt inputs. In addition every POR T 0/2 pin can be configu red as an
• Processor wakeup from Power-down mode via any interrupt able to operate during
• Two independent power domains allow fine tuning of power consumption based on
• Brownout detect with separate thresholds for interrupt and forced reset.
• On-chip Power On Reset.
• On-chip crystal oscillator with an operating range of 1 MHz to 24 MHz.
• 4 MHz internal RC oscillator that can optionally be used as the system clock. For USB
• On-chip PLL allows CPU operation up to the maximum CPU rate without the need for
• Boundary scan for simplified board testing is available in LPC2364FET100,
• Versatile pin function selections allow more possibilities for using on-chip peripheral
UM10211
Chapter 1: LPC23XX Introductory information
– Watchdog Timer. The watchdog timer can be clocked from the internal RC
oscillator, the RTC oscillator, or the APB clock.
edge sensing interrupt.
Power-down mode (includes external interrupts, RTC interrupt, and Ethernet wakeup
interrupt).
needed features.
and CAN application, the use of an external clock source is suggested.
a high-frequency crystal. May be run from the main oscillator, the internal RC
oscillator, or the RTC oscillator.
LPC2368FET100 (TFBGA packages), LPC2377/78, and LPC2388.
functions.
3.2 Features available on LPC2361/62
• Device/Host/OTG controller available.
• No Ethernet on LPC2361.
3.3 Features available in LPC2377/78 and LPC2388
External memory controller that supports stat ic devices such as Flash and SRAM. An 8-bit
data/16-bit address parallel bus is available.
3.4 Features available in LPC2387 and LPC2388
• 64 kB of SRAM on the ARM local bus for high performance CPU access.
• 16 kB Static RAM for USB interface. Can also be used as general purpose SRAM.
3.5 Overview
The following table shows the differ ences between LPC23xx parts. Features that are the
same for all parts are not included.
UM10211_1 © NXP B.V. 2009. All rights reserved.
User manual Rev. 02 — 11 February 2009 5 of 706
NXP Semiconductors
UM10211
Chapter 1: LPC23XX Introductory information
Table 2. LPC23xx features overview
Part Local
bus
SRAM
(kB)
LPC2361 8 64 no 8 yes yes no 16 2 no 6 70
LPC2362 32 128 no 8 yes yes yes 16 2 no 6 70
LPC2364 8 128 no 8 yes no yes 16 2 no 6 70
LPC2365 32 256 no 8 no no yes 16 - no 6 70
LPC2366 32 256 no 8 yes no yes 16 2 no 6 70
LPC2367 32 512 no 8 no no yes 16 - yes 6 70
LPC2368 32 512 no 8 yes no yes 16 2 yes 6 70
LPC2377 32 512 Mini 8 no no yes 16 - yes 8 104
LPC2378 32 512 Mini 8 yes no yes 16 2 yes 8 104
LPC2387 64 512 no 16 yes yes yes 16 2 yes 6 70
LPC2388 64 512 Mini 16 yes yes yes 16 2 yes 8 104
Flash
(kB)
EMC USB/
GP
SRAM
(kB)
USB
device
USB
host/
OTG
Ethernet Ethernet
GP
SRAM
(kB)
CAN
channels
SD/
MMC
ADC
channels
GPIO
pins
4. Applications
• Industrial control
• Medical systems
5. Ordering information and options
For ordering information for all LPC23xx parts, see Table 1–3. For ordering options, see
• Table 1–4 for LPC2361/62 parts.
• Table 1–5 for LPC2364/65/66/67/68 part s.
• Table 1–6 for LPC2377/78.
• Table 1–7 for LPC2387.
• Table 1–8 for LPC2388.
Table 3. LPC23xx ordering information
Type number Package
LPC2361FBD100 LQFP100 plastic low profile quad flat package; 100 leads; body 14 × 14 × 1.4 mm SOT407-1
LPC2362FBD100 LQFP100 plastic low profile quad flat package; 100 leads; body 14 × 14 × 1.4 mm SOT407-1
LPC2364FBD100 LQFP100 plastic low profile quad flat package; 100 leads; body 14 × 14 × 1.4 mm SOT407-1
LPC2364FET100 TFBGA100 plastic thin fine-pitch ball grid array package; 100 balls; body 9 × 9 × 0.7 mm SOT926-1
LPC2365FBD100 LQFP100 plastic low profile quad flat package; 100 leads; body 14 × 14 × 1.4 mm SOT407-1
LPC2366FBD100 LQFP100 plastic low profile quad flat package; 100 leads; body 14 × 14 × 1.4 mm SOT407-1
LPC2367FBD100 LQFP100 plastic low profile quad flat package; 100 leads; body 14 × 14 × 1.4 mm SOT407-1
LPC2368FBD100 LQFP100 plastic low profile quad flat package; 100 leads; body 14 × 14 × 1.4 mm SOT407-1
LPC2368FET100 TFBGA100 plastic thin fine-pitch ball grid array package; 100 balls; body 9 × 9 × 0.7 mm SOT926-1
LPC2377FBD144 LQFP144 plastic low profile quad flat package; 144 leads; body 20 × 20 × 1.4 mm SOT486-1
Name Description Version
UM10211_1 © NXP B.V. 2009. All rights reserved.
User manual Rev. 02 — 11 February 2009 6 of 706
NXP Semiconductors
UM10211
Chapter 1: LPC23XX Introductory information
Table 3. LPC23xx ordering information
…continued
Type number Package
Name Description Version
LPC2378FBD144 LQFP144 plastic low profile quad flat package; 144 leads; body 20 × 20 × 1.4 mm SOT486-1
LPC2387FBD100 LQFP100 plastic low profile quad flat package; 100 leads; body 14 × 14 × 1.4 mm SOT407-1
LPC2388FBD144 LQFP144 plastic low profile quad flat package; 144 leads; body 20 × 20 × 1.4 mm SOT486-1
(kB)
SRAM (kB) Ethernet USB
device +
4kB
GP
DMA
Channels Te mp range
CAN ADC DAC
Table 4. LPC2361/62 Ordering options
Type number Flash
FIFO
Local bus
Ethernet buffer
GP/USB
RTC
Total
LPC2361FBD100 64 8 16
[1]
8234- yes yes 2 6 1 −40 °C to +85 °C
LPC2362FBD100 128 32 16 8 2 58 RMII yes yes 2 6 1 −40 °C to +85 °C
[1] Available as general purpose SRAM for the LPC2361.
(kB)
Local
bus
SRAM (kB) Ether
Ethernet
buffers
GP/
RTC Total CAN ADC DAC
USB
net
USB
device
+ 4 kB
FIFO
SD/
MMC
GP
DMA
Channels Temp
range
Table 5. LPC2364/65/66/67/68 Ordering options
Type number Flash
LPC2364FBD100 128 8 16 8 2 34 RMII yes no yes 2 6 1 −40 °C
to
+85 °C
LPC2364FET100 128 8 16 8 2 34 RMII yes no yes 2 6 1 −40 °C
to
+85 °C
LPC2365FBD100 256 32 16 8 2 58 RMII no no yes - 6 1 −40 °C
to
+85 °C
LPC2366FBD100 256 32 16 8 2 58 RMII yes no yes 2 6 1 −40 °C
to
+85 °C
LPC2367FBD100 512 32 16 8 2 58 RMII no yes yes - 6 1 −40 °C
to
+85 °C
LPC2368FBD100 512 32 16 8 2 58 RMII yes yes yes 2 6 1 −40 °C
to
+85 °C
LPC2368FET100 512 32 16 8 2 58 RMII yes yes yes 2 6 1 −40 °C
to
+85 °C
UM10211_1 © NXP B.V. 2009. All rights reserved.
User manual Rev. 02 — 11 February 2009 7 of 706
NXP Semiconductors
UM10211
Chapter 1: LPC23XX Introductory information
(kB)
(kB)
SRAM (kB) External bus Ether
Local bus
Ethernet buffer
GP/USB
RTC
Total
address, and 2 chip
select lines
address, and 2 chip
select lines
SRAM (kB) Ether
Local
bus
Ethernet
buffers
GP/
RTC Total CAN ADC DAC
USB
USB
net
RMII no - yes yes 8 1 −40 °C to
RMII yes 2 yes yes 8 1 −40 °C to
net
device
+ 4 kB
FIFO
USB
device
OTG
host +
4kB
FIFO
SD/
MMC
SD/
MMC
CAN channels
GP
DMA
GP
DMA
Channels Temp
ADC channels
Temp
range
DAC channels
+85 °C
+85 °C
range
to
+85 °C
Table 6. LPC2377/78 ordering options
Type number Flash
LPC2377FBD144 512 32 16 8 2 58 MiniBus: 8 data, 16
LPC2378FBD144 512 32 16 8 2 58 MiniBus: 8 data, 16
Table 7. LPC2387 ordering options
Type number Flash
LPC2387FBD100 512 64 16 16 2 98 RMII yes yes yes 2 6 1 −40 °C
(kB)
SRAM (kB) External bus Ether
Local bus
Ethernet buffer
GP/USB
RTC
Total
address, and 2 chip
select lines
USB
net
RMII yes 2 yes yes 8 1 −40 °C to
device
host
OTG+
4kB
FIFO
SD/
MMC
CAN channels
GP
DMA
ADC channels
DAC channels
Temp
range
+85 °C
Table 8. LPC2388 ordering options
Type number Flash
LPC2388FBD144 512 64 16 16 2 98 MiniBus: 8 data, 16
6. Architectural overview
The LPC2300 consists of an ARM7TDMI-S CPU with emulation support, the ARM7 Local
Bus for closely coupled, high speed access to the majority of on-chip memory, the AMBA
Advanced High-performance Bus (AHB) interfacing to high speed on-chip peripherals an d
external memory, and the AMBA Advanced Peripheral Bus (APB) for connection to other
on-chip peripheral functions. The microcontroller permanently configures the
ARM7TDMI-S processor for little-endian byte order.
The microcontroller implements two AHB buses in order to allow the Etherne t block to
operate without interference caused by other system activity. The primary AHB, referred
to as AHB1, includes the V ectored Interrupt Controller, General Purpose DMA Controller,
External Memory Controller, USB interface, and 8/16 kB SRAM primarily intended for use
by the USB.
UM10211_1 © NXP B.V. 2009. All rights reserved.
User manual Rev. 02 — 11 February 2009 8 of 706
NXP Semiconductors
The second AHB, referred to as AHB2, includes only the Ethernet block and an
associated 16 kB SRAM. In addition, a bus bridge is provided that allows the secondary
AHB to be a bus master on AHB1, allowing expansion of Ethernet buffer space into
off-chip memory or unused space in memory resid ing on AHB1.
In summary, bus masters with access to AHB1 are the ARM7 itself, the USB block, the
General Purpose DMA function, and the Ethernet block (via the bus bridge from AHB2).
Bus masters with access to AHB2 are the ARM7 and the Ethernet block.
AHB peripherals are allocated a 2 MB range of addresses at the very top of the 4 GB
ARM memory space. Each AHB peripheral is allocated a 16 kB address space within the
AHB address space. Lower speed peripheral functions are connected to the APB bus.
The AHB to APB bridge interfaces the APB bus to the AHB bus. APB peripherals are also
allocated a 2 MB range of addresses, beginning at the 3.5 GB address point. Each APB
peripheral is allocated a 16 kB address space within the APB address space.
7. ARM7TDMI-S processor
The ARM7TDMI-S is a general purpose 32 bit microprocessor, which offers high
performance and very low power consumption. The ARM architecture is based on
Reduced Instruction Set Computer (RISC) principles, and the instruction set and related
decode mechanism are much simpler than those of microprogrammed Complex
Instruction Set Computers. This simplicity results in a high instruction throughput and
impressive real-time interrupt response from a small and cost-effective processor core.
UM10211
Chapter 1: LPC23XX Introductory information
Pipeline techniques are employed so that all pa rts of the p rocessing and memory systems
can operate continuously. Typically, while one instruction is being executed, its successor
is being decoded, and a third instruction is being fetched from memory.
The ARM7TDMI-S processor also employs a unique architectural strategy known as
THUMB, which makes it ideally suited to high-volume applications with memory
restrictions, or applications where code density is an issue.
The key idea behind THUMB is that of a super-reduced instruction set. Essentially, the
ARM7TDMI-S processor has two instruction sets:
• The standard 32 bit ARM instruction set.
• A 16 bit THUMB instruction set.
The THUMB set’s 16 bit instruction length allows it to approach twice the density of
standard ARM code while retaining most of the ARM’s performance advantage over a
traditional 16 bit processor using 16 bit registers. This is possible because THUMB code
operates on the same 32 bit register set as ARM code.
THUMB code is able to provide up to 65% of the code size of ARM, and 160% of the
performance of an equivalent ARM processor connected to a 16 bit memory system.
The ARM7TDMI-S processor is described in detail in the ARM7TDMI-S Datasheet that
can be found on official ARM website.
UM10211_1 © NXP B.V. 2009. All rights reserved.
User manual Rev. 02 — 11 February 2009 9 of 706
NXP Semiconductors
8. On-chip flash memory system
The LPC2300 includes a Flash memory system with up to 512 kB. This memory may be
used for both code and data storage. Programming of the Flash memory may be
accomplished in several ways. It may be programmed In System via the serial port. The
application program may also erase and/or program the Flash while the application is
running, allowing a great degree of flexibility for data storage field firmware upgrades, etc.
The Flash is 128 bits wide and includes pre -fetching and buf fering techniques to allow it to
operate at SRAM speeds.
9. On-chip Static RAM
The LPC2300 includes a static RAM memory up to 64 kB in size, that may be used for
code and/or data storage.
The SRAM controller incorporates a write-back buffer in order to prevent CPU stalls
during back-to-back writes. The write-back buffer always holds the last data sent by
software to the SRAM. The data is only written to the SRAM when software does another
write. After a "warm" chip reset, the SRAM does not reflect the last write operation. Two
identical writes to a location guarantee that the data will be present after a Reset.
Alternatively, a dummy write operation before entering idle or power-down mode will
similarly guarantee that the last data written will be present after a subsequent Reset.
UM10211
Chapter 1: LPC23XX Introductory information
UM10211_1 © NXP B.V. 2009. All rights reserved.
User manual Rev. 02 — 11 February 2009 10 of 706
PWM1
ARM7TDMI-S
PLL
EINT3 to EINT0
FLASH
P3, P4
P0, P1, P2,
LEGACY GPI/O
52 PINS TOTAL
P0, P1
SCK, SCK0
MOSI, MOSI0
SSEL, SSEL0
SCK1
MOSI1
MISO1
SSEL1
SCL0, SCL1, SCL2
I2SRX_CLK
I2STX_CLK
I2SRX_WS
I2STX_WS
6 × AD0
RTCX1
RTCX2
RXD0, RXD2, RXD3
TXD1
RXD1
RD1, RD2
TD1, TD2
CAN1, CAN2
USB port 1
XTAL1
TCK TDO
EXTIN0
XTAL2
RESET
TRST
TDITMS
HIGH-SPEED
GPI/O
70 PINS
TOTAL
LPC2361/62
8/32 kB
SRAM
64/128 kB
FLASH
INTERNAL
CONTROLLERS
TEST/DEBUG
INTERFACE
EMULATION
TRACE MODULE
trace signals
AHB
BRIDGE
AHB
BRIDGE
ETHERNET
MAC WITH
DMA
(1)
16 kB
SRAM
MASTER
PORT
AHB TO
AHB BRIDGE
SLAVE
PORT
system
clock
SYSTEM
FUNCTIONS
INTERNAL RC
OSCILLATOR
V
DDA
V
DD(3V3)
VREF
V
SSA
, V
SS
VECTORED
INTERRUPT
CONTROLLER
8 kB
SRAM
USB WITH
4 kB RAM
AND DMA
GP DMA
CONTROLLER
I2S INTERFACE
SPI, SSP0 INTERFACE
I2SRX_SDA
I2STX_SDA
MISO, MISO0
SSP1 INTERFACE
TXD0, TXD2, TXD3
UART0, UART2, UART3
UART1
DTR1, RTS1
DSR1, CTS1, DCD1,
RI1
I
2
C0, I2C1, I2C2
SDA0, SDA1, SDA2
EXTERNAL INTERRUPTS
CAPTURE/COMPARE
TIMER0/TIMER1/
TIMER2/TIMER3
A/D CONVERTER
D/A CONVERTER
2 kB BATTERY RAM
RTC
OSCILLATOR
REAL-
TIME
CLOCK
WATCHDOG TIMER
SYSTEM CONTROL
2 × CAP0/CAP1/
CAP2/CAP3
4 × MAT2,
2 × MAT0/MAT1/
MAT3
6 × PWM1
2 × PCAP1
AOUT
VBAT
AHB TO
APB BRIDGE
SRAM
RMII(8)
V
BUS
002aad964
P0, P2
power domain 2
AHB2
AHB1
power domain 2
V
DD(DCDC)(3V3)
NXP Semiconductors
10. Block diagram
UM10211
Chapter 1: LPC23XX Introductory information
(1) LPC2362 only.
Fig 1. LPC2361/62 block diagram
UM10211_1 © NXP B.V. 2009. All rights reserved.
User manual Rev. 02 — 11 February 2009 11 of 706
PWM1
ARM7TDMI-S
PLL
EINT3 to EINT0
FLASH
P3, P4
P0, P1, P2,
LEGACY GPI/O
52 PINS TOTAL
P0, P1
SCK, SCK0
MOSI, MOSI0
SSEL, SSEL0
SCK1
MOSI1
MISO1
SSEL1
SCL0, SCL1, SCL2
I2SRX_CLK
I2STX_CLK
I2SRX_WS
I2STX_WS
6 × AD0
RTCX1
RTCX2
MCICLK, MCIPWR
RXD0, RXD2, RXD3
TXD1
RXD1
RD1, RD2
TD1, TD2
CAN1, CAN2
(2)
USB_D+, USB_D−
XTAL1
TCK TDO
EXTIN0
XTAL2
RESET
TRST
TDITMS
HIGH-SPEED
GPI/O
70 PINS
TOTAL
LPC2364/65/66/67/68
8/32 kB
SRAM
128/256/
512 kB
FLASH
INTERNAL
CONTROLLERS
TEST/DEBUG
INTERFACE
EMULATION
TRACE MODULE
trace signals
AHB
BRIDGE
AHB
BRIDGE
ETHERNET
MAC WITH
DMA
16 kB
SRAM
MASTER
PORT
AHB TO
AHB BRIDGE
SLAVE
PORT
system
clock
SYSTEM
FUNCTIONS
INTERNAL RC
OSCILLATOR
V
DDA
V
DD(3V3)
VREF
V
SSA
, V
SS
VECTORED
INTERRUPT
CONTROLLER
8 kB
SRAM
USB WITH
4 kB RAM
AND DMA
(2)
GP DMA
CONTROLLER
I2S INTERFACE
SPI, SSP0 INTERFACE
I2SRX_SDA
I2STX_SDA
MISO, MISO0
SSP1 INTERFACE
SD/MMC CARD
INTERFACE
(1)
MCICMD,
MCIDAT[3:0]
TXD0, TXD2, TXD3
UART0, UART2, UART3
UART1
DTR1, RTS1
DSR1, CTS1, DCD1,
RI1
I
2
C0, I2C1, I2C2
SDA0, SDA1, SDA2
EXTERNAL INTERRUPTS
CAPTURE/COMPARE
TIMER0/TIMER1/
TIMER2/TIMER3
A/D CONVERTER
D/A CONVERTER
2 kB BATTERY RAM
RTC
OSCILLATOR
REAL-
TIME
CLOCK
WATCHDOG TIMER
SYSTEM CONTROL
2 × CAP0/CAP1/
CAP2/CAP3
4 × MAT2,
2 × MAT0/MAT1/
MAT3
6 × PWM1
2 × PCAP1
AOUT
VBAT
AHB TO
APB BRIDGE
SRAM
RMII(8)
V
BUS
USB_CONNECT
USB_UP_LED
002aac566
P0, P2
power domain 2
AHB2
AHB1
power domain 2
V
DD(DCDC)(3V3)
NXP Semiconductors
UM10211
Chapter 1: LPC23XX Introductory information
(1) LPC2367/68 only.
(2) LPC2364/66/68 only.
Fig 2. LPC2364/65/66/67/68 block diagram
UM10211_1 © NXP B.V. 2009. All rights reserved.
User manual Rev. 02 — 11 February 2009 12 of 706
NXP Semiconductors
power domain 2
LPC2377/78
A[15:0]
D[7:0]
EXTERNAL
MEMORY
CONTROLLER
ALARM
002aac574
PWM1
ARM7TDMI-S
PLL
EINT3 to EINT0
FLASH
P3, P4
P0, P1, P2,
LEGACY GPI/O
56 PINS TOTAL
P0, P1
SCK, SCK0
MOSI, MOSI0
SSEL, SSEL0
SCK1
MOSI1
MISO1
SSEL1
SCL0, SCL1, SCL2
I2SRX_CLK
I2STX_CLK
I2SRX_WS
I2STX_WS
8 × AD0
RTCX1
RTCX2
MCICLK, MCIPWR
RXD0, RXD2, RXD3
TXD1
RXD1
RD1, RD2
TD1, TD2
CAN1, CAN2
(1)
2 × USB_D+/USB_D−
XTAL1
TCK TDO
EXTIN0
XTAL2
TRST
TDITMS
HIGH-SPEED
GPI/O
104 PINS
TOTAL
32 kB
SRAM
512 kB
FLASH
INTERNAL
CONTROLLERS
TEST/DEBUG
INTERFACE
EMULATION
TRACE MODULE
trace signals
AHB
BRIDGE
AHB
BRIDGE
ETHERNET
MAC WITH
DMA
16 kB
SRAM
MASTER
PORT
AHB TO
AHB BRIDGE
SLAVE
PORT
system
clock
SYSTEM
FUNCTIONS
INTERNAL RC
OSCILLATOR
V
DDA
V
DD(3V3)
V
DD(DCDC)(3V3)
VREF
V
SSA
, V
SS
VECTORED
INTERRUPT
CONTROLLER
8 kB
SRAM
USB WITH
4 kB RAM
AND DMA
(1)
GP DMA
CONTROLLER
I2S INTERFACE
SPI, SSP0 INTERFACE
I2SRX_SDA
I2STX_SDA
MISO, MISO0
SSP1 INTERFACE
SD/MMC CARD
INTERFACE
MCICMD,
MCIDAT[3:0]
TXD0, TXD2, TXD3
UART0, UART2, UART3
UART1
DTR1, RTS1
DSR1, CTS1, DCD1,
RI1
I
2
C0, I2C1, I2C2
SDA0, SDA1, SDA2
EXTERNAL INTERRUPTS
CAPTURE/COMPARE
TIMER0/TIMER1/
TIMER2/TIMER3
A/D CONVERTER
D/A CONVERTER
2 kB BATTERY RAM
RTC
OSCILLATOR
REAL-
TIME
CLOCK
WATCHDOG TIMER
SYSTEM CONTROL
2 × CAP0/CAP1/
CAP2/CAP3
4 × MAT2,
2 × MAT0/MAT1/
MAT3
6 × PWM1
2 × PCAP1
AOUT
VBAT
AHB TO
APB BRIDGE
SRAM
RMII(8)
RESET
V
BUS
2 × USB_CONNECT
2 × USB_UP_LED
DBGEN
P0, P2
AHB2 AHB1
OE, CS0, CS1,
BLS0
UM10211
Chapter 1: LPC23XX Introductory information
(1) LPC2378 only.
Fig 3. LPC2377/78 block diagram
UM10211_1 © NXP B.V. 2009. All rights reserved.
User manual Rev. 02 — 11 February 2009 13 of 706
PWM1
ARM7TDMI-S
PLL
EINT3 to EINT0
FLASH
P3, P4
P0, P1, P2,
LEGACY GPI/O
52 PINS TOTAL
P0, P1
SCK, SCK0
MOSI, MOSI0
SSEL, SSEL0
SCK1
MOSI1
MISO1
SSEL1
SCL0, SCL1, SCL2
I2SRX_CLK
I2STX_CLK
I2SRX_WS
I2STX_WS
6 × AD0
RTCX1
RTCX2
MCICLK, MCIPWR
RXD0, RXD2, RXD3
TXD1
RXD1
RD1, RD2
TD1, TD2
CAN1, CAN2
USB port 1
XTAL1
TCK TDO
EXTIN0
XTAL2
RESET
TRST
TDITMS
HIGH-SPEED
GPIO
70 PINS
TOTAL
LPC2387
64 kB
SRAM
512 kB
FLASH
INTERNAL
CONTROLLERS
TEST/DEBUG
INTERFACE
EMULATION
TRACE MODULE
trace signals
AHB
BRIDGE
AHB
BRIDGE
ETHERNET
MAC WITH
DMA
16 kB
SRAM
MASTER
PORT
AHB TO
AHB BRIDGE
SLAVE
PORT
system
clock
SYSTEM
FUNCTIONS
INTERNAL RC
OSCILLATOR
V
DDA
V
DD(3V3)
VREF
V
SSA
, V
SS
VECTORED
INTERRUPT
CONTROLLER
16 kB
SRAM
USB WITH
4 kB RAM
AND DMA
GP DMA
CONTROLLER
I2S INTERFACE
SPI, SSP0 INTERFACE
I2SRX_SDA
I2STX_SDA
MISO, MISO0
SSP1 INTERFACE
SD/MMC CARD
INTERFACE
MCICMD,
MCIDAT[3:0]
TXD0, TXD2, TXD3
UART0, UART2, UART3
UART1
DTR1, RTS1
DSR1, CTS1, DCD1,
RI1
I
2
C0, I2C1, I2C2
SDA0, SDA1, SDA2
EXTERNAL INTERRUPTS
CAPTURE/COMPARE
TIMER0/TIMER1/
TIMER2/TIMER3
A/D CONVERTER
D/A CONVERTER
2 kB BATTERY RAM
RTC
OSCILLATOR
REAL-
TIME
CLOCK
WATCHDOG TIMER
SYSTEM CONTROL
2 × CAP0/CAP1/
CAP2/CAP3
4 × MAT2,
2 × MAT0/MAT1/
MAT3
6 × PWM1
2 × PCAP1
AOUT
VBAT
AHB TO
APB BRIDGE
SRAM
RMII(8)
V
BUS
002aad328
P0, P2
power domain 2
AHB2
AHB1
power domain 2
V
DD(DCDC)(3V3)
NXP Semiconductors
UM10211
Chapter 1: LPC23XX Introductory information
Fig 4. LPC2387 block diagram
UM10211_1 © NXP B.V. 2009. All rights reserved.
User manual Rev. 02 — 11 February 2009 14 of 706
PWM1
ARM7TDMI-S
PLL
EINT3 to EINT0
FLASH
P3, P4
P0, P1, P2,
LEGACY GPI/O
56 PINS TOTAL
P0, P1
SCK, SCK0
MOSI, MOSI0
SSEL, SSEL0
SCK1
MOSI1
MISO1
SSEL1
SCL0, SCL1, SCL2
I2SRX_CLK
I2STX_CLK
I2SRX_WS
I2STX_WS
8 × AD0
RTCX1
RTCX2
MCICLK, MCIPWR
RXD0, RXD2, RXD3
TXD1
RXD1
RD1, RD2
TD1, TD2
CAN1, CAN2
USB port 1
XTAL1
TCK TDO
EXTIN0
XTAL2
RESET
TRST
TDITMS
HIGH-SPEED
GPI/O
104 PINS
TOTAL
LPC2388
USB port 2
64 kB
SRAM
512 kB
FLASH
INTERNAL
CONTROLLERS
TEST/DEBUG
INTERFACE
EMULATION
TRACE MODULE
trace signals
AHB
BRIDGE
AHB
BRIDGE
ETHERNET
MAC WITH
DMA
16 kB
SRAM
MASTER
PORT
AHB TO
AHB BRIDGE
SLAVE
PORT
system
clock
SYSTEM
FUNCTIONS
INTERNAL RC
OSCILLATOR
V
DDA
V
DD(3V3)
VREF
V
SSA
, V
SS
VECTORED
INTERRUPT
CONTROLLER
16 kB
SRAM
USB WITH
4 kB RAM
AND DMA
GP DMA
CONTROLLER
I2S INTERFACE
SPI, SSP0 INTERFACE
I2SRX_SDA
I2STX_SDA
MISO, MISO0
SSP1 INTERFACE
SD/MMC CARD
INTERFACE
MCICMD,
MCIDAT[3:0]
TXD0, TXD2, TXD3
UART0, UART2, UART3
UART1
DTR1, RTS1
DSR1, CTS1, DCD1,
RI1
I
2
C0, I2C1, I2C2
SDA0, SDA1, SDA2
EXTERNAL INTERRUPTS
CAPTURE/COMPARE
TIMER0/TIMER1/
TIMER2/TIMER3
A/D CONVERTER
D/A CONVERTER
2 kB BATTERY RAM
RTC
OSCILLATOR
REAL-
TIME
CLOCK
WATCHDOG TIMER
SYSTEM CONTROL
2 × CAP0/CAP1/
CAP2/CAP3
4 × MAT2,
2 × MAT0/MAT1/
MAT3
6 × PWM1
2 × PCAP1
AOUT
VBAT
AHB TO
APB BRIDGE
SRAM
RMII(8)
V
BUS
002aad332
P0, P2
power domain 2
AHB2
AHB1
power domain 2
V
DD(DCDC)(3V3)
A[15:0]
D[7:0]
EXTERNAL
MEMORY
CONTROLLER
OE, CS0, CS1,
BLS0
ALARM
NXP Semiconductors
UM10211
Chapter 1: LPC23XX Introductory information
Fig 5. LPC2388 block diagram
UM10211_1 © NXP B.V. 2009. All rights reserved.
User manual Rev. 02 — 11 February 2009 15 of 706
UM10211
Chapter 2: LPC23XX memory addressing
Rev. 02 — 11 February 2009 User manual
1. Memory map and peripheral addressing
ARM processors have a single 4 GB address space. The following table shows how this
space is used on NXP embedded ARM devices. For memory option det ails see Table 1–2
Table 9. LPC2300 memory usage
Address range General use Address range details and description
0x0000 0000 to
0x3FFF FFFF
0x4000 0000 to
0x7FFF FFFF
0x8000 0000 to
0xDFFF FFFF
0xE000 0000 to
0xEFFF FFFF
0xF000 0000 to
0xFFFF FFFF
on-chip
NV memory
and fast I/O
on-chip RAM 0x4000 0000 - 0x4000 7FFF RAM (up to 32 kB)
off-chip memory Two static memory banks, 64 KB each (LPC2377/78 and LPC2388 only):
APB peripherals 0xE000 0000 - 0xE008 FFFF 36 peripheral blocks, 16 kB each (some unused),
AHB peripherals 0xFFE0 0000 - 0xFFE0 3FFF Ethernet Controller (not LPC2361)
0x0000 0000 - 0x0007 FFFF flash memory (up to 512 kB)
0x3FFF C000 - 0x3FFF FFF F fast GPIO registers
0x4000 0000 - 0x4000 FFFF RAM (64 kB for LPC2387/88)
0x7FD0 0000 - 0x7FD0 1FFF USB RAM (8 kB)
0x7FD0 0000 - 0x7FD0 3FFF USB RAM (16 kB for LPC2387/88)
0x7FE0 0000 - 0x7FE0 3FFF Ethernet RAM (16 kB)
0x8000 0000 - 0x8000 FFFF static memory bank 0, 64 KB
0x8100 0000 - 0x8100 FFFF static memory bank 1, 64 KB
see Table 2–10
0xE01F C000 - 0xE01F FFFF System Control Block
0xFFE0 4000 - 0xFFE0 7FFF General Purpose DMA Controller
0xFFE0 8000 - 0xFFE0 BFFF External Memory Controller (EMC) (LPC2377/78,
LPC2388 only)
0xFFE0 C000 - 0xFFE0 FFFF USB Controller (LPC2361/62/64/66/68, LPC2378,
LPC2387, and LPC2388 only).
0xFFFF F000 - 0xFFFF FFFF Vectored Interrupt Controller (VIC)
.
.
2. Memory maps
The LPC2300 incorporates several distinct memory regions, shown in the following
figures. Figure 2–7
address space from the user program viewpoint following reset. Th e interrupt vector area
supports address remapping, which is described later in this section.
UM10211_2 © NXP B.V. 2009. All rights reserved.
User manual Rev. 02 — 11 February 2009 16 of 706
, Figure 2–8, and Figure 2–9 show the overall map of the entire
NXP Semiconductors
0.0 GB
1.0 GB
TOTAL OF 64 kB ON-CHIP NON-VOLATILE MEMORY (LPC2361)
TOTAL OF 128 kB ON-CHIP NON-VOLATILE MEMORY (LPC2362)
0x0000 0000
0x0000 FFFF
0x0001 0000
0x0001 FFFF
0x0002 0000
RESERVED FOR ON-CHIP MEMORY
8 kB LOCAL ON-CHIP STATIC RAM (LPC2361)
32 kB LOCAL ON-CHIP STATIC RAM (LPC2362)
RESERVED ADDRESS SPACE
RESERVED ADDRESS SPACE
0x4000 0000
0x4000 2000
0x4000 8000
0x7FD0 0000
0x7FE0 0000
0x7FD0 1FFF
0x7FE0 3FFF
0x4000 1FFF
0x4000 7FFF
2.0 GB
0x8000 0000
BOOT ROM AND BOOT FLASH
(BOOT FLASH REMAPPED FROM ON-CHIP FLASH)
3.0 GB 0xC000 0000
RESERVED ADDRESS SPACE
3.75 GB
4.0 GB
3.5 GB
AHB PERIPHERALS
APB PERIPHERALS
0xE000 0000
0xF000 0000
0xFFFF FFFF
GENERAL PURPOSE OR USB RAM (8 KB)
ETHERNET RAM (16 kB)
002aae283
UM10211
Chapter 2: LPC23XX memory addressing
Fig 6. LPC2461/63 memory map
UM10211_2 © NXP B.V. 2009. All rights reserved.
User manual Rev. 02 — 11 February 2009 17 of 706
NXP Semiconductors
0.0 GB
1.0 GB
TOTAL OF 128 kB ON-CHIP NON-VOLATILE MEMORY (LPC2364)
TOTAL OF 512 kB ON-CHIP NON-VOLATILE MEMORY (LPC2367/68)
TOTAL OF 256 kB ON-CHIP NON-VOLATILE MEMORY (LPC2365/66)
0x0000 0000
0x0001 FFFF
0x0002 0000
0x0003 FFFF
0x0007 FFFF
0x0008 0000
0x0004 0000
RESERVED FOR ON-CHIP MEMORY
8 kB LOCAL ON-CHIP STATIC RAM (LPC2364)
32 kB LOCAL ON-CHIP STATIC RAM (LPC2365/66/67/68)
RESERVED ADDRESS SPACE
RESERVED ADDRESS SPACE
0x4000 0000
0x4000 2000
0x4000 8000
0x7FD0 0000
0x7FE0 0000
0x7FD0 1FFF
0x7FE0 3FFF
0x4000 1FFF
0x4000 7FFF
2.0 GB
0x8000 0000
BOOT ROM AND BOOT FLASH
(BOOT FLASH REMAPPED FROM ON-CHIP FLASH)
3.0 GB 0xC000 0000
RESERVED ADDRESS SPACE
3.75 GB
4.0 GB
3.5 GB
AHB PERIPHERALS
APB PERIPHERALS
0xE000 0000
0xF000 0000
0xFFFF FFFF
GENERAL PURPOSE OR USB RAM (8 KB)
ETHERNET RAM (16 kB)
002aac577
UM10211
Chapter 2: LPC23XX memory addressing
Fig 7. LPC2364/65/66/67/68 system mem ory map
UM10211_2 © NXP B.V. 2009. All rights reserved.
User manual Rev. 02 — 11 February 2009 18 of 706
NXP Semiconductors
0.0 GB
1.0 GB
TOTAL OF 512 kB ON-CHIP NON-VOLATILE MEMORY
0x0000 0000
0x0007 FFFF
0x0008 0000
RESERVED ADDRESS SPACE
32 kB LOCAL ON-CHIP STATIC RAM
RESERVED ADDRESS SPACE
RESERVED ADDRESS SPACE
0x4000 0000
0x4000 8000
0x7FD0 0000
0x7FE0 0000
0x7FD0 1FFF
0x7FE0 3FFF
0x4000 7FFF
2.0 GB
0x8000 0000
0x8000 FFFF
0x8100 FFFF
0x8100 0000
BOOT ROM AND BOOT FLASH
(BOOT FLASH REMAPPED FROM ON-CHIP FLASH)
3.0 GB 0xC000 0000
RESERVED ADDRESS SPACE
3.75 GB
4.0 GB
3.5 GB
AHB PERIPHERALS
APB PERIPHERALS
0xE000 0000
0xF000 0000
0xFFFF FFFF
GENERAL PURPOSE OR USB RAM (8 kB)
ETHERNET RAM (16 kB)
002aac585
EXTERNAL MEMORY BANK 0 (64 kB)
EXTERNAL MEMORY BANK 1 (64 kB)
UM10211
Chapter 2: LPC23XX memory addressing
Fig 8. LPC2377/78 system memory map
UM10211_2 © NXP B.V. 2009. All rights reserved.
User manual Rev. 02 — 11 February 2009 19 of 706
NXP Semiconductors
0.0 GB
1.0 GB
TOTAL OF 512 kB ON-CHIP NON-VOLATILE MEMORY
0x0000 0000
0x0007 FFFF
0x0008 0000
RESERVED FOR ON-CHIP MEMORY
64 kB LOCAL ON-CHIP STATIC RAM
RESERVED ADDRESS SPACE
RESERVED ADDRESS SPACE
0x4000 0000
0x4001 0000
0x7FD0 0000
0x7FE0 0000
0x7FD0 3FFF
0x7FE0 3FFF
0x4000 FFFF
2.0 GB
BOOT ROM AND BOOT FLASH
(BOOT FLASH REMAPPED FROM ON-CHIP FLASH)
3.0 GB 0xC000 0000
RESERVED ADDRESS SPACE
3.75 GB
4.0 GB
3.5 GB
AHB PERIPHERALS
APB PERIPHERALS
0xE000 0000
0xF000 0000
0xFFFF FFFF
USB RAM (16 kB)
ETHERNET RAM (16 kB)
002aad331
0x8000 0000
0x8000 FFFF
0x8100 FFFF
0x8100 0000
EXTERNAL MEMORY BANK 0 (64 kB)
EXTERNAL MEMORY BANK 1 (64 kB)
UM10211
Chapter 2: LPC23XX memory addressing
Fig 9. LPC2387 memory map
UM10211_2 © NXP B.V. 2009. All rights reserved.
User manual Rev. 02 — 11 February 2009 20 of 706
NXP Semiconductors
0.0 GB
1.0 GB
TOTAL OF 512 kB ON-CHIP NON-VOLATILE MEMORY
0x0000 0000
0x0007 FFFF
0x0008 0000
RESERVED FOR ON-CHIP MEMORY
64 kB LOCAL ON-CHIP STATIC RAM
RESERVED ADDRESS SPACE
RESERVED ADDRESS SPACE
0x4000 0000
0x4001 0000
0x7FD0 0000
0x7FE0 0000
0x7FD0 3FFF
0x7FE0 3FFF
0x4000 FFFF
2.0 GB
BOOT ROM AND BOOT FLASH
(BOOT FLASH REMAPPED FROM ON-CHIP FLASH)
3.0 GB 0xC000 0000
RESERVED ADDRESS SPACE
3.75 GB
4.0 GB
3.5 GB
AHB PERIPHERALS
APB PERIPHERALS
0xE000 0000
0xF000 0000
0xFFFF FFFF
USB RAM (16 kB)
ETHERNET RAM (16 kB)
002aad331
0x8000 0000
0x8000 FFFF
0x8100 FFFF
0x8100 0000
EXTERNAL MEMORY BANK 0 (64 kB)
EXTERNAL MEMORY BANK 1 (64 kB)
UM10211
Chapter 2: LPC23XX memory addressing
Fig 10. LPC2388 memory map
UM10211_2 © NXP B.V. 2009. All rights reserved.
User manual Rev. 02 — 11 February 2009 21 of 706
NXP Semiconductors
RESERVED
RESERVED
0xF000 0000
0xEFFF FFFF
APB PERIPHERALS
0xE020 0000
0xE01F FFFF
0xE000 0000
AHB PERIPHERALS
0xFFFF FFFF
0xFFE0 0000
0xFFDF FFFF
3.75 GB
3.5 GB
3.5 GB + 2 MB
4.0 GB - 2 MB
4.0 GB
UM10211
Chapter 2: LPC23XX memory addressing
Fig 11. Peripheral memory map
Figure 12 and Table 2–10 show different views of the peripheral address space. Both the
AHB and APB peripheral areas are 2 megabyte spaces which are divided up into 128
peripherals. Each peripheral space is 16 kilobytes in size. This allows simplifying the
address decoding for each peripheral.
UM10211_2 © NXP B.V. 2009. All rights reserved.
User manual Rev. 02 — 11 February 2009 22 of 706
NXP Semiconductors
VECTORED INTERRUPT CONTROLLER
(AHB PERIPHERAL #0)
0xFFFF F000 (4G - 4K)
0xFFFF C000
0xFFFF 8000
(AHB PERIPHERAL #4)
(AHB PERIPHERAL #3)
(AHB PERIPHERAL #2)
(AHB PERIPHERAL #1)
(AHB PERIPHERAL #126)
0xFFE1 8000
0xFFE1 4000
0xFFE1 0000
0xFFE0 C000
0xFFE0 8000
0xFFE0 4000
0xFFE0 0000
ETHERNET CONTROLLER
GENERAL PURPOSE DMA CONTROLLER
EXTERNAL MEMORY CONTROLLER
USB CONTROLLER
NOT USED
(AHB PERIPHERAL #5)
NOT USED
All peripheral register addresses are word aligned (to 32 bit boundaries) regardless of
their size. This eliminates the need for byte lane mapping hardware that would be required
to allow byte (8 bit) or half-word (16 bit) accesses to occur at smaller boundaries. An
implication of this is that word and half-word registers must be accessed all at once. For
example, it is not possible to read or write the upper byte of a word register separately.
UM10211
Chapter 2: LPC23XX memory addressing
UM10211_2 © NXP B.V. 2009. All rights reserved.
User manual Rev. 02 — 11 February 2009 23 of 706
Fig 12. AHB peripheral map
NXP Semiconductors
3. APB peripheral addresses
The following table shows the APB address map. No APB peripheral uses all of the 16 kB
space allocated to it. T ypically each device’ s registers are "aliased" or re peated at multiple
locations within each 16 kB range.
Table 10. APB peripherals and base addresses
APB Peripheral Base Address Peripheral Name
0 0xE000 0000 Watchdog Timer
1 0xE000 4000 Timer 0
2 0xE000 8000 Timer 1
3 0xE000 C000 UART0
4 0xE001 0000 UART1
5 0xE001 4000 Not used
6 0xE001 8000 PWM1
7 0xE001 C000 I
8 0xE002 0000 SPI
9 0xE002 4000 RTC
10 0xE002 8000 GPIO
1 1 0xE002 C000 Pin Connect Block
12 0xE003 0000 SSP1
13 0xE003 4000 ADC
14 0xE003 8000 CAN Acceptance Filter RAM
15 0xE003 C000 CAN Acceptance Filter Registers
16 0xE004 0000 CAN Common Registers
17 0xE004 4000 CAN Controller 1
18 0xE004 8000 CAN Controller 2
19 to 22 0xE004 C000 to 0xE005 8000 Not used
23 0xE005 C000 I
24 0xE006 0000 Not used
25 0xE006 4000 Not used
26 0xE006 8000 SSP0
27 0xE006 C000 DAC
28 0xE007 0000 Timer 2
29 0xE007 4000 Timer 3
30 0xE007 8000 UART2
31 0xE007 C000 UART3
32 0xE008 0000 I
33 0xE008 4000 Battery RAM
34 0xE008 8000 I2S
35 0xE008 C000 SD/MMC Card Interface
36 to 126 0xE009 0000 to 0xE01F BFFF Not used
127 0xE01F C000 System Control Block
UM10211
Chapter 2: LPC23XX memory addressing
2
C0
[1]
[1]
[1]
[1]
[1]
2
C1
2
C2
[2]
[1] CAN interface is available in LPC2364/66/68, LPC2378, LPC2387, and LPC2388.
UM10211_2 © NXP B.V. 2009. All rights reserved.
User manual Rev. 02 — 11 February 2009 24 of 706
NXP Semiconductors
Chapter 2: LPC23XX memory addressing
[2] The SD/MMC card interface is available in LPC2365/66, LPC2377/78, LPC2387, and LPC2388.
4. LPC2300 memory re-mapping and boot ROM
4.1 Memory map concepts and operating modes
The basic concept on the LPC2300 is that each memory area has a "natural" location in
the memory map. This is the address range for which code residing in that area is written.
The bulk of each memory space remains permanently fixed in the same location,
eliminating the need to have portions of the code designed to run in different address
ranges.
Because of the location of the interrupt vectors on the ARM7 processor (at addresses
0x0000 0000 through 0x0000 001C, as shown in Table 2–11
Boot ROM and SRAM spaces need to be re-mapped in order to allow alternative uses of
interrupts in the differen t operating modes described in Table 2–12
interrupts is accomplished via the Memory Mapping Contro l feature (Section 2–5 “
mapping control” on page 27).
Table 11. ARM exception vector locations
Address Exception
0x0000 0000 Reset
0x0000 0004 Undefined Instruction
0x0000 0008 Software Interrupt
0x0000 000C Prefetch Abort (instruction fetch memory fault)
0x0000 0010 Data Abort (data access memory fault)
0x0000 0014 Reserved
UM10211
below), a small portion of the
. Re-mapping of the
Memory
Note: Identified as reserved in ARM documentation, this location is used
by the Boot Loader as the Valid User Program key. This is described in
detail in Section 29–3.1.1
0x0000 0018 IRQ
0x0000 001C FIQ
Table 12. LPC2300 Memory mapping modes
Mode Activation Usage
Boot
Loader
mode
UM10211_2 © NXP B.V. 2009. All rights reserved.
User manual Rev. 02 — 11 February 2009 25 of 706
Hardware
activation by
any Reset
The Boot Loader always executes after any reset. The Boot ROM
interrupt vectors are mapped to the bottom of memory to allow
handling exceptions and using interrupts during the Boot Loading
process. A sector of the Flash memory (the Boot Flash) is available to
hold part of the Boot Code.
.
NXP Semiconductors
Table 12. LPC2300 Memory mapping modes
Mode Activation Usage
User
Flash
mode
User RAM
mode
User
External
Memory
mode
[1] See EMCControl register address mirror bit in Table5–60 for address of external memory bank 0.
4.2 Memory re-mapping
In order to allow for compatibility with future derivatives, the entire Boot ROM is mapped
to the top of the on-chip memory space. In this manner, the use of larger or smaller flash
modules will not require changing the location of the Boot ROM (which would require
changing the Boot Loader code itself) or changing the mapping of the Boot ROM interru pt
vectors. Memory spaces other than the interrupt vectors remain in fixed locations.
Figure 2–13
UM10211
Chapter 2: LPC23XX memory addressing
Software
activation by
boot code
Software
activation by
user program
Software
activation by
user code
shows the on-chip memory mapping in the modes defined above.
Activated by the Boot Loader when a valid User Program Signature is
recognized in memory and Boot Loader operation is not forced.
Interrupt vectors are not re-mapped and are found in the bottom of the
Flash memory.
Activated by a User Program as desired. Interrupt vectors are
re-mapped to the bottom of the Static RAM.
Activated by a User Program as desired. Interrupt vectors are
re-mapped to external memory bank 0
[1]
.
The portion of memory that is re-mapped to allow interrupt processing in different modes
includes the interrupt vector area (32 bytes) and an additional 32 bytes for a total of
64 bytes, that facilitates branching to interrupt handlers at distant physical addresses. The
remapped code locations overlay addresses 0x0000 0000 through 0x0000 003F. A typical
user program in the Flash memory can place the entire FIQ handler at address
0x0000 001C without any need to consider mem or y bo un d ar ies. The vector contained in
the SRAM, external memory , and Boot ROM must cont ain branches to the actual interrupt
handlers, or to other instructions that accomplish the branch to the interrupt hand lers.
There are three reasons this configuration was chosen:
1. To give the FIQ handler in the Flash memory the advantage of not having to take a
memory boundary caused by the remapping into account.
2. Minimize the need to for the SRAM and Boot ROM vectors to deal with arbitrary
boundaries in the middle of code space.
3. To provide space to store constants for jumping beyond the range of single word
branch instructions.
Re-mapped memory areas, including the Boot ROM and interrupt vectors, continue to
appear in their original location in addition to the re-mapped address.
Details on re-mapping and examples can be found in Section 2–5 “
Memory mapping
control” on page 27.
UM10211_2 © NXP B.V. 2009. All rights reserved.
User manual Rev. 02 — 11 February 2009 26 of 706
NXP Semiconductors
5. Memory mapping control
The Memory Mapping Control alters the mapping of the interrupt vectors that appear
beginning at address 0x0000 0000. This allows code running in different memory spaces
to have control of the interrupts.
5.1 Memory Mapping Control Register (MEMMAP - 0xE01F C040)
Whenever an exception handling is necessary, microcontroller will fetch an instruction
residing on exception corresponding address as described in Table 2–11 “
vector locations” on page 25. The MEMMAP register determines the source of data that
will fill this table.
Table 13. Memory mapping control registers
Name Description Access Reset
MEMMAP Memory mapping control. Selects whether the
ARM interrupt vectors are read from the Boot
ROM, User Flash, or RAM.
UM10211
Chapter 2: LPC23XX memory addressing
ARM exception
Address
value
R/W 0x00 0xE01F C040
Table 14. Memory Mapping control register (MEMMAP - address 0xE01F C040) bit
description
Bit Symbol Value Description Reset
1:0 MAP 00 Boot Loader Mode. Interrupt vectors are re-mapped to Boot ROM. 00
01 User Flash Mode. Interrupt vectors are not re-mapped and reside
in Flash.
10 User RAM Mode. Interrupt vectors are re-mapped to Static RAM.
11 User External Memory Mode (available on LPC2377/78 and
LPC2388 only).
Warning: Improper setting of this value may result in incorrect operation of
the device.
7:2 - - Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
5.2 Memory mapping control usage notes
Memory Mapping Control simply selects one out of three available sources of data (set s of
64 bytes each) necessary for handling ARM exceptions (interrupts).
For example, whenever a Software Interrupt request is generated, ARM core will always
fetch 32 bit data "residing" on 0x0000 0008 see Table 2–11 “
locations” on page 25. This means that when MEMMAP[1:0] = 10 (User RAM Mode),
read/fetch from 0x0000 0008 will provide data stored in 0x4000 0008. In case of
MEMMAP[1:0] = 00 (Boot Loader Mode), read/fetch from 0x0000 0008 will provide data
available also at 0x7FFF E008 (Boot ROM remapped from on-chip Bootloader).
ARM exception vector
value
NA
UM10211_2 © NXP B.V. 2009. All rights reserved.
User manual Rev. 02 — 11 February 2009 27 of 706
NXP Semiconductors
0.0 GB
0x8000 0000
0x4000 0000
0x3FFF FFFF
0x0000 0000
1.0 GB
2.0 GB - 8 kB
2.0 GB
upper limit depends on
specific part number
ACTIVE INTERRUPT VECTORS
(FROM FLASH, SRAM, BOOT ROM, OR EXT MEMORY)
BOOT FLASH
RESERVED FOR ON-CHIP MEMORY
(SRAM INTERRUPT VECTORS)
FLASH MEMORY
RESERVED FOR ON-CHIP MEMORY
(BOOT ROM INTERRUPT VECTORS)
8 kB BOOT ROM
STATIC RAM
0x7FFF FFFF
FAST GPIO REGISTERS
PARTCFG REGISTERS
0x3FFF 8000
0x3FFF C000
0x3FFF BFFF
upper limit depends on
specific part number
8 kB BOOT FLASH
(RE-MAPPED FROM TOP OF FLASH MEMORY)
EXTERNAL MEMORY INTERRUPT VECTORS
0x7FFF E000
0x7FFE FFFF
0x7FFE E000
2.0 GB - 64 kB
2.0 GB - 72 kB
UM10211
Chapter 2: LPC23XX memory addressing
Fig 13. M ap of lower memory is showing re-mapped and re-mappable areas
UM10211_2 © NXP B.V. 2009. All rights reserved.
User manual Rev. 02 — 11 February 2009 28 of 706
NXP Semiconductors
6. Prefetch abort and data abort exceptions
The LPC2300 generates the appropriate bus cycle abort exception if an access is
attempted for an address that is in a reserved or unassigned address region. The regions
are:
• Areas of the memory map that are not implemented for a specific ARM derivative. Fo r
the LPC2300, this is:
– Address space between On-Chip Non-Volatile Memory and the Special Register
space. Labelled "Reserved for On-Chip Memory" in Figure 2–7
Figure 2–9
– Address space between On-Chip Static RAM and the Boot ROM. Labelled
"Reserved Address Space" in Figure 2–7
– External Memory
– Reserved regions of the AHB and APB spaces. See Figure 2–11
• Unassigned AHB peripheral spaces. See Figure 2–12.
• Unassigned APB peripheral spaces. See Table 2–10.
.
UM10211
Chapter 2: LPC23XX memory addressing
, Figure 2–8, and
, Figure 2–8, and Figure 2–9.
.
For these areas, both attempted data acce ss and in struction fetch genera te an exception.
In addition, a Prefetch Abort exception is generated for an y instruction fetch that maps to
an AHB or APB peripheral address, or to the Special Register space located just below
the SRAM at addresses 0x3FFF8000 through 0x3FFFFFFF.
Within the address space of an existing APB peripheral, a data abort exception is not
generated in response to an access to an undefined address. Address decoding within
each peripheral is limited to that needed to distinguish defined registers within the
peripheral itself. For example, an access to address 0xE000 D000 (an undefined addre ss
within the UART0 space) may result in an access to the register defined at address
0xE000 C000. Details of such address aliasing within a peripheral space are not defined
in the LPC2300 documentation and are not a supporte d feature.
If software executes a write directly to the Flash memory, the MAM generates a data abort
exception. Flash programming must be accomplished using the specified Flash
programming interface provided by the Boot Code.
Note that the ARM core stores the Prefetch Abort flag along with the associated
instruction (which will be meaningless) in the pipeline and processes the abort only if an
attempt is made to execute the instruction fetched from the illegal address. This prevents
accidental aborts that could be caused by prefetches that occur when code is executed
very near a memory boundary.
UM10211_2 © NXP B.V. 2009. All rights reserved.
User manual Rev. 02 — 11 February 2009 29 of 706
1. Introduction
UM10211
Chapter 3: LPC23XX System control block
Rev. 02 — 11 February 2009 User manual
The system control block includes several system features and control registers for a
number of functions that are not related to specific peripheral devices. These include:
• Reset
• Brown-Out Detection
• External Interrupt Input s
• Miscellaneous System Controls and Status
• Code Security vs. Debugging
Each type of function has its own register(s) if any are required and unneeded bit s are
defined as reserved in order to allow future expansion. Unrelated functions never share
the same register addresses
2. Pin description
Table 3–15 shows pins that are associated with System Control block functions.
Table 15. Pin summary
Pin name Pin
EINT0 Input External Interrupt Input 0 - An active low/high level or
EINT1 Input External Interrupt Input 1 - See the EINT0 description ab ove.
EINT2 Input External Interrupt Input 2 - See the EINT0 description ab ove.
EINT3 Input External Interrupt Input 3 - See the EINT0 description ab ove.
RESET
3. Register description
All registers, regardless of size, are on word address boundaries. Details of the registers
appear in the description of each function.
T able 16. Summary of system control registers
Name Description Access Reset
External interrupts
EXTINT External Interrupt Flag Register R/W 0x00 0xE01F C140
EXTMODE External Interrupt Mode register R/W 0x00 0xE01F C148
EXTPOLAR External Interrupt Polarity Register R/W 0x00 0xE01F C14C
Pin description
direction
falling/rising edge general purpose interrupt input. This pin may be
used to wake up the processor from Idle or Power down modes.
Input External Reset input - A LOW on this pin resets the chip, causing
I/O ports and peripherals to take on their default states, and the
processor to begin execution at address 0x0000 0000.
Address
value
UM10211_2 © NXP B.V. 2009. All rights reserved.
User manual Rev. 02 — 11 February 2009 30 of 706
Loading...