NXP TDA 8359 J Datasheet

INTEGRATED CIRCUITS

DATA SH EET

TDA8359J

Fullbridgeverticaldeflectionoutput
circuit in LVDMOS

Product specification
Supersedes data of 13 March 2000
Filed under Integrated Circuits, IC02

2002 Jan 21

Philips Semiconductors Product specification

Full bridge vertical deflection output circuit

TDA8359J

in LVDMOS

FEATURES

• Few external components required

• High efficiency fully DC-coupled vertical bridge output

circuit

• Vertical flyback switch with short rise and fall times

• Built-in guard circuit

• Thermal protection circuit

• Improved EMC performance due to differential inputs.

QUICK REFERENCE DATA

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supplies

V

P

V

FB

I

q(P)(av)

I

q(FB)(av)

P

tot

supply voltage 7.5 12 18 V
flyback supply voltage 2 × VP45 66 V
average quiescent supply current during scan − 10 15 mA
average quiescent flyback supply current during scan −−10 mA
total power dissipation −−10 W

Inputs and outputs

V

i(p-p)

I

o(p-p)

input voltage (peak-to-peak value) − 1000 1500 mV
output current (peak-to-peak value) −−3.2 A

Flyback switch

I

o(peak)

maximum (peak) output current t ≤ 1.5 ms −−±1.8 A

Thermal data; in accordance with IEC 60747-1

T

stg

T

amb

T

j

storage temperature −55 −+150 °C
ambient temperature −25 −+85 °C
junction temperature −−150 °C

GENERAL DESCRIPTION

The TDA8359J is a power circuit for use in 90° and 110°
colour deflection systems for 25 to 200 Hz field
frequencies, and for 4 : 3 and 16 : 9 picturetubes. The IC
contains a vertical deflection output circuit, operating as a
high efficiency class G system. The full bridge output
circuit allows DC coupling of the deflection coil in
combination with single positive supply voltages.

The IC is constructed in a Low Voltage DMOS (LVDMOS)
process that combines bipolar, CMOS and DMOS
devices. DMOS transistors are used in the output stage
because of absence of second breakdown.

ORDERING INFORMATION

TYPE

NUMBER

NAME DESCRIPTION VERSION

PACKAGE

TDA8359J DBS9P plastic DIL-bent-SIL power package; 9 leads (lead length

12/11 mm); exposed die pad

2002 Jan 21 2

SOT523-1

Philips Semiconductors Product specification

Full bridge vertical deflection output circuit
in LVDMOS

BLOCK DIAGRAM

handbook, full pagewidth

V

V

I(bias)

I(bias)

V

i(p-p)

1

INA

0

V

i(p-p)

INB

2

0

GUARD

86

GUARD

CIRCUIT

INPUT

AND

FEEDBACK

CIRCUIT

D1

TDA8359J

V

P

3

M2

M4

M1

M3

D3

V

FB

M5

D2

OUTA

7

9

FEEDB

4

OUTB

PINNING

SYMBOL PIN DESCRIPTION

INA 1 input A
INB 2 input B
V

P

3 supply voltage
OUTB 4 output B
GND 5 ground
V

FB

6 flyback supply voltage
OUTA 7 output A
GUARD 8 guard output
FEEDB 9 feedback input

5

GND

Fig.1 Block diagram.

handbook, halfpage

TDA8359J

MGL862

INA
INB

V

P

OUTB

GND

V

FB

OUTA

GUARD

FEEDB

1
2
3
4
5

TDA8359J

6
7
8
9

MGL863

2002 Jan 21 3

The exposed die pad is connected to pin GND.

Fig.2 Pin configuration.

Philips Semiconductors Product specification

Full bridge vertical deflection output circuit
in LVDMOS

FUNCTIONAL DESCRIPTION
Vertical output stage

The vertical driver circuit has a bridge configuration. The
deflection coil is connected between the complimentary
driven output amplifiers. The differential input circuit is
voltage driven. The input circuit is specially designed for
direct connection to driver circuits delivering a differential
signal but it is also suitable for single-ended applications.
For processors with output currents, the currents are
converted to voltages by the conversion resistors
R

and R

CV1

and INB. The differential input voltage is compared with
the voltage across the measuring resistor RM, providing
feedback information. The voltage across RM is
proportional with the output current. The relationship
between the differential input voltage and the output
current is defined by:

V

i(dif)(p-p)=Io(p-p)

V

i(dif)(p-p)

The output current should not exceed 3.2 A (p-p) and is
determined by the value of RMand RCV. The allowable
input voltage range is 100 mV to 1.6 V for each input. The
formula given does not include internal bondwire
resistances. Depending on the values of RM and the
internal bondwire resistance (typical value of 50 mΩ) the
actual value of the current in the deflection coil will be
approximately 5% lower than calculated.

Flyback supply

The flyback voltage is determined by the flyback supply
voltage VFB.Theprincipleoftwosupplyvoltages(class G)
allows to use an optimum supply voltage VP for scan and
an optimum flyback supply voltage VFB for flyback, thus
very high efficiency is achieved. The available flyback
output voltage across the coil is almost equal to VFB, due
to the absence of a coupling capacitor which is not
required in a bridge configuration. The very short rise and
fall times of the flyback switch are determined mainly by
the slew rate value of more than 300 V/µs.

(see Fig.5) connected to pins INA

CV2

× R

M

= V

INA

− V

INB

TDA8359J

Guard circuit

A guard circuit with output pin GUARD is provided.
The guard circuit generates a HIGH-level during the

flyback period. The guard circuit is also activated for one
of the following conditions:

• During thermal protection (Tj= 170 °C)

• During an open-loop condition.

The guard signal can be used for blanking the picture tube
and signalling fault conditions. The vertical
synchronization pulses of the guard signal can be used by
an On Screen Display (OSD) microcontroller.

Damping resistor compensation

HF loop stability is achieved by connecting a damping
resistor RD1across the deflection coil. The current values
in RD1 during scan and flyback are significantly different.
Boththeresistor current and the deflection coilcurrentflow
intomeasuringresistor RM,resultingina too low deflection
coil current at the start of the scan.

The difference in the damping resistor current values
during scan and flyback have to be externally
compensated in order to achieve a short settling time. For
that purpose a compensation resistor R
a zener diode is connected between pins OUTA and INA
(see Fig.4). The zener diode voltage value should be
equal to VP. The value of R

VFBV

– V

R

CMP

=

-----------------------------------------------------------------------------------------------------------­V

FBVloss FB()

loss FB()

– I

is calculated by:

CMP

–()R

× R

Z

coil peak()

where:

• V

isthe voltage loss between pins VFBand OUTA

loss(FB)

at flyback

• R

is the deflection coil resistance

coil

• VZ is the voltage of zener diode D4.

in series with

CMP

×

D1

CV1

R

×–()R

×

coil

M

Protection

The output circuit contains protection circuits for:

• Too high die temperature

• Overvoltage of output A.

2002 Jan 21 4

Philips Semiconductors Product specification

Full bridge vertical deflection output circuit

TDA8359J

in LVDMOS

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 60134).

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V

P

V

FB

V

n

I

n

I

lu

V

es

P

tot

T

stg

T

amb

T

j

supply voltage − 18 V
flyback supply voltage − 68 V
DC voltage

pin OUTA note 1 − 68 V
pin OUTB − V
pins INA, INB, GUARD and FEEDB −0.5 V

P
P

V
V

DC current

pins OUTA and OUTB during scan (p-p) − 3.2 A
pins OUTA and OUTB at flyback (peak); t ≤ 1.5 ms −±1.8 A
pins INA, INB, GUARD and FEEDB −20 +20 mA

latch-up current current into any pin; pin voltage is

−+200 mA

1.5 × VP; note 2
current out of any pin; pin voltage is

−1.5 × V

; note 2

P

−200 − mA

electrostatic handling voltage machine model; note 3 −500 +500 V

human body model; note 4 −5000 +5000 V
total power dissipation − 10 W
storage temperature −55 +150 °C
ambient temperature −25 +85 °C
junction temperature note 5 − 150 °C

Notes

1. When the voltage at pin OUTA supersedes 70 V the circuit will limit the voltage.

2. At T

j(max)

.

3. Equivalent to 200 pF capacitance discharge through a 0 Ω resistor.

4. Equivalent to 100 pF capacitance discharge through a 1.5 kΩ resistor.

5. Internally limited by thermal protection at Tj= 170 °C.

THERMAL CHARACTERISTICS

In accordance with IEC 60747-1.

SYMBOL PARAMETER CONDITIONS MAX. UNIT

R
R

th(j-c)
th(j-a)

thermal resistance from junction to case 3 K/W
thermal resistance from junction to ambient in free air 65 K/W

2002 Jan 21 5

Philips Semiconductors Product specification

Full bridge vertical deflection output circuit

TDA8359J

in LVDMOS

CHARACTERISTICS

VP= 12 V; VFB= 45 V; f
specified.

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supplies

V

P

V

FB

I

q(P)(av)

I

q(P)

I

q(FB)(av)

operating supply voltage 7.5 12 18 V
flyback supply voltage note 1 2 × VP45 66 V
average quiescent supply current during scan − 10 15 mA
quiescent supply current no signal; no load − 45 75 mA
average quiescent flyback supply

current

Inputs A and B

V

i(p-p)

V

I(bias)

I

I(bias)

input voltage (peak-to-peak value) note 2 − 1000 1500 mV
input bias voltage note 2 100 880 1600 mV
input bias current source − 25 35 µA

Outputs A and B

V

loss(1)

V

loss(2)

I

o(p-p)

voltage loss first scan part note 3

voltage loss second scan part note 4

output current
(peak-to-peak value)

LE linearity error I

V

offset

∆V

offset(T)

offset voltage across RM; V

offset voltage variation with
temperature

V

O

G

v(ol)

f

− 3dB(h)

G

v

∆G

v(T)

DC output voltage V
open-loop voltage gain notes 7 and 8 − 60 − dB
high −3 dB cut-off frequency open-loop − 1 − kHz
voltage gain note 9 − 1 −
voltage gain variation with the

temperature

PSRR power supply rejection ratio note 10 80 90 − dB

= 50 Hz; V

vert

I(bias)

= 880 mV; T

=25°C; measured in test circuit of Fig.3; unless otherwise

amb

during scan −−10 mA

= 1.1 A −−4.5 V

I

o

I

= 1.6 A −−6.6 V

o

= −1.1 A −−3.3 V

I

o

I

= −1.6 A −−4.8 V

o

−−3.2 A

= 3.2 A; notes 5 and 6

o(p-p)

adjacent blocks − 12%
non adjacent blocks − 13%

=0V

i(dif)

V

= 200 mV −−±15 mV

I(bias)

V

=1V −−±20 mV

I(bias)

across RM; V

=0V − 0.5 × VP− V

i(dif)

=0V −−40 µV/K

i(dif)

−−10

−4

K

−1

2002 Jan 21 6