NXP TDA 8359 J Datasheet

INTEGRATED CIRCUITS

DATA SH EET

TDA8359J

Fullbridgeverticaldeflectionoutput
circuit in LVDMOS

Product specification
Supersedes data of 13 March 2000
Filed under Integrated Circuits, IC02

2002 Jan 21

Philips Semiconductors Product specification

Full bridge vertical deflection output circuit

TDA8359J

in LVDMOS

FEATURES

• Few external components required

• High efficiency fully DC-coupled vertical bridge output

circuit

• Vertical flyback switch with short rise and fall times

• Built-in guard circuit

• Thermal protection circuit

• Improved EMC performance due to differential inputs.

QUICK REFERENCE DATA

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supplies

V

P

V

FB

I

q(P)(av)

I

q(FB)(av)

P

tot

supply voltage 7.5 12 18 V
flyback supply voltage 2 × VP45 66 V
average quiescent supply current during scan − 10 15 mA
average quiescent flyback supply current during scan −−10 mA
total power dissipation −−10 W

Inputs and outputs

V

i(p-p)

I

o(p-p)

input voltage (peak-to-peak value) − 1000 1500 mV
output current (peak-to-peak value) −−3.2 A

Flyback switch

I

o(peak)

maximum (peak) output current t ≤ 1.5 ms −−±1.8 A

Thermal data; in accordance with IEC 60747-1

T

stg

T

amb

T

j

storage temperature −55 −+150 °C
ambient temperature −25 −+85 °C
junction temperature −−150 °C

GENERAL DESCRIPTION

The TDA8359J is a power circuit for use in 90° and 110°
colour deflection systems for 25 to 200 Hz field
frequencies, and for 4 : 3 and 16 : 9 picturetubes. The IC
contains a vertical deflection output circuit, operating as a
high efficiency class G system. The full bridge output
circuit allows DC coupling of the deflection coil in
combination with single positive supply voltages.

The IC is constructed in a Low Voltage DMOS (LVDMOS)
process that combines bipolar, CMOS and DMOS
devices. DMOS transistors are used in the output stage
because of absence of second breakdown.

ORDERING INFORMATION

TYPE

NUMBER

NAME DESCRIPTION VERSION

PACKAGE

TDA8359J DBS9P plastic DIL-bent-SIL power package; 9 leads (lead length

12/11 mm); exposed die pad

2002 Jan 21 2

SOT523-1

Philips Semiconductors Product specification

Full bridge vertical deflection output circuit
in LVDMOS

BLOCK DIAGRAM

handbook, full pagewidth

V

V

I(bias)

I(bias)

V

i(p-p)

1

INA

0

V

i(p-p)

INB

2

0

GUARD

86

GUARD

CIRCUIT

INPUT

AND

FEEDBACK

CIRCUIT

D1

TDA8359J

V

P

3

M2

M4

M1

M3

D3

V

FB

M5

D2

OUTA

7

9

FEEDB

4

OUTB

PINNING

SYMBOL PIN DESCRIPTION

INA 1 input A
INB 2 input B
V

P

3 supply voltage
OUTB 4 output B
GND 5 ground
V

FB

6 flyback supply voltage
OUTA 7 output A
GUARD 8 guard output
FEEDB 9 feedback input

5

GND

Fig.1 Block diagram.

handbook, halfpage

TDA8359J

MGL862

INA
INB

V

P

OUTB

GND

V

FB

OUTA

GUARD

FEEDB

1
2
3
4
5

TDA8359J

6
7
8
9

MGL863

2002 Jan 21 3

The exposed die pad is connected to pin GND.

Fig.2 Pin configuration.

Philips Semiconductors Product specification

Full bridge vertical deflection output circuit
in LVDMOS

FUNCTIONAL DESCRIPTION
Vertical output stage

The vertical driver circuit has a bridge configuration. The
deflection coil is connected between the complimentary
driven output amplifiers. The differential input circuit is
voltage driven. The input circuit is specially designed for
direct connection to driver circuits delivering a differential
signal but it is also suitable for single-ended applications.
For processors with output currents, the currents are
converted to voltages by the conversion resistors
R

and R

CV1

and INB. The differential input voltage is compared with
the voltage across the measuring resistor RM, providing
feedback information. The voltage across RM is
proportional with the output current. The relationship
between the differential input voltage and the output
current is defined by:

V

i(dif)(p-p)=Io(p-p)

V

i(dif)(p-p)

The output current should not exceed 3.2 A (p-p) and is
determined by the value of RMand RCV. The allowable
input voltage range is 100 mV to 1.6 V for each input. The
formula given does not include internal bondwire
resistances. Depending on the values of RM and the
internal bondwire resistance (typical value of 50 mΩ) the
actual value of the current in the deflection coil will be
approximately 5% lower than calculated.

Flyback supply

The flyback voltage is determined by the flyback supply
voltage VFB.Theprincipleoftwosupplyvoltages(class G)
allows to use an optimum supply voltage VP for scan and
an optimum flyback supply voltage VFB for flyback, thus
very high efficiency is achieved. The available flyback
output voltage across the coil is almost equal to VFB, due
to the absence of a coupling capacitor which is not
required in a bridge configuration. The very short rise and
fall times of the flyback switch are determined mainly by
the slew rate value of more than 300 V/µs.

(see Fig.5) connected to pins INA

CV2

× R

M

= V

INA

− V

INB

TDA8359J

Guard circuit

A guard circuit with output pin GUARD is provided.
The guard circuit generates a HIGH-level during the

flyback period. The guard circuit is also activated for one
of the following conditions:

• During thermal protection (Tj= 170 °C)

• During an open-loop condition.

The guard signal can be used for blanking the picture tube
and signalling fault conditions. The vertical
synchronization pulses of the guard signal can be used by
an On Screen Display (OSD) microcontroller.

Damping resistor compensation

HF loop stability is achieved by connecting a damping
resistor RD1across the deflection coil. The current values
in RD1 during scan and flyback are significantly different.
Boththeresistor current and the deflection coilcurrentflow
intomeasuringresistor RM,resultingina too low deflection
coil current at the start of the scan.

The difference in the damping resistor current values
during scan and flyback have to be externally
compensated in order to achieve a short settling time. For
that purpose a compensation resistor R
a zener diode is connected between pins OUTA and INA
(see Fig.4). The zener diode voltage value should be
equal to VP. The value of R

VFBV

– V

R

CMP

=

-----------------------------------------------------------------------------------------------------------­V

FBVloss FB()

loss FB()

– I

is calculated by:

CMP

–()R

× R

Z

coil peak()

where:

• V

isthe voltage loss between pins VFBand OUTA

loss(FB)

at flyback

• R

is the deflection coil resistance

coil

• VZ is the voltage of zener diode D4.

in series with

CMP

×

D1

CV1

R

×–()R

×

coil

M

Protection

The output circuit contains protection circuits for:

• Too high die temperature

• Overvoltage of output A.

2002 Jan 21 4

Philips Semiconductors Product specification

Full bridge vertical deflection output circuit

TDA8359J

in LVDMOS

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 60134).

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V

P

V

FB

V

n

I

n

I

lu

V

es

P

tot

T

stg

T

amb

T

j

supply voltage − 18 V
flyback supply voltage − 68 V
DC voltage

pin OUTA note 1 − 68 V
pin OUTB − V
pins INA, INB, GUARD and FEEDB −0.5 V

P
P

V
V

DC current

pins OUTA and OUTB during scan (p-p) − 3.2 A
pins OUTA and OUTB at flyback (peak); t ≤ 1.5 ms −±1.8 A
pins INA, INB, GUARD and FEEDB −20 +20 mA

latch-up current current into any pin; pin voltage is

−+200 mA

1.5 × VP; note 2
current out of any pin; pin voltage is

−1.5 × V

; note 2

P

−200 − mA

electrostatic handling voltage machine model; note 3 −500 +500 V

human body model; note 4 −5000 +5000 V
total power dissipation − 10 W
storage temperature −55 +150 °C
ambient temperature −25 +85 °C
junction temperature note 5 − 150 °C

Notes

1. When the voltage at pin OUTA supersedes 70 V the circuit will limit the voltage.

2. At T

j(max)

.

3. Equivalent to 200 pF capacitance discharge through a 0 Ω resistor.

4. Equivalent to 100 pF capacitance discharge through a 1.5 kΩ resistor.

5. Internally limited by thermal protection at Tj= 170 °C.

THERMAL CHARACTERISTICS

In accordance with IEC 60747-1.

SYMBOL PARAMETER CONDITIONS MAX. UNIT

R
R

th(j-c)
th(j-a)

thermal resistance from junction to case 3 K/W
thermal resistance from junction to ambient in free air 65 K/W

2002 Jan 21 5

Philips Semiconductors Product specification

Full bridge vertical deflection output circuit

TDA8359J

in LVDMOS

CHARACTERISTICS

VP= 12 V; VFB= 45 V; f
specified.

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supplies

V

P

V

FB

I

q(P)(av)

I

q(P)

I

q(FB)(av)

operating supply voltage 7.5 12 18 V
flyback supply voltage note 1 2 × VP45 66 V
average quiescent supply current during scan − 10 15 mA
quiescent supply current no signal; no load − 45 75 mA
average quiescent flyback supply

current

Inputs A and B

V

i(p-p)

V

I(bias)

I

I(bias)

input voltage (peak-to-peak value) note 2 − 1000 1500 mV
input bias voltage note 2 100 880 1600 mV
input bias current source − 25 35 µA

Outputs A and B

V

loss(1)

V

loss(2)

I

o(p-p)

voltage loss first scan part note 3

voltage loss second scan part note 4

output current
(peak-to-peak value)

LE linearity error I

V

offset

∆V

offset(T)

offset voltage across RM; V

offset voltage variation with
temperature

V

O

G

v(ol)

f

− 3dB(h)

G

v

∆G

v(T)

DC output voltage V
open-loop voltage gain notes 7 and 8 − 60 − dB
high −3 dB cut-off frequency open-loop − 1 − kHz
voltage gain note 9 − 1 −
voltage gain variation with the

temperature

PSRR power supply rejection ratio note 10 80 90 − dB

= 50 Hz; V

vert

I(bias)

= 880 mV; T

=25°C; measured in test circuit of Fig.3; unless otherwise

amb

during scan −−10 mA

= 1.1 A −−4.5 V

I

o

I

= 1.6 A −−6.6 V

o

= −1.1 A −−3.3 V

I

o

I

= −1.6 A −−4.8 V

o

−−3.2 A

= 3.2 A; notes 5 and 6

o(p-p)

adjacent blocks − 12%
non adjacent blocks − 13%

=0V

i(dif)

V

= 200 mV −−±15 mV

I(bias)

V

=1V −−±20 mV

I(bias)

across RM; V

=0V − 0.5 × VP− V

i(dif)

=0V −−40 µV/K

i(dif)

−−10

−4

K

−1

2002 Jan 21 6

Philips Semiconductors Product specification

Full bridge vertical deflection output circuit

TDA8359J

in LVDMOS

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Flyback switch

I

o(peak)

V

loss(FB)

Guard circuit

V

O(grd)

V

O(grd)(max)

I

O(grd)

Notes

1. To limit V
and VFB at the first part of the flyback.

2. Allowable input range for both inputs: V

3. This value specifies the sum of the voltage losses of the internal current paths between pins VP and OUTA, and
between pins OUTB and GND. Specified for Tj= 125 °C. The temperature coefficient for V

4. This value specifies the sum of the voltage losses of the internal current paths between pins VP and OUTB, and
between pins OUTA and GND. Specified for Tj= 125 °C. The temperature coefficient for V

5. The linearity error is measured for a linear input signal without S-correction and is based on the ‘on screen’
measurement principle. This method is defined as follows. The output signal is divided in 22 successive equal time
parts. The 1st and 22nd parts are ignored, and the remaining 20 parts form 10 successive blocks k. A block consists
of two successive parts. The voltage amplitudes are measured across RM, starting at k = 1 and ending at k = 10,
where Vk and V
maximum and average voltages respectively. The linearity errors are defined as:

maximum (peak) output current t ≤ 1.5 ms −−±1.8 A
voltage loss at flyback note 11

I

= 1.1 A − 7.5 8.5 V

o

= 1.6 A − 89V

I

o

guard output voltage I
allowable guard voltage maximum leakage current

output current V

to 68 V, VFB must be 66 V due to the voltage drop of the internal flyback diode between pins OUTA

OUTA

I(bias)+Vi

are the measured voltages of two successive blocks. V

k+1

= 100 µA 567V

O(grd)

−−18 V

I

=10µA

L(max)

= 0 V; not active −−10 µA

O(grd)

= 4.5 V; active 1 − 2.5 mA

V

O(grd)

< 1600 mV and V

− Vi> 100 mV.

I(bias)

min

, V

max

and V

is a positive value.

loss(1)

is a positive value.

loss(2)

are the minimum,

avg

–

V

a) % (adjacent blocks)

LE

b) % (non adjacent blocks)

LE

kVk1+

------------------------- ­V

avg

–

V

maxVmin

-------------------------------

V

avg

100×=

100×=

6. The linearity errors are specified for a minimum input voltage of 300 mV (p-p). Lower input voltages lead to voltage
dependent S-distortion in the input stage.

7.

G

vol()

V

=

-------------------------------------------­V

–

OUTAVOUTB

–

FEEDBVOUTB

8. Pin FEEDB not connected.

9.

10. V

V

G

=

--------------------------------------------

v

P(ripple)

–

FEEDBVOUTB

V

–

INAVINB

= 500 mV (RMS value); 50 Hz < f

< 1 kHz; measured across RM.

P(ripple)

11. This value specifies the internal voltage loss of the current path between pins VFB and OUTA.

2002 Jan 21 7

Philips Semiconductors Product specification

Full bridge vertical deflection output circuit
in LVDMOS

APPLICATION INFORMATION

handbook, full pagewidth

V

I(bias)

0

V

I(bias)

0

V

I

I(bias)

I

I(bias)

V

i(p-p)

I

i(dif)

i(p-p)

R

CV1

2.2 kΩ
(1%)

R

CV2

2.2 kΩ
(1%)

INA

INB

1

2

R

GRD

4.7 kΩ
GUARD

863

GUARD

CIRCUIT

D1

INPUT

AND

FEEDBACK

CIRCUIT

V

P

M2

M4

M1

M3

5

GND

V

FB

M5

D3

TDA8359J

D2

7

9

4

MGL864

OUTA

FEEDB

OUTB

C1
100 nFC2100 nF

R

S

2.7 kΩ

C

M

10 nF

TDA8359J

V

P

V

FB

R

L

3.2 Ω

R

M

0.5 Ω

Fig.3 Test diagram.

2002 Jan 21 8

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2002 Jan 21 9

R

GRD

12 kΩ

GUARD

863

ok, full pagewidth

V

P

VP = 14 V
V

= 30 V

FB

V

FB

C3

100 nF

C1
47 µF
(100 V)

C4

100 nF

C2
220 µF
(25 V)

Philips Semiconductors Product specification

Full bridge vertical deflection output circuit

in LVDMOS

V

I(bias)

0

TV SIGNAL

PROCESSOR

V

I(bias)

0

V

V

i(p-p)

i(p-p)

C6

2.2 nF

C7

2.2 nF

R

CV1

2.2 kΩ
(1%)

R

CV2

2.2 kΩ
(1%)

INA

INB

1

2

GUARD

CIRCUIT

INPUT

AND

FEEDBACK

CIRCUIT

D1

M2

M4

M1

M3

5

GND

M5

D3

TDA8359J

D2

MBL364

7

9

4

OUTA

FEEDB

OUTB

D4

(14 V)

R

CMP

680 kΩ

2.7 kΩ

D1

deflection
coil
5 mH
6 Ω
(W66ESF)

R

M

0.5 Ω

C

D

47 nF

R

D2

1.5 Ω

R
270 Ω

R

S

TDA8359J

f

= 50 Hz; tFB= 640 µs; I

vert

I(bias)

= 400 µA; I

i(p-p)

= 290 µA; I

o(p-p)

= 2.4 A.

Fig.4 Application diagram.

Philips Semiconductors Product specification

Full bridge vertical deflection output circuit
in LVDMOS

RM calculation

Most Philips brand TV signal processors have outputs in
the form of current. This current has to be converted to a
voltage by using resistors at the input of the TDA8359J
(R

and R

CV1

resistors can be calculated by:

V

idif()pp–()

For calculating the measuring resistor R
differential input voltage (V
be measured between pins INA and INB (see Fig.5). The
calculation for RM is:

V

=

R

--------------------------- -

M

handbook, halfpage

). The differential voltage across these

CV2

I

i1 p p–()

idif()pp–()

I

op p–()

I

I(bias)

TV SIGNAL

PROCESSOR

R

× I–

CV1

i(dif)(p-p)

I

i1(p-p)

0

2.2 nF

()R

i2 p p–()

). This voltage can also

R

C6

CV1

2.2 kΩ

×–=

, use the

M

INA

CV2

1

TDA8359J

Supply voltage calculation

For calculating the minimum required supply voltage,
several specific application parameter values have to be
known. These parameters are the required maximum
(peak) deflection coil current I
R

coil

and L

, and the measuring resistance of RM. The

coil

coil(peak)

required maximum (peak) deflection coil current should
also include overscan.

The deflection coil resistance has to be multiplied by 1.2 in
order to take account of hot conditions.

Chapter “Characteristics” supplies values for voltage
losses of the vertical output stage. For the first part of the
scan, the voltage loss is given by V
part of the scan, the voltage loss is given by V

The voltage drop across the deflection coil during scan is
determined by the coil impedance. For the first part of the
scan the inductive contribution and the ohmic contribution
to the total coil voltage drop are of opposite sign, while for
the second part of the scan the inductive part and the
ohmic part have the same sign.

For the vertical frequency the maximum frequency
occurring must be applied to the calculations.

The required power supply voltage VP for the first part of
the scan is given by:

V

P1()Icoil peak()

L

coil2Icoil peak()

×=

R

coilRM

f

vert max()

+()

, the coil impedance

. For the second

loss(1)

V

+××–

loss 1()

loss(2)

.

INB

2

R

CV2

2.2 kΩ

MBL366

I

I(bias)

C7

2.2 nF

I

i2(p-p)

0

Fig.5 Input Circuit

E

XAMPLE

Measured or given values: I

I(bias)

= 400 µA; I

i1(p-p)=Ii2(p-p)

=

290 µA.
The differential input voltage will be:

V

idif()pp–()

290µA 2.2kΩ 290µA– 2.2kΩ×()–× 1.27V==

2002 Jan 21 10

The required power supply voltage VPfor the second part
of the scan is given by:

V

P2()Icoil peak()

L

coil2Icoil peak()

R

+()×=

coilRM

f

vert max()

V

+××+

loss 2()

The minimum required supply voltage VP shall be the
highest of the two values V

P(1)

and V

. Spread in supply

P(2)

voltage and component values also has to be taken into
account.

Philips Semiconductors Product specification

Full bridge vertical deflection output circuit
in LVDMOS

Flyback supply voltage calculation

If the flyback time is known, the required flyback supply
voltage can be calculated by the simplified formula:

R

+

coilRM

coil

+

− P

L

I

coil peak()

------------------------

P

×=

-------------------------- -

–

1e

2

t–FBx⁄

V

0.015 [A] 0.3 [W]+×+×=

P

V

FBIcoil p p–()

where:

=

-------------------------- ­R

coilRM

L

x

The flyback supply voltage calculated this way is
approximately 5% to 10% higher than required.

Calculation of the power dissipation of the vertical
output stage

The IC total power dissipation is given by the formula:
P

tot=Psup

The power to be supplied is given by the formula:

sup

V

P

In this formula 0.3 [W] represents the average value of the
losses in the flyback supply.

TDA8359J

Table 2 Calculated values

SYMBOL VALUE UNIT

V

P

RM+R
t

vert

(hot) 7.8 Ω

coil

x 0.000641
V

FB

P

sup

P

L

P

tot

Heatsink calculation

The value of the heatsink can be calculated in a standard
way with a method based on average temperatures. The
required thermal resistance of the heatsink is determined
bythemaximumdie temperature of 150 °C. In general we

recommend to design for an average die temperature
not exceeding 130 °C.

E

XAMPLE

Measured or given values: P
Tj= 120 °C; R

The required heatsink thermal resistance is given by:

14 V

0.02 s

30 V

8.91 W

3.74 W

5.17 W

= 4 K/W; R

th(j-c)

= 6 W; T

tot

th(c-h)

amb(max)

= 2 K/W.

=40°C;

The average external load power dissipation in the
deflection coil and the measuring resistor is given by the
formula:

I

()

------------------------------- -

L

coil peak()

P

2

3

R

coilRM

+()×=

Example
Table 1 Application values

SYMBOL VALUE UNIT

I

coil(peak)

I

coil(p-p)

L

coil

R

coil

R

M

f

vert

t

FB

1.2 A

2.4 A
5mH
6 Ω

0.6 Ω
50 Hz
640 µs

TjT

–

amb

R

th h a–()

----------------------- ­P

tot

R

th j c–()

R

+()–=

th c h–()

When we use the values given we find:

R

th h a–()

120 40–

----------------------

6

42+()– 7 K/W==

The heatsink temperature will be:
Th=T

amb

+(R

th(h-a)

× P

)=40+(7×6) = 82 °C

tot

2002 Jan 21 11

Philips Semiconductors Product specification

Full bridge vertical deflection output circuit
in LVDMOS

INTERNAL PIN CONFIGURATION

PIN SYMBOL EQUIVALENT CIRCUIT

1 INA

1

2 INB

2

300 Ω

300 Ω

TDA8359J

MBL100

3V

P

4 OUTB
5 GND
6V

FB

7 OUTA

MBL102

MGS805

6

3

7

4
5

2002 Jan 21 12

Philips Semiconductors Product specification

Full bridge vertical deflection output circuit
in LVDMOS

PIN SYMBOL EQUIVALENT CIRCUIT

8 GUARD

300 Ω

9 FEEDB

300 Ω

TDA8359J

8

MBL103

9

MBL101

2002 Jan 21 13

Philips Semiconductors Product specification

Full bridge vertical deflection output circuit
in LVDMOS

PACKAGE OUTLINE

DBS9P: plastic DIL-bent-SIL power package; 9 leads (lead length 12/11 mm); exposed die pad

non-concave

x

D

D

D

1

P

k

q

2

view B: mounting base side

A

2

E

h

h

TDA8359J

SOT523-1

q

1

E

19

Z

DIMENSIONS (mm are the original dimensions)

(2)

UNIT b

A

p

2

2.7

mm

Notes

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

2. Plastic surface within circle area D1 may protrude 0.04 mm maximum.

0.80

2.3

0.65

OUTLINE

VERSION

SOT523-1

cD

0.58

0.48

(1)

(2)

D

1

13.2

6.2

12.8

5.8

IEC JEDEC EIAJ

e

1

E

3.5

b

e

h

2.54

e

(1)

D

h

14.7

3.5

14.3

w M

p

0 10 mm5

scale

e

e

1

2

3.0

1.27

5.08 4.85

REFERENCES

2.0

12.4

11.0

B

q

L

3

L

2

L

L

Qc

m

L

Lq

11.4

10.0

L

L

m

2.8

Pk

3.4

3.1

1

2

3

6.7

4.5

5.5

3.7

e

2

QE

q

q

1

1.15

17.5

0.85

16.3

EUROPEAN

PROJECTION

1

v M

(1)

v

2

3.8

3.6

w

0.8

0.3

ISSUE DATE

98-11-12
00-07-03

x

0.02

Z

1.65

1.10

2002 Jan 21 14

Philips Semiconductors Product specification

Full bridge vertical deflection output circuit
in LVDMOS

SOLDERING
Introduction to soldering through-hole mount

packages

This text gives a brief insight to wave, dip and manual
soldering.Amorein-depthaccount of soldering ICs can be
found in our

Packages”

Wave soldering is the preferred method for mounting of
through-hole mount IC packages on a printed-circuit
board.

Soldering by dipping or by solder wave

The maximum permissible temperature of the solder is
260 °C; solder at this temperature must not be in contact
with the joints for more than 5 seconds.

Suitability of through-hole mount IC packages for dipping and wave soldering methods

DBS, DIP, HDIP, SDIP, SIL suitable suitable

“Data Handbook IC26; Integrated Circuit

(document order number 9398 652 90011).

PACKAGE

Thetotalcontact time of successive solder wavesmustnot
exceed 5 seconds.

The device may be mounted up to the seating plane, but
the temperature of the plastic body must not exceed the
specified maximum storage temperature (T
printed-circuit board has been pre-heated, forced cooling
may be necessary immediately after soldering to keep the
temperature within the permissible limit.

Manual soldering

Apply the soldering iron (24 V or less) to the lead(s) of the
package, either below the seating plane or not more than
2 mm above it. If the temperature of the soldering iron bit
is less than 300 °C it may remain in contact for up to
10 seconds. If the bit temperature is between
300 and 400 °C, contact may be up to 5 seconds.

SOLDERING METHOD

DIPPING WAVE

(1)

TDA8359J

). If the

stg(max)

Note

1. For SDIP packages, the longitudinal axis must be parallel to the transport direction of the printed-circuit board.

2002 Jan 21 15

Philips Semiconductors Product specification

Full bridge vertical deflection output circuit

TDA8359J

in LVDMOS

DATA SHEET STATUS

PRODUCT

DATA SHEET STATUS

Objective data Development This data sheet contains data from the objective specification for product

Preliminary data Qualification This data sheet contains data from the preliminary specification.

Product data Production This data sheet contains data from the product specification. Philips

Notes

1. Please consult the most recently issued data sheet before initiating or completing a design.

2. The product status of the device(s) described in this data sheet may have changed since this data sheet was
published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.

(1)

STATUS

(2)

development. Philips Semiconductors reserves the right to change the
specification in any manner without notice.

Supplementary data will be published at a later date. Philips
Semiconductors reserves the right to change the specification without
notice, in order to improve the design and supply the best possible
product.

Semiconductors reserves the right to make changes at any time in order
to improve the design, manufacturing and supply. Changes will be
communicated according to the Customer Product/Process Change
Notification (CPCN) procedure SNW-SQ-650A.

DEFINITIONS

DEFINITIONS
Short-form specification  The data in a short-form

specification is extracted from a full data sheet with the
same type number and title. For detailed information see
the relevant data sheet or data handbook.

Limiting values definition  Limiting values given are in
accordance with the Absolute Maximum Rating System
(IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device.
These are stress ratings only and operation of the device
attheseoratany other conditions above those given in the
Characteristics sections of the specification is not implied.
Exposure to limiting values for extended periods may
affect device reliability.

Application information  Applications that are
described herein for any of these products are for
illustrative purposes only. Philips Semiconductors make
norepresentationor warranty that suchapplicationswillbe
suitable for the specified use without further testing or
modification.

DISCLAIMERS
Life support applications  These products are not

designed for use in life support appliances, devices, or
systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips
Semiconductorscustomersusing or selling theseproducts
for use in such applications do so at their own risk and
agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.

Right to make changes  Philips Semiconductors
reserves the right to make changes, without notice, in the
products, including circuits, standard cells, and/or
software, described or contained herein in order to
improve design and/or performance. Philips
Semiconductors assumes no responsibility or liability for
theuseof any of these products, conveysnolicenceortitle
under any patent, copyright, or mask work right to these
products,andmakesnorepresentationsor warranties that
these products are free from patent, copyright, or mask
work right infringement, unless otherwise specified.

2002 Jan 21 16

Philips Semiconductors Product specification

Full bridge vertical deflection output circuit
in LVDMOS

NOTES

TDA8359J

2002 Jan 21 17

Philips Semiconductors Product specification

Full bridge vertical deflection output circuit
in LVDMOS

NOTES

TDA8359J

2002 Jan 21 18

Philips Semiconductors Product specification

Full bridge vertical deflection output circuit
in LVDMOS

NOTES

TDA8359J

2002 Jan 21 19

Philips Semiconductors – a w orldwide compan y

Contact information

For additional information please visit http://www.semiconductors.philips.com. Fax: [phone]
For sales offices addresses send e-mail to: [e-mail].

© Koninklijke Philips Electronics N.V. 2002
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.

Printed in The Netherlands 753504/25/02/pp20 Date of release: 2002 Jan 21 Document order number: 9397750 08868

SCA74