NXP SMD 4093 Datasheet

HEF4093B

Quad 2-input NAND Schmitt trigger

Rev. 8 — 21 November 2011 Product data sheet

1. General description

The HEF4093B is a quad two-input NAND gate. Each input has a Schmitt trigger circuit.
The gate switches at different points for positive-going and negative-going signals. The
difference between the positive voltage (V
hysteresis voltage (V

) and the negative voltage (VT) is defined as

T+

).

H

It operates over a recommended V
(usually ground). Unused inputs must be connected to V

power supply range of 3 V to 15 V referenced to VSS

DD

, VSS, or another input.

DD

2. Features and benefits

 Schmitt trigger input discrimination
 Fully static operation
 5 V, 10 V, and 15 V parametric ratings
 Standardized symmetrical output characteristics
 Specifie d from40 C to +85 C and 40 C to +125 C
 Complies with JEDEC standard JESD 13-B

3. Applications

 Wave and pulse shapers
 Astable multivibrators
 Monostable multivibrators

4. Ordering information

Table 1. Ordering information

All types operate from 40 C to +125 C

Type number Package

HEF4093BP DIP14 plastic dual in-line package; 14 leads (300 mil) SOT27-1
HEF4093BT SO14 plastic small outline package; 14 leads; body width 3.9 mm SOT108-1

Name Description Version

NXP Semiconductors

001aag104

1

1A

2

1B

5

2A

6

2B

8

3A

9

3B

12

4A

13

4B

3

4

10

11

1Y

2Y

3Y

4Y

001aag105

nA

nB

nY

HEF4093B

1A V

DD

1B 4B

1Y 4A

2Y 4Y

2A 3Y

2B 3B

V

SS

3A

001aag106

1

2

3

4

5

6

7

8

10

9

12

11

14

13

5. Functional diagram

HEF4093B

Quad 2-input NAND Schmitt trigger

Fig 1. Functional diagram Fig 2. Logic diagram (one gate)

6. Pinning information

6.1 Pinning

Fig 3. Pin configuration

HEF4093B All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.

Product data sheet Rev. 8 — 21 November 2011 2 of 15

NXP Semiconductors

6.2 Pin description

Table 2. Pin description

Symbol Pin Description

1A to 4A 1, 5, 8, 12 input
1B to 4B 2, 6, 9, 13 input
1Y to 4Y 3, 4, 10, 11 output
V

DD

V

SS

14 supply voltage
7 ground (0 V)

7. Functional description

HEF4093B

Quad 2-input NAND Schmitt trigger

Table 3. Function table

[1]

Input Output
nA nB nY

LLH
LHH
HLH
HHL

[1] H = HIGH voltage level; L = LOW voltage level.

8. Limiting values

Table 4. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to V

Symbol Parameter Conditions Min Max Unit

V

DD

I

IK

V

I

I

OK

I

I/O

I

DD

T

stg

T

amb

P

tot

supply voltage 0.5 +18 V
input clamping current VI< 0.5 V or VI>VDD + 0.5 V - 10 mA
input voltage 0.5 VDD + 0.5 V
output clamping current VO< 0.5 V or VO>VDD + 0.5 V - 10 mA
input/output current - 10 mA
supply current - 50 mA
storage temperature 65 +150 C
ambient temperature 40 +125 C
total power dissipation T

= 40 C to +125 C

amb

DIP14
SO14

[1]

- 750 mW

[2]

- 500 mW

P power dissipation per output - 100 mW

= 0 V (ground).

SS

[1] For DIP14 packages: above T
[2] For SO14 packages: above T

HEF4093B All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.

Product data sheet Rev. 8 — 21 November 2011 3 of 15

= 70 C, P

amb

= 70 C, P

amb

derates linearly with 12 mW/K.

tot

derates linearly with 8 mW/K.

tot

NXP Semiconductors

HEF4093B

Quad 2-input NAND Schmitt trigger

9. Recommended operating conditions

Table 5. Recommended operating conditions

Symbol Parameter Conditions Min Max Unit

V

DD

V

I

T

amb

supply voltage 3 15 V
input voltage 0 V

DD

V

ambient temperature in free air 40 +125 C

10. Static characteristics

Table 6. Static characteristics

VSS = 0 V; VI=VSS or VDD; unless otherwise specified.

Symbol Parameter Conditions V

V

OH

HIGH-level

IO < 1 A 5 V 4.95 - 4.95 - 4.95 - 4.95 - V

output voltage

V

OL

LOW-level

IO < 1 A 5 V - 0.05 - 0.05 - 0.05 - 0.05 V

output voltage

I

OH

HIGH-level
output current

I

OL

LOW-level
output current

I

I

input leakage

VO = 2.5 V 5 V - 1.7 - 1.4 - 1.1 - 1.1 mA
V

= 4.6 V 5 V - 0.64 - 0.5 - 0.36 - 0.36 mA

O

= 9.5 V 10 V - 1.6 - 1.3 - 0.9 - 0.9 mA

V

O

= 13.5 V 15 V - 4.2 - 3.4 - 2.4 - 2.4 mA

V

O

VO = 0.4 V 5 V 0.64 - 0.5 - 0.36 - 0.36 - mA

= 0.5 V 10 V 1.6 - 1.3 - 0.9 - 0.9 - mA

V

O

= 1.5 V 15 V 4.2 - 3.4 - 2.4 - 2.4 - mA

V

O

current

I

DD

supply current all valid input

combinations;

=0A

I

O

C

I

input
capacitance

10 V 9.95 - 9.95 - 9.95 - 9.95 - V
15 V 14.95 - 14.95 - 14.95 - 14.95 - V

10 V - 0.05 - 0.05 - 0.05 - 0.05 V
15 V - 0.05 - 0.05 - 0.05 - 0.05 V

15 V - 0.1 - 0.1 - 1.0 - 1.0 A

5 V - 0.25 - 0.25 - 7.5 - 7.5 A
10 V - 0.5 - 0.5 - 15.0 - 15.0 A
15 V - 1.0 - 1.0 - 30.0 - 30.0 A

DD

T

= 40 C T

amb

= +25 C T

amb

= +85 C T

amb

= +125 C Unit

amb

Min Max Min Max Min Max Min Max

---7.5-- - -pF

HEF4093B All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.

Product data sheet Rev. 8 — 21 November 2011 4 of 15

NXP Semiconductors

HEF4093B

Quad 2-input NAND Schmitt trigger

11. Dynamic characteristics

Table 7. Dynamic characteristics

T

= 25 C; CL = 50 pF; tr = tf  20 ns; wave forms see Figure 4; test circuit see Figure 5; unless otherwise specified.

amb

Symbol Parameter Conditions V

t

PHL

HIGH to LOW

nA or nB to nY 5 V 63 ns + (0.55 ns/pF)C

propagation delay

t

PLH

LOW to HIGH

nA or nB to nY 5 V 58 ns + (0.55 ns/pF)C

propagation delay

t

THL

HIGH to LOW output

nY to LOW 5 V 10 ns + (1.00 ns/pF)C

transition time

t

TLH

LOW to HIGH output
transition time

nA or nB to
HIGH

DD

Extrapolation formula

10 V 29 ns + (0.23 ns/pF)C
15 V 22 ns + (0.16 ns/pF)C

10 V 29 ns + (0.23 ns/pF)C
15 V 22 ns + (0.16 ns/pF)C

10 V 9 ns + (0.42 ns/pF)C
15 V 6 ns + (0.28 ns/pF)C

5 V 10 ns + (1.00 ns/pF)C
10 V 9 ns + (0.42 ns/pF)C
15 V 6 ns + (0.28 ns/pF)C

[1]

Min Typ Max Unit

- 90 185 ns

L

-4080ns

L

-3060ns

L

- 85 170 ns

L

-4080ns

L

-3060ns

L

- 60 120 ns

L

-3060ns

L

-2040ns

L

- 60 120 ns

L

-3060ns

L

-2040ns

L

[1] Typical value of the propagation delay and output transition time can be calculated with the extrapolation formula (CL in pF).

Table 8. Dynamic power dissipation

VSS = 0 V; tr = tf  20 ns; T

Symbol Parameter V

P

D

dynamic power
dissipation

= 25 C.

amb

Typical formula where:

DD

5V PD = 1300  fi + (fo  CL)  V
10 V P
15 V P

= 6400  fi + (fo  CL)  V

D

= 18700  fi + (fo  CL)  V

D

2

(W) fi = input frequency in MHz;

DD
DD

2

DD

(W)

2

(W)

f

= output frequency in MHz;

o

C

= output load capacitance in pF;

L

(fo  CL) = sum of the outputs;
V

= supply voltage in V.

DD

HEF4093B All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.

Product data sheet Rev. 8 — 21 November 2011 5 of 15