NXP S32V234 Specifications
NXP Semiconductors
S32V234_1N81U
Mask Set Errata
Mask Set Errata for Mask 1N81U
This report applies to mask 1N81U for these products:
• S32V234
Table 1. Errata and Information Summary
Erratum ID Erratum Title
ERR011152 2D-ACE: FIFO_HI and FIFO_LO status flag may be set incorrectly
ERR010327 ADC: Incorrect channel under measure is indicated after sampling phase of conversion until
conversion completes
ERR011287 CMU: Sudden loss of clock does not signal the Fault Collection and Control Unit
ERR006939 Core: Interrupted loads to SP can cause erroneous behavior
ERR009004 Core: ITM can deadlock when global timestamping is enabled
ERR009005 Core: Store immediate overlapping exception return operation might vector to incorrect interrupt
ERR006940 Core: VDIV or VSQRT instructions might not complete correctly when very short ISRs are used
ERR010493 Cortex-A53 MP Core:855873 – B: An eviction might overtake a cache clean operation
ERR010513 Cortex-A53 MPCore 850469 -C: Snoop requests might prevent a store exclusive from passing
ERR010512 Cortex-A53 MPCore 851672-C: ETM might trace an incorrect exception address
ERR010511 Cortex-A53 MPCore 851871-C: ETM might lose counter events while entering wfx mode
ERR010510 Cortex-A53 MPCore 852071-C: Direct branch instructions executed before a trace flush might be
output in an atom packet after flush acknowledgement
ERR010509 Cortex-A53 MPCore 852521-C: A64 unconditional branch might jump to incorrect address
ERR010503 Cortex-A53 MPCore 853172 C : ETM might assert AFREADY before all data has been output
ERR010502 Cortex-A53 MPCore 854821 C : A stream of instruction cache invalidate by address operations might
cause denial of service
ERR010498 Cortex-A53 MPCore 855831 C: A core might indefinitely delay the response to a DVM Sync message
after executing an LDM instruction
ERR010516 Cortex-A53 MPCore 820719-C: Device stores might cause denial of service
ERR010501 Cortex-A53 MPCore 855827 C : PMU counter values might be inaccurate when monitoring certain
events
ERR010500 Cortex-A53 MPCore 855829 C : Reads of PMEVCNTRn are not masked by HDCR.HPMN
ERR010499 Cortex-A53 MPCore 855830 C: Loads of mismatched size might not be single-copy atomic
Rev. 1.4
Table continues on the next page...
Table 1. Errata and Information Summary (continued)
Erratum ID Erratum Title
ERR010496 Cortex-A53 MPCore 855872: B: A Store-Exclusive instruction might pass when it should fail
ERR010497 Cortex-A53 MPCore 855874 C: APB data is not masked when PSLVERR is set
ERR010494 Cortex-A53 MPCore- 855871 B: ETM does not report IDLE state when disabled using OSLOCK
ERR008821 Cortex-A53: 836870-C Non-allocating reads might prevent a store exclusive from passing
ERR008823 Cortex-A53: 836919-C Write of JMCR in EL0 does not generate an UNDEFINED exception
ERR009235 Cortex-A53: 845719-B A load might read incorrect data.
ERR010183 Cortex-A53: MPCore 843819-B Memory locations might be accessed speculatively due to instruction
fetches when HCR.VM is set
ERR010101 DEC200 : DEC200 generates multiple Flush done interrupt(FLUSH_DN_INT) for a single Frame data
transfer from 2D ACE.
ERR050090 DSPI/SPI: Incorrect data may be transmitted in slave mode
ERR009656 DSPI: Frame transfer does not restart in case of SPI parity error in master mode
ERR009976 DSPI: Incorrect data received by master with Modified transfer format enabled when using Continuous
serial communication clock mode
ERR009420 FCCU: FOSU may give destructive reset when a hardware recoverable fault of width less than one
safe clock occurs
ERR011543 FlexCAN: Nominal Phase SJW incorrectly applied at CRC Delimiter
ERR050119 FlexRay: Disabling of FlexRay Message Buffer during the STARTUP Protocol State takes longer than
expected three Slots
ERR009265 FTM: Incorrect match may be generated if intermediate load feature is used in toggle mode
ERR011133 FXOSC: Device will not properly boot if using external oscillator
ERR010820 H264_DEC: H264 Decoder may fail if its configuration registers are programmed while the H264
Decoder clock is enabled.
ERR010206 ISP: Spurious Single-Error-Correction or Double-Error-Detection (SEC/DED) might get reported to the
Fault Collection & Control Unit (FCCU) if an IPU initialization procedure is triggered after generation of
an actual SEC/DED event from Instruction memory (IMEM).
ERR007274 LINFlexD: Consecutive headers received by LIN Slave triggers the LIN FSM to an unexpected state
ERR009685 MC_RGM: Unexpected reset is observed if DDR Handshake timeout value is set to 1
ERR010598 MEMU: The Memory Error Management Unit may not report a consecutive correctable or
uncorrectable error from the same address in FlexRay memory
ERR011172 MIPICSI2: Start of Transmission Error can occur at lower speeds
ERR050070 MMDC: Hardware Write Leveling Calibration Error bits MMDC_MPWLGCR[WL_HW_ERRn] are
incorrectly de-asserted
ERR011136 MMDC: HW calibration is not supported in 16 bit DDR configuration
ERR011222 MMDC: I/O pad glitches during power ramp-up which may lead to memory
corruption and boot failures when using LPDDR2
ERR011155 MMDC: ZQ calibration issue when interfacing to LPDDR2 memory with two chip selects
ERR010081 OTFAD: MDPC_SRTAR[DMNC] always reads as zero
ERR009196 PCIE: 9000611337-RC Root Error Message Controls Not Fully Implemented.
ERR009193 PCIE: 9000680610-Bus and Device Number not Cleared on Hot Reset
ERR010136 PCIE: 9000783666- AXI Bridge Master (RC): B-Channel Write Response Queue Overflows
Table continues on the next page...
Mask Set Errata for Mask 1N81U, Rev. 1.4
2 NXP Semiconductors
Table 1. Errata and Information Summary (continued)
Erratum ID Erratum Title
ERR009190 PCIE: 9000851378-Gen2: DSP Core Advertising Gen2 Speed Support Does Not Correctly Set
Selectable Deemphasis Bit In TS2s Transmitted In Recovery.RcvrCfg State
ERR010170 QuadSPI: Insufficient read data may be received in the RX Data Buffer register
ERR009658 SPI: Inconsistent loading of shift register data into the receive FIFO following an overflow event
ERR010400 SSE : Watchdog Error may not get asserted when the Watchdog Counter times out.
ERR010016 TMC: The RSZ register of the Cortex-M4 ETF shows an incorrect RAM size
ERR011151 TPIU: Trace may get corrupted or stalled when functional reset occurs
ERR010436 ZipWire: SIPI can have only one initiator with one outstanding write frame at time
Table 2. Revision History
Revision Changes
1 Initial revision
1.1 The following erratum was removed.
• ERR010481
The following errata were added.
• ERR011222
• ERR011155
1.2 The following erratum was removed.
• ERR010542
The following errata were added.
• ERR011287
• ERR010820
1.3 The following erratum was added.
• ERR050070
1.4 The following errata were added.
• ERR050119
• ERR050090
• ERR011543
The following errata were revised.
• ERR010500
• ERR006940
• ERR008823
Mask Set Errata for Mask 1N81U, Rev. 1.4
NXP Semiconductors 3
ERR011152: 2D-ACE: FIFO_HI and FIFO_LO status flag may be set incorrectly
Description:
Workaround:
The status flags Pm_FIFO_HI and Pm_FIFO_LO from the status register DCU_INT_STATUS
indicate whether the FIFO has reached its upper or lower threshold. These flags may be set
even when the condition has not occurred. Monitoring these flags for buffer fill status is not
recommended.
Use DCU_INT_STATUS[UNDRUN] flag to monitor if the 2D-ACE is getting sufficient
bandwidth to fetch data from memories.
ERR010327: ADC: Incorrect channel under measure is indicated after sampling phase
of conversion until conversion completes
Description:
Workaround:
The Main Status Register Channel under measure address field (ADC_MSR[CHADDR])
indicates which ADC channel is currently performing a conversion. This field indicates the
correct channel during the sampling phase of conversion, but will display an incorrect value in
the subsequent phases until conversion is complete.
User must only consider ADC_MSR[CHADDR] to be valid when the ADC is in the sample
phase of conversion. The Main Status Register Status of the ADC field shows when the ADC
is in the sample phase (ADC_MSR[ADCSTATUS] = 0b100).
ERR011287: CMU: Sudden loss of clock does not signal the Fault Collection and
Control Unit
Description:
Workaround:
The Clock Monitor Unit (CMU) detects when a monitored clock frequency drops below a
programmed threshold through the Frequency Less than Low Threshold (FLL) signal. This FLL
signal is routed to the Fault Collection and Control Unit ( FCCU ) providing a mechanism to
react to the clock fault. Due to it’s implementation, the FLL signal will not be triggered when the
monitored clock source suddenly stops.
The CMU has an internal signal which is designed to give an indication that the monitored
clock has dropped below 1/4 of the reference clock CLKMT0_RMN. This provides an
alternative means to detect the sudden loss of clock, however since this internal signal is not
routed to the FCCU, the user software must periodically poll bitfield [3] of CMU_ISR register to
detect a sudden loss of clock. Write ‘0b1’ to clear the bitfield [3] of CMU_ISR after enabling
CMU.
ERR006939: Core: Interrupted loads to SP can cause erroneous behavior
Description:
Arm Errata 752770: Interrupted loads to SP can cause erroneous behavior
This issue is more prevalent for user code written to manipulate the stack. Most compilers will
not be affected by this, but please confirm this with your compiler vendor. MQX™ and
FreeRTOS™ are not affected by this issue.
Affects: Cortex-M4, Cortex-M4F
Fault Type: Programmer Category B
Fault Status: Present in: r0p0, r0p1 Open.
Mask Set Errata for Mask 1N81U, Rev. 1.4
4 NXP Semiconductors
If an interrupt occurs during the data-phase of a single word load to the stack-pointer (SP/
R13), erroneous behavior can occur. In all cases, returning from the interrupt will result in the
load instruction being executed an additional time. For all instructions performing an update to
the base register, the base register will be erroneously updated on each execution, resulting in
the stack-pointer being loaded from an incorrect memory location.
The affected instructions that can result in the load transaction being repeated are:
1) LDR SP,[Rn],#imm
2) LDR SP,[Rn,#imm]!
3) LDR SP,[Rn,#imm]
4) LDR SP,[Rn]
5) LDR SP,[Rn,Rm]
The affected instructions that can result in the stack-pointer being loaded from an incorrect
memory address are:
1) LDR SP,[Rn],#imm
2) LDR SP,[Rn,#imm]!
Conditions:
1) An LDR is executed, with SP/R13 as the destination.
2) The address for the LDR is successfully issued to the memory system.
3) An interrupt is taken before the data has been returned and written to the stack-pointer.
Implications:
Unless the load is being performed to Device or Strongly-Ordered memory, there should be no
implications from the repetition of the load. In the unlikely event that the load is being
performed to Device or Strongly-Ordered memory, the repeated read can result in the final
stack-pointer value being different than had only a single load been performed.
Interruption of the two write-back forms of the instruction can result in both the base register
value and final stack-pointer value being incorrect. This can result in apparent stack corruption
and subsequent unintended modification of memory.
Workaround:
Most compilers are not affected by this, so a workaround is not required.
However, for hand-written assembly code to manipulate the stack, both issues may be worked
around by replacing the direct load to the stack-pointer, with an intermediate load to a generalpurpose register followed by a move to the stack-pointer.
If repeated reads are acceptable, then the base-update issue may be worked around by
performing the stack pointer load without the base increment followed by a subsequent ADD or
SUB instruction to perform the appropriate update to the base register.
ERR009004: Core: ITM can deadlock when global timestamping is enabled
Description:
ARM ERRATA 806422
The Cortex-M4 processor contains an optional Instrumentation Trace Macrocell (ITM). This
can be used to generate trace data under software control, and is also used with the Data
Watchpoint and Trace (DWT) module which generates event driven trace. The processor
supports global timestamping. This allows count values from a system-wide counter to be
included in the trace stream.
Mask Set Errata for Mask 1N81U, Rev. 1.4
NXP Semiconductors 5
When connected directly to a CoreSight funnel (or other component which holds ATREADY
low in the idle state), the ITM will stop presenting trace data to the ATB bus after generating a
timestamp packet. In this condition, the ITM_TCR.BUSY register will indicate BUSY.
Once this condition occurs, a reset of the Cortex-M4 is necessary before new trace data can
be generated by the ITM.
Timestamp packets which require a 5 byte GTS1 packet, or a GTS2 packet do not trigger this
erratum. This generally only applies to the first timestamp which is generated.
Devices which use the Cortex-M optimized TPIU (CoreSight ID register values 0x923 and
0x9A1) are not affected by this erratum.
Workaround:
There is no software workaround for this erratum. If the device being used is susceptible to this
erratum, you must not enable global timestamping.
ERR009005: Core: Store immediate overlapping exception return operation might
vector to incorrect interrupt
Description:
Arm Errata 838869: Store immediate overlapping exception return operation might vector to
incorrect interrupt
Affects: Cortex-M4, Cortex-M4F
Fault Type: Programmer Category B Rare
Fault Status: Present in: r0p0, r0p1 Open.
The Cortex-M4 includes a write buffer that permits execution to continue while a store is
waiting on the bus. Under specific timing conditions, during an exception return while this
buffer is still in use by a store instruction, a late change in selection of the next interrupt to be
taken might result in there being a mismatch between the interrupt acknowledged by the
interrupt controller and the vector fetched by the processor.
Configurations Affected
This erratum only affects systems where writeable memory locations can exhibit more than
one wait state.
Workaround:
6 NXP Semiconductors
For software not using the memory protection unit, this erratum can be worked around by
setting DISDEFWBUF in the Auxiliary Control Register.
In all other cases, the erratum can be avoided by ensuring a DSB occurs between the store
and the BX instruction. For exception handlers written in C, this can be achieved by inserting
the appropriate set of intrinsics or inline assembly just before the end of the interrupt function,
for example:
ARMCC:
...
__schedule_barrier();
__asm{DSB};
__schedule_barrier();
}
GCC:
...
Mask Set Errata for Mask 1N81U, Rev. 1.4
__asm volatile (“dsb 0xf” ::: “memory”);
}
ERR006940: Core: VDIV or VSQRT instructions might not complete correctly when
very short ISRs are used
Description:
Workaround:
Arm Errata 776924: VDIV or VSQRT instructions might not complete correctly when very short
ISRs are used
Affects: Cortex-M4F
Fault Type: Programmer Category B
Fault Status: Present in: r0p0, r0p1 Open.
On Cortex-M4 with FPU, the VDIV and VSQRT instructions take 14 cycles to execute. When
an interrupt is taken a VDIV or VSQRT instruction is not terminated, and completes its
execution while the interrupt stacking occurs. If lazy context save of floating point state is
enabled then the automatic stacking of the floating point context does not occur until a floating
point instruction is executed inside the interrupt service routine.
Lazy context save is enabled by default. When it is enabled, the minimum time for the first
instruction in the interrupt service routine to start executing is 12 cycles. In certain timing
conditions, and if there is only one or two instructions inside the interrupt service routine, then
the VDIV or VSQRT instruction might not write its result to the register bank or to the FPSCR.
A workaround is only required if the floating point unit is present and enabled. A workaround is
not required if the memory system inserts one or more wait states to every stack transaction.
There are two workarounds:
1) Disable lazy context save of floating point state by clearing LSPEN to 0 (bit 30 of the
FPCCR at address 0xE000EF34).
2) Ensure that every interrupt service routine contains more than 2 instructions in addition to
the exception return instruction.
ERR010493: Cortex-A53 MP Core:855873 – B: An eviction might overtake a cache
clean operation
Description:
NXP Semiconductors 7
The Cortex-A53 processor supports instructions for cache clean operations. To avoid data
corruption, the processor must ensure correct ordering between evictions and cache clean
operations for the same address.
Because of this erratum, the processor might issue an eviction and an L2 cache clean
operation to the interconnect in the wrong order. The processor might also issue the
transactions such that they are outstanding in the interconnect at the same time. This violates
the ACE protocol specification and might cause the transactions to be erroneously re-ordered
in the interconnect.
Conditions
The erratum can be hit if the following conditions are met under specific timing conditions.
1) One or both of the following are true:
1. L2ACTLR[14] is set to 1. This enables sending of WriteEvict transactions on the ACE
interface when the processor evicts data that it holds in the UniqueClean state.
Mask Set Errata for Mask 1N81U, Rev. 1.4
2. L2ACTLR[3] is set to 0. This enables sending of Evict transactions on the ACE interface
when the processor evicts clean data.
2) A core executes a cache clean by address operation for a line that is present and dirty in the
L2 cache.
3) A core performs a memory access to the same set. This could be any type of memory
access including a pagewalk, an instruction fetch, a cache maintenance operation, or a data
access.
4) The instruction in condition (3) triggers an L2 cache eviction.
5) The line chosen for eviction from the L2 cache is the same line that was targeted by the
cache clean operation in condition (2).
Implications
If the processor is connected to an interconnect that has a system cache or a snoop filter then
this erratum might cause data corruption.
Workaround:
The erratum can be avoided by upgrading cache clean by address operations to cache clean
and invalidate operations. For Cortex-A53 r0p3 and later releases, this can be achieved by
setting CPUACTLR.ENDCCASCI to 1. For earlier releases, software that uses DCCMVAC or
DCCMVAU instructions can replace them with DCCIMVAC instructions.
ERR010513: Cortex-A53 MPCore 850469 -C: Snoop requests might prevent a store
exclusive from passing
Description:
If a Cortex-A53 processor is executing a load and store exclusive instruction in a loop, then
there are certain conditions that are allowed to cause the store exclusive instruction to
repeatedly fail. This includes another processor repeatedly writing to the same cache line.
In addition to these allowed conditions, a ReadOnce snoop request from the same CPU,
another CPU, or another master in the system might also cause the store exclusive instruction
to repeatedly fail.
Conditions
1) CPU A executes a loop containing a store exclusive instruction. The loop will continue until
the store exclusive instruction succeeds.
2) CPU A, another CPU, or another master in the system issues a ReadOnce transaction for
an address with the same L1 data cache index as the store exclusive instruction. On CortexA53, a CPU might issue a ReadOnce transaction in the following scenarios:
. The CPU performs an instruction fetch to cacheable memory.
. The CPU executes a load instruction to cacheable memory that does not cause an allocation
into the cache. This might be because the memory is marked as no read allocate or transient
in the translation tables, or because a non-temporal load instruction is used.
3) The cache line of the ReadOnce transaction is present in the L1 cache of CPU A, and is not
present in the L2 cache.
4) The ReadOnce transaction triggers a snoop request that arrives at CPU A at the same time
as the store exclusive instruction is executing. This causes the store exclusive instruction to
fail.
5) The ReadOnce transaction is repeated at exactly the same frequency as the store exclusive
loop, so that every time around the loop, a snoop arrives at CPU A at the same time as the
store exclusive instruction is executing.
Mask Set Errata for Mask 1N81U, Rev. 1.4
8 NXP Semiconductors
CPU A can trigger the stream of ReadOnce snoop requests itself under the following
conditions:
1) CPU A issues a ReadOnce transaction for an instruction fetch to cacheable memory.
2) CPU A issues two or more instruction fetches to cacheable memory with the same L1
instruction cache index as the first instruction fetch. This causes the cache line for the first
instruction fetch to be invalidated.
3) The sequence is repeated so that the first instruction fetch repeatedly misses in the L1
instruction cache and issues another ReadOnce transaction.
Implications
CPU A can be prevented from making progress, resulting in a software livelock. The full set of
conditions are unlikely to be met within CPU A because it is unusual for several instruction
fetches to compete for the same set in the instruction cache with the frequency required to hit
the erratum. However, malicious code executing on another CPU or master might attempt to
use this erratum to cause a denial of service attack on CPU A. This is unlikely to be successful
because disturbances in the system such as an interrupt or other bus traffic could easily alter
the frequency of the loop or the instruction fetch sufficiently to break the livelock.
Workaround:
A workaround is not expected to be necessary. However, if a workaround is required then a
denial of service on a process can be avoided if the OS sets up a timer-based interrupt source
to interrupt all snoop generating masters periodically.
ERR010512: Cortex-A53 MPCore 851672-C: ETM might trace an incorrect exception
address
Description:
The address in an exception packet should be the preferred exception return address.
Because of this erratum, the address might be equal to the target address of the exception.
The trace stream is not corrupted, and decompression can continue after the affected packet.
Conditions
The following sequence is required to hit this erratum:
1) The ETM must start tracing instructions because of one of the following:
. Viewinst goes high.
. The security state changes such that trace is now permitted.
. The values of the external debug interface (DBGEN, SPIDEN, NIDEN, SPNIDEN) change
such that trace is now permitted.
. The core exits debug mode.
2) Before the core executes any other behavior which would cause trace to be generated, it
executes a direct branch instruction, which might be taken or not-taken.
3) The next instruction is a load or store that takes a Data Abort or Watchpoint exception.
After this sequence, provided certain timing specific conditions are met, the address in the
exception packet might be incorrect.
Implications
The trace decompressor might incorrectly infer execution of many instructions from the branch
target to the provided address.
Mask Set Errata for Mask 1N81U, Rev. 1.4
NXP Semiconductors 9
Workaround:
The trace decompressor can detect that this erratum has occurred by checking if the exception
address is in the Vector Table and the branch was not expected to be taken to the Vector
Table.
A decompressor can infer the correct address of the exception packet. It will be given by the
target of the preceding branch (If the branch was taken), or the next instruction after the
branch (If the branch was not-taken).
ERR010511: Cortex-A53 MPCore 851871-C: ETM might lose counter events while
entering wfx mode
Description:
Workaround:
If the ETM resources become inactive because of low-power state, there is a one-cycle
window during which the counters and the sequencer might ignore counter-at-zero resources.
Conditions
The following sequence is required to hit this erratum:
1) The core executes a WFI or WFE instruction.
2) The ETM enters low-power state because of this.
3) In a one-cycle window around this point, either:
. A counter in self-reload mode generates a counter-at-zero resource.
. A counter in normal mode gets a RLDEVENT on the cycle in which it has just transitioned to
zero.
4) A counter or sequencer is sensitive to the counter-at-zero resource.
Implications
Counters sensitive to a counter-at-zero resource might not reload or decrement. If the
sequencer is sensitive to a counter-at-zero resource, it might not change state, or might
change to an incorrect state.
The ETM can be prevented from entering low-power mode by programming LPOVERRIDE bit
of TRCEVENTCTL1R to 1. This workaround is only needed if there is a counter or sequencer
sensitive to a counter-at-zero resource, and is not normally necessary.
ERR010510: Cortex-A53 MPCore 852071-C: Direct branch instructions executed before
a trace flush might be output in an atom packet after flush
acknowledgement
Description:
10 NXP Semiconductors
The Embedded Trace Macrocell (ETMv4) architecture requires that when a trace flush is
requested on the AMBA Trace Bus (ATB), a processor must complete any packets that are in
the process of being encoded and output them prior to acknowledging the flush request. When
trace is enabled, the Cortex-A53 processor attempts to combine multiple direct branch
instructions into a single Atom packet. If a direct branch instruction is executed, and an Atom
packet is in the process of being generated, Cortex-A53 does not force completion of the
packet prior to acknowledging the flush request. This is a violation of the ETMv4 architecture.
Conditions
1) ETM is enabled.
2) Instruction tracing is active.
Mask Set Errata for Mask 1N81U, Rev. 1.4
3) One or more direct branch instructions are executed.
4) An Atom packet is being encoded but is not complete.
5) A trace flush is requested on the AMBA ATB.
Implications
When the above conditions occur, the Atom packet being encoded should complete and be
output prior to the trace flush request being acknowledged. Because of this erratum, the Atom
packet is output after the flush is acknowledged. Therefore, it will appear to software
monitoring the trace that the direct branch was executed after that requested flush.
Workaround:
Enabling the timestamp by setting TRCCONFIGR.TS will solve the issue as it will complete the
atom packets through the timestamp behavior.
ERR010509: Cortex-A53 MPCore 852521-C: A64 unconditional branch might jump to
incorrect address
Description:
When executing in AArch64 state with address translation disabled, unconditional immediate
branch instructions might jump to an incorrect address.
Conditions
1) The processor is executing in AArch64 state.
2) The SCTLR_ELx.M bit for the current exception level is 0.
3) The HCR_EL2.VM bit is 0.
4) A B or BL instruction from the “Unconditional branch (immediate)” encoding class is
executed.
5) This branch has an imm26 field of 0x1FFFFFF, encoding a branch target of {pc}
+0x7FFFFFC.
Implications
If these conditions are met, then the processor might incorrectly branch to the target
{pc}-0x8000004 instead of {pc}+0x7FFFFFC.
Workaround:
The workaround for this erratum is to avoid the conditions described.
ERR010503: Cortex-A53 MPCore 853172 C : ETM might assert AFREADY before all
data has been output
Description:
NXP Semiconductors 11
When the AFVALID signal on the ATB interface is asserted, the ETM should immediately start
outputting all buffered trace. It should assert the AFREADY output one cycle after all trace that
was buffered on the cycle in which AFVALID was first asserted.
Because of this erratum, the AFREADY signal might be asserted before all the necessary
trace has been output.
Conditions
The ETM must contain buffered trace.
Implications
Mask Set Errata for Mask 1N81U, Rev. 1.4
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