NXP RT600 Application Note
AN13056
Low-Power Modes and Wake-Up Time
Rev. 0 — 12/2020
Contents
1 RT600 Introduction
The RT6xx is a family of dual-core microcontrollers featuring an Arm CortexM33 CPU combined with a Cadence Xtensa HiFi 4 advanced audio Digital
Signal Processor (DSP). The family offers a rich set of peripherals with a
feature of very low-power consumption.
This application note introduces the various low-power modes of the RT600
series, the software APIs details to enter in low-power mode and wakeup source used for each low-power mode. This document also describes
hardware and software environment as well as procedure to measure supply current and wake-up time for each low-power mode.
The application note covers the following topics:
1. All low-power modes in RT600.
2. Overview on entry and wake-up Implementations for low-power modes.
3. Demonstrate how to measure current and wake-up time for each low-power mode.
1 RT600 Introduction..........................1
2 RT600 low-power modes
introduction......................................1
3 Entering low-power modes and
waking up........................................ 6
4 Low-power mode demo.................11
5 Conclusion.....................................20
6 References....................................20
Application Note
2 RT600 low-power modes introduction
On the RT600, there are four reduced power modes:
• Sleep mode
• Deep-sleep mode
• Deep power-down mode
• Full deep power-down mode
There are three special modes of the processor for power reduction like; sleep mode, deep-sleep mode, and deep power-down
mode. These modes can be activated by power modes library API from the SDK software package.
Power usage is controlled by settings in the register within the SYSCON block, regulator settings controlled via a Power API, and
the operating mode of a CPU. The following modes are supported in order from maximum to minimum power consumption.
2.1 Active mode
In active mode, clocks are enabled to the CPU and memories & peripherals are enabled.
The chip is in active mode after reset and the default power configuration is determined by the boot values of the PDRUNCFG
and PSCCTL registers. Power and clocks to selected peripherals can be optimized for power consumption during runtime. The
active mode consumes the highest power among all power modes. All low-power modes can be invoked from this power mode.
2.2 Sleep mode
In sleep mode, the clock to the CPU is stopped and execution of instructions is suspended until either a reset or an interrupt occurs.
The selected peripherals can be clocked to continue the operation during sleep mode and they may generate the interrupts or
can be configured as a wake-up source to resume the execution of the processor. Sleep mode eliminates dynamic power used
NXP Semiconductors
RT600 low-power modes introduction
by the processor itself, memory systems and related controllers, and internal buses. The SRAM contents can be retained based
on software configuration.
2.3 Deep-sleep mode
In the deep-sleep mode, the system clock to the processor is disabled like the sleep mode. The main clock, all peripheral clocks,
and primary clock source are also disabled.
All the analog blocks are powered down by default but these blocks are configurable to keep running during this mode and can be
used as a wake-up source. Deep-sleep mode reduces the overall power consumption by eliminating the power used by analog
peripherals, dynamic power used by the processor, memory systems and related controllers, and internal buses. The SRAM
contents can be retained based on software configuration.
2.4 Deep power-down mode
In the deep power-down mode, all clocks, the core, and all peripherals are powered down except RTC.
The device can wake-up from deep power-down mode via RESET pin, PMIC_IRQ_N pin, and RTC alarm. The device can enter
into deep power-down mode only by CM33. External power supply should be left on deep power-down mode. The contents of
SRAM and registers are not retained.
2.5 Full deep power-down mode
The full deep power-down and deep power-down mode are quite similar. In the full deep power-down mode, the whole system
shuts down making all power pins externally powered off (except VDD_AO18).
The device can be wake-up by external interrupts such as RESET pin, PMIC_IRQ_N pin, and RTC alarm. Apart from the normal
operations like full deep power-down mode which allows the device power pins to be externally powered off. The contents of
SRAM and registers are not retained.
2.6 Power down the Interfaces
The RT600 provides a PDRUNCFG registers to power down the desired interface. The power to various analog blocks (RAMs,
PLL, oscillators, and many others) can be controlled individually through the PDRUNCFG registers.
SYSCTLx_PDRUNCFGx register controls the power to various blocks during normal operation. Configuring PDRUNCFG
is typically accomplished using a Power APIs that handles all the details of altering PDRUNCFG bits. In this
application, the peripheral list shown in Table 1, Table 2, Table 3, and Table 4 are power-down by setting the bit in
SYSCTLx_PDRUNCFGx register.
Table 1. Run configuration register 1 (SYSCTL0_PDRUNCFG0)
Bit Symbol Description
14 LPOSC_PD 1 MHz low power oscillator
0 – Function is Enable
1 – Function is Powered Down
21 ADC_PD ADC Analog Function
0 – Function is Enable
1 – Function is Powered Down
22 ADC_LP ADC Low Power Mode
0 – Function is Enable
Table continues on the next page...
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RT600 low-power modes introduction
Table 1. Run configuration register 1 (SYSCTL0_PDRUNCFG0) (continued)
Bit Symbol Description
1 – Function is Powered Down
23 ADCTEMPSNS_PD ADC Temperature Sensor
0 – Function is Enable
1 – Function is Powered Down
25 ACMP_PD Analog Comparator
0 – Function is Enable
1 – Function is Powered Down
26 HSPAD0_VDET_LP FlexSPI high speed pad voltage detects sleep mode
0 – High Speed pad VDET in normal mode
1 - High Speed pad VDET in sleep mode
27 HSPAD0_REF_PD FlexSPI high speed pad sleep mode
0 – High Speed pad VREF Enabled
1 – High speed pad VREF in power down
28 HSPAD2_VDET_LP SDIO0 high speed pad voltage detects sleep mode
0 – High Speed pad VDET in normal mode
1 - High Speed pad VDET in sleep mode
29 HSPAD2_REF_PD SDIO0 high speed pad sleep mode
0 – High Speed pad VDET in normal mode
1 - High Speed pad VDET in sleep mode
Table 2. Run configuration register 2 (SYSCTL0_PDRUNCFG1)
Bit Symbol Description
0 PQ SRAM APD Array Power Down for Power Quad SRAM
0 – Function is Enable
1 – Function is Powered Down
1 PQ SRAM PPD Periphery Power Down for Power Quad SRAM
0 – Enable
1 – Disable
4 USBHS_SRAM_APD Array Power Down for USB SRAM
0 – Function is Enable
1 – Function is Powered Down
Table continues on the next page...
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RT600 low-power modes introduction
Table 2. Run configuration register 2 (SYSCTL0_PDRUNCFG1) (continued)
Bit Symbol Description
5 USBHS_SRAM_PPD Periphery Power Down for USB SRAM
0 – Function is Enable
1 – Function is Powered Down
6 USDHC0_SRAM_APD Array Power Down for uSDHC0 SRAM
0 – Function is Enable
1 – Function is Powered Down
7 USDHC0_SRAM_PPD Periphery Power Down for uSDHC0 SRAM
0 – Function is Enable
1 – Function is Powered Down
8 USDHC1_SRAM_APD Array Power Down for uSDHC1 SRAM
0 – Function is Enable
1 – Function is Powered Down
9 USDHC1_SRAM_PPD Periphery Power Down for uSDHC1 SRAM
0 – Function is Enable
1 – Function is Powered Down
10 CASPER_SRAM_APD Array Power Down for Casper SRAM
0 – Function is Enable
1 – Function is Powered Down
11 CASPER_SRAM_PPD Periphery Power Down for Casper SRAM
0 – Function is Enable
1 – Function is Powered Down
Table 3. Run configuration register 3 (SYSCTL0_PDRUNCFG2)
Bit Symbol Description
0 SRAM_IF0_APD Array Power Down for SRAM Interface 0
0 – Function is Enable
1 – Function is Powered Down
1 SRAM_IF1_APD Array Power Down for SRAM Interface 1
0 – Function is Enable
1 – Function is Powered Down
2 SRAM_IF2_APD Array Power Down for SRAM Interface 2
Table continues on the next page...
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RT600 low-power modes introduction
Table 3. Run configuration register 3 (SYSCTL0_PDRUNCFG2) (continued)
Bit Symbol Description
0 – Function is Enable
1 – Function is Powered Down
29:3 SRAM_IF[Bit]_APD Array Power Down for SRAM Interface [Bit]
0 – Function is Enable
1 – Function is Powered Down
Table 4. Run configuration register 4 (SYSCTL0_PDRUNCFG3)
Bit Symbol Description
0 SRAM_IF0_PPD Periphery Power Down for SRAM Interface 0
0 – Function is Enable
1 – Function is Powered Down
1 SRAM_IF1_PPD Periphery Power Down for SRAM Interface 1
0 – Function is Enable
1 – Function is Powered Down
2 SRAM_IF2_PPD Periphery Power Down for SRAM Interface 2
0 – Function is Enable
1 – Function is Powered Down
29:3 SRAM_IF[Bit]_PPD Periphery Power Down for SRAM Interface [Bit]
0 – Function is Enable
1 – Function is Powered Down
2.7 Low-power mode summary
Table 5 describes the peripherals that can be configured during power saving modes.
Table 5. Peripheral configuration in reduced power modes
Peripheral/clock Reduced power mode
Sleep Deep-sleep Deep power-down
(applies to both deep power-
down and full deep power-
down modes)
1m_lposc Software configured Software configured Off
16m_irc Software configured Software configured Off
Table continues on the next page...
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Entering low-power modes and waking up
Table 5. Peripheral configuration in reduced power modes (continued)
Peripheral/clock Reduced power mode
Sleep Deep-sleep Deep power-down
(applies to both deep power-
down and full deep power-
down modes)
48/60m_irc Software configured Software configured Off
Crystal Oscillator Software configured Software configured Off
RTC and RTC Oscillator Software configured Software configured Off
System PLL Software configured Software configured Software configured
Audio PLL Software configured Software configured Off
SRAM Memory Arrays Software configured Software configured Off
SRAM Periphery Software configured Software configured Off
Boot ROM On Off Off
Other Digital peripherals Software configured Software configured Off
A to D Convertor Software configured Software configured Off
Analog comparator Software configured Software configured
(the comparator may be
on in deep-sleep mode,
but cannot generate a wake-
up interrupt)
Off
3 Entering low-power modes and waking up
Power to the RT600 is supplied via two power domains. The “main power domain” has number of pins and options, and supplies
to the core, peripheral, memories, inputs, and outputs.
There is a secondary
always has power as long as sufficient voltage is supplied to VDD_AO1V8.
Power usage is controlled by settings in register within the SYSCON block, regulator settings controlled by Power APIs, and the
operating mode of a CPU. This application note describes how to enter and wake-up from the various low-power modes.
3.1 Power control API
always-on power domain
powered by VDD_AO1V8, it includes the RTC and wake-up timer. This domain
The power control APIs provide the functions to configure the system for expected performance requirements. Table 6 shows the
list of power APIs used in the application.
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Table 6. Power API ROM Calls
Function prototype API description
Entering low-power modes and waking up
void BOARD_SetPmicVoltageForFreq(uint32_t
main_clk_freq, uint32_t dsp_main_clk_freq);
void POWER_EnterSleep(void); Configures and enters in SLEEP low-power mode.
Void POWER_EnterDeepSleep(const
uint32_t exclude_from_pd[4]);
void POWER_EnterDeepPowerDown(const
uint32_t exclude_from_pd[4]);
void POWER_EnterFullDeepPowerDown(const
uint32_t exclude_from_pd[4]);
PMIC based on input frequency to provide different voltages.
PMC Deep Sleep function call. This function call configures the
board to enter in deep sleep mode.
PMC Deep Power Down function call. This function configures
the board to enter in deep power down mode.
PMC Full Deep Power Down function call. This function
configures the board to enter in full deep power down mode.
3.1.1 BOARD_SetPmicVoltageForFreq
The BOARD_SetPmicVoltageForFreq API is used to set different voltages based on input frequency provided.
Table 7. BOARD_SetPmicVoltageForFreq
Routine API description
Function Prototype BOARD_SetPmicVoltageForFreq(uint32_t main_clk_freq, uint32_t dsp_main_clk_freq);
Input Parameter Main clock frequency and DSP main clock frequency
Result None
Description PMIC based on input frequency to provide different voltages
3.1.2 POWER_EnterSleep
The POWER_EnterSleep API is used to configure and enter into sleep mode. It stops the system clock to the CPU and suspends
the execution of instruction until a reset or interrupt occurs. Selected peripheral function can continue operation during sleep mode
and may cause wake-up interrupt.
Table 8. POWER_EnterSleep
Routine API description
Function Prototype void POWER_EnterSleep(void);
Input Parameter None
Result None
Description Configures and enters in sleep low-power mode.
3.1.3 POWER_EnterDeepSleep
The POWER_EnterDeepSleep API is used to configure and enter into deep sleep mode. Selected analog blocks can be kept
running by using this API in the deep sleep mode and it can be used as wake-up source.
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