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QCVS DDR
User Manual
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NXP QCVS DDR User Manual

NXP Semiconductors Document identifier: QCVS_DDR_User_Guide
User's Guide Rev. 4.x, 01/2021
QCVS DDR Tool User Guide
NXP Semiconductors

Contents

Chapter 1 DDR Configuration and Validation........................................................ 3
1.1 DDR configuration..................................................................................................................... 3
1.1.1 Using DDR configuration tool......................................................................................................3
1.1.1.1 Create a new QorIQ configuration project..................................................................................... 4
1.1.1.2 Configure DDR controller...............................................................................................................6
1.1.2 Importing DDR configuration.....................................................................................................13
1.1.3 Exporting DDR configuration.....................................................................................................21
1.1.4 Advanced DDR configuration options....................................................................................... 21
1.2 DDR validation.........................................................................................................................28
1.2.1 Overview of DDR validation UI..................................................................................................28
1.2.2 Using DDR validation tool......................................................................................................... 33
1.2.3 Advanced DDR validation operations....................................................................................... 39
1.2.4 Licensing................................................................................................................................... 48
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Chapter 1 DDR Configuration and Validation
This document introduces the double data rate (DDR) RAM configuration and validation tool, which is an embedded component of QorIQ Configuration and Validation Suite (QCVS).
The DDR tool has two components: DDR configuration tool and DDR validation tool. The DDR configuration tool allows you to create a configuration for the DDR component and the DDR validation tool allows you to validate the DDR configuration using various validation scenarios.
This chapter is divided into the following sections:
• DDR configuration
• DDR validation

1.1 DDR configuration

This section describes how to create a new QorIQ configuration project, how to configure the DDR component, and how to perform some basic operations using the DDR configuration tool.
The DDR configuration tool inside the QCVS configures the DDR controller embedded in various supported QorIQ/Qonverge device families.
The DDR configuration tool provides a user-friendly graphical interface to configure the DDR controller. It can be used for tweaking some of the configuration parameters when you want to use different DDR Dual In-line Memory Modules (DIMMs) than the ones received with the board or when you want to optimize the DDR configuration.
While configuring DDR, you can view register values of the DDR controller. The register values will be exported by the DDR tool into C, TCL, or GDB code. After configuring the DDR controller, you can generate code that will fit easily into your software environment in the following ways:
• OS-agnostic low-level C source code that configures the DDR controller(s) registers' values.
• C source code that outputs the register values in the format required by U-Boot. This file can replace an existing file inside uBoot.
• Source code in DDR related part of the CodeWarrior target initialization file *.tcl. The code in this file can be used inside CodeWarrior projects.
This section contains the following subsections:
• Using DDR configuration tool
• Importing DDR configuration
• Exporting DDR configuration

1.1.1 Using DDR configuration tool

The DDR configuration tool helps you configure the DDR controller in a QorIQ processor, based on the DDR implementation (discrete or DIMM) used in the processor.
The DDR implementation may differ by various parameters, such as number of chip selects, memory size, or ranks interleaving. To configure a new DDR controller, you need to use the specifications from the DDR manufacturer data sheet and fill the values in the interface. The DDR parameters are grouped together by functionality.
This section contains the following subsections:
• Create a new QorIQ configuration project
• Configure DDR controller
• Generate code from DDR component
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DDR Configuration and Validation
1.1.1.1 Create a new QorIQ configuration project
To use the DDR configuration tool, you first need to create a QorIQ configuration project with DDR configuration.
To create a new QorIQ configuration project for DDR configuration, follow these steps:
1. Select File > New > QorIQ Configuration Project. Follow the steps in the New QorIQ Configuration Project wizard.
2. Enter project name.
3. Select the target SoC.
4. On the Toolset selection page, select the DDR Memory Controller Configuration checkbox.
Figure 1. Toolset selection page
5. Click Next. The DDR configuration page appears.
• To configure the DDR with DIMM settings, select the DIMM option.
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DDR Configuration and Validation
Figure 2. DDR configuration for DIMM
NOTE Lead-in skew is the difference between the A/C bus trace length and data bus trace length from the controller pins
to the DIMM connector pins.
• For designs that utilize embedded, discrete devices, select the Discrete DRAM option.
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DDR Configuration and Validation
Figure 3. DDR configuration for discrete DRAM
6. Click Finish to complete project creation.
This creates a QorIQ configuration project for DDR configuration.
1.1.1.2 Configure DDR controller
After creating a QorIQ configuration project with the DDR toolset, you can configure the DDR controller using the DDR configuration tool.
Perform the following steps to configure DDR controller:
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DDR Configuration and Validation
1. Select the DDR component under the Components folder in the Components view, as shown in the following figure. The properties of the DDR component opens in the Component Inspector view.
NOTE If the Component Inspector view is closed, you can open it by right-clicking the DDR component in the Components
view and choosing the Inspector option from the shortcut menu.
Figure 4. Select DDR components in Components view
NOTE You can add multiple DDR components to a project. Each DDR component maps to one DDR controller of the SoC.
For example, LS2088A SoC has two embedded DDR controllers, so if you want to configure both of them, add two
DDR components from the Components Library to the project, one component for each controller. Right-click the
DDR component in the Categories tab and select Add to project with Wizard from the shortcut menu, as shown in
the following figure.
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Figure 5. Add DDR component to project
DDR Configuration and Validation
2. Modify the following basic DDR parameters according to your requirements:
• Memory type: Specify the DDR memory type, for example, DDR 4 or DDR 3L
Figure 6. Set memory type
• DDR Bus Clock: For each DDR bus clock, there is a specific bus clock frequency that measures the duration of a bus clock cycle
Figure 7. Set DDR bus clock
• DIMM type: Specify the DIMM type: unbuffered or registered
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Figure 8. Set DIMM type
DDR Configuration and Validation
• Timing Configuration 1: Set four basic DDR timings:
tRAS
. The timings are measured in bus clock cycles.
tCL, tRCD, tRP, tRAS
specified usually as
tCL-tRCD-tRP-
Figure 9. Set timing configuration 1
• Chip Select 0, 1, 2, 3: Specify the number of physical ranks or chip selects. A DIMM can have 1, 2, or 4 ranks and are specified in the basic DIMM information as 1R ... or 2R... or 4R. For this, from the four chip selects, enable the ones that correspond to the ranks (each chip select corresponds to one rank). Also, set size of the DIMM. The size is configured inside each chip select. For example, a 32 GB dual-ranked DIMM has its size split evenly between the two ranks such that each chip select is of 16 GB size.
Figure 10. Set chip select / physical ranks
3. Set rest of the parameters as per the datasheet of the DDR device. The datasheet can be obtained from the DDR manufacturer's website or directly from the DDR manufacturer.
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DDR Configuration and Validation
NOTE For each step of the configuration process, you might receive validation errors for some specific parameters along
with information on how to fix the validation conflict.
You can import register values of the DDR component from a memory dump, containing the values of the DDR memory-mapped registers. Memory dumps can be obtained from U-Boot (using the md command) or CodeWarrior (using the Export registers/ memory feature).
1. Select the Import tab in the Component Inspector view.
Figure 11. Import tab - DDR component
2. Specify the location of the input file in the Input file field. The red mark denoting an error/conflict disappears.
NOTE The red marks indicate errors; therefore, before clicking the Import button, ensure that no red mark is displaying.
3. Choose an appropriate file format for the input file from the File format menu. If the file content is not in accordance with the chosen format, the import operation will fail and an error message will pop up.
4. Specify the number of bytes by choosing an option from the Addressable size menu.
5. Specify byte order by choosing an option from the Endianness menu.
6. Specify valid address information of the memory dump file in the First address from memory dump file field.
7. Specify the beginning address of the memory-mapped DDR registers inside the memory dump in the Start address of DDR memory controller field. The First address from memory dump file and Start address of DDR memory controller fields are enabled for editing only after deselecting the Use default checkbox.
8. Click Import. The input file is imported.
9. Click OK in the Import complete dialog (shown below).
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Figure 12. Import complete dialog
10. Open the Problems view to see reported errors if any.
You can also configure the DDR component while creating the QorIQ project. On the DDR Configuration page (see
Figure 3), select the appropriate option, Auto configuration or From memory file, and provide the necessary details
corresponding to the selected option.
1.1.1.3 Generate code from DDR component
NOTE
DDR Configuration and Validation
After you finish configuring the DDR controller, you can generate code from DDR component to get updated output of the component.
The source code generated from the DDR component helps you configure the DDR controller registers and it can be used in the CodeWarrior projects.
The code generation from the DDR component is based on the properties set in the Component Inspector view. You can use any of the following options to generate DDR component code:
• Click the Generate Processor Expert Code icon
in the Components view, as shown in the following figure.
• Right-click ProcessorExpert.pe in the Project Explorer and choose Generate Processor Expert Code from the shortcut menu.
• Choose the Project > Generate Processor Expert Code option from the Eclipse IDE menu.
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Figure 13. Generate Processor Expert code
The output file is generated and placed in the Generated_Code folder of the Project Explorer. The output file is named according to the DDR component name used in the QorIQ Configuration project, as shown in the figure below.
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DDR Configuration and Validation
Figure 14. DDR-generated code file in Project Explorer

1.1.2 Importing DDR configuration

The DDR tool allows you to import a memory dump, which can be in a format, such as U-Boot, S-Record, AnnotatedHex, Signed/Unsigned decimal, CodeWarrior Regs, Hex, or Raw Binary.
The memory dump is decoded into a DDR configuration, which then can be visualized, validated, and adjusted, if required.
To import a DDR configuration, a QorIQ Configuration project must be created. You can import the DDR configuration during project creation or later for any component already added to the project. Perform the following steps:
1. On the DDR Configuration page of the New QorIQ Configuration Project wizard (shown below), select the From memory file option.
2. Specify the memory dump file to be imported in the Input file text box.
3. Based on file content, choose a file format for the input file from the File format menu.
4. Choose byte order from the Endian mode menu.
5. Click Import and wait to see if the import was done correctly. The Finish button will be enabled.
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DDR Configuration and Validation
Figure 15. Selecting input file for DDR configuration
6. Click Finish. The DDR project is created.
7. Open Component Inspector for the DDR project.
8. Select the Import tab and set the following parameters as shown in the next figure:
• Input file: Specify the file that encapsulates the memory dump
• File format: Choose a file format for the input file based on the file content. If the file content is not in accordance with the chosen format, the import operation will fail and an error message will pop up.
You can also import a DDR configuration from the target board by choosing Import from target from the File format menu. This action only works if an active and working connection is configured in the Connections View (see
Getting Started Guide
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for more information). If such a connection exists, the DDR tool reads the DDR registers from
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the board and populates the active component with the data read. Note that this type of action is relevant only if the DDR registers were previously configured (for example, by U-Boot).
• Addressable size: Specify the number of bytes
• Endianness: Specify byte order
• First address from memory dump file: Specify valid address information of the memory dump file
• Start address of DDR memory controller: Specify the beginning address of the memory-mapped DDR registers inside the memory dump. The First address from memory dump file and Start address of DDR memory controller fields are enabled for editing only after deselecting the Use default checkbox.
DDR Configuration and Validation
Figure 16. Component Inspector - Specifying import parameters
NOTE In case the input file does not contain the DDR data rate value on the first line, you will be prompted to choose a
data rate value.
This is how a DDR configuration can be imported.
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