NXP PMGD780SN Schematic [ru]

132

4

56

S

1

D

1

G1S

2

msd901

D

2

G

2

PMGD780SN

Dual N-channel μTrenchMOS standard level FET

Rev. 02 — 19 April 2010 Product data sheet

1. Product profile

1.1 General description

Dual N-channel enhancement mode field-effect transistor in a small SOT363 (SC-88)
Surface-Mounted Device (SMD) plastic package using TrenchMOS technology.

1.2 Features and benefits

 Surface-mounted package  Footprint 40 % smaller than SOT23
 Standard level threshold voltage  Fast switching
 Low on-state resistance  Dual device

1.3 Applications

 Driver circuits  Switching in portable appliances

1.4 Quick reference data

 V
 P

≤ 60 V  ID≤ 0.49 A

DS

≤ 0.41 W  R

tot

2. Pinning information

Table 1. Pinning - SOT363 (SC-88), simplified outline and symbol

Pin Description Simplified outline Graphic symbol

1 source1 (S1)

2 gate1 (G1)

3 drain2 (D2)

4 source2 (S2)

5 gate2 (G2)

6 drain1 (D1)

≤ 920 mΩ

DSon

SOT363 (SC-88)

NXP Semiconductors

3. Ordering information

PMGD780SN

Dual N-channel μTrenchMOS standard level FET

Table 2. Ordering information

Type number Package

PMGD780SN SC-88 plastic surface-mounted package; 6 leads SOT363

Name Description Ver s ion

4. Limiting values

Table 3. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol Parameter Conditions Min Max Unit

V

DS

V

DGR

V

GS

I

D

I

DM

P

tot

T

stg

T

j

Source-drain diode

I

S

I

SM

drain-source voltage 25 °C ≤ Tj≤ 150 °C-60V

drain-gate voltage 25 °C ≤ Tj≤ 150 °C; RGS=20kΩ -60V

gate-source voltage - ±20 V

drain current Tsp=25°C; VGS=10V; Figure 2 and 3

peak drain current Tsp=25°C; pulsed; tp≤ 10 μs; Figure 3

total power dissipation Tsp=25°C; Figure 1 -0.41W

storage temperature −55 +150 °C

junction temperature −55 +150 °C

source current Tsp=25°C

peak source current Tsp=25°C; pulsed; tp≤ 10 μs

[1]

-0.49A

=100°C; VGS=10V; Figure 2

T

sp

[1]

-0.31A

[1]

-0.99A

[1]

-0.34A

[1]

-0.69A

[1] Single device conducting.

PMGD780SN_2 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.

Product data sheet Rev. 02 — 19 April 2010 2 of 14

NXP Semiconductors

Tsp (°C)

0 20015050 100

03aa17

40

80

120

P

der

(%)

0

Tsp (°C)

0 20015050 100

03aa25

40

80

120

I

der

(%)

0

P

der

P

tot

P

tot 25 C°()

------------ -----------

100%×=

I

der

I

D

I

D25C

°

()

------------ -------

100%×=

03an22

10

-3

10

-2

10

-1

1

10

10

-1

1 10 10

2

VDS(V)

I

D

(A)

DC

10 ms

Limit R

DSon

= V

DS

/ I

D

1 ms

tp = 10 μs

100 ms

100 μs

PMGD780SN

Dual N-channel μTrenchMOS standard level FET

Fig 1. Normalized total power dissipation as a

function of solder point temperature

Fig 2. Normalized continuous drain current as a

function of solder point temperature

Tsp=25°C; IDM is single pulse; VGS=10V

Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage

PMGD780SN_2 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.

Product data sheet Rev. 02 — 19 April 2010 3 of 14

NXP Semiconductors

03an28

1

10

10

2

10

3

10

-4

10

-3

10

-2

10

-1

1 10

tp (s)

Z

th(j-sp)

(K/W)

single pulse

δ

= 0.5

0.2

0.1

0.05

0.02

t

p

t

p

T

P

t

T

δ =

5. Thermal characteristics

PMGD780SN

Dual N-channel μTrenchMOS standard level FET

Table 4. Thermal characteristics

Symbol Parameter Conditions Min Typ Max Unit

R

th(j-sp)

thermal resistance from junction to solder point Figure 4 - - 300 K/W

Fig 4. Transient thermal impedance from junction to solder point as a function of pulse duration

PMGD780SN_2 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.

Product data sheet Rev. 02 — 19 April 2010 4 of 14

NXP Semiconductors

6. Characteristics

PMGD780SN

Dual N-channel μTrenchMOS standard level FET

Table 5. Characteristics

=25°C unless otherwise specified.

T

j

Symbol Parameter Conditions Min Typ Max Unit

Static characteristics

V

(BR)DSS

V

GS(th)

drain-source breakdown voltage ID= 250 μA; VGS=0V

=25°C 60--V

T

j

= −55 °C 55--V

T

j

gate-source threshold voltage ID= 0.25 mA; VDS=VGS; Figure 9

Tj=25°C 122.5V

=150°C0.6−−V

T

j

= −55 °C −−3.5 V

T

j

I

DSS

I

GSS

R

DSon

drain leakage current VDS=60V; VGS=0V

=25°C-0.051μA

T

j

=150°C - - 100 μA

T

j

gate leakage current VGS= ±20 V; VDS= 0 V - 10 100 nA

drain-source on-state resistance VGS=10V; ID=0.3A; Figure 7 and 8

Tj=25°C - 780 920 mΩ

=150°C - 1445 1700 mΩ

T

V

GS

j

= 4.5 V; ID=0.075A; Figure 7 and 8 -11001400mΩ

Dynamic characteristics

Q

Q

Q

C

C

C

t

d(on)

t

r

t

d(off)

t

f

G(tot)

GS

GD

iss

oss

rss

total gate charge ID=1A; VDD=30V; VGS=10V; Figure 13 -1.05-nC

gate-source charge - 0.2 - nC

gate-drain charge - 0.22 - nC

input capacitance VGS=0V; VDS= 30 V; f = 1 MHz; Figure 11 -23-pF

output capacitance - 5 - pF

reverse transfer capacitance - 3.5 - pF

turn-on delay time VDD=30V; RL=30Ω; VGS=10V; RG=6Ω -2-ns

rise time -4-ns

turn-off delay time - 5 - ns

fall time -2.2-ns

Source-drain diode

V

SD

source-drain voltage IS= 0.3 A; VGS=0V; Figure 12 - 0.83 1.2 V

PMGD780SN_2 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.

Product data sheet Rev. 02 — 19 April 2010 5 of 14