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Philips Semiconductors Product specification
PowerMOS transistor PIP3104-P Logic level TOPFET

DESCRIPTION QUICK REFERENCE DATA

Monolithic temperature and SYMBOL PARAMETER MAX. UNIT overload protected logic level power MOSFET in TOPFET2 technology V assembled in a 3 pin plastic I package. P

APPLICATIONS R

D
T
DS
D j
DS(ON)
Drain-source on-state resistance 100 mΩ
General purpose switch for driving I
lamps
ISL
Input supply current VIS = 5 V 650 µA
motors solenoids heaters

FEATURES FUNCTIONAL BLOCK DIAGRAM

TrenchMOS output stage Current limiting Overload protection Overtemperature protection Protection latched reset by input 5 V logic compatible input level Control of output stage and supply of overload protection circuits derived from input Low operating input current permits direct drive by micro-controller ESD protection on all pins Overvoltage clamping for turn off of inductive loads
INPUT
RIG
LOGIC AND
PROTECTION
O / V
CLAMP
DRAIN
POWER MOSFET
SOURCE
Fig.1. Elements of the TOPFET.

PINNING - SOT78B PIN CONFIGURATION SYMBOL

PIN DESCRIPTION
1 input 2 drain 3 source
tab drain
May 2001 1 Rev 1.000
mb mb
123
Front view
MBL292
TOPFET
I
D
P
S
Philips Semiconductors Product specification
PowerMOS transistor PIP3104-P Logic level TOPFET

LIMITING VALUES

Limiting values in accordance with the Absolute Maximum Rating System (IEC 134)
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
V I
I I I P T T
T
DS
D
D I IRM
D stg j
sold
Continuous drain source voltage Continuous drain current VIS = 5 V; T
Continuous drain current VIS = 5 V; T Continuous input current - -5 5 mA Non-repetitive peak input current tp ≤ 1 ms -10 10 mA Total power dissipation Tmb ≤ 25 ˚C - 40 W Storage temperature - -55 175 ˚C Continuous junction temperature
Lead temperature during soldering - 260 ˚C

ESD LIMITING VALUE

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
1
- - 50 V 25 ˚C - self - A
mb =
limited
110 ˚C-8A
mb ≤
2
normal operation - 150 ˚C
V
C
Electrostatic discharge capacitor Human body model; - 2 kV voltage C = 250 pF; R = 1.5 kΩ

OVERVOLTAGE CLAMPING LIMITING VALUES

At a drain source voltage above 50 V the power MOSFET is actively turned on to clamp overvoltage transients.
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
Inductive load turn-off IDM = 8 A; VDD ≤ 20 V
E
DSM
E
DRM
Non-repetitive clamping energy Tmb ≤ 25 ˚C - 100 mJ Repetitive clamping energy Tmb ≤ 95 ˚C; f = 250 Hz - 20 mJ

OVERLOAD PROTECTION LIMITING VALUE

With an adequate protection supply provided via the input pin, TOPFET can protect itself from two types of overload
- overtemperature and short circuit load.
SYMBOL PARAMETER REQUIRED CONDITION MIN. MAX. UNIT
V
DS
Drain source voltage
3
4 V ≤ VIS ≤ 5.5 V 0 35 V

THERMAL CHARACTERISTIC

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Thermal resistance
R
th j-mb
Junction to mounting base - - 2.5 3.1 K/W
1 Prior to the onset of overvoltage clamping. For voltages above this value, safe operation is limited by the overvoltage clamping energy. 2 A higher Tj is allowed as an overload condition but at the threshold T 3 All control logic and protection functions are disabled during conduction of the source drain diode.
the over temperature trip operates to protect the switch.
j(TO)
May 2001 2 Rev 1.000
Philips Semiconductors Product specification
PowerMOS transistor PIP3104-P Logic level TOPFET

OUTPUT CHARACTERISTICS

Limits are for -40˚C ≤ Tmb ≤ 150˚C; typicals are for Tmb = 25 ˚C unless otherwise specified
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
= 0 V
IS
V
(CL)DSS
Off-state V Drain-source clamping voltage ID = 10 mA 50 - - V
IDM = 1 A; tp ≤ 300 µs; δ ≤ 0.01 50 60 70 V
I
DSS
Drain source leakage current VDS = 40 V - - 100 µA
Tmb = 25 ˚C - 0.1 10 µA
On-state IDM = 3 A; tp ≤ 300 µs; δ ≤ 0.01
R
DS(ON)
Drain-source resistance VIS ≥ 4.4 V - - 190 mΩ
Tmb = 25 ˚C - 68 100 mΩ
VIS ≥ 4 V - - 200 mΩ
Tmb = 25 ˚C - 72 105 mΩ

OVERLOAD CHARACTERISTICS

-40˚C ≤ Tmb ≤ 150˚C unless otherwise specified.
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Short circuit load VDS = 13 V
I
P T
T
D
D(TO) DSC
j(TO)
Drain current limiting VIS = 5 V; Tmb = 25˚C 8 12 16 A
4.4 V ≤ VIS ≤ 5.5 V 6 - 18 A 4 V ≤ VIS ≤ 5.5 V 5 - 18 A
Overload protection VIS = 5 V; Tmb = 25˚C Overload power threshold device trips if PD > P
D(TO)
Characteristic time which determines trip time
1
20 55 80 W
200 350 600 µs
Overtemperature protection
Threshold junction 150 170 - ˚C temperature
2
1 Trip time t 2 This is independent of the dV/dt of input voltage VIS.
varies with overload dissipation PD according to the formula t
d sc
d sc
≈ T
/ ln[ PD / P
DSC
D(TO)
].
May 2001 3 Rev 1.000
Philips Semiconductors Product specification
PowerMOS transistor PIP3104-P Logic level TOPFET

INPUT CHARACTERISTICS

The supply for the logic and overload protection is taken from the input. Limits are for -40˚C ≤ T
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
≤ 150˚C; typicals are for Tmb = 25˚C unless otherwise specified
mb
V
IS(TO)
Input threshold voltage VDS = 5 V; ID = 1 mA 0.6 - 2.4 V
Tmb = 25˚C 1.1 1.6 2.1 V
I
IS
Input supply current normal operation; VIS = 5 V 100 220 400 µA
VIS = 4 V 80 195 330 µA
I
ISL
Input supply current protection latched; VIS = 5 V 200 400 650 µA
VIS = 3 V 130 250 430 µA V t
lr
V R
ISR
(CL)IS
IG
Protection reset voltage Latch reset time V Input clamping voltage II = 1.5 mA 5.5 - 8.5 V Input series resistance
1
2
reset time tr ≥ 100 µs 1.5 2 2.9 V
= 5 V, V
IS1
< 1 V 10 40 100 µs
IS2
Tmb = 25˚C- 33 - kΩ
to gate of power MOSFET

SWITCHING CHARACTERISTICS

Tmb = 25 ˚C; VDD = 13 V; resistive load RL = 4 Ω. Refer to waveform figure and test circuit.
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
t t t t
d on
r
d off
f
Turn-on delay time VIS = 5 V - 10 20 µs Rise time - 20 40 µs Turn-off delay time VIS = 0 V - 30 60 µs Fall time - 20 40 µs
1 The input voltage below which the overload protection circuits will be reset. 2 Not directly measureable from device terminals.
May 2001 4 Rev 1.000
Philips Semiconductors Product specification
PowerMOS transistor PIP3104-P Logic level TOPFET

MECHANICAL DATA

Plastic single-ended package; heatsink mounted; 1 mounting hole; 3-leads SOT78B
E
p
∅ p
1
A
A
1
q
D
1
D
L
1
b
1
L
L
123
(1)
b
e
e
DIMENSIONS (mm are the original dimensions)
(1)
b
A
4.5
4.1
A
1.39
1.27
1
UNIT
mm
Notes
1. The positional accuracy of the terminals is controlled within zone L1 max.
2. Mounting base configuration is not defined within the dimensions E and D
OUTLINE VERSION
SOT78B
b
1
0.85
1.3
0.60
1.0
IEC JEDEC EIAJ
0.7
0.4
c
D
15.8
15.2
REFERENCES
w M
0 5 10 mm
scale
E
D
1
6.4
10.3
5.9
9.7
mounting
base
(2)
2
Q
c
L
3.30
2.79
L
2
1
max.
3.0
p
∅ p
1
3.8
4.3
3.6
4.1
EUROPEAN
PROJECTION
qQ
3.0
2.6
2.7
2.2
ISSUE DATE
01-02-22
w
0.4
2.54
e
L
15.0
13.5
Fig.2. SOT78B (TO220AB) package1, pin 2 connected to mounting base.
1 Refer to mounting instructions for SOT78 (TO220) envelopes. Epoxy meets UL94 V0 at 1/8". Net mass: 2 g
May 2001 5 Rev 1.000
Philips Semiconductors Product specification
PowerMOS transistor PIP3104-P Logic level TOPFET

DEFINITIONS

DATA SHEET STATUS DATA SHEET PRODUCT DEFINITIONS
STATUS
Objective data Development This data sheet contains data from the objective specification for
Preliminary data Qualification This data sheet contains data from the preliminary specification.
Product data Production This data sheet contains data from the product specification. Philips
Limiting values
Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of this specification is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
Philips Electronics N.V. 2001
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, it is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights.
1
STATUS
2
product development. Philips Semiconductors reserves the right to change the specification in any manner without notice
Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in ordere to improve the design and supply the best possible product
Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Changes will be communicated according to the Customer Product/Process Change Notification (CPCN) procedure SNW-SQ-650A

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale.
1 Please consult the most recently issued datasheet before initiating or completing a design. 2 The product status of the device(s) described in this datasheet may have changed since this datasheet was published. The latest information is
May 2001 6 Rev 1.000
available on the Internet at URL http://www.semiconductors.philips.com.
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