NXP PF8101, PF8201 Product data sheet

1 Overview

2 Features

PF8101; PF8201

9-channel power management integrated circuit for high performance applications

Rev. 4 — 24 February 2021 Product data sheet

The PF8101/PF8201 is a power management integrated circuit (PMIC) designed for high performance i.MX 8 based applications. It features five high efficiency buck converters and three linear regulators for powering the processor, memory and miscellaneous peripherals.

Built-in one time programmable memory stores key startup configurations, drastically reducing external components typically used to set output voltage and sequence of external regulators. Regulator parameters are adjustable through high-speed I2C after start up offering flexibility for different system states.

• Up to five high efficiency buck converters

• Three linear regulators with load switch options

• RTC supply and coin cell charger

• Watchdog timer/monitor

• Monitoring circuit to fit ASIL B safety level

• One time programmable device configuration

• 3.4 MHz I2C communication interface

• 56-pin 8 x 8 QFN package

NXP Semiconductors

MCU

aaa- 029315

VDD_SNVS

VDD_DDRIO

VDD_MAIN

3.3 V I/O

(HV GPIO)

VDD_GPU

VDD_CPU(A35)

1.8 V I/O

(LV GPIO)

VDD_SCU

SDCARD0

2.5 V l/O

VIN:

2.7 V to

5.5 V

PF8101 / PF8201

VSNVS

BUCK7

BUCK6

BUCK5

BUCK2

BUCK1

LDO1

LDO2

LDO3

INTERFACING AND

I2C COMMUNICATIONS

Ethernet

eMMC SupplySIMCARD

SD Card

DRAM

CONTROL

SIGNALS

I2C

LPDDR

Memor y

MISCELLANEOUS

PERIPHERALS

9-channel power management integrated circuit for high performance applications

3 Simplified application diagram

PF8101; PF8201

Figure 1. Simplified application diagram

4 Ordering information

Table 1. Device options

PF8101 (automotive)

PF8201 (automotive)

PF8101 (industrial)

Table 2. Ordering information

Part number

MC33PF8101A0ES Automotive n/a Not programmed QM n/a

MC34PF8101A0EP Industrial n/a Not programmed QM n/a

MC33PF8201A0ES Automotive n/a Not programmed ASIL B n/a

[1] To order parts in tape and reel, add the R2 suffix to the part number.

Product data sheet Rev. 4 — 24 February 2021

[1]

Target market NXP processor System comments Safety grade OTP ID

PackageType

Name Description Version

HVQFN56

HVQFN56, plastic, thermally enhanced very thin quad; flat non-leaded package, wettable flanks; 56 terminals; 0.5 mm pitch; 8 mm x 8 mm x 0.85 mm body

HVQFN56, plastic, thermally enhanced very thin quad; flat non-leaded package, 56 terminals; 0.5 mm pitch; 8 mm x 8 mm x 0.85 mm body

SOT684-21 (DD/SC)

SOT684-21

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NXP Semiconductors

9-channel power management integrated circuit for high performance applications

5 Applications

• Automotive Infotainment

• High-end consumer and industrial

PF8101; PF8201

Product data sheet Rev. 4 — 24 February 2021

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NXP Semiconductors

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EPAD

LDO3

LDO30 UT

LDO2EN

VSELECT

LDO3IN

SW5FB SW7IN SW7LX

Digita l Signal(s)

Analog Referenc e(s)

20 MHz Cl ock/Deriva tive

100 kHz Cl ock/Deriva tive

LDO2

LDO12IN

LDO2OUT

LDO2 VMO N

LDO3 VMO N

AND

DRIVE R

SW7 MISC

REFEREN CE

SW7

VMON

LDO1

LDO1OUT

SYNCIN

SYNCOUT

AMUX

AGND

DGND

VIN

VSNVS

LICELL

V1P5D

VSNVS

VIN

OVLO

LDO1 VMO N

CLOCK MA NAGEMENT

(100 kHz / 20 MHz / PLL /

DIGITAL MO DULE)

24 CHAN NEL

ANALO G MUX

PMIC

INTERN AL

MONITO RS

PGOOD

MONITORS

SW1VMON

SW2VMO N

SW5VMO N

SW6VMON

SW7VMO N

LDO1VMON

LDO2V MON

LDO3V MON

EXTE RNAL

CHANN EL

INPUT

10 x DIE

TEMPER ATURE

MONITO RS

MANUA L TUNING

SPRE AD SPECTRUM

EXTER NAL CLOCK

SYNC

V1P5A

FSOBPGOOD

BG2

BG1

XFAILB

COIN CELL CHARG ER

V1P5D

LDO

V1P5A

LDO

REGUL ATION

BANDG AP

COMPAR ATOR

MONITOR ING

BANDG AP

FAIL SAFE CONTRO L

EWARN BINTBRESETB MCU

WATCHDOG

TIMER

DIGITAL CO RE

AND

STATE MACHINE

THERMA L MONITORING

/ SHUTD OWN

OTP MEMO RY

WD monito ring

XINTTBBENSTANDBYPWRONWDISCLVDDIO VDDOTPSDA

BG2

EPAD

SW5FB

SW5IN

SW5LX

AND

DRIVE R

REF

SELEC.

BG2

SW5

VMON

EPAD

SW6FB SW6IN SW6LX

AND

DRIVE R

VTT

REFEREN CE

SELECTOR

SW6

VMON

REF

SELEC.

SW6 DVS

AND MI SC

REFEREN CE

SW5 DVS

AND MISC

REFEREN CE

÷ 2

BG2

EPAD

SW2FB

SW2IN

SW2LX

AND

DRIVE R

REF

SELEC.

BG2

SW2

VMON

SW2 DVS

AND MISC

REFEREN CE

EPAD

SW1FB

SW1IN

SW1LX

AND

DRIVE R

REF

SELEC.

BG2

SW1

VMON

SW1 DVS

AND MISC

REFEREN CE

9-channel power management integrated circuit for high performance applications

6 Internal block diagram

PF8101; PF8201

Figure 2. Internal block diagram

Product data sheet Rev. 4 — 24 February 2021

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NXP Semiconductors

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PGOOD

V1P5A

V1P5D

XINTB

SW7FB

SW7IN

SW7LX

SW6IN

SW6LX

SW5LX

SW5IN

SW5FB

SW6FB

FSOB

LDO1OUT

VSELECT

LDO12IN

LDO2OUT

WDI

EWARN

RESETB MCU

PWRON

STANDBY

INTB

LDO3OUT

LDO3IN

DNC8

DNC9

DNC1

SW2FB

SW1FB

SW1IN

SW1LX

SW2LX

SW2IN

EPAD

DNC2

DNC3

DNC4

DNC5

DNC6

DNC7

TBBEN

9-channel power management integrated circuit for high performance applications

7 Pinning information

7.1 Pinning

PF8101; PF8201

7.2 Pin description

Figure 3. Pin configuration for HVQFN56

Table 3. HVQFN56 pin description

Pin number Symbol Application description Pin type Min. Max. Units

1 DNC1 Do not connect — — — V

2 SW2FB Buck 2 output voltage feedback I −0.3 6.0 V

3 SW1FB Buck 1 feedback input I −0.3 6.0 V

4 SW1IN Buck 1 input supply I −0.3 6.0 V

5 SW1LX

6 SW2LX

7 SW2IN Buck 2 input supply I −0.3 6.0 V

8 DNC2 Do not connect — — — V

9 DNC3 Do not connect — — — V

10 DNC4 Do not connect — — — V

11 DNC5 Do not connect — — — V

Product data sheet Rev. 4 — 24 February 2021

[1]

Buck 1 switching node O −0.3 6.0 V

[1]

Buck 2 switching node O −0.3 6.0 V

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NXP Semiconductors

PF8101; PF8201

9-channel power management integrated circuit for high performance applications

Pin number Symbol Application description Pin type Min. Max. Units

12 DNC6 Do not connect — — — V

13 DNC7 Do not connect — — — V

14 TBBEN Try Before Buy enable pin I −0.3 6.0 V

15 LDO1OUT LDO1 output O −0.3 6.0 V

16 VSELECT LDO2 voltage select input I −0.3 6.0 V

17 LDO12IN LDO1 and LDO2 input supply I −0.3 6.0 V

18 LDO2OUT LDO2 output O −0.3 6.0 V

19 WDI Watchdog Input from MCU I −0.3 6.0 V

20 EWARN Early warning to MCU O −0.3 6.0 V

21 RESETBMCU RESETBMCU open-drain output O −0.3 6.0 V

22 PWRON PWRON input I −0.3 6.0 V

23 STANDBY STANDBY input I −0.3 6.0 V

24 INTB INTB open-drain output O −0.3 6.0 V

25 LDO3OUT LDO3 output O −0.3 6.0 V

26 LDO3IN LDO3 input supply I −0.3 6.0 V

27 DNC8 Do not connect — — — V

28 DNC9 Do not connect — — — V

29 FSOB Safety output pin O −0.3 6.0 V

30 SW6FB Buck 6 output voltage feedback I −0.3 6.0 V

31 SW5FB Buck 5 output voltage feedback I −0.3 6.0 V

32 SW5IN Buck 5 input supply I −0.3 6.0 V

33 SW5LX

34 SW6LX

35 SW6IN Buck 6 input supply I -0.3 6.0 V

36 SW7LX

37 SW7IN Buck 7 input supply I −0.3 6.0 V

38 SW7FB Buck 7 output voltage feedback I −0.3 6.0 V

39 XINTB External interrupt input I −0.3 6.0 V

40 V1P5D 1.6 V digital core supply O −0.3 2.0 V

41 V1P5A 1.6 V analog core supply O −0.3 2.0 V

42 PGOOD PGOOD open-drain output O −0.3 6.0 V

43 LDO2EN LDO2 enable pin I −0.3 6.0 V

44 XFAILB External synchronization pin I/O -0.3 6.0 V

45 DGND Digital ground GND −0.3 0.3 V

46 LICELL Coin cell input I −0.3 5.5 V

47 VSNVS VSNVS regulator output O −0.3 6.0 V

48 SYNCIN External clock input pin for

49 SYNCOUT Clock out pin for external part

50 VIN Main input voltage to PMIC I −0.3 6.0 V

51 AGND Analog ground GND −0.3 0.3 V

[1]

Buck 5 switching node O −0.3 6.0 V

[1]

Buck 6 switching node O −0.3 6.0 V

[1]

Buck 7 switching node O −0.3 6.0 V

synchronization

I −0.3 6.0 V

O −0.3 6.0 V

Product data sheet Rev. 4 — 24 February 2021

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NXP Semiconductors

PF8101; PF8201

9-channel power management integrated circuit for high performance applications

Pin number Symbol Application description Pin type Min. Max. Units

52 AMUX Analog multiplexer output O −0.3 6.0 V

53 VDDOTP OTP selection input I −0.3 10 V

54 VDDIO I/O supply voltage. Connect to

voltage rail between 1.6 V and 3.3 V

55 SCL I2C clock signal I −0.3 6.0 V

56 SDA I2C data signal I/O −0.3 6.0 V

57 EPAD Exposed pad

Connect to ground

[1] Minimum voltage specification is given for DC voltage condition. While the regulator is switching, the LX pin may experience transient voltage spikes as

low as −3.0 V during the dead band time(<5 ns). The LX pins are tolerant to such transient spikes, however, it is responsibility of the hardware designer to follow proper layout design guidelines to minimize the impact of parasitic inductance in the power path of the switching regulator, thus keeping the magnitude of the negative voltage spike at the LX pin below 3.0 V.

I −0.3 6.0 V

GND −0.3 0.3 V

8 Absolute maximum ratings

Table 4. Absolute maximum ratings

Symbol Parameter Min Typ Max Unit

VIN Main input supply voltage

SWxVIN, LDOxVIN

VDDOTP OTP programming input supply voltage −0.3 — 10 V

VLICELL Coin cell voltage −0.3 — 5.5 V

Regulator input supply voltage

[1]

−0.3 — 6.0 V

[1]

−0.3 — 6.0 V

[1] Pin reliability may be affected if system voltages are above the maximum operating range of 5.5 V for extended periods of time. To minimize system

reliability impact, system must not operate above 5.5 V for more than 1800 sec over the lifetime of the device.

9 ESD ratings

Table 5. ESD ratings

All ESD specifications are compliant with AEC-Q100 specification.

Symbol Parameter Min Typ Max Unit

ESD

LATCHUP

[1] ESD testing is performed in accordance with the human body model (HBM) (CZAP = 100 pF, RZAP = 1500 Ω), and the charge device model (CDM),

robotic (CZAP = 4.0 pF)

Human Body Model

Charge Device Model

QFN package - all pins

Latch-up current — — 100 mA

[1]

— — 2000 V

[1]

—

500

10 Thermal characteristics

Table 6. Thermal characteristics

Symbol Parameter Min Typ Max Unit

Ambient operating temperature

Junction temperature −40 — 150 °C

Storage temperature range −55 — 150 °C

[1]

−40 — 105 °C

Product data sheet Rev. 4 — 24 February 2021

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NXP Semiconductors

PF8101; PF8201

9-channel power management integrated circuit for high performance applications

Symbol Parameter Min Typ Max Unit

PPRT

[1] All parameters are specified up to a junction temperature of 150 °C. All parameters are tested at TA from −40°C to 105 °C to allow headroom for self

heating during operation. If higher TA operation is required, proper thermal and loading consideration must be made to ensure device operation below the maximum TJ = 150 °C.

Table 7. QFN56 thermal resistance and package dissipation ratings

Symbol Parameter Min Max Unit

θJA

θJMA

θJB

θJC

ΨJT Junction to package (top)

Peak package reflow temperature — — 260 °C

Junction to Ambient Natural Convection

[1] [2]

— 81 °C/W

Single Layer Board (1s)

Junction to Ambient Natural Convection

[1] [2]

— 27 °C/W

Four Layer Board (2s2p)

Junction to Ambient Natural Convection

— 22 °C/W

Eight Layer Board (2s6p)

Junction to Ambient (@200ft/min)

[1] [3]

— 66 °C/W

Single Layer Board (1s)

Junction to Ambient (@200ft/min)

[1] [3]

— 22 °C/W

Four Layer Board (2s2p)

Junction to Board

Junction to Case (bottom)

[4]

— 11 °C/W

[5]

— 0.6 °C/W

[6]

— 1 °C/W

[1] Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient

temperature, air flow, power dissipation of other components on the board, and board thermal resistance. [2] Per JEDEC JESD51-2 with natural convection for horizontally oriented board. Board meets JESD51-9 specification for 1s or 2s2p board, respectively. [3] Per JEDEC JESD51-6 with forced convection for horizontally oriented board. Board meets JESD51-9 specification for 1s or 2s2p board, respectively. [4] Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface of the board

near the package. [5] Thermal resistance between the die and the solder pad on the bottom of the package. Interface resistance is ignored. [6] Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2.

When Greek letters are not available, the thermal characterization parameter is written as Psi-JT.

11 Operating conditions

Table 8. Operating conditions

Symbol Parameter Min Typ Max Unit

LICELL

Main input supply voltage UVDET — 5.5 V

LICELL input voltage range — — 4.2 V

12 General description

12.1 Features

The PF8101/PF8201 is a power management integrated circuit (PMIC) designed to be the primary power management building block for NXP high-end multimedia application processors from the i.MX 8 series. It is also capable of providing power solution to the high end i.MX 6 series as well as several non-NXP processors.

• Buck regulators – SW1, SW2, SW5, SW6: 0.4 V to 1.8 V; 2500 mA; up to 1.5 % accuracy

Product data sheet Rev. 4 — 24 February 2021

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NXP Semiconductors

9-channel power management integrated circuit for high performance applications

– SW7; 1.0 V to 4.1 V; 2500 mA; 2 % accuracy – Dynamic voltage scaling on SW1, SW2, SW5, SW6 – SW1, SW2 configurable as a dual phase regulator – SW5, SW6 configurable as a dual phase regulator – VTT termination mode on SW6 – Programmable current limit – Spread-spectrum and manual tuning of switching frequency

• LDO regulators – LDO1, 1.5 V to 5.0 V, 400 mA: 3 % accuracy with optional load switch mode – LDO2, 1.5 V to 5.0 V, 400 mA; 3 % accuracy with optional load switch mode and

– LDO3, 1.5 V to 5.0 V, 400 mA; 3 % accuracy with optional load switch mode

• RTC LDO/Switch supply from system supply or coin cell – RTC supply VSNVS 1.8 V/3.0 V/3.3 V, 10 mA – Battery backed memory including coin cell charger with programmable charge

• System features – Fast PMIC startup – Advanced state machine for seamless processor interface – High speed I2C interface support (up to 3.4 MHz) – PGOOD monitor – User programmable standby and off modes – Programmable soft start sequence and power down sequence – Programmable regulator configuration – 24 channel analog multiplexer for smart system monitoring/diagnostic

• OTP (One time programmable) memory for device configuration

• Monitoring circuit to fit ASIL B safety level – Independent voltage monitoring with programmable fault protection – Advance thermal monitoring and protection – External watchdog monitoring and programmable internal watchdog counter – I2C CRC and write protection mechanism – Analog built-in self-test (ABIST)

PF8101; PF8201

selectable hardware/software control

current and voltage

Product data sheet Rev. 4 — 24 February 2021

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NXP Semiconductors

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PF8101 / PF8201 FUNCTIONAL BLOCK DIAGR AM

LDO1

(1.5 V TO 5 V, 400 mA)

VSNVS (RTC SUPPLY)

(1.8 V/3.0 V/3.3 V, 10 mA)

LDO2

(1.5 V TO 5 V, 400 mA)

LOGIC AND CONTROL

I2C

WATCHDOG

MCU INTERFACE

REGUL ATOR CONTRO L

FAULT DETECTION

FUNCTIONAL SAFETY

(ABIST )

LDO3

(1.5 V TO 5 V, 400 mA)

24 CHANNEL AMUX

(DIAGNOSTICS)

OTP

(FLEXIBLE CONFIGUR ATION)

BUCK1 (MASTER /SL AVE)

(0.4 V TO 1.8 V, 2.5 A)

BUCK2 (MASTER /SLAVE)

(0.4 V TO 1.8 V, 2.5 A)

BUCK5 (MASTER/SLAVE)

(0.4 V TO 1.8 V, 2.5 A)

BUCK6 (MASTER/SLAVE)

(VT T/0.4 V TO 1.8 V, 2.5 A)

BUCK7 (INDEPENDENT)

(1.0 V TO 4.1 V, 2.5 A)

9-channel power management integrated circuit for high performance applications

12.2 Functional block diagram

PF8101; PF8201

Figure 4. Functional block diagram

12.3 Power tree summary

The following table shows a summary of the voltage regulators in the PF8101/PF8201.

Table 9. Voltage supply summary

Regulator Type Input supply Regulated output

SW1 Buck SW1IN 0.4 V to 1.8 V 6.25 2500

SW2 Buck SW2IN 0.4 V to 1.8 V 6.25 2500

SW5 Buck SW5IN 0.4 V to 1.8 V 6.25 2500

SW6 Buck SW6IN VTT/0.4 V to 1.8 V 6.25 2500

SW7 Buck SW7IN 1.0 V to 4.1 V — 2500

LDO1 Linear (P-type) LDO12IN 1.5 V to 5.0 V — 400

LDO2 Linear (P-type) LDO12IN 1.5 V to 5.0 V — 400

LDO3 Linear (P-type) LDO3IN 1.5 V to 5.0 V — 400

VSNVS LDO/Switch VIN/LICELL 1.8 V/3.0 V/3.3 V — 10

Product data sheet Rev. 4 — 24 February 2021

range (V)

VOUT programmable step (mV)

IRATED (mA)

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NXP Semiconductors

PF8101; PF8201

9-channel power management integrated circuit for high performance applications

12.4 Device differences

Table 10. Device differences

Description PF8201 PF8101 Bits not available on PF8101

During the self-test, the device checks:

• The high speed oscillator circuit is operating within

a maximum of 15 % tolerance

• A CRC is performed on the mirror registers during

the self-test routine to ensure the integrity of the registers before powering up

• ABIST test on all voltage monitors and toggling

signals

Fail-safe state: to lock down the system in case of critical failures cycling the PMIC on/off

ABIST on demand Available Not available AB_RUN

Active safe state: allow the FSOB to remain asserted as long as any of the non-safe conditions are present. Allow the system to be set in safe state via the FSOB pin.

Secure I2C write: I2C write procedure to modify registers dedicated to safety features (I2C CRC is still available)

Available Not available AB_SWx_OV

AB_SWx_UV AB_LDOx_OVAB_LDOx_UV STEST_NOK

Available Not available FS_CNT[3:0]

OTP_FS_BYPASS OTP_FS_MAX_CNT[3:0] OTP_FS_OK_TIMER[2:0]

Available Not available FSOB_ASS_NOK

OTP_FSOB_ASS_EN (always 0)

Available Not available I2C_SECURE_EN

OTP_I2C_SECURE _EN (always 0) RANDOM_GEN[7:0] RANDOM_CHK[7:0]

Product data sheet Rev. 4 — 24 February 2021

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NXP Semiconductors

aaa-029376

Fault

WD_Reset

Fault

POWER DOWN

Turn-Off

POWER DOWN

1. WD_FAIL_CNT = WD_MAX_CNT OR

2. PU_FAIL = True OR

3. FAULT_CNT = FAULT_MAX_CNT OR

4. Fault_Timer_Expired OR

5. Tj > TSD

1. PWRON = 0 OR

2. PWRON H to L && PWRON = 0 > TRESET OR

3. PMIC_OFF = 1 && 500us_Shutdown_timer_expired OR

4. VIN_OVLO_SDWN = 1 && VIN_OVLO detected

5. XFAILB H to L && 20us Sync time expired. (Only if OTP_XFAILB_EN = 1)

* Output is enabled/asserted if it is programmed to do so by the OTP configuration

Turn-off

Power Up

Sequence

Off Modes

Hard WD Reset

Event

System ON

Power up regulators

per OTP sequence

PU_FAIL = True

Power up

failure

BG_OK OTP_OK 20 MHz_OK

FS_CNT++ Regulators off VSNVS = On*

FSOB = LOW*

Fail self-test (ST_COUNT < 3)

FS_CNT = FS_MAX_CNT && OTP_FS_BYPASS = 0

1. FS_CNT < FS_MAX_CNT OR

2. OTP_FS_BYPASS = 1

Regulators off FSOB = LOW* VSNVS = On*

TRIM_NOK = 0

&& OTP_NOK = 0

&& STEST_NOK = 0

VIN > UVDET

V1P5D_POR V1P5A_POR

VIN < UVDET

CRITICAL FAILURE

WD_FAIL_CNT++

RESETBMCU = HIGH

Sys ON

Sequence

RUN

(

)

Standby

QPU_Off

LP_Off

Self-

Test

2 ms delay

OTP &

Trim Load

VSNVS On*

Fail-Safe

State

Fail-Safe

Transition

Power Down

POWER

PF8201 only

PF8101 only

9-channel power management integrated circuit for high performance applications

13 State machine

The PF8101/PF8201 features a state of the art state machine for seamless processor interface. The state machine handles the IC start up, provides fault monitoring and reporting, and protects the IC and the system during fault conditions.

PF8101; PF8201

Product data sheet Rev. 4 — 24 February 2021

Figure 5. State diagram

Table 11 lists the conditions for the different state machine transitions.

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NXP Semiconductors

PF8101; PF8201

9-channel power management integrated circuit for high performance applications

Table 11. State machine transition definition

Symbol Description Conditions

Transition A Standby to run

Transition B Run to standby

Transition C System on to WD reset 1. Hard WD Reset event

Transition D WD reset to system on 1. 30 µs delay passed && WD_EVENT_CNT < WD_MAX_CNT

Transition E WD reset to power down (fault) 1. WD_EVENT_CNT = WD_MAX_CNT

Transition J LP_Off to self-test (PF8201 only)

Transition K Self-test to QPU_Off (PF8201 only)

Transition F LP_Off to QPU_Off (PF8101 only)

1. STANDBY = 0 && STANDBYINV bit = 0

2. STANDBY = 1 && STANDBYINV bit = 1

1. STANDBY = 1 && STANDBYINV bit = 0

2. STANDBY = 0 && STANDBYINV bit = 1

Transitory off state: device pass through LP_Off to Self-Test to QPU_ Off (no power up event present)

1. LPM_OFF = 1 && TBBEN = Low

Power up event from LP_Off state

2. LPM_OFF = 0 && TBBEN = Low && (PWRON = 1 && OTP_PWRON_MODE = 0) && UVDET< VIN < VIN_OVLO (or VIN_OVLO disabled) && TJ < T && TRIM_NOK = 0 && OTP_NOK = 0

Power up event from LP_Off state

3. LPM_OFF = 0 && TBBEN = Low && (PWRON H to L && OTP_PWRON_MODE = 1 && UVDET < VIN < VIN_OVLO (or VIN_OVLO disabled) && TJ < T && TRIM_NOK = 0 && OTP_NOK = 0

Conditions: Transitory Off state to go into TBB Mode. Device pass through LP_Off to Self-Test to QPU_Off (no power up event present)

4. TBBEN = high (V1P5D)

1. Pass Self-Tests

2. TBBEN = high (V1P5D)

Transitory Off state: device pass through LP_Off to QPU_Off (no power up event present)

1. LPM_OFF = 1 && TBBEN = Low

Power up event from LP_Off state

2. LPM_OFF = 0 && TBBEN = Low && (PWRON = 1 && OTP_PWRON_MODE = 0) && UVDET< VIN < VIN_OVLO (or VIN_OVLO disabled) && TJ < T && TRIM_NOK = 0 && OTP_NOK = 0

Power up event from LP_Off state

3. LPM_OFF = 0 && TBBEN = Low && (PWRON H to L && OTP_PWRON_MODE = 1) && UVDET < VIN < VIN_OVLO (or VIN_OVLO disabled) && TJ < TSD && TRIM_NOK = 0 && OTP_NOK = 0

Transitory Off state: device pass through LP_Off to QPU_Off (no power up event present)

4. TBBEN = High (V1P5D)

Product data sheet Rev. 4 — 24 February 2021

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NXP Semiconductors

9-channel power management integrated circuit for high performance applications

Symbol Description Conditions

Transitory QPU_Off state, power on event occurs from LP_Off state, after self-test is passed, QPU_Off is just a transitory state until power up sequence starts.

1. LPM_OFF = 0 && TBBEN = Low && TRIM_NOK = 0 && OTP_NOK = 0 && STEST_NOK=0

Power up event from QPU_Off state

2. LPM_OFF = 1 && (PWRON = 1 && OTP_PWRON_MODE = 0) && UVDET < VIN < VIN_OVLO (or VIN_OVLO disabled && TJ < T && TRIM_NOK = 0 && OTP_NOK = 0 && STEST_NOK = 0

Power up event from QPU_Off state

3. LPM_OFF = 1 && (PWRON H to L && OTP_PWRON_MODE = 1) && UVDET < VIN < VIN_OVLO (or VIN_OVLO disabled) && TJ < T && TRIM_NOK = 0 && OTP_NOK = 0 && STEST_NOK = 0

Power up event from QPU_Off state

4. TBBEN = High && (PWRON = 1 && OTP_PWRON_MODE = 0) && UVDET < VIN < VIN_OVLO (or VIN_OVLO disabled

J < T

&& T

&& TRIM_NOK = 0 && OTP_NOK = 0 && STEST_NOK = 0

Transition L QPU_Off to power up

Power up event from QPU_Off state

5. TBBEN = High && (PWRON H to L && OTP_PWRON_MODE = 1) && UVDET < VIN < VIN_OVLO (or VIN_OVLO disabled) && TJ < T && TRIM_NOK = 0 && OTP_NOK = 0 && STEST_NOK = 0

Transitory QPU_Off state, Power on event occurs from LP_Off state, after self-test is passed, QPU_Off is just a transitory state until power up sequence starts

6. LPM_OFF = 0 && TBBEN = Low && TRIM_NOK = 0 && OTP_NOK = 0 && STEST_NOK = 0 && OTP_XFAILB_EN = 1 && XFAILB = HIGH

Power up event from QPU_Off state

7. LPM_OFF = 1 && (PWRON = 1 && OTP_PWRON_MODE = 0) && TJ < T && UVDET < VIN < VIN_OVLO (or VIN_OVLO disabled && TRIM_NOK = 0 && OTP_NOK = 0 && STEST_NOK = 0 && OTP_XFAILB_EN = 1 && XFAILB = HIGH

Power up event from QPU_Off state

8. LPM_OFF = 1 && (PWRON H to L && OTP_PWRON_MODE = 1) && TJ < T && UVDET < VIN < VIN_OVLO (or VIN_OVLO disabled) && TRIM_NOK = 0 && OTP_NOK = 0 && STEST_NOK = 0 && OTP_XFAILB_EN = 1 && XFAILB = HIGH

PF8101; PF8201

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9-channel power management integrated circuit for high performance applications

Symbol Description Conditions

Power up event from QPU_Off state during TBB mode

9. TBBEN =1 && (PWRON = 1 && OTP_PWRON_MODE = 0) && TJ < T && UVDET < VIN < VIN_OVLO (or VIN_OVLO disabled) && TRIM_NOK = 0 && OTP_NOK = 0 && STEST_NOK = 0 && OTP_XFAILB_EN = 1 && XFAILB = HIGH

Power up event from QPU_Off state during TBB mode

10. TBBEN = 1 && (PWRON H to L && OTP_PWRON_MODE = 1) && TJ < T && UVDET < VIN < VIN_OVLO (or VIN_OVLO disabled) && TRIM_NOK = 0 && OTP_NOK = 0 && STEST_NOK = 0 && OTP_XFAILB_EN = 1 && XFAILB = HIGH

Transition M Power up sequence to system on 1. RESETBMCU is released as part of the power up sequence

Requested turn off event

1. OTP_PWRON_MODE = 0 && PWRON = 0

Requested turn off event

2. OTP_PWRON_MODE = 1 && (PWRON H to L && PWRON = low for t > TRESET)

Requested turn off event

Transition N System on to power down (turn off)

Transition Z System on to power down (fault)

Transition O Power down (turn off) to LP_Off Requested turn off event moves directly to LP_Off

Transition Q Power up to power down (fault) Power up failure

Transition R Self-test to fail-safe transition 1. Self-tests fail 3 times

Transition S Power down (fault) to fail-safe transition Turn off event due to a fault condition moves to fail-safe transition

Transition U Fail-safe transition to LP_Off

Transition P Fail-safe transition to fail-safe state

(PF8201 only)

3. PMIC_OFF = 1 && 500µs_Shutdown_Timer_Expired

Protective turn off event (no PMIC fault)

4. VIN_OVLO_SDWN=1 && VIN_OVLO detected for longer than VIN_ OVLO_DBNC time

External turn off event (no PMIC fault)

5. OTP_XFAILB_EN = 1 && XFAILB → Low && 20 µs synchronization time is expired

Turn off event due to PMIC fault

1. Fault Timer expired

Turn off event due to PMIC fault

2. FAULT_CNT = FAULT_MAX_CNT

Turn off event due to PMIC fault

3. Thermal shutdown TJ > T

1. Power down sequences finished

1. Failure during power up sequence

&& TBBEN = low

1. Power down sequence is finished

1. FS_CNT < FS_MAX_CNT

2. OTP_FS_BYPASS = 1

1. FS_CNT = FS_MAX_CNT && OTP_FS_BYPASS = 0

13.1 States description

13.1.1 OTP/TRIM load

Upon VIN application V1P5D and V1P5A regulators are turned on automatically. Once the V1P5D and V1P5A cross their respective POR thresholds, the fuses (for trim and OTP) are loaded into the mirror registers and into the functional I2C registers if configured by the voltage on the VDDOTP pin.

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The fuse circuits have a CRC error check routine which reports and protects against register loading errors on the mirror registers. If a register loading error is detected, the corresponding TRIM_NOK or OTP_NOK flag is asserted. See Section 17 "OTP/TBB and

default configurations" for details on handling fuse load errors.

If no fuse load errors are present, VSNVS is configured as indicated in the OTP configuration bits, and the state machine moves to the LP_OFF state.

13.1.2 LP_Off state

The LP_Off state is a low power off mode selectable by the LPM_OFF bit during the system on modes. By default, the LPM_OFF = 0 when VIN crosses the UVDET threshold, therefore the state machine stops at the LP_Off state until a valid power up event is present. When LPM_OFF= 1, the state machine transitions automatically to the QPU_Off state if no power up event has been present and waits in the QPU_Off until a valid power up event is present.

The selection of the LPM_OFF bit is based on whether prioritizing low quiescent current (stay in LP_Off) or quick power up (move to QPU_Off state).

If a power up event is started in LP_Off state with LPM_OFF = 0 and a fuse loading error is detected, the PF8101/PF8201 ignores the power up event and remains in the LP_Off state to avoid any potential damage to the system.

PF8101; PF8201

To be in LP_Off state, it is necessary to have VIN present. If a valid LICELL is present, but VIN is below the UVDET, the PF8101/PF8201 enters the coin cell state.

13.1.3 Self-test routine (PF8201 only)

When device transitions from the LP_Off state, it turns on all necessary internal circuits as it moves into the self-test routine and performs a self-check routine to verify the integrity of the internal circuits.

During the self-test routine the following blocks are verified:

• The high speed clock circuit is operating within a maximum of 15 % tolerance

• The output of the voltage generation bandgap and the monitoring bandgap are not

more than 4 % to 12 % apart from each other

• A CRC is performed on the mirror registers during the self-test routine, to ensure the integrity of the registers before powering up

• ABIST test on all voltage monitors.

To allow for varying settling times for the internal bandgap and clocks, the self-test block is executed up to 3 times (with 2.0 ms between each test) if a failure is encountered, the state machine proceeds to the fail-safe transition.

A failure in the ABIST test is not interpreted as a self-test failure and it only sets the corresponding ABIST flag for system information. The MCU is responsible for reading the information and deciding whether it can continue with a safe operation. See Section 18.1

"System safety strategy" for more information about the functional safety strategy of

PF8201.

Upon a successful self-test, the state machine proceeds to the QPU_Off state.

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13.1.4 QPU_Off state

The QPU_Off state is a higher power consumption off mode, in which all internal circuitry required for a power on is biased and ready to start a power up sequence.

If LPM_OFF = 1 and no turn on event is present, the device stops at the QPU_Off state, and waits until a valid turn on event is present.

In this state, if VDDIO supply is provided externally, the device is able to communicate through I2C to access and modify the mirror registers in order to operate the device in TBB mode or to program the OTP registers as described in Section 17 "OTP/TBB and

default configurations".

By default, the coin cell charger is disabled during the QPU_Off state when VIN crosses the UVDET threshold, but it may be turned on or off in this state once it is programmed by COINCHG_OFF during the system-on states.

If a power up event is started and any of the TRIM_NOK, OTP_NOK or STEST_NOK flags are asserted, the device ignores the power up event and remains in the QPU_Off state. See Section 17 "OTP/TBB and default configurations" for more details on debugging a fuse loading failure.

Upon a power up event, the default configuration from OTP or hardwire is loaded into their corresponding I2C functional register in the transition from QPU_Off to power up state.

PF8101; PF8201

13.1.5 Power up sequence

During the power up sequence, the external regulators are turned on in a predefined order as programmed by the default (OTP or hardwire) sequence.

If PGOOD is used as a GPO, it can also be set high as part of the power up sequence in order to allow sequencing of any external supply/device controlled by the PGOOD pin.

The RESETBMCU is also programmed as part of the power up sequence, and it is used as the condition to enter system-on states. The RESETBMCU may be released in the middle of the power up sequence, in this case, the remaining supplies in the power up continues to power up as the device is in the run state. See Section 14.5.2 "Power up

sequencing" for details.

13.1.6 System-on states

During the system-on states, the MCU is powered and out of reset and the system is fully operational.

The system on is a virtual state composed by two modes of operations:

• Run state

• Standby state

Register to control the regulators output voltage, regulator enable, interrupt masks, and other miscellaneous functions can be written to or read from the functional I2C register map during the system-on states.

13.1.6.1 Run state

If the power up state is successfully completed, the state machine transitions to the run state. In this state, RESETBMCU is released high, and the MCU is expected to boot up and set up specific registers on the PMIC as required during the system boot up process.

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The run mode is intended to be used as the normal mode of operation for the system.

Each regulator has specific registers to control its output voltage, operation mode and/or enable/disable state during the run state.

By default, the VSWx_RUN[7:0] / VLDOx_RUN[3:0] registers are loaded with the data stored in the OTP_VSWx[7:0] or OTP_VLDOx[3:0] bits respectively.

SW7 uses only one global register to configure the output voltage during run or standby mode. Upon power up the VSW7[4:0] bits are loaded with the values of the OTP_VSW7[4:0].

Upon power up, if the switching regulator is part of the power up sequence, the SWx_RUN_MODE[1:0] bits will be loaded as needed by the system:

• When OTP_SYNCIN_EN = 1, default SWx_RUN_MODE at power up is always set to PWM (0b01)

• When OTP_SYNCOUT_EN = 1, default SWx_RUN_MODE at power up is always set to PWM (0b01)

• When OTP_FSS_EN = 1, default SWx_RUN_MODE at power up shall always set to PWM (0b01)

• If none of the above conditions are met, the default value of the SWx_RUN_MODE bits at power up will be set by the OTP_SW_MODE bits.

PF8101; PF8201

When OTP_SW_MODE = 0, the default value of the SWx_RUN_MODE bits are set to 0b11 (autoskip).

When OTP_SW_MODE = 1, the default value of the SWx_RUN_MODE bits are set to 0b01 (PWM).

If the switching regulator is not part of the power up sequence, the SWx_RUN_MODE[1:0] bits are loaded with 0b00 (OFF mode).

Likewise, if the LDO is part of the power up sequence, the LDOx_RUN_EN bit is set to 1 (enabled) by default. If the LDO is not selected as part of the power up sequence, the LDOx_RUN_EN bit is set to 0 (disabled) by default.

In a typical system, each time the processor boots up (PMIC transitions from off mode to run state), all output voltage configurations are reset to the default OTP configuration, and the MCU should configure the PMIC to its desired usage in the application.

13.1.6.2 Standby state

The standby state is intended to be used as a low power (state retention) mode of operation. In this state, the voltage regulators can be preset to a specific low power configuration in order to reduce the power consumption during system’s sleep or state retention modes of operations.

The standby state is entered when the STANDBY pin is pulled high or low as defined by the STANBYINV bit. The STANDBY pin is pulled high/low by the MCU to enter/exit system low power mode. See Section 14.9.2 "STANDBY" for detailed configuration of the STANDBY pin.

Each regulator has specific registers to control its output voltage, operation mode and/or enable/disable state during the standby state.

By default, the VSWx_STBY[7:0] / VLDOx_STBY[3:0] registers are loaded with the data stored in the OTP_VSWx[7:0] or OTP_VLDOx[3:0] bits respectively.

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Upon power up, if the switching regulator is part of the power up sequence, the SWx_STBY_MODE[1:0] bits will be loaded as needed by the system:

• When OTP_SYNCIN_EN = 1, default SWx_STBY_MODE at power up is always set to PWM (0b01)

• When OTP_SYNCOUT_EN = 1, default SWx_STBY_MODE at power up is always set to PWM (0b01)

• When OTP_FSS_EN = 1, default SWx_STBY_MODE at power up shall always set to PWM (0b01)

• If none of the conditions above are met, the default value of the SWx_STBY_MODE bits at power up will be set by the OTP_SW_MODE bits.

When OTP_SW_MODE = 0, the default value of the SWx_STBY_MODE bits are set to 0b11 (autoskip).

When OTP_SW_MODE = 1, the default value of the SWx_STBY_MODE bits are set to 0b01 (PWM).

If the switching regulator is not part of the power up sequence, the SWx_STBY_MODE[1:0] bits are loaded with 0b00 (OFF mode).

PF8101; PF8201

Upon power up, the standby registers are loaded with the same default OTP values as the run mode. The MCU is expected to program the desired standby values during boot up.

If any of the external regulators are disabled in the standby state, the power down sequencer is engaged as described in Section 14.6.2 "Power down sequencing".

13.1.7 WD_Reset

When a hard watchdog reset is present, the state machine increments the WD_EVENT_CNT[3:0] register and compares against the WD_MAX_CNT[3:0] register. If WD_EVENT_CNT[3:0] = WD_MAX_CNT[3:0], the state machine detects a cyclic watchdog failure, it powers down the external regulators and proceeds to the fail-safe transition.

If WD_EVENT_CNT[3:0] < WD_MAX_CNT[3:0], the state machine performs a hard WD reset.

A hard WD reset can be generated from either a transition in the WDI pin or a WD event initiated by the internal watchdog counter as described in Section 15.11.2 "Watchdog

reset behaviors".

13.1.8 Power down state

During power down state, all regulators except VSNVS are disabled as configured in the power down sequence. The power down sequence is programmable as defined in

Section 14.6.2 "Power down sequencing".

Two types of events may lead to the power down sequence:

• Non faulty turn off events: move directly into LP_Off state as soon as power down sequence is finalized

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• Turn off events due to a PMIC fault: move to the fail-safe transition as soon as the

power down sequence is finalized

13.1.9 Fail-safe transition

The fail-safe transition is entered if the PF8101/PF8201 initiates a turn off event due to a PMIC fault.

If the fail-safe transition is entered, the PF8101/PF8201 provides four FAIL bits to indicate the source of the failure:

• The PU_FAIL is set to 1 when the device shuts down due to a power up failure

• The WD_FAIL is set to 1 when the device shuts down due to a watchdog event counter

max out

• The REG_FAIL is set to 1 when the device shuts down due to a regulator failure (fault counter maxed out or fault timer expired)

• The TSD_FAIL is set to 1 when the device shuts down due to a thermal shutdown

The value of the FAIL bits is retained as long as VIN > UVDET.

The MCU can read the FAIL bits during the system-on states in order to obtain information about the previous failure and can clear them by writing a 1 to them, provided the state machine is able to power up successfully after such failure.

PF8101; PF8201

In PF8201, when the state machine enters the fail-safe transition, a fail-safe counter is compared and increased, if the FS_CNT[3:0] reaches the maximum count, the device can be programmed to move directly to the fail-safe state to prevent a cyclic failure from happening.

13.1.10 Fail-safe state (PF8201 only)

The fail-safe state works as a safety lock-down upon a critical device/system failure. It is reached when the FS_CNT [3:0] = FS_MAX_CNT [3:0].

A bit is provided to enable or disable the device to enter the fail-safe state upon a cyclic failure. When the OTP_FS_BYPASS = 1, the fail-safe bypass operation is enabled and the device always move to the LP_Off state, regardless of the value of the FS_CNT[3:0]. If the OTP_FS_BYPASS = 0, the fail-safe bypass is disabled, and the device moves to the fail-safe state when the proper condition is met.

The maximum number of times the device can pass through the fail-safe transition continuously prior to moving to a fail state is programmed by the OTP_FS_MAX_CNT[3:0] bits. If the FS_MAX_CNT[3:0] = 0x00, the device moves into the fail-safe state as soon as it fails for the very first time.

If the FSOB pin is programmed to assert upon a specific fault, the FSOB pin remains asserted low during the fail-safe state if the corresponding fault is present when PF8201 reaches the fail-safe state.

The device can exit the fail-safe state only after a power cycle (VIN crossing UVDET) event is present.

To avoid reaching the fail-safe state due to isolated fail-safe transition events, the FS_CNT [3:0] is gradually decreased based on a fail-safe OK timer. The OTP_FS_OK_TIME[2:0] bits select the default time configuration for the fail-safe OK timer between 1 to 60 min.

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Table 12. Fail-safe OK timer configuration

OTP_FS_OK_TIME[2:0] FS_CNT decrease period (min)

000 1

001 5

010 10

011 15

100 20

101 30

110 45

111 60

When the fail-safe OK timer reaches the configured time during the system-on states, the state machine decreases the FS_CNT[3:0] bits by one and starts a new count until the FS_CNT[3:0] is 0x00. The FS_CNT[3:0] may be manually cleared during the system on state if the system wants to control this counter manually.

13.1.11 Coin cell state

PF8101; PF8201

When VIN is not present and LICELL pin has a valid voltage, the device is placed into a coin cell state. In such state, only VSNVS remains on (if programmed to do so by the OTP_VSNVSVOTL[1:0] bits) and is expected to provide power to the SNVS domain on the MCU as long as the LICELL pin has a valid input suitable to supply the configured VSNVS output voltage.

14 General device operation

14.1 UVDET

UVDET works as the main operation threshold for the PF8101/PF8201. Crossing UVDET on the rising edge is a mandatory condition for OTP fuses to be loaded into the mirror registers and allows the main PF8101/PF8201 operation.

If VIN is below the UVDET threshold, the device remains in an unpowered state if no valid LICELL is present, or in the LICELL mode if a valid LICELL voltage is present. A 200 mV hysteresis is implemented on the UVDET comparator to set the falling threshold.

Table 13. UVDET threshold

Symbol Parameter Min Typ Max Unit

UVDET Rising UVDET 2.7 2.8 2.9 V

UVDET Falling UVDET 2.5 2.6 2.7 V

14.2 VIN OVLO condition

The VIN_OVLO circuit monitors the main input supply of the PF8101/PF8201. When this block is enabled, the PF8101/PF8201 monitors its input voltage and can be programmed to react to an overvoltage in two ways:

• When the VIN_OVLO_SDWN = 0, the VIN_OVLO event triggers an OVLO interrupt but does not turn off the device

• When the VIN_OVLO_SDWN = 1, the VIN_OVLO event initiates a power down sequence

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When the VIN_OVLO_EN = 0, the OVLO monitor is disabled and when the VIN_OVLO_EN = 1, the OVLO monitor is enabled. The default configuration of the VIN_OVLO_EN bit is set by the OTP_VIN_OVLO_EN bit in OTP. Likewise, the default value of the VIN_OVLO_SDWN bit is set by the OTP_VIN_OVLO_SDWN upon power up.

During a power up transition, if the OTP_VIN_OVLO_SDWN = 0 the device allows the external regulators to come up and the PF8101/PF8201 announces the VIN_OVLO condition through an interrupt. If the OTP_VIN_OVLO_SDWN = 1, the device stops the power up sequence and returns to the corresponding off mode.

Debounce on the VIN_OVLO comparator is programmable to 10 µs, 100 µs or 1.0 ms, by the VIN_OVLO_DBNC[1:0] bits. The default value for the VIN_OVLO debounce is set by the OTP_VIN_OVLO_DBNC[1:0] bits upon power up.

Table 14. VIN_OVLO debounce configuration

VIN_OVLO_DBNC[1:0] VIN OVLO debounce value (µs)

00 10

01 100

10 1000

11 Reserved

PF8101; PF8201

Table 15. VIN_OVLO specifications

Symbol Parameter Min Typ Max Unit

VIN_OVLO VIN overvoltage lockout rising

VIN_OVLO_HYS VIN overvoltage lockout hysteresis

[1] Operating the device above the maximum VIN = 5.5 V for extended periods of time may degrade and cause permanent

damage to the device.

14.3 IC startup timing with PWRON pulled up

The PF8101/PF8201 features a fast internal core power up sequence to fulfill system power up timings of 5.0 ms or less, from power application until MCU is out of reset. Such requirement needs a maximum ramp up time of 1.5 ms for VIN to cross the UVDET threshold in the rising edge.

A maximum core biasing time of 1.5 ms from VIN crossing to UVDET until the beginning of the power up sequence is ensured to allow up to 1.5 ms time frame for the voltage regulators power up sequence.

Timing for the external regulators to start up is programmed by default in the OTP fuses.

The 5.0 ms power up timing requirement is only applicable when the PWRON pin operates in level sensitive mode OTP_PWRON_MODE = 0, however turn on timing is expected to be the same for both level or edge sensitive modes after the power on event is present.

In applications using the VSNVS regulator, if VSNVS is required to reach regulation before system regulators come up, the system should use the SEQ[7:0] bits to delay the system regulators to allow enough time for VSNVS to reach regulation before the power up sequence is started.

[1]

5.55 5.8 6.0 V

[1]

— — 200 mV

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aaa-028052

reg2reset

first

Self Test

RESETBMCU

Regulator Outputs

(enable signals)

STEST done

(internal signal)

PWRON

VSNVS

V1P5D

UVDET

VIN

Fuse Load

1.6 V

stest_done

Final VSNVS Regulation

vin_rise

9-channel power management integrated circuit for high performance applications

PF8101; PF8201

Figure 6. Startup with PWRON pulled up

Table 16. Startup timing requirements (PWRON pulled up)

Symbol Parameter Min Typ Max Unit

vin_rise

Rise time of VIN from VPWR application to

10 — 1500 µs

UVDET (system dependent)

stest_done

Time from VIN crossing UVDET to STEST_

— — 1.4 ms done going high (self-test performed and passed)

first

Time from STEST_done to first slot of power up

— — 100 µs sequence

reg2reset

[1] External regulators power up sequence time (t

time to ensure power up within 5.0 ms.

Time from first regulator enabled to RESETBMCU asserted to guarantee 5.0 ms PMIC boot up

14.4 IC startup timing with PWRON pulled low during VIN application

It is possible that PWRON is held low when VIN is applied. By default, LPM_OFF bit is

) is programmed by OTP and may be longer than 1.5 ms. However, 1.5 ms is the maximum allowed

reg2reset

[1]

— — 1.5 ms

reset to 0 upon crossing UVDET, therefore the PF8101/PF8201 remains in the LP_Off state as described in Section 13.1.2 "LP_Off state". In this scenario, quiescent current in the LP_Off state is kept to a minimum. When PWRON goes high with LPM_OFF = 0, the PMIC startup is expected to take longer, since it has to enable most of the internal circuits and perform the self-test before starting a power up sequence.

Figure 7 shows startup timing with LPM_OFF = 0.

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reg2reset

LP_OFF State

first

pwrup_lpm

Self-Test

RESETBMCU

Regulator Outputs

Fuse load done (internal signal)

STEST done

(internal signal)

PWRON

VSNVS

V1P5D

UVDET

VIN

Fuse Load

fuseLoad

1.6 V

Final Regulation

vin_rise

9-channel power management integrated circuit for high performance applications

PF8101; PF8201

Figure 7. Startup with PWRON driven high externally and bit LPM_OFF = 0

Table 17. Startup with PWRON driven high externally and LPM_OFF = 0

Symbol Parameter Min Typ Max Unit

vin_rise

Rise time of VIN from VPWR application to

10 — 1500 µs UVDET (system dependent)

fuseload

pwrup_lpm

first

reg2reset

Time from VIN crossing UVDET to Fuse_Load_ done (fuse loaded correctly)

Time from PWRON going high to the STEST_ done (self-test performed and passed)

Time from STEST_done to first slot of power up sequence

Time from first regulator enabled to

— — 600 µs

— — 700 µs

— — 100 µs

[1]

— — 1.5 ms RESETBMCU asserted to guarantee 5.0 ms PMIC boot up

[1] External regulators power up sequence time (t

) is programmed by OTP and may be longer than 1.5 ms.

reg2reset

14.5 Power up

14.5.1 Power up events

Upon a power cycle (VIN > UVDET), the LPM_OFF bit is reset to 0, therefore the device moves to the LP_Off state by default. The actual value of the LPM_OFF bit can be changed during the run mode and is maintained until VIN crosses the UVDET threshold.

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In either one of the off modes, the PF8101/PF8201 can be enabled by the following power up events:

1. When OTP_PWRON_MODE = 0, PWRON pin is pulled high.

2. When OTP_PWRON_MODE = 1, PWRON pin experiences a high to low transition

A power up event is valid only if:

• VIN > UVDET

• VIN < VIN_OVLO (unless the OVLO is disabled or OTP_VIN_OVLO_SDWN = 0)

• Tj < thermal shutdown threshold

• TRIM_NOK = 0 && OTP_NOK = 0 && STEST_NOK = 0

14.5.2 Power up sequencing

The power up sequencer controls the time and order in which the voltage regulators and other controlling I/O are enabled when going from the off mode into the run state.

The OTP_SEQ_TBASE[1:0] bits set the default time base for the power up and power down sequencer.

PF8101; PF8201

and remains low for as long as the PWRON_DBNC timer.

The SEQ_TBASE[1:0] bits can be modified during the system-on states in order to change the sequencer timing during run/standby transitions as well as the power down sequence.

Table 18. Power up time base register

OTP bits OTP_SEQ_TBASE[1:0]

00 00 30

01 01 120

10 10 250

11 11 500

Functional bits SEQ_TBASE[1:0]

Sequencer time base (µs)

The power up sequence may include any of the following:

• Switching regulators

• LDO Regulators

• PGOOD pin if programmed as a GPO

• RESETBMCU

The default sequence slot for each one of these signals is programmed via the OTP configuration registers. And they can be modified in the functional I2C register map to change the order in which the sequencer behaves during the run/standby transitions as well as the power down sequence.

The _SEQ[7:0] bits set the regulator/pin sequence from 0 to 254. Sequence code 0x00 indicates that the particular output is not part of the startup sequence and remains in off (in case of a regulator) or remains low/disabled (in case of PGOOD pin used as a GPO).

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System On

End of

PWRUP

End of

PWRDN

Power down Seq.

Run to Off

Power up Seq.

Off to Run

INTB

LDO2

SW2

SW5

LDO1

SW1

RESETBMCU

Start of

PWRDN

9-channel power management integrated circuit for high performance applications

Table 19. Power up sequence registers

OTP bits OTP_SWx_SEQ[7:0]/ OTP_LDOx_SEQ[7:0]/ OTP_PGOOD_SEQ[7:0]/ OTP_RESETBMCU_SEQ[7:0]

00000000 00000000 Off Off

00000001 00000001 0 SLOT0

00000010 00000010 1 SEQ_TBASE x SLOT1

. . .

11111111 11111111 254 SEQ_TBASE x SLOT254

If RESETBMCU is not programmed in the OTP sequence, it will be enabled by default after the last regulator programmed in the power up sequence.

When the _SEQ[7:0] bits of all regulators and PGOOD used as a GPIO are set to 0x00 (off) and a power on event is present, the device moves to the run state in slave mode. In this mode, the device is enabled without any voltage regulator or GPO enabled. If the RESETBMCU is not programed in a power up sequence slot, it is released when the device enters the run state.

Functional bits SWx_SEQ[7:0]/ LDOx_SEQ[7:0]/ PGOOD_SEQ[7:0]/ RESETBMCU_SEQ[7:0]

. . .

PF8101; PF8201

Sequence slot Startup time

. . .

(µs)

(right after PWRON event is valid)

. . .

The slave mode is a special case of the power up sequence to address the scenario where the PF8101/PF8201 is working as a slave PMIC, and supplies are meant to be enabled by the MCU during the system operation. In this scenario, if RESETBMCU is used, it is connected to the master RESETBMCU pin.

The PWRUP_I interrupt bit is asserted at the end of the power up sequence when the time slot of the last regulator in the sequence has ended.

Figure 8 provides an example of the power up/down sequence coming from the off

modes.

Figure 8. Power up/down sequence between off and system-on states

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PWRUP_lPWRDN_l

Run

Mode

STBY Mode

PWRDN Sequence

from Run to STBY

PWRUP Sequence

from STBY to Run

INTB

RESETBMCU

LDO2

SW5

SW2

SW1

LDO1

9-channel power management integrated circuit for high performance applications

When transitioning from standby mode to run mode, the power up sequencer is activated only if any of the external regulators is re-enabled during this transition. If none of the regulators toggle from off to on and only voltage changes are being performed when entering or exiting standby mode, the changes for the voltage regulators are made simultaneously rather than going through the power up sequencer.

Figure 9 shows an example of the power up/down sequence when transitioning between

run and standby modes.

PF8101; PF8201

Figure 9. Power up/down sequence between run and standby

The PWRUP_I interrupt is set while transitioning from standby to run, even if the sequencer is not used. This is used to indicate that the transition is complete and device is ready to perform proper operation.

14.6 Power down

14.6.1 Turn off events

Turn off events may be requested by the MCU (non-PMIC fault related) or due to a critical failure of the PMIC (hard fault condition).

The following are considered non-PMIC failure turn off events:

1. When OTP_PWRON_MODE = 0, the device starts a power down sequence when the PWRON pin is pulled low.

2. When OTP_PWRON_MODE = 1, the device starts a power down sequence when the PWRON pin sees a transition from high to low and remains low for longer than TRESET.

3. When bit PMIC_OFF is set to 1, the device starts a 500 µs shutdown timer. When the shutdown timer is started, the PF8101/PF8201 sets the SDWN_I interrupt and asserts the INTB pin provided it is not masked. At this point, the MCU can read the interrupt and decide whether to continue with the turn off event or stop it in case it was sent by mistake. If the SDWN_I bit is cleared before the 500 µs shutdown timer is expired, the shutdown request is cancelled and the shutdown timer is reset; otherwise, if the shutdown timer is expired, the PF8101/PF8201 starts a power down sequence.

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The PMIC_OFF bit self-clears after SDWN_I flag is cleared.

4. When VIN_OVLO_EN = 1 and VIN_OVLO_SDWN = 1, and a VIN_OVLO event is present.

Turn off events due to a hard fault condition:

1. If an OV, UV or ILIM condition is present long enough for the fault timer to expire.

2. In the event that an OV, UV or ILIM condition appears and clears cyclically, and the FAULT_CNT[3:0] = FAULT_MAX_CNT[3:0].

3. If the watchdog fail counter is overflown, that is WD_EVENT_CNT = WD_MAX_CNT.

4. When Tj crosses the thermal shutdown threshold as the temperature rises.

When the PF8101/PF8201 experience a turn off event due to a hard fault condition, the devices pass through the fail-safe transition after regulators have been powered down.

14.6.2 Power down sequencing

During a power down sequence, output voltage regulators can be turned off in two different modes as defined by the PWRDWN_MODE bit.

1. When PWRDWN_MODE = 0, the regulators power down in sequential mode.

2. When PWRDWN_MODE = 1, the regulators power down by groups.

PF8101; PF8201

During transition from run to standby, the power down sequencer is activated in the corresponding mode. If any of the external regulators are turned off in the standby configuration. If external regulators are not turned off during this transition, the power down sequencer is bypassed and the transition happens at once (any associated DVS transitions could still take time).

The PWRDN_I interrupt is set at the end of the transition from run to standby when the last regulator has reached its final state, even if external regulators are not turned off during this transition.

14.6.2.1 Sequential power down

When the device is set to the sequential power down, it uses the same _SEQ[7:0] registers as the power up sequence to power down in reverse order.

All regulators with the _SEQ[7:0] bits set to 0x00, power down immediately and the remaining regulators power down one OTP_SEQ_TBASE[1:0] delay after, in reverse order as defined in the _SEQ[7:0] bits.

If PGOOD pin is used as a GPO, it is de-asserted as part of the power down sequence as indicated by the PGOOD_SEQ[7:0] bits.

If the MCU requires a different power down sequence, it can change the values of the SEQ_TBASE[1:0] and the _SEQ[7:0] bits during the system-on states.

When the state machine pass through any of the off modes, the contents of the SEQ_TBASE[1:0] and _SEQ[7:0] bits are reloaded with the corresponding mirror register (OTP) values before it starts the next power up sequence.

14.6.2.2 Group power down

When the device is configured to power down in groups, the regulators are assigned to a specific power down group. All regulators assigned to the same group are disabled at the same time when the corresponding group is due to be disabled.

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Power down groups shut down in decreasing order starting from the lowest hierarchy group with a regulator shutting down (for instance, Group 4 being the lowest hierarchy and Group 1 the highest hierarchy group). If no regulators are set to the lowest hierarchy group, the power down sequence timer starts off the next available group that contains a regulator to power down.

Each regulator has its own _PDGRP[1:0] bits to set the power down group it belongs to as shown in Table 20.

Table 20. Power down regulator group bits

OTP_SWx_PDGRP[1:0] OTP_LDOx_PDGRP[1:0] OTP_PGOOD_PDGRP[1:0] OTP_RESETBMCU_PDGRP[1:0]

00 00 Regulator belongs to Group 4

01 01 Regulator belongs to Group 3

10 10 Regulator belongs to Group 2

11 11 Regulator belongs to Group 1

If PGOOD pin is used as a GPO, the PGOOD_PDGRP[1:0] is used to turn off the PGOOD pin in a specific group during the power down sequence. If PGOOD pin is used in power good mode, it is recommended that the OTP_PGOOD_PDGRP bits are set to 11 to ensure the group power down sequencer does not detect these bits as part of Group 4.

SWx_PDGRP[1:0] LDOx_PDGRP[1:0] PGOOD_PDGRP[1:0] RESETBMCU_PDGRP[1:0]

PF8101; PF8201

Description

Each one of power down groups have programmable time delay registers to set the time delay after the regulators in this group have been turned off, and the next group can start to power down.

Table 21. Power down counter delay

OTP bits OTP_GRPx_DLY[1:0]

00 00 120

01 01 250

10 10 500

11 11 1000

Functional bits GRPx_DLY[1:0]

Power down delay (µs)

If RESETBMCU is required to be asserted first before any of the external regulators from the corresponding group, the RESETBMCU_DLY provides a selectable delay to disable the regulators after RESETBMCU is asserted.

Table 22. Programmable delay after RESETBMCU is asserted

OTP bits OTP_RESETBMCU_DLY[1:0]

00 00 No delay

01 01 10

10 10 100

11 11 500

Functional bits RESETBMCU_DLY[1:0]

RESETBMCU delay (µs)

If RESETBMCU_DLY is set to 0x00, all regulators in the same power down group as RESETBMCU is disabled at the same time RESETBMCU is asserted.

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120 µs

GRP3 _DLY

120 µs

GRP2_DLY

120 µs

GRP1_DLY

PWRDN EVENT

GRP3 SDWN

RESETB MCU

asser ted

GRP1 SDW N

SUPPLIES

End of Power

Down

GRP2 SDWN

10 µs

PWRON

PDWN_GRP1

GPR1_DLY = 120 µs

SW1

LDO1

RESETB MCU_ DLY = 10 µS

PDWN_GRP2

GPR2 _DLY = 120 µs

SW2 SW5 SW6

PDWN_GRP3

GPR3_ DLY = 120 µs

LDO2 LDO3

PDWN_GRP4

LDO2

LDO3

SW2

SW5

SW6

RESETB MCU

SW1

LDO1

9-channel power management integrated circuit for high performance applications

Figure 10 shows an example of the power down sequence when PWRDWN_MODE = 1.

PF8101; PF8201

Product data sheet Rev. 4 — 24 February 2021

Figure 10. Group power down sequence example

14.6.2.3 Power down delay

After a power down sequence is started, the PWRON pin shall be masked until the sequence is finished and the programmable power down delay is reached, then the device can power up again if a power-up event is present. The power down delay time can be programed on OTP via the OTP_PD_SEQ_DLY[1:0] bits.

Table 23. Power down delay selection

OTP_PD_SEQ_DLY[1:0] Delay after power down sequence

00 No delay

01 1.5 ms

10 5.0 ms

11 10 ms

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