NXP PESD5V2S2UT Datasheet

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DATA SH EET
DISCRETE SEMICONDUCTORS
PESDxS2UT series
Double ESD protection diodes in SOT23 package
Product data sheet Supersedes data of 2003 Aug 20
2004 Apr 15
NXP Semiconductors Product data sheet
2
1
3
0
Double ESD protection diodes in SOT23 package

FEATURES

Uni-directional ESD protection of up to two lines
Max. peak pulse power: Ppp = 330 W at tp = 8/20 µs
Low clamping voltage: V
Ultra-low reverse leakage curre nt: IRM < 700 nA
ESD protection > 23 kV
IEC 61000-4-2; level 4 (ESD)
IEC 61000-4-5 (surge); Ipp = 18 A at tp = 8/20 µs.

APPLICATIONS

Computers and peripherals
Communication systems
Audio and video equipment
High speed data lines
Parallel ports.
= 20 V at Ipp = 18 A
(CL)R
PESDxS2UT series

QUICK REFERENCE DATA

SYMBOL PARAMETER VALUE UNIT
V
RWM
C
d

PINNING

reverse stand-off voltage
diode capacitance
= 0 V;
V
R
= 1 MHz
f number of
3.3, 5.2, 12, 15 and 24
207, 152, 38, 32 and 23
2
protected lines
PIN DESCRIPTION
1 cathode 1 2 cathode 2 3 common anode
V
pF

DESCRIPTION

Uni-directional double ESD protection diodes in a SOT23 plastic package. Designed to protect up to two transmission or data lines from ElectroStatic Discharge (ESD) damage.

MARKING

T YPE NUMBER MARKING CODE
(1)
PESD3V3S2UT *U9 PESD5V2S2UT *U1 PESD12VS2UT *U2 PESD15VS2UT *U3 PESD24VS2UT *U4
Note
1. * = p : made in Hong Kong. * = t : made in Malaysia. * = W : made in China.
1
3
2
001aaa49
sym022
Fig.1 Simplified outline (SOT23) and symbol.
2004 Apr 15 2
NXP Semiconductors Product data sheet
Double ESD protection diodes in SOT23
PESDxS2UT series
package

ORDERING INFORMATION

T YPE NUMBER
PESD3V3S2UT plastic surface mounted package; 3 leads SOT23 PESD5V2S2UT PESD12VS2UT PESD15VS2UT PESD24VS2UT

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 60134).
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
P
pp
I
pp
T
j
T
amb
T
stg
peak pulse power 8/20 µs pulse; notes 1 and 2
PESD3V3S2UT 330 W PESD5V2S2UT 260 W PESD12VS2UT 180 W PESD15VS2UT 160 W PESD24VS2UT 160 W
peak pulse current 8/20 µs pulse; notes 1 and 2
PESD3V3S2UT 18 A PESD5V2S2UT 15 A PESD12VS2UT 5 A PESD15VS2UT 5 A
PESD24VS2UT 3 A junction temperature 150 °C operating ambient temperature −65 +150 °C storage temperature −65 +150 °C
NAME DESCRIPTION VERSION
PACKAGE
Notes
1. Non-repetitive current pulse 8/20µ µs exponential decay waveform; see Fig.2.
2. Measured across either pins 1 and 3 or pins 2 and 3.
2004 Apr 15 3
NXP Semiconductors Product data sheet
1
1
t
Double ESD protection diodes in SOT23
PESDxS2UT series
package

ESD maximum ratings

SYMBOL PARAMETER CONDITIONS VALUE UNIT
ESD electrostatic discharge
capability
Notes
1. Device stressed with ten non-repetitive ElectroStatic Discharge (ESD) pulses; see Fig.3.
2. Measured across either pins 1 and 3 or pins 2 and 3.

ESD standards compliance

IEC 61000-4-2 (contact discharge);
1 and 2
notes
PESD3V3S2UT 30 kV PESD5V2S2UT 30 kV PESD12VS2UT 30 kV PESD15VS2UT 30 kV PESD24VS2UT 23 kV
HBM MIL-Std 883
PESDxS2UT series 10 kV
ESD STANDARD CONDITIONS
IEC 61000-4-2; level 4 (ESD); see Fig.3 >15 kV (air); > 8 kV (contact) HBM MIL-Std 883; class 3 >4 kV
120
handbook, halfpage
I
pp
(%)
80
40
0
010
100 % Ipp; 8 µs
t
e
20
50 % Ipp; 20 µs
MLE218
t (µs)
40
30
00 % 90 %
10 %
I
pp
tr = 0.7 to 1 ns
30 ns
60 ns
001aaa19
Fig.2 8/20 µs pulse waveform according to
IEC 61000-4-5.
Fig.3 ElectroStatic Discharge (ESD) pulse
waveform according to IEC 61000-4-2.
2004 Apr 15 4
NXP Semiconductors Product data sheet
Double ESD protection diodes in SOT23
PESDxS2UT series
package

ELECTRICAL CHARACTERISTICS

Tj = 25 °C unless otherwise specified.
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
V
I
V
C
V
RM
RWM
BR
d
(CL)R
reverse stand-off voltage
PESD3V3S2UT 3.3 V
PESD5V2S2UT 5.2 V
PESD12VS2UT 12 V
PESD15VS2UT 15 V
PESD24VS2UT 24 V reverse leakage current
PESD3V3S2UT V
PESD5V2S2UT V
PESD12VS2UT V
PESD15VS2UT V
PESD24VS2UT V
= 3.3 V 0.7 2 µA
RWM
= 5.2 V 0.15 1 µA
RWM
= 12 V <0.02 1 µA
RWM
= 15 V <0.02 1 µA
RWM
= 24 V <0.02 1 µA
RWM
breakdown voltage IZ = 5 mA
PESD3V3S2UT 5.2 5.6 6.0 V
PESD5V2S2UT 6.4 6.8 7.2 V
PESD12VS2UT 14.7 15.0 15.3 V
PESD15VS2UT 17.6 18.0 18.4 V
PESD24VS2UT 26.5 27.0 27.5 V diode capacitance f = 1 MHz; VR = 0 V
PESD3V3S2UT 207 300 pF
PESD5V2S2UT 152 200 pF
PESD12VS2UT 38 75 pF
PESD15VS2UT 32 70 pF
PESD24VS2UT 23 50 pF clamping voltage notes 1 and 2
PESD3V3S2UT Ipp = 1 A 7 V
Ipp = 18 A 20 V
PESD5V2S2UT Ipp = 1 A 9 V
Ipp = 15 A 20 V
PESD12VS2UT Ipp = 1 A 19 V
Ipp = 5 A 35 V
PESD15VS2UT Ipp = 1 A 23 V
Ipp = 5 A 40 V
PESD24VS2UT Ipp = 1 A 36 V
Ipp = 3 A 70 V
2004 Apr 15 5
NXP Semiconductors Product data sheet
001aaa147
Double ESD protection diodes in SOT23
PESDxS2UT series
package
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
R
diff
Notes
1. Non-repetitive current pulse 8/20 µs exponential decay waveform; see Fig.2.
2. Measured either across pins 1 and 3 or pins 2 and 3.

GRAPHICAL DATA

4
10
differential resistance
PESD3V3S2UT IR = 1 mA 400
PESD5V2S2UT IR = 1 mA 80
PESD12VS2UT IR = 1 mA 200
PESD15VS2UT IR = 1 mA 225
PESD24VS2UT IR = 0.5 mA 300
1.2
001aaa193
P
pp
(W)
3
10
2
10
10
110
(1) PESD3V3S2UT and PESD5V2S2UT. (2) PESD12VS2UT, PESD15VS2UT, PESD24VS2UT
T
= 25 °C.
amb
tp = 8/20 µs exponential decay waveform; see Fig.2.
10 10
(1)
(2)
2
3
10
t
p
4
(µs)
P
P
PP(25°C)
PP
0.8
0.4
Fig.5 Relative variation of peak pulse power as a
Fig.4 Peak pulse power dissipation as a function
of pulse time; typical values.
0
0 20015050 100
Tj (°C)
function of junction temperature; typical values.
2004 Apr 15 6
NXP Semiconductors Product data sheet
001aaa148
001aaa149
Double ESD protection diodes in SOT23 package
240
C
d
(pF)
200
160
120
80
40
054231
(1) PESD3V3S2UT; V (2) PESD5V2S2UT; V
T
= 25 °C; f = 1 MHz.
amb
(1)
(2)
VR (V)
= 3.3 V.
RWM
= 5 V.
RWM
50
C
d
(pF)
40
30
20
10
0
0252010 155
(1) PESD12VS2UT; V (2) PESD15VS2UT; V (3) PESD24VS2UT; V
T
= 25 °C; f = 1 MHz.
amb
PESDxS2UT series
(1) (2)
(3)
= 12 V.
RWM
= 15 V.
RWM
= 24 V.
RWM
VR (V)
Fig.6 Diode capacitance as a function of reverse
voltage; typical values.
Fig.7 Diode capacitance as a function of reverse
voltage; typical values.
2004 Apr 15 7
NXP Semiconductors Product data sheet
Double ESD protection diodes in SOT23 package
10
I
R
I
R(25˚C)
1
1
10
100 150100050−50
(1) PESD3V3S2UT; V
PESD5V2S2UT; V
RWM RWM
(1)
= 3.3 V. = 5 V.
001aaa270
Tj (°C)
PESDxS2UT series
IR is less than 10 nA at 150 °C for: PESD12V52UT; V PESD15VS2UT; V PESD24VS2UT; V
RWM
RWM RWM
= 12 V.
= 15 V. = 24 V.
Fig.8 Relative variation of reverse leakage
current as a function of junction temperature; typical values.
2004 Apr 15 8
NXP Semiconductors Product data sheet
2
G
G
Double ESD protection diodes in SOT23 package
ESD TESTER
R
Z
C
Z
note 1
Note 1: IEC61000-4-2 network C
= 150 pF; RZ = 330
Z
vertical scale = 200 V/div horizontal scale = 50 ns/div
450
D.U.T.: PESDxS2UT
RG 223/U 50 coax
GND
10×
ATTENUATOR
PESDxS2UT series
4 GHz DIGITAL
OSCILLOSCOPE
50
vertical scale = 20 V/div horizontal scale = 50 ns/div
PESD24VS2UT
GND
GND
GND
ND
GND
unclamped +1 kV ESD voltage waveform (IEC61000-4-2 network)
ND
unclamped 1 kV ESD voltage waveform (IEC61000-4-2 network)
vertical scale = 200 V/div horizontal scale = 50 ns/div
clamped +1 kV ESD voltage waveform (IEC61000-4-2 network)
GND
clamped 1 kV ESD voltage waveform (IEC61000-4-2 network)
PESD15VS2UT
PESD12VS2UT
PESD5V2S2UT
PESD3V3S2UT
vertical scale = 10 V/div horizontal scale = 50 ns/div
001aaa49
Fig.9 ESD clamping test set-up and waveforms.
2004 Apr 15 9
NXP Semiconductors Product data sheet
1
d
Double ESD protection diodes in SOT23
PESDxS2UT series
package

APPLICATION INFORMATION

The PESDxS2UT series is designed for uni-directional protection for up to two lines against damage caused by ElectroStatic Discharge (ESD) and surge pulses. The PESDxS2UT series may be used on lines where the signal polarities are below ground. PESDxS2UT series provide a surge capability of up to 330 waveform.
line 1 to be protected line 2 to be protected
PESDxS2UT
ground
unidirectional protection
of two lines
bidirectional protection
line 1 to be protecte
PESDxS2UT
ground
of one line
Fig.10 Typical application: ESD protection of data lines.
W (Ppp) per line for an 8/20 µs
001aaa49

Circuit board layout and protection device placement

Circuit board layout is critical for the suppression of ESD, Electrical Fast Transient (EFT) and surge transients. The following guidelines are recommended:
Place the PESDxS2UT as close as possible to the input terminal or connector.
The path length between the PESDxS2UT and the protected line should be minimized.
Keep parallel signal paths to a minimum.
Avoid running protected conductors in paralle l with unprotected conductors.
Minimize all printed-circuit board conductive loops including power and gr ound loops.
Minimize the length of transient return paths to ground.
Avoid using shared return paths to a common ground point.
Ground planes should be used whenever possib le. For multilayer printed-circuit boards use ground vias .
2004 Apr 15 10
NXP Semiconductors Product data sheet
3
Double ESD protection diodes in SOT23
PESDxS2UT series
package

PACKAGE OUTLINE

Plastic surface-mounted package; 3 leads SOT2
D
3
E
H
E
AB
X
v
M
A
12
e
1
DIMENSIONS (mm are the original dimensions)
A
1
0.1
b
p
0.48
0.15
0.38
0.09
IEC JEDEC JEITA
UNIT
A
max.
1.1
mm
0.9
OUTLINE VERSION
SOT23 TO-236AB
b
p
e
cD
3.0
2.8
w
M
B
0 1 2 mm
scale
e
0.95
H
1
2.5
2.1
e
E
1.4
1.9
1.2
REFERENCES
Q
A
A
1
c
L
p
detail X
L
Qwv
p
E
0.55
0.45
0.15
0.45
0.2
0.1
EUROPEAN
PROJECTION
ISSUE DATE
04-11-04 06-03-16
2004 Apr 15 11
NXP Semiconductors Product data sheet
Double ESD protection diodes in SOT23
PESDxS2UT series
package

DATA SHEET STATUS

DOCUMENT
STATUS
Objective data sheet Development This document contains data from the objective specification for product
Preliminary data sheet Qualification This document contains data from the preliminary specification. Product data sheet Production This document co ntains the product specification.
Notes
1. Please consult the most recently issued document before initiating or completing a design.
2. The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at
http://www.nxp.com.
URL
DISCLAIMERS General Information in this document is believed to be
accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information.
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Applications ⎯ Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modificati on .
(1)
PRODUCT
STATUS
(2)
DEFINITION
development.
above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability.
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Export control This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities.
Quick reference data The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding.
Limiting values Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC the device. Limiting values are stress ratings only an d operation of the device at these or any other conditions
2004 Apr 15 12
60134) may cause permanent damage to
NXP Semiconductors
Customer notification
This data sheet was changed to reflect the new company name NXP Semiconductors, including new legal definitions and disclaimers. No changes were made to the technical content, except for package outline drawings which were updated to the latest version.
Contact information
For additional information please visit: http://www.nxp.com For sales offices addresses send e-mail to: salesaddresses@nxp.com
© NXP B.V. 2009 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this documen t d oes not form part of any quotation or contract, is believe d t o b e a ccur ate a nd re li a ble and may be change d without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industri al or intellectual property rights.
Printed in The Netherlands R76/03/pp13 Date of release: 2004 Apr 15 Document order number: 9397 750 12823
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