NXP PDTC114EE, PDTC114EM, PDTC114ET, PDTC114EU Schematic [ru]
PDTC114E series
NPN resistor-equipped transistors;
R1 = 10 k, R2 = 10 k
Rev. 12 — 21 December 2011 Product data sheet
1. Product profile
1.1 General description
NPN Resistor-Equipped Transistor (RET) family in small Surface-Mounted Device (SMD)
plastic packages.
Table 1. Product overview
Type number Package PNP
PDTC114EE SOT416 SC-75 - PDTA114EE ultra small
PDTC114EM SOT883 SC-101 - PDTA114EM leadless ultra small
PDTC114ET SOT23 - TO-236AB PDT A114ET small
PDTC114EU SOT323 SC-70 - PDTA114EU very small
NXP JEITA JEDEC
complement
Package
configuration
1.2 Features and benefits
100 mA output current capability Reduces component count
Built-in bias resistors Reduces pick and place costs
Simplifies circuit design AEC-Q101 qualified
1.3 Applications
Digital application in automotive and
industrial segments
Cost-saving alternative for BC847/857
series in digital applications
Control of IC inputs Switching loads
1.4 Quick reference data
Table 2. Quick reference data
Symbol Parameter Conditions Min Typ Max Unit
V
CEO
I
O
R1 bias resistor 1 (input) 7 10 13 k
R2/R1 bias resistor ratio 0.8 1.0 1.2
collector-emitter voltage open base - - 50 V
output current - - 100 mA
NXP Semiconductors
006aaa144
12
3
sym007
3
2
1
R1
R2
3
1
2
Transparent
top view
sym007
3
2
1
R1
R2
2. Pinning information
Table 3. Pinning
Pin Description Simplified outline Graphic symbol
SOT23; SOT323; SOT416
1 input (base)
2 GND (emitter)
3 output (collector)
SOT883
1 input (base)
2 GND (emitter)
3 output (collector)
PDTC114E series
NPN resistor-equipped transistors; R1 = 10 k, R2 = 10 k
3. Ordering information
Table 4. Ordering information
Type number Package
PDTC114EE SC-75 plastic surface-mounted package; 3 leads SOT416
PDTC114EM SC-101 leadless ultra small plastic package; 3 solder lands;
PDTC114ET - plastic surface-mounted package; 3 leads SOT23
PDTC114EU SC-70 plastic surface-mounted package; 3 leads SOT323
4. Marking
Table 5. Marking codes
Type number Marking code
PDTC114EE 09
PDTC114EM DS
PDTC114ET *16
PDTC114EU *09
[1] * = placeholder for manufacturing site code.
Name Description Version
SOT883
body 1.0 0.6 0.5 mm
[1]
PDTC114E_SER All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 12 — 21 December 2011 2 of 17
NXP Semiconductors
5. Limiting values
Table 6. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
V
CBO
V
CEO
V
EBO
V
I
I
O
I
CM
P
tot
T
j
T
amb
T
stg
[1] Device mounted on an FR4 Printed-Circuit Board (PCB), single-sided copper, tin-plated and standard
footprint.
[2] Reflow soldering is the only recommended soldering method.
[3] Device mounted on an FR4 PCB with 70 m copper strip line, standard footprint.
PDTC114E series
NPN resistor-equipped transistors; R1 = 10 k, R2 = 10 k
collector-base voltage open emitter - 50 V
collector-emitter voltage open base - 50 V
emitter-base voltage open collector - 10 V
input voltage
positive - +40 V
negative - 10 V
output current - 100 mA
peak collector current single pulse; tp 1ms - 100 mA
total power dissipation T
PDTC114EE (SOT416)
PDTC114EM (SOT883)
PDTC114ET (SOT23)
PDTC114EU (SOT323)
junction temperature - 150 C
ambient temperature 65 +150 C
storage temperature 65 +150 C
amb
25 C
[1][2]
-150mW
[2][3]
-250mW
[1]
-250mW
[1]
-200mW
PDTC114E_SER All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 12 — 21 December 2011 3 of 17
NXP Semiconductors
PDTC114E series
NPN resistor-equipped transistors; R1 = 10 k, R2 = 10 k
(1) SOT23; FR4 PCB, standard footprint
SOT883; FR4 PCB with 70 m copper strip line, standard footprint
(2) SOT323; FR4 PCB, standard footprint
(3) SOT416; FR4 PCB, standard footprint
Fig 1. Power derating curves
6. Thermal characteristics
300
P
tot
(mW)
200
100
0
-75 17512525 75-25
006aac778
(1)
(2)
(3)
T
(°C)
amb
Table 7. Thermal characteristics
Symbol Parameter Conditions Min Typ Max Unit
R
th(j-a)
thermal resistance from junction
in free air
to ambient
PDTC114EE (SOT416)
PDTC114EM (SOT883)
PDTC114ET (SOT23)
PDTC114EU (SOT323)
[1] Device mounted on an FR4 PCB, single-sided copper, tin-plated and standard footprint.
[2] Reflow soldering is the only recommended soldering method.
[3] Device mounted on an FR4 PCB with 70 m copper strip line, standard footprint.
[1][2]
--830K/W
[2][3]
--500K/W
[1]
--500K/W
[1]
--625K/W
PDTC114E_SER All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 12 — 21 December 2011 4 of 17
NXP Semiconductors
006aac781
10
-5
1010
-2
10
-4
10
2
10
-1
tp (s)
10
-3
10
3
1
10
2
10
10
3
Z
th(j-a)
(K/W)
1
duty cycle = 1
0.75
0.5
0.33
0.2
0.1
0.05
0.02
0.01
0
006aac782
10
-5
1010
-2
10
-4
10
2
10
-1
tp (s)
10
-3
10
3
1
10
2
10
10
3
Z
th(j-a)
(K/W)
1
duty cycle = 1
0.75
0.5
0.33
0.2
0.1
0.05
0.02
0.01
0
PDTC114E series
NPN resistor-equipped transistors; R1 = 10 k, R2 = 10 k
FR4 PCB, standard footprint
Fig 2. Transient thermal impedance from junction to ambient as a function of pulse duration for
PDTC114EE (SOT416); typical values
FR4 PCB, 70 m copper strip line
Fig 3. Transient thermal impedance from junction to ambient as a function of pulse duration for
PDTC114EM (SOT883); typical values
PDTC114E_SER All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 12 — 21 December 2011 5 of 17
NXP Semiconductors
006aac779
10
-5
1010
-2
10
-4
10
2
10
-1
tp (s)
10
-3
10
3
1
10
2
10
10
3
Z
th(j-a)
(K/W)
1
duty cycle = 1
0.75
0.5
0.33
0.2
0.1
0.05
0.02
0.01
0
006aac780
10
-5
1010
-2
10
-4
10
2
10
-1
tp (s)
10
-3
10
3
1
10
2
10
10
3
Zth(j-a)
(K/W)
1
duty cycle = 1
0.75
0.5
0.33
0.2
0.1
0.05
0.02
0.01
0
PDTC114E series
NPN resistor-equipped transistors; R1 = 10 k, R2 = 10 k
FR4 PCB, standard footprint
Fig 4. Transient thermal impedance from junction to ambient as a function of pulse duration for
PDTC114ET (SOT23); typical values
FR4 PCB, standard footprint
Fig 5. Transient thermal impedance from junction to ambient as a function of pulse duration for
PDTC114EU (SOT323); typical values
PDTC114E_SER All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 12 — 21 December 2011 6 of 17
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