NXP PCF 8583 T Datasheet

INTEGRATED CIRCUITS

DATA SH EET

PCF8583

Clock/calendar with 240 × 8-bit
RAM

Product specification
Supersedes data of 1997 Mar 28
File under Integrated Circuits, IC12

1997 Jul 15

Philips Semiconductors Product specification

Clock/calendar with 240 × 8-bit RAM PCF8583

CONTENTS

1 FEATURES
2 GENERAL DESCRIPTION
3 QUICK REFERENCE DATA
4 ORDERING INFORMATION
5 BLOCK DIAGRAM
6 PINNING
7 FUNCTIONAL DESCRIPTION

7.1 Counter function modes

7.2 Alarm function modes

7.3 Control/status register

7.4 Counter registers

7.5 Alarm control register

7.6 Alarm registers

7.7 Timer

7.8 Event counter mode

7.9 Interrupt output

7.10 Oscillator and divider

7.11 Initialization
8 CHARACTERISTICS OF THE I2C-BUS

8.1 Bit transfer

8.2 Start and stop conditions

8.3 System configuration

8.4 Acknowledge
9I

9.1 Addressing

9.2 Clock/calendar READ/WRITE cycles

2

C-BUS PROTOCOL

10 LIMITING VALUES
11 HANDLING
12 DC CHARACTERISTICS
13 AC CHARACTERISTICS
14 APPLICATION INFORMATION

14.1 Quartz frequency adjustment

14.1.1 Method 1: fixed osci capacitor

14.1.2 Method 2: OSCI Trimmer

14.1.3 Method 3:
15 PACKAGE OUTLINES
16 SOLDERING

16.1 Introduction

16.2 DIP

16.2.1 Soldering by dipping or by wave

16.2.2 Repairing soldered joints

16.3 SO

16.3.1 Reflow soldering

16.3.2 Wave soldering

16.3.3 Repairing soldered joints
17 DEFINITIONS
18 LIFE SUPPORT APPLICATIONS
19 PURCHASE OF PHILIPS I2C COMPONENTS

1997 Jul 15 2

Philips Semiconductors Product specification

Clock/calendar with 240 × 8-bit RAM PCF8583

1 FEATURES

• I2C-bus interface operating supply voltage: 2.5 V to 6 V

• Clock operating supply voltage (0 to +70 °C):

1.0 V to 6.0 V

• 240 × 8-bit low-voltage RAM

• Data retention voltage: 1.0 V to 6 V

• Operating current (at f

= 0 Hz): max. 50 µA

SCL

• Clock function with four year calendar

• Universal timer with alarm and overflow indication

• 24 or 12 hour format

• 32.768 kHz or 50 Hz time base

2

• Serial input/output bus (I

C)

• Automatic word address incrementing

• Programmable alarm, timer and interrupt function

• Slave address:

– READ: A1 or A3
– WRITE: A0 or A2.

3 QUICK REFERENCE DATA

2 GENERAL DESCRIPTION

The PCF8583 is a clock/calendar circuit based on a
2048-bit static CMOS RAM organized as 256 words by
8 bits. Addresses and data are transferred serially via the
two-line bidirectional I

2

C-bus. The built-in word address
register is incremented automatically after each written or
read data byte. Address pin A0 is used for programming
the hardware address, allowing the connection of two
devices to the bus without additional hardware.

The built-in 32.768 kHz oscillator circuit and the first
8 bytes of the RAM are used for the clock/calendar and
counter functions. The next 8 bytes may be programmed
as alarm registers or used as free RAM space.
The remaining 240 bytes are free RAM locations.

SYMBOL PARAMETER CONDITION MIN. TYP. MAX. UNIT

V

DD

I

DD

I

DDO

T

amb

T

stg

supply voltage operating mode I2C-bus active 2.5 − 6.0 V

2

I

C-bus inactive 1.0 − 6.0 V
supply current operating mode f
supply current clock mode f

= 100 kHz −−200 µA

SCL

= 0 Hz; VDD=5V − 10 50 µA

SCL

f

= 0 Hz; VDD=1V − 210µA

SCL

operating ambient temperature range −40 − +85 °C
storage temperature range −65 − +150 °C

4 ORDERING INFORMATION

TYPE

NUMBER

NAME DESCRIPTION VERSION

PACKAGE

PCF8583P DIP8 plastic dual in-line package; 8 leads (300 mil) SOT97-1
PCF8583T SO8 plastic small outline package; 8 leads; body width 7.5 mm SOT176-1

1997 Jul 15 3

Philips Semiconductors Product specification

Clock/calendar with 240 × 8-bit RAM PCF8583

5 BLOCK DIAGRAM

handbook, full pagewidth

OSCI

OSCO

INT

V

DD

V

SS

A0

SCL

SDA

1
2
7
8
4

3
6

5

PCF8583

OSCILLATOR

32.768 kHz

POWER-ON

RESET

2

C-BUS

I

INTERFACE

DIVIDER

1 : 256

OR

100 : 128

CONTROL

LOGIC

ADDRESS

REGISTER

100 Hz

control/status

hundredth of a second

seconds

minutes

hours

year/date

weekdays/months

timer

alarm control

alarm registers

or RAM

RAM

(240 × 8)

00
01

07
08

0F

Fig.1 Block diagram.

6 PINNING

SYMBOL PIN DESCRIPTION

OSCI 1 oscillator input, 50 Hz or event-pulse

input
OSCO 2 oscillator output
A0 3 address input
V

SS

4 negative supply
SDA 5 serial data line
SCL 6 serial clock line
INT 7 open drain interrupt output (active

LOW)

V

DD

8 positive supply

handbook, halfpage

1

OSCI

2

OSCO

V

SS

A0

PCF8583P
PCF8583T

3
4

MRB014

Fig.2 Pinning diagram.

FF

MRB001

V

8

DD

7

INT

6

SCL

5

SDA

1997 Jul 15 4

Philips Semiconductors Product specification

Clock/calendar with 240 × 8-bit RAM PCF8583

7 FUNCTIONAL DESCRIPTION

The PCF8583 contains a 256 by 8-bit RAM with an 8-bit
auto-increment address register, an on-chip 32.768 kHz
oscillator circuit, a frequency divider, a serial two-line
bidirectional I2C-bus interface and a power-on reset circuit.

The first 16 bytes of the RAM (memory addresses
00 to 0F) are designed as addressable 8-bit parallel
special function registers. The first register (memory
address 00) is used as a control/status register.
The memory addresses 01 to 07 are used as counters for
the clock function. The memory addresses 08 to 0F may
be programmed as alarm registers or used as free RAM
locations, when the alarm is disabled.

7.1 Counter function modes

When the control/status register is programmed, a

32.768 kHz clock mode, a 50 Hz clock mode or an
event-counter mode can be selected.

In the clock modes the hundredths of a second, seconds,
minutes, hours, date, month (four year calendar) and
weekday are stored in a BCD format. The timer register
stores up to 99 days. The event counter mode is used to
count pulses applied to the oscillator input (OSCO left
open-circuit). The event counter stores up to 6 digits of
data.

When one of the counters is read (memory locations
01 to 07), the contents of all counters are strobed into
capture latches at the beginning of a read cycle. Therefore,
faulty reading of the count during a carry condition is
prevented.

When a counter is written, other counters are not affected.

7.2 Alarm function modes

By setting the alarm enable bit of the control/status register
the alarm control register (address 08) is activated.

Whenever an alarm event occurs the alarm flag of the
control/status register is set. A timer alarm event will set
the alarm flag and an overflow condition of the timer will set
the timer flag. The open drain interrupt output is switched
on (active LOW) when the alarm or timer flag is set
(enabled). The flags remain set until directly reset by a
write operation.

When the alarm is disabled (Bit 2 of control/status
register = 0) the alarm registers at addresses 08 to 0F
may be used as free RAM.

7.3 Control/status register

The control/status register is defined as the memory
location 00 with free access for reading and writing via the

2

C-bus. All functions and options are controlled by the

I
contents of the control/status register (see Fig.3).

7.4 Counter registers

In the clock modes 24 h or 12 h format can be selected by
setting the most significant bit of the hours counter
register. The format of the hours counter is shown in Fig.5.

The year and date are packed into memory location 05
(see Fig.6). The weekdays and months are packed into
memory location 06 (see Fig.7). When reading these
memory locations the year and weekdays are masked out
when the mask flag of the control/status register is set.
This allows the user to read the date and month count
directly.

In the event-counter mode events are stored in BCD
format. D5 is the most significant and D0 the least
significant digit. The divider is by-passed.

In the different modes the counter registers are
programmed and arranged as shown in Fig.4. Counter
cycles are listed in Table 1.

By setting the alarm control register a dated alarm, a daily
alarm, a weekday alarm or a timer alarm may be
programmed. In the clock modes, the timer register
(address 07) may be programmed to count hundredths of
a second, seconds, minutes, hours or days. Days are
counted when an alarm is not programmed.

1997 Jul 15 5

Philips Semiconductors Product specification

Clock/calendar with 240 × 8-bit RAM PCF8583

handbook, full pagewidth

MSB LSB

76543210

MRB017

memory location 00
reset state: 0000 0000

timer flag (50% duty factor
seconds flag if alarm
enable bit is 0)

alarm flag (50% duty factor
minutes flag if alarm
enable bit is 0)

alarm enable bit:

0 alarm disabled: flags toggle
alarm control register disabled
(memory locations 08 to 0F
are free RAM space)
1 enable alarm control register
(memory location 08 is the
alarm control register)

mask flag:

0 read locations 05 to 06
unmasked
1 read date and month count
directly

function mode :

00 clock mode 32.768 kHz
01 clock mode 50 Hz
10 event-counter mode
11 test modes

hold last count flag :

0 count
1 store and hold last count in
capture latches

stop counting flag :

0 count pulses
1 stop counting, reset divider

Fig.3 Control/status register.

1997 Jul 15 6

Philips Semiconductors Product specification

Clock/calendar with 240 × 8-bit RAM PCF8583

handbook, full pagewidth

control/status

hundredth of a second

1/10 s

10 s

10 min

10 h

10 day

weekday/month

10 month

10 day

alarm control

hundredth of a second

1/10 s 1/100 s

alarm seconds

alarm minutes

alarm hours

alarm month

alarm timer

1/100 s

seconds

1 s

minutes

1 min

hours

1 h

year/date

1 day

1 month

timer

1 day

alarm date

control/status

D1

D3

D5

T1

alarm control

alarm alarm

D1
D3

D5

alarm timer

free

free

free

timer

free
free

free

D0

D2

D4

T0

D0
D2

D4

00

01

02

03

04

05

06

07

08

09

0A

0B

0C

0D

0E

0F

free RAM free RAM

CLOCK MODES EVENT COUNTER

Fig.4 Register arrangement.

1997 Jul 15 7

MRB015

Philips Semiconductors Product specification

Clock/calendar with 240 × 8-bit RAM PCF8583

andbook, full pagewidth

handbook, full pagewidth

MSB LSB

76543210

MRB002

Fig.5 Format of the hours counter.

MSB LSB

765 43210

MRB003

memory location 04 (hours counter)
reset state: 0000 0000

unit hours BCD
ten hours (0 to 2 binary)
AM/PM flag:

0 AM
1 PM

format:
0 24 h format, AM/PM flag
remains unchanged
1 12 h format, AM/PM flag
will be updated

memory location 05 (year/date)
reset state: 0000 0001

unit days BCD
ten days (0 to 3 binary)

year (0 to 3 binary, read as 0 if
the mask flag is set)

Fig.6 Format of the year/date counter.

handbook, full pagewidth

MSB LSB

76543 210

MRB004

Fig.7 Format of the weekdays/month counter.

1997 Jul 15 8

memory location 06 (weekdays/months)
reset state: 0000 0001

unit months BCD
ten months

weekdays (0 to 6 binary, read as 0 if
the mask flag is set)

Philips Semiconductors Product specification

Clock/calendar with 240 × 8-bit RAM PCF8583

Table 1 Cycle length of the time counters, clock modes

UNIT COUNTING CYCLE CARRY TO NEXT UNIT

Hundredths of a second 00 to 99 99 to 00 −
Seconds 00 to 59 59 to 00 −
Minutes 00 to 59 59 to 00 −
Hours (24 h) 00 to 23 23 to 00 −
Hours (12 h) 12 AM −−

01 AM to 11 AM −−
12 PM −−
01 PM to 11 PM 11 PM to 12 AM −

Date 01 to 31 31 to 01 1, 3, 5, 7, 8, 10 and 12

01 to 30 30 to 01 4, 6, 9 and 11
01 to 29 29 to 01 2, year = 0

01 to 28 28 to 01 2, year = 1, 2 and 3
Months 01 to 12 12 to 01 −
Year 0 to 3 −−
Weekdays 0 to 6 6 to 0 −
Timer 00 to 99 no carry −

7.5 Alarm control register

When the alarm enable bit of the control/status register is
set (address 00, bit 2) the alarm control register (address

08) is activated. All alarm, timer, and interrupt output
functions are controlled by the contents of the alarm
control register (see Fig.8).

An alarm signal is generated when the contents of the
alarm registers matches bit-by-bit the contents of the
involved counter registers. The year and weekday bits are
ignored in a dated alarm. A daily alarm ignores the month
and date bits. When a weekday alarm is selected, the
contents of the alarm weekday/month register will select
the weekdays on which an alarm is activated (see Fig.9).

CONTENTS OF THE

MONTH COUNTER

7.6 Alarm registers

All alarm registers are allocated with a constant address
offset of hexadecimal 08 to the corresponding counter
registers (see Fig.4, Register arrangement).

1997 Jul 15 9

Remark: In the 12 h mode, bits 6 and 7 of the alarm hours
register must be the same as the hours counter.

Philips Semiconductors Product specification

Clock/calendar with 240 × 8-bit RAM PCF8583

handbook, full pagewidth

MSB LSB

7654 3210

MRB005

memory location 08
reset state: 0000 0000

timer function :

000 no timer
001 hundredths of a second
010 seconds
011 minutes
100 hours
101 days
110 not used
111 test mode, all counters
in parallel (factory use only)

timer interrupt enable :

0 timer flag, no interrupt
1 timer flag, interrupt

clock alarm function :

00 no clock alarm
01 daily alarm
10 weekday alarm
11 dated alarm

timer alarm enable :

0 no timer alarm
1 timer alarm

alarm interrupt enable :

(valid only when 'alarm enable' in
control / status register is set

Fig.8 Alarm control register; clock mode.

1997 Jul 15 10

0 alarm flag, no interrupt
1 alarm flag, interrupt

Philips Semiconductors Product specification

Clock/calendar with 240 × 8-bit RAM PCF8583

handbook, full pagewidth

MSB LSB

76543210

MRB006

Fig.9 Selection of alarm weekdays.

7.7 Timer

The timer (location 07) is enabled by setting the
control/status register = XX0X X1XX. The timer counts up
from 0 (or a programmed value) to 99. On overflow, the
timer resets to 0. The timer flag (LSB of control/status
register) is set on overflow of the timer. This flag must be
reset by software. The inverted value of this flag can be
transferred to the external interrupt by setting bit 3 of the
alarm control register.

Additionally, a timer alarm can be programmed by setting
the timer alarm enable (bit 6 of the alarm control register).
When the value of the timer equals a pre-programmed
value in the alarm timer register (location 0F), the alarm
flag is set (bit 1 of the control/status register). The inverted
value of the alarm flag can be transferred to the external
interrupt by enabling the alarm interrupt (bit 6 of the alarm
control register).

Resolution of the timer is programmed via the 3 LSBs of
the alarm control register (see Fig.11, Alarm and timer
Interrupt logic diagram).

7.8 Event counter mode

Event counter mode is selected by bits 4 and 5 which are
logic 1, 0 in the control/status register. The event counter
mode is used to count pulses externally applied to the
oscillator input (OSCO left open-circuit).

memory location 0E (alarm weekday / month)

weekday 0 enabled when set
weekday 1 enabled when set

weekday 2 enabled when set
weekday 3 enabled when set
weekday 4 enabled when set
weekday 5 enabled when set
weekday 6 enabled when set
not used

The event counter stores up to 6 digits of data, which are
stored as 6 hexadecimal values located in locations 1, 2,
and 3. Thus, up to 1 million events may be recorded.

An event counter alarm occurs when the event counter
registers match the value programmed in locations 9, A,
and B, and the event alarm is enabled (bits 4 and 5 which
are logic 0, 1 in the alarm control register). In this event,
the alarm flag (bit 1 of the control/status register) is set.
The inverted value of this flag can be transferred to the
interrupt pin (pin 7) by setting the alarm interrupt enable in
the alarm control register. In this mode, the timer
(location 07) increments once for every one, one-hundred,
ten thousand, or 1 million events, depending on the value
programmed in bits 0, 1 and 2 of the alarm control register.
In all other events, the timer functions are as in the clock
mode.

7.9 Interrupt output

The conditions for activating the open-drain n-channel
interrupt output

INT (active LOW) are determined by
appropriate programming of the alarm control register.
These conditions are clock alarm, timer alarm, timer
overflow, and event counter alarm. An interrupt occurs
when the alarm flag or the timer flag is set, and the
corresponding interrupt is enabled. In all events, the
interrupt is cleared only by software resetting of the flag
which initiated the interrupt.

1997 Jul 15 11

Philips Semiconductors Product specification

Clock/calendar with 240 × 8-bit RAM PCF8583

handbook, full pagewidth

MSB LSB

7654 3210

MRB007

memory location 08
reset state: 0000 0000

timer function :

000 no timer
001 units
010 100
011 10 000
100 1 000 000
101 not allowed
110 not allowed
111 test mode, all counters
in parallel

timer interrupt enable :

0 timer flag, no interrupt
1 timer flag, interrupt

clock alarm function :

00 no event alarm
01 event alarm
10 not allowed
11 not allowed

timer alarm enable :

0 no timer alarm
1 timer alarm

alarm interrupt enable :

0 alarm flag, no interrupt
1 alarm flag, interrupt

Fig.10 Alarm control register, event-counter mode.

In the clock mode, if the alarm enable is not activated
(alarm enable bit of control/status register is logic 0), the
interrupt output toggles at 1 Hz with a 50% duty cycle (may
be used for calibration). This is the default power-on state
of the device. The OFF voltage of the interrupt output may
exceed the supply voltage, up to a maximum of 6.0 V.
A logic diagram of the interrupt output is shown in Fig.11.

7.10 Oscillator and divider

A 32.768 kHz quartz crystal has to be connected to OSCI
(pin 1) and OSCO (pin 2). A trimmer capacitor between
OSCI and V

is used for tuning the oscillator (see quartz

DD

frequency adjustment). A 100 Hz clock signal is derived
from the quartz oscillator for the clock counters.

In the 50 Hz clock mode or event-counter mode the
oscillator is disabled and the oscillator input is switched to
a high impedance state.

1997 Jul 15 12

This allows the user to feed the 50 Hz reference frequency
or an external high speed event signal into the input OSCI.

7.11 Initialization

2

When power-up occurs the I

C-bus interface, the
control/status register and all clock counters are reset.
The device starts time-keeping in the 32.768 kHz clock
mode with the 24 h format on the first of January at

0.00.00: 00. A 1 Hz square wave with 50% duty cycle
appears at the interrupt output pin (starts HIGH).

It is recommended to set the stop counting flag of the
control/status register before loading the actual time into
the counters. Loading of illegal states may lead to a
temporary clock malfunction.

Philips Semiconductors Product specification

Clock/calendar with 240 × 8-bit RAM PCF8583

handbook, full pagewidth

MUX

mode
select

oscillator

counter
control

CLOCK/CALENDAR

ALARM

clock

alarm

76543210

CONTROL/STATUS

REGISTER

(1)

alarm

control

alarm

interrupt

TIMER

timer

alarm

timer overflow

interrupt

overflow

76543210

INT

control

timer

ALARM

CONTROL

REGISTER

(1) If the alarm enable bit of the control/status register is reset (logic 0), a 1 Hz signal can be observed on the interrupt pin INT.

Fig.11 Alarm and timer interrupt logic diagram.

1997 Jul 15 13

MBD818

Philips Semiconductors Product specification

Clock/calendar with 240 × 8-bit RAM PCF8583

8 CHARACTERISTICS OF THE I2C-BUS

The I2C-bus is for bidirectional, two-line communication between different ICs or modules. The two lines are a serial data
line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor. Data
transfer may be initiated only when the bus is not busy.

8.1 Bit transfer (see Fig.12)
One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period

of the clock pulse as changes in the data line at this time will be interpreted as a control signal.

SDA

SCL

data line

stable;

data valid

change

of data

allowed

MBC621

Fig.12 Bit transfer.

8.2 Start and stop conditions (see Fig.13)
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line, while the

clock is HIGH is defined as the start condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is
defined as the stop condition (P).

SDA

SCL

S

P

SDA

SCL

START condition

Fig.13 Definition of start and stop conditions.

1997 Jul 15 14

STOP condition

MBC622

Philips Semiconductors Product specification

Clock/calendar with 240 × 8-bit RAM PCF8583

8.3 System configuration (see Fig.14)
A device generating a message is a ‘transmitter’, a device receiving a message is the ‘receiver’. The device that controls

the message is the ‘master’ and the devices which are controlled by the master are the ‘slaves’.

SDA

SCL

MASTER

TRANSMITTER /

RECEIVER

SLAVE

RECEIVER

Fig.14 System configuration.

8.4 Acknowledge (see Fig.15)
The number of data bytes transferred between the start

and stop conditions from transmitter to receiver is
unlimited. Each byte of eight bits is followed by an
acknowledge bit. The acknowledge bit is a HIGH level
signal put on the bus by the transmitter during which time
the master generates an extra acknowledge related clock
pulse. A slave receiver which is addressed must generate
an acknowledge after the reception of each byte. Also a
master receiver must generate an acknowledge after the
reception of each byte that has been clocked out of the
slave transmitter.

SLAVE

TRANSMITTER /

RECEIVER

MASTER

TRANSMITTER

MASTER

TRANSMITTER /

RECEIVER

MBA605

The device that acknowledges must pull down the SDA
line during the acknowledge clock pulse, so that the SDA
line is stable LOW during the HIGH period of the
acknowledge related clock pulse (set-up and hold times
must be taken into consideration). A master receiver must
signal an end of data to the transmitter by not generating
an acknowledge on the last byte that has been clocked out
of the slave. In this event the transmitter must leave the
data line HIGH to enable the master to generate a stop
condition.

DATA OUTPUT

BY TRANSMITTER

DATA OUTPUT

BY RECEIVER

SCL FROM

MASTER

S

START

CONDITION

Fig.15 Acknowledgment on the I2C-bus.

1997 Jul 15 15

not acknowledge

acknowledge

MBC602

9821

clock pulse for

acknowledgement

Philips Semiconductors Product specification

Clock/calendar with 240 × 8-bit RAM PCF8583

9I2C-BUS PROTOCOL

9.1 Addressing

2

Before any data is transmitted on the I
always carried out with the first byte transmitted after the start procedure.

The clock/calendar acts as a slave receiver or slave transmitter. Therefore the clock signal SCL is only an input signal,
but the data signal SDA is a bidirectional line.

The clock/calendar slave address is shown in Fig.16. Bit A0 corresponds to hardware address pin A0. Connecting this
pin to VDD or VSS allows the device to have one of two different addresses.

C-bus, the device which should respond is addressed first. The addressing is

handbook, halfpage

101000A0R/W

group 1

group 2

MRB016

Fig.16 Slave address.

9.2 Clock/calendar READ/WRITE cycles

2

The I

C-bus configuration for the different PCF8583 READ and WRITE cycles is shown in Figs 17, 18 and 19.

handbook, full pagewidth

acknowledgement

from slave

S 0ASLAVE ADDRESS WORD ADDRESS A ADATA P

R/W

acknowledgement

from slave

n bytes

acknowledgement

from slave

auto increment

memory word address

MBD822

Fig.17 Master transmits to slave receiver (WRITE) mode.

1997 Jul 15 16

Philips Semiconductors Product specification

Clock/calendar with 240 × 8-bit RAM PCF8583

handbook, full pagewidth

S 0ASLAVE ADDRESS WORD ADDRESS A A

acknowledgement

from slave

R/W

acknowledgement

from slave

SLAVE ADDRESS

S1

at this moment master ­transmitter becomes
master - receiver and
PCF8593 slave - receiver
becomes slave - transmitter

Fig.18 Master reads after setting word address (write word address; READ data).

acknowledgement

from slave

R/W

MBD823

acknowledgement

from master

DATA

n bytes

auto increment

memory word address

last byte

memory word address

A

no acknowledgement

from master

P

1DATA

auto increment

handbook, full pagewidth

S

SLAVE ADDRESS DATA

acknowledgement

from slave

1A

R/W

n bytes last bytes

Fig.19 Master reads slave immediately after first byte (READ mode).

1997 Jul 15 17

acknowledgement

from slave

A1DATA

auto increment

word address

acknowledgement

from slave

P

auto increment

word address

MBD824

Philips Semiconductors Product specification

Clock/calendar with 240 × 8-bit RAM PCF8583

10 LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

SYMBOL PARAMETER MIN. MAX. UNIT

V

DD

I

DD

I

SS

V

I

I

I

I

O

P

tot

P

O

T

amb

T

stg

supply voltage (pin 8) −0.8 +7.0 V
supply current (pin 8) − 50 mA
supply current (pin 4) − 50 mA
input voltage −0.8 VDD+ 0.8 V
DC input current − 10 mA
DC output current − 10 mA
total power dissipation per package − 300 mW
power dissipation per output − 50 mW
operating ambient temperature −40 +85 °C
storage temperature −65 +150 °C

11 HANDLING

Inputs and outputs are protected against electrostatic charge in normal handling. However, to be totally safe, it is
desirable to take normal precautions appropriate to handling MOS devices. Advice can be found in Data Handbook IC12
under

“Handling MOS Devices”.

12 DC CHARACTERISTICS

V

= 2.5 to 6.0 V; VSS=0V; T

DD

SYMBOL PARAMETER CONDITIONS MIN. TYP.

V

DD

supply voltage
(operating mode)

V

DDosc

supply voltage

= −40 to +85 °C unless otherwise specified.

amb

I2C-bus active 2.5 − 6.0 V

2

I

C-bus inactive 1.0 − 6.0 V

T

= 0 to 70 °C; note 2 1.0 − 6.0 V

amb

(1)

MAX. UNIT

(quartz oscillator)

I

DD

I

DDO

I

DDR

V

EN

supply current
(operating mode)

supply current
(clock mode)

data retention f

f

= 100 kHz; clock mode;

SCL

−−200 µA

note 3
see Fig.20

f

= 0 Hz; VDD = 5 V − 10 50 µA

SCL

f

= 0 Hz; VDD = 1 V − 210µA

SCL

= 0 Hz; VDD= 1 V

OSCI

T

= −40 to + 85 °C −−5 µA

amb

T

= −25 to + 70 °C −−2 µA

amb

I2C-bus enable level note 4 1.5 1.9 2.3 V

SDA

V

IL

V

IH

I

OL

I

LI

C

i

LOW level input voltage note 5 −0.8 − 0.3V
HIGH level input voltage note 5 0.7V

− VDD+0.8 V

DD

DD

V

LOW level output current VOL= 0.4 V 3 −− mA
input leakage current VI=VDDor V

SS

−1 − +1 µA

input capacitance note 6 −−7pF

1997 Jul 15 18

Philips Semiconductors Product specification

Clock/calendar with 240 × 8-bit RAM PCF8583

SYMBOL PARAMETER CONDITIONS MIN. TYP.

(1)

MAX. UNIT

A0; OSCI

I

LI

input leakage current Vl=VDDor V

SS

−250 − +250 nA

INT

I

OL

I

LI

LOW level output current VOL= 0.4 V 3 −− mA
input leakage current Vl=VDDor V

SS

−1 − +1 µA

SCL

C

i

I

LI

input capacitance note 6 −−7pF
input leakage current VI=VDDor V

SS

−1 − +1 µA

Notes

1. Typical values measured at T

amb

=25°C.

2. When powering-up the device, VDD must exceed 1.5 V until stable operation of the oscillator is established.

3. Event counter mode: supply current dependant upon input frequency.

4. The I2C-bus logic is disabled if VDD<VEN.

5. When the voltages are above or below the supply voltages VDD or VSS, an input current may flow; this current
must not exceed ±0.5 mA.

6. Tested on sample basis.

f

SCL

= 32 kHz; T

MRB012

V (V)

DD

amb

=25°C.

12

handbook, halfpage

I

DDO

(µA)

8

4

0

0

246

Fig.20 Typical supply current in clock mode as a function of supply voltage.

1997 Jul 15 19

Philips Semiconductors Product specification

Clock/calendar with 240 × 8-bit RAM PCF8583

13 AC CHARACTERISTICS

V

= 2.5 to 6.0 V; VSS= 0 V; T

DD

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Oscillator

C

osc

integrated oscillator
capacitance

∆f

f

osc

i

oscillator stability for ∆VDD= 100 mV;

input frequency note 1 −−1 MHz

Quartz crystal parameters (f = 32.768 kHz)

R

s

C

L

C

T

2

C-bus timing (see Fig.21; notes 2 and 3)

I

f

SCL

t

SP

t

BUF

t

SU;STA

t

HD;STA

t

LOW

t

HIGH

t

r

t

f

t

SU;DAT

t

HD;DAT

t

VD;DAT

t

SU;STO

series resistance −−40 kΩ
parallel load capacitance − 10 − pF
trimmer capacitance 5 − 25 pF

SCL clock frequency −−100 kHz
tolerable spike width on bus −−100 ns
bus free time 4.7 −−µs
START condition set-up time 4.7 −−µs
START condition hold time 4.0 −−µs
SCL LOW time 4.7 −−µs
SCL HIGH time 4.0 −−µs
SCL and SDA rise time −−1.0 µs
SCL and SDA fall time −−0.3 µs
data set-up time 250 −−ns
data hold time 0 −−ns
SCL LOW to data out valid −−3.4 µs
STOP condition set-up time 4.0 −−µs

= −40 to +85 °C; unless otherwise specified.

amb

T

=25°C; VDD= 1.5 V

amb

− 40 − pF

− 2 × 10

−7

−

Notes

1. Event counter mode only.

2. All timing values are valid within the operating supply voltage and ambient temperature range and reference to V
and VIH with an input voltage swing of VSS to VDD.

3. A detailed description of the I2C-bus specification, with applications, is given in brochure

use it”

. This brochure may be ordered using the code 9398 393 40011.

“The I2C-bus and how to

1997 Jul 15 20

IL

Philips Semiconductors Product specification

Clock/calendar with 240 × 8-bit RAM PCF8583

handbook, full pagewidth

PROTOCOL

SCL

SDA

CONDITION

t

SU;STA

t

BUF

START

(S)

t

HD;STA

t

LOW

t

r

BIT 7

MSB
(A7)

t

HIGH

t

f

t

SU;DAT

BIT 6

(A6)

1 / f

Fig.21 I2C-bus timing diagram; rise and fall times refer to VIL and VIH.

14 APPLICATION INFORMATION

14.1 Quartz frequency adjustment

14.1.1 M

ETHOD 1: FIXED OSCI CAPACITOR

By evaluating the average capacitance necessary for the
application layout a fixed capacitor can be used.
The frequency is best measured via the 1 Hz signal
available after power-on at the interrupt output (pin 7).
The frequency tolerance depends on the quartz crystal
tolerance, the capacitor tolerance and the
device-to-device tolerance (on average ±5 × 10−6).
Average deviations of ±5 minutes per year can be
achieved.

14.1.2 M

ETHOD 2: OSCI TRIMMER

SCL

t

HD;DAT

BIT 0

(R/W)

LSB

t

VD;DAT

ACKNOWLEDGE

(A)

MBD820

STOP

CONDITION

(P)

Procedure:

• Power-on

• Initialization (alarm functions).

Routine:

• Set clock to time T and set alarm to time T + dT

• At time T + dT (interrupt) repeat routine.

14.1.3 M

ETHOD 3:

Direct measurement of OSC out (accounting for test probe
capacitance).

The PCF8583 slave address has a fixed combination 1010
as group 1.

t

SU;STO

Using the alarm function (via the I2C-bus) a signal faster
than 1 Hz can be generated at the interrupt output for fast
setting of a trimmer.

1997 Jul 15 21

Philips Semiconductors Product specification

Clock/calendar with 240 × 8-bit RAM PCF8583

V

DD

handbook, full pagewidth

SDA

MASTER

V

DD

A0

CLOCK

CALENDAR

OSCI

PCF8583

'1010'

OSCO

V

DD

1

V

DD

A0

OSCI

OSCO

EVENT

COUNTER

PCF8583

'1010'

SCL

SDA

V

SS

SCL

SDA

V

SS

TRANSMITTER

SCL

V

DD

RR

R: pull-up resistor
R = t

/ C-bus

rise

SDA SCL

(I C-bus)

Fig.22 Application diagram.

1997 Jul 15 22

2

MRB018

Philips Semiconductors Product specification

Clock/calendar with 240 × 8-bit RAM PCF8583

15 PACKAGE OUTLINES

DIP8: plastic dual in-line package; 8 leads (300 mil)

D

seating plane

A

L

Z

e

b

8

pin 1 index

1

w M

b

1

b

2

5

SOT97-1

M

E

A

2

A

c

(e )

1

M

H

E

1

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

A

A

A

UNIT

max.

mm

inches

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

OUTLINE
VERSION

SOT97-1

12

min.

max.

050G01 MO-001AN

b

1.73

1.14

0.068

0.045

IEC JEDEC EIAJ

0.53

0.38

0.021

0.015

b

1

1.07

0.89

0.042

0.035

4

0 5 10 mm

scale

b

REFERENCES

cD E e M

2

0.36

9.8

0.23

9.2

0.014

0.39

0.009

0.36

1997 Jul 15 23

(1) (1)

6.48

6.20

0.26

0.24

L

e

1

M

3.60

8.25

3.05

7.80

0.14

0.32

0.12

0.31

EUROPEAN

PROJECTION

E

10.0

0.39

0.33

H

8.3

w

max.

0.2542.54 7.62

1.154.2 0.51 3.2

0.010.10 0.30

0.0450.17 0.020 0.13

ISSUE DATE

92-11-17
95-02-04

(1)

Z

Philips Semiconductors Product specification

Clock/calendar with 240 × 8-bit RAM PCF8583

SO8: plastic small outline package; 8 leads; body width 7.5 mm

D

c

y

Z

8

pin 1 index

1

e

5

A

2

A

1

4

w M

b

p

E

H

E

detail X

SOT176-1

A

X

v M

A

Q

(A )

L

p

L

A

3

θ

0 5 10 mm

scale

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

mm

OUTLINE
VERSION

SOT176-1

A

max.

2.65

0.10

A1A2A

0.3

2.45

0.1

2.25

0.012

0.096

0.004

0.089

IEC JEDEC EIAJ

0.25

0.01

b

3

p

0.49

0.32

0.36

0.23

0.019

0.013

0.014

0.009

UNIT

inches

Note

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

(1)E(1)

cD

7.65

7.45

0.30

0.29

REFERENCES

7.6

7.4

0.30

0.29

1.27

0.050

1997 Jul 15 24

eHELLpQywv θ

1.45

0.057

1.1

0.45

0.043

0.018

1.1

1.0

0.043

0.039

0.25 0.1

0.25

0.01 0.004

0.01

EUROPEAN

PROJECTION

10.65

10.00

0.419

0.394

(1)

Z

2.0

1.8

0.079

0.071

ISSUE DATE

95-02-25
97-05-22

o

8

o

0

Philips Semiconductors Product specification

Clock/calendar with 240 × 8-bit RAM PCF8583

16 SOLDERING

16.1 Introduction

There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.

This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our

“IC Package Databook”

(order code 9398 652 90011).

16.2 DIP

16.2.1 SOLDERING BY DIPPING OR BY WAVE

The maximum permissible temperature of the solder is
260 °C; solder at this temperature must not be in contact
with the joint for more than 5 seconds. The total contact
time of successive solder waves must not exceed
5 seconds.

The device may be mounted up to the seating plane, but
the temperature of the plastic body must not exceed the
specified maximum storage temperature (T

stg max

). If the
printed-circuit board has been pre-heated, forced cooling
may be necessary immediately after soldering to keep the
temperature within the permissible limit.

16.2.2 R

EPAIRING SOLDERED JOINTS

Apply a low voltage soldering iron (less than 24 V) to the
lead(s) of the package, below the seating plane or not
more than 2 mm above it. If the temperature of the
soldering iron bit is less than 300 °C it may remain in
contact for up to 10 seconds. If the bit temperature is
between 300 and 400 °C, contact may be up to 5 seconds.

16.3 SO

16.3.1 REFLOW SOLDERING
Reflow soldering techniques are suitable for all SO

packages.

Several techniques exist for reflowing; for example,
thermal conduction by heated belt. Dwell times vary
between 50 and 300 seconds depending on heating
method. Typical reflow temperatures range from
215 to 250 °C.

Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 minutes at
45 °C.

16.3.2 W

AVE SOLDERING

Wave soldering techniques can be used for all SO
packages if the following conditions are observed:

• A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave) soldering
technique should be used.

• The longitudinal axis of the package footprint must be
parallel to the solder flow.

• The package footprint must incorporate solder thieves at
the downstream end.

During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.

Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
6 seconds. Typical dwell time is 4 seconds at 250 °C.

A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.

16.3.3 R

EPAIRING SOLDERED JOINTS

Fix the component by first soldering two diagonally­opposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320 °C.

Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.

1997 Jul 15 25

Philips Semiconductors Product specification

Clock/calendar with 240 × 8-bit RAM PCF8583

17 DEFINITIONS

Data sheet status

Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

18 LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.

19 PURCHASE OF PHILIPS I

Purchase of Philips I
components in the I2C system provided the system conforms to the I2C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.

2

C COMPONENTS

2

C components conveys a license under the Philips’ I2C patent to use the

1997 Jul 15 26

Philips Semiconductors Product specification

Clock/calendar with 240 × 8-bit RAM PCF8583

NOTES

1997 Jul 15 27

Philips Semiconductors – a worldwide company

Argentina: see South America
Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113,

Tel. [phone], Fax. [phone]
Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213, Tel. [phone],

Fax. [phone]
Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6,

220050 MINSK, Tel. [phone], Fax. [phone]

Belgium: see The Netherlands
Brazil: see South America
Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor,

51 James Bourchier Blvd., 1407 SOFIA,
Tel. [phone], Fax. [phone]

Canada: PHILIPS SEMICONDUCTORS/COMPONENTS,
Tel. [phone]

China/Hong Kong: 501 Hong Kong Industrial Technology Centre,
72 Tat Chee Avenue, Kowloon Tong, HONG KONG,
Tel. [phone], Fax. [phone]

Colombia: see South America
Czech Republic: see Austria
Denmark: Prags Boulevard 80, PB 1919, DK-2300 COPENHAGEN S,

Tel. [phone], Fax. [phone]
Finland: Sinikalliontie 3, FIN-02630 ESPOO,

Tel. [phone], Fax. [phone]
France: 4 Rue du Port-aux-Vins, BP317, 92156 SURESNES Cedex,

Tel. [phone], Fax. [phone]
Germany: Hammerbrookstraße 69, D-20097 HAMBURG,

Tel. [phone], Fax. [phone]
Greece: No. 15, 25th March Street, GR 17778 TAVROS/ATHENS,

Tel. [phone], Fax. [phone]

Hungary: see Austria
India: Philips INDIA Ltd, Band Box Building, 2nd floor,

254-D, Dr. Annie Besant Road, Worli, MUMBAI 400 025,
Tel. [phone], Fax. [phone]

Indonesia: see Singapore
Ireland: Newstead, Clonskeagh, DUBLIN 14,

Tel. [phone], Fax. [phone]
Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053,

TEL AVIV 61180, Tel. [phone], Fax. [phone]
Italy: PHILIPS SEMICONDUCTORS, Piazza IV Novembre 3,

20124 MILANO, Tel. [phone], Fax. [phone]
Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku, TOKYO 108,

Tel. [phone], Fax. [phone]
Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL,

Tel. [phone], Fax. [phone]
Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR,

Tel. [phone], Fax. [phone]
Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905,

Tel. [phone]

Middle East: see Italy

Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB,

Tel. [phone], Fax. [phone]
New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND,

Tel. [phone], Fax. [phone]
Norway: Box 1, Manglerud 0612, OSLO,

Tel. [phone], Fax. [phone]
Philippines: Philips Semiconductors Philippines Inc.,

106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI,
Metro MANILA, Tel. [phone], Fax. [phone]

Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA,
Tel. [phone], Fax. [phone]

Portugal: see Spain
Romania: see Italy
Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW,

Tel. [phone], Fax. [phone]
Singapore: Lorong 1, Toa Payoh, SINGAPORE 1231,

Tel. [phone], Fax. [phone]

Slovakia: see Austria
Slovenia: see Italy
South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale,

2092 JOHANNESBURG, P.O. Box 7430 Johannesburg 2000,
Tel. [phone], Fax. [phone]

South America: Rua do Rocio 220, 5th floor, Suite 51,
04552-903 São Paulo, SÃO PAULO - SP, Brazil,
Tel. [phone], Fax. [phone]

Spain: Balmes 22, 08007 BARCELONA,
Tel. [phone], Fax. [phone]

Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM,
Tel. [phone], Fax. [phone]

Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH,
Tel. [phone], Fax. [phone]

Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1,
TAIPEI, Taiwan Tel. [phone], Fax. [phone]

Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd.,
209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260,
Tel. [phone], Fax. [phone]

Turkey: Talatpasa Cad. No. 5, 80640 GÜLTEPE/ISTANBUL,
Tel. [phone], Fax. [phone]

Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7,
252042 KIEV, Tel. [phone], Fax. [phone]

United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes,
MIDDLESEX UB3 5BX, Tel. [phone], Fax. [phone]

United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,
Tel. [phone]

Uruguay: see South America
Vietnam: see Singapore
Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,

Tel. [phone], Fax.[phone]

For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications,
Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. [phone]

© Philips Electronics N.V. 1997 SCA55
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.

Internet: http://www.semiconductors.philips.com

Printed in The Netherlands 417067/00/05/pp28 Date of release: 1997 Jul 15 Document order number: 9397 750 02588