NXP PCF8574ATS/3 Datasheet

PCF8574; PCF8574A

Remote 8-bit I/O expander for I2C-bus with interrupt

Rev. 5 — 27 May 2013 Product data sheet

1. General description

The PCF8574/74A provides general-purpose remote I/O expansion via the two-wire bidirectional I

The devices consist of eight quasi-bidirectional ports, 100 kHz I hardware address inputs and interrupt output operating between 2.5 V and 6 V. The quasi-bidirectional port can be independently assigned as an input to monitor interrupt status or keypads, or as an output to activate indicator devices such as LEDs. System master can read from the input port or write to the output port through a single register.

The low current consumption of 2.5 A (typical, static) is great for mobile applications and the latched output ports directly drive LEDs.

The PCF8574 and PCF8574A are identical, except for the different fixed portion of the slave address. The three hardware address pins allow eight of each device to be on the same I the same I

The active LOW open-drain interrupt output (INT of the microcontroller and is activated when any input state dif fers from its corresponding input port register state. It is used to indicate to the microcontroller that an input state has changed and the device needs to be interrogate d without the m icrocontroller continuously polling the input register via the I

The internal Power-On Reset (POR) initializes the I/Os as inputs with a weak internal pull-up 100 A current source.

C-bus (serial clock (SCL), serial data (SDA)).

C-bus interface, three

C-bus, so there can be up to 16 of th ese I/O exp anders PCF8574/74 A together on

C-bus, supporting up to 128 I/Os (for example, 128 LEDs).

) can be connected to the interrupt logic

C-bus.

2. Features and benefits

 I2C-bus to parallel port expander  100 kHz I  Operating supply voltage 2.5 V to 6 V with non-overvoltage tolerant I/O held to V

with 100 A current source

 8-bit remote I/O pins that default to inputs at power-up  Latched outputs directly drive LEDs  Total package sink capability of 80 mA  Active LOW open-drain interrupt output  Eight programmable slave addresses using three address pins  Low standby current (2.5 A typical)  40 C to +85 C operation  ESD protection exceeds 2000 V HBM per JESD22-A114 and 1000 V CDM per

JESD22-C101

C-bus interface (Standard-mode I2C-bus)

NXP Semiconductors

 Latch-up testing is done to JEDEC standard JESD78 which exceeds 100 mA  Packages offered: DIP16, SO16, SSOP20

3. Applications

 LED signs and displays  Servers  Key pads  Industrial control  Medical equipment  PLC  Cellular telephones  Mobile devices  Gaming machines  Instrumentation and test measurement

4. Ordering information

PCF8574; PCF8574A

Remote 8-bit I/O expander for I2C-bus with interrupt

Table 1. Ordering information

Type number T opside mark Package

PCF8574P PCF8574P DIP16 plastic dual in-line package; 16 leads (300 mil) SOT38-4 PCF8574AP PCF8574AP PCF8574T/3 PCF8574T SO16 plastic small outline package; 16 leads; body width 7.5 mm SOT162-1 PCF8574AT/3 PCF8574AT PCF8574TS/3 8574TS SSOP20 plastic shrink small outline package; 20 leads; PCF8574ATS/3 8574A

Name Description Version

SOT266-1

body width 4.4 mm

4.1 Ordering options

Table 2. Ordering options

Type number Orderable

PCF8574P PCF8574P,112 DIP16 Standard marking

PCF8574AP PCF8574AP,112 DIP16 Standard marking

PCF8574T/3 PCF8574T/3,512 SO16 Standard marking

PCF8574AT/3 PCF8574AT/3,512 SO16 Standard marking

Package Packing method Minimum

part number

* IC’s tube - DSC bulk pack

* tube dry pack

PCF8574T/3,518 SO16 Reel 13” Q1/T1

*standard mark SMD dry pack

* tube dry pack

PCF8574AT/3,518 SO16 Reel 13” Q1/T1

*standard mark SMD dry pack

order quantity

1000 T

1920 T

1000 T

1920 T

1000 T

Temperature range

= 40 C to +85 C

amb

= 40 C to +85 C

amb

= 40 C to +85 C

amb

= 40 C to +85 C

amb

= 40 C to +85 C

amb

= 40 C to +85 C

amb

Product data sheet Rev. 5 — 27 May 2013 2 of 33

NXP Semiconductors

002aac109

write pulse

read pulse

power-on reset

data from Shift Register

trt(pu)

100 μA

P0 to P7

data to Shift Register

to interrupt logic

Remote 8-bit I/O expander for I2C-bus with interrupt

Table 2. Ordering options …continued

Type number Orderable

part number

PCF8574TS/3 PCF8574TS/3,112 SSOP20 Standard marking

PCF8574TS/3,118 SSOP20 Reel 13” Q1/T1

PCF8574ATS/3 PCF8574ATS/3,118 SSOP20 Reel 13” Q1/T1

Package Packing method Minimum

* IC’s tube - DSC bulk pack

*standard mark SMD

5. Block diagram

PCF8574 PCF8574A

INT

LP FILTER

PCF8574; PCF8574A

Temperature range order quantity

1350 T

2500 T

INTERRUPT

LOGIC

= 40 C to +85 C

amb

= 40 C to +85 C

amb

= 40 C to +85 C

amb

A0 A1

A2 SCL SDA

Fig 1. Block diagram

INPUT

FILTER

POWER-ON

RESET

C-BUS

CONTROL

SHIFT

write pulse read pulse

8 bits

I/O

PORT

002aad624

P0 P1 P2 P3 P4 P5 P6 P7

Product data sheet Rev. 5 — 27 May 2013 3 of 33

Fig 2. Simplified schematic diagram of P0 to P7

NXP Semiconductors

PCF8574P

PCF8574AP

A0 V

A1 SDA

A2 SCL

P0 INT

P1 P7

P2 P6

P3 P5

002aad625

A0 V

A1 SDA A2 SCL P0 INT P1 P7 P2 P6 P3 P5

PCF8574T/3

PCF8574AT/3

002aad626

1 2 3 4 5 6 7 8

12 11

14 13

16 15

6. Pinning information

6.1 Pinning

PCF8574; PCF8574A

Remote 8-bit I/O expander for I2C-bus with interrupt

Fig 3. Pin configuration for DIP16 Fig 4. Pin configuration for SO16 Fig 5. Pin configuration for

6.2 Pin description

Table 3. Pin description

Symbol Pin Description

DIP16, SO16 SSOP20

A0 1 6 address input 0 A1 2 7 address input 1 A2 3 9 address input 2 P0 4 10 quasi-bidirectional I/O 0 P1 5 11 quasi-bidirectional I/O 1 P2 6 12 quasi-bidirectional I/O 2 P3 7 14 quasi-bidirectional I/O 3 V

P4 9 16 quasi-bidirectional I/O 4 P5 10 17 quasi-bidirectional I/O 5 P6 11 19 quasi-bidirectional I/O 6 P7 12 20 quasi-bidirectional I/O 7 INT SCL 14 2 serial clock line SDA 15 4 serial data line V

n.c. - 3, 8, 13, 18 not connected

8 15 supply ground

13 1 interrupt output (active LOW)

16 5 supply voltage

INT

SCL P6

n.c. n.c.

SDA P5

A0 A1 P3

n.c. n.c.

A2 P2 P0 P1

6 7 8 9

PCF8574TS/3

PCF8574ATS/3

002aad627

20 19 18 17 16 15 14 13 12 11

SSOP20

P4 V

Product data sheet Rev. 5 — 27 May 2013 4 of 33

NXP Semiconductors

R/W

002aad628

0 1 0 0 A2 A1 A0

hardware

selectable

slave address

fixed

R/W

002aad629

0 1 1 1 A2 A1 A0

hardware

selectable

slave address

fixed

7. Functional description

Refer to Figure 1 “Block diagram”.

7.1 Device address

Following a START condition, the bus master must send the address of th e slav e it is accessing and the operation it wants to perform (rea d or write) . The address for mat of th e PCF8574/74A is shown in Figure 6 LOW to choose one of eight slave addresses. To conserve power, no internal pull-up resistors are incorporated on A2, A1 or A0, so they must be externally held HIGH or LOW. The address pins (A2, A1, A0) can connect to V

PCF8574; PCF8574A

Remote 8-bit I/O expander for I2C-bus with interrupt

. Slave address pins A2, A1 and A0 are held HIGH or

or VSS directly or through resistors.

a. PCF8574 b. PCF8574A

Fig 6. PCF8574 and PCF8574A slave addresses

The last bit of the first byte defines the operation to be performed. When set to logic 1 a read is selected, while a logic 0 selects a write operation (write operation is shown in

Figure 6

7.1.1 Address maps

The PCF8574 and PCF8574A are functionally the sam e, but have a d if ferent fixed portio n (A6 to A3) of the slave address. This allows eight of the PCF8574 and eight of the PCF8574A to be on the same I

T able 4. PCF8574 address map

Pin connectivity Address of PCF8574 Address byte value 7-bit

A2 A1 A0 A6 A5 A4 A3 A2 A1 A0 R/W Write Read

SSVSSVSS

SSVSSVDD

SSVDDVSS

SSVDDVDD

DDVSSVSS

DDVSSVDD

DDVDDVSS

DDVDDVDD

C-bus without address conflict.

hexadecimal

address

without R/W

0100000 - 40h 41h 20h 0100001 - 42h 43h 21h 0100010 - 44h 45h 22h 0100011 - 46h 47h 23h 0100100 - 48h 49h 24h 0100101 - 4Ah 4Bh 25h 0100110 - 4Ch 4Dh 26h 0100111 - 4Eh 4Fh 27h

Product data sheet Rev. 5 — 27 May 2013 5 of 33

NXP Semiconductors

Table 5. PCF8574 A add ress map

Pin connectivity Address of PCF8574A Address byte value 7-bit

A2 A1 A0 A6 A5 A4 A3 A2 A1 A0 R/W Write Read

SSVSSVSS

SSVSSVDD

SSVDDVSS

SSVDDVDD

DDVSSVSS

DDVSSVDD

DDVDDVSS

DDVDDVDD

8. I/O programming

PCF8574; PCF8574A

Remote 8-bit I/O expander for I2C-bus with interrupt

hexadecimal

address

without R/W

0111000 - 70h 71h 38h 0111001 - 72h 73h 39h 0111010 - 74h 75h 3Ah 0111011 - 76h 77h 3Bh 0111100 - 78h 79h 3Ch 0111101 - 7Ah 7Bh 3Dh 0111110 - 7Ch 7Dh 3Eh 0111111 - 7Eh 7Fh 3Fh

8.1 Quasi-bidirectional I/Os

A quasi-bidirectional I/O is an input or output port without using a direction control register. Whenever the master reads the register, the value returned to master depends on the actual voltage or status of the pin. At power on, all the ports are HIGH with a weak 100 A internal pull-up to V

, but can be driven LOW by an internal transistor, or an external

signal. The I/O ports are entirely independent of each other, but each I/O octal is controlled by the same read or write data byte.

Advantages of the quasi-bidirectional I/O over totem pole I/O inc lud e:

• Better for driving LEDs since the p-channel (transistor to V

) is small, which saves

die size and therefore cost. LED drive only requires an internal transistor to ground, while the LED is connected to V

through a current-limiting resistor. To tem pole I/O

have both n-channel and p-channel tran sistors, which allow solid HIGH and LOW output levels without a pull-up resistor — good for logic levels.

• Simp ler architectu re — only a single register and the I/O can be both inpu t and o utput

at the same time. Totem pole I/O have a direction re gis te r tha t spe cif ies the po rt pin direction and it is always in that configuration unless the direction is explicitly changed.

• Does not require a command byte. The simplicity of one register (no need for the

pointer register or, technically, the command byte) is an advantage in some embedded systems where every byte counts because of memory or bandwidth limitations.

Product data sheet Rev. 5 — 27 May 2013 6 of 33

NXP Semiconductors

002aah683

weak 100 µA

current source

(inactive when

output LOW)

output HIGH

output LOW

accelerator pull-up

P port

P7 - P0

pull-down with

resistor to V

external drive LOW

input LOW

pull-up with

resistor to V

external drive HIGH

input HIGH

There is only one register to control four possibilities of the port pin: Input HIGH, input LOW, output HIGH, or output LOW.

Input HIGH: The master needs to write 1 to the register to set the po rt as an input mode if the device is not in the default power-on condition. The master reads the register to check the input status. If the external source pulls the port pin up to V logic 1, then the master will read the value of 1.

Input LOW: The master needs to write 1 to the register to set the port to input mode if the device is not in the default power-on condition. The master reads the register to check the input status. If the external source pulls the port pin down to V logic 0, which sinks the weak 100 A current source, then the master will read the value of 0.

Output HIGH: The master writes 1 to the register. There is an additional ‘accelerator’ or strong pull-up current when the master sets the port HIGH. The additional strong pull-up is only active during the HIGH time of the acknowledge clock cycle. This accelerator current helps the port’s 100 A current source make a faster rising edge into a heavily loaded output, but only at the start of the acknowledge clock cycle to avoid bus contention if an external signal is pulling the port LOW to V logic 0 at the same time. After the half clock cycle there is only the 100 A current source to hold the port HIGH.

Output LOW: The master writes 0 to the register. There is a strong current sink transistor that holds the port pin LOW. A large current may flow into the port, which could potentially damage the part if the master writes a 0 to the register and an external source is pulling the port HIGH at the same time.

PCF8574; PCF8574A

Remote 8-bit I/O expander for I2C-bus with interrupt

or drives

/driving the port with

Product data sheet Rev. 5 — 27 May 2013 7 of 33

Fig 7. Simple quasi-bidirectional I/O

NXP Semiconductors

A5 A4 A3 A2 A1 A0 0 ASA6

slave address

START condition R/W

acknowledge from slave

002aah349

P6 1P7

data 1

acknowledge from slave

12345678SCL 9

SDA

acknowledge from slave

write to port

data output from port

v(Q)

data 2

DATA 2 VALID

P4 P3 P2 P1 P0 P7 P4 P3 P2 P1 P0P6P50

v(Q)

DATA 1 VALID

P5 output voltage

trt(pu)

P5 pull-up output current

d(rst)

INT

8.2 Writing to the port (Output mode)

The master (microcontroller) sends the START condition and slave address setting the last bit of the address byte to logic 0 for the write mode. The PCF8574/74A acknowledges and the master then sends the data byte for P7 to P0 to the port register. As the clock line goes HIGH, the 8-bit data is presented on the port lines after it has been acknowledged by the PCF8574/74A. If a LOW is written, the strong pull-down turns on and stays on. If a HIGH is written, the strong pull-up turns on for HIGH by the weak current source. The master can th en sen d a STOP or ReSTART condition or continue sending data. The number of data bytes that can be sent successively is not limited and the previous data is overwritten every time a data byte has been sent and acknowledged.

Ensure a logic 1 is written for any port that is being used as an input to ensure the strong external pull-down is turned off.

PCF8574; PCF8574A

Remote 8-bit I/O expander for I2C-bus with interrupt

⁄2of the clock cycle, then the line is held

Fig 8. Write mode (output)

Product data sheet Rev. 5 — 27 May 2013 8 of 33

Simple code WRITE mode:

Remark: Bold type = generated by slave device.

NXP Semiconductors

8.3 Reading from a port (Input mode)

The port must have been previously written to logic 1, which is the condition after power-on reset. To enter the Read mode the master (microcontroller) addresses the slave device and sets the last bit of the address byte to logic 1 (address byte read). The slave will acknowledge and then send the data byte to the master. The master will NACK and then send the STOP condition or ACK and read the input register again.

The read of any pin being used as an output will indicate HIGH or LOW depending on the actual state of the pin.

If the data on the input port changes faster than the master can read, this data may be lost. The DATA 2 and DATA3 are lost becau se these dat a did no t meet the setu p time and hold time (see Figure 9

slave address

PCF8574; PCF8574A

Remote 8-bit I/O expander for I2C-bus with interrupt

no acknowledge

data from port

from master

SDA 1

read from

port

data at

port

INT

A LOW-to-HIGH transition of SDA while SCL is HIGH is defined as the STOP condition (P). Transfer of data can be stopped at any moment by a STOP condition. When this occurs, data present at the last acknowledge phase is valid (output mode). Input data is lost.

A5 A4 A3 A2 A1 A0 1 ASA6

START condition R/W acknowledge

v(INT)

Fig 9. Read mode (input)

Simple code for Read mode:

Remark: Bold type = generated by slave device.

8.4 Power-on reset

DATA 1

h(D)

from slave

rst(INT)

DATA 2

DATA 1

DATA 3

su(D)

acknowledge from master

rst(INT)

DATA 4

STOP condition

002aah383

When power is applied to VDD, an internal Power-On Reset (POR) holds the PCF8574/74A in a reset condition until V condition is released and the PCF8574/74A registers and I will initialize to their default states of all I/Os to inputs with weak current source to V Thereafter V

must be lowered below V

has reached V

and back up to the operation voltage for

POR

. At that point, the reset

POR

C-bus/SMBus state machine

power-on reset cycle.

Product data sheet Rev. 5 — 27 May 2013 9 of 33

NXP Semiconductors

002aad634

MICROCONTROLLER

INT

PCF8574

INT

PCF8574

INT

device 1 device 2

PCF8574A

INT

device 16

8.5 Interrupt output (INT)

The PCF8574/74A provides an open-drain output (INT) which can be fed to a corresponding input of the microcontroller (see Figure 10 changed, the INT

PCF8574; PCF8574A

Remote 8-bit I/O expander for I2C-bus with interrupt

). As soon as a port input is

will be active (LOW) and notify the microcontroller.

An interrupt is generated at any rising or falling edge of the port inputs. After time t signal INT

is valid.

v(Q)

, the

The interrupt will reset to HIGH when data on the port is changed to the original setting or data is read or written by the master.

In the Write mode, the interrupt may be reset (HIGH) on the rising edge of the acknowledge bit of the address byte and also on the rising edge of the write to port pulse. The interrupt will always be reset (HIGH) on the falling edge of the write to port pulse (see

Figure 8

The interrupt is reset (HIGH) in the Read mode on the rising edge of the read from port pulse (see Figure 9

During the interrupt reset, any I/O change close to the read or write pulse may not generate an interrupt, or the interrupt will have a very short pulse. After the interrupt is reset, any change in I/Os will be detected and transmitted as an INT

At power-on reset all ports are in Input mode and the initial state of the ports is HIGH, therefore, for any port pin that is pulled LOW or driven LOW by external source, the interrupt output will be active (output LOW).

Product data sheet Rev. 5 — 27 May 2013 10 of 33

Fig 10. Application of multiple PCF8574/74As wi th inte rrupt

+ 23 hidden pages

NXP PCF8574ATS/3 Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual

1. General description

2. Features and benefits

3. Applications

4. Ordering information

4.1 Ordering options

5. Block diagram

6. Pinning information

6.1 Pinning

6.2 Pin description

7. Functional description

7.1 Device address

7.1.1 Address maps

8. I/O programming

8.1 Quasi-bidirectional I/Os

8.2 Writing to the port (Output mode)

8.3 Reading from a port (Input mode)

8.4 Power-on reset

8.5 Interrupt output (INT)