NXP PCA9646 Technical data

PCA9646

Buffered 4-channel 2-wire bus switch

Rev. 1 — 1 March 2011 Product data sheet

1. General description

The PCA9646 is a monolithic CMOS integrated circuit for 2-wire bus buffering and
switching in applications including I
similar principles.

Each of the four outputs may be inde pendently enabled i n any combination as d etermined
by the contents of the programmable control register. Each I/O is impedance isolated from
all others, thus allowing a total of five branches of 2-wire bus with the maximum specified
load (e.g., 5  400 pF for Fm+ I
(Ref. 1

). More than one PCA9646 may be used in series, providing a substantial fan-o ut

capability.
As per the PCA9525 and PCA9605 simple bus buffers, the PCA9646 includes a

unidirectional buffer for the clock signal, and a bidirectional buffer for the data signal. The
direction of the clock signal may also be set by the contents of the programmable control
register. Clock stretching and timing must always be under control of the master device.

The PCA9646 has excellent application to 2-wire bus address expansion and increasing
of maximum load capacitance. Very large LED displays are a perfect example.

2. Features and benefits

 Drop-in pin compatible with PCA9546A, etc.
 Each I/O is impedance isolated from all others allowing maximum capacitance on all

branches

 30 mA static sink capability on all ports
 Works with I

SMBus (standard and high power mode) , and PMBus

 Fast switching times allow operation in excess of 1 MHz
 Allows driving of large loads (e.g., 5  4nF)
 Hysteresis on I/O increases noise immunity
 Operating voltages from 2.7 V to 5.5 V
 Uncomplicated characteristics suitable for quick implementation in most common

2-wire bus applications

2

C-bus, SMBus, PMBus, and other systems based on

2

C-bus at 1 MHz, or 5  4 nF at lower frequencies)

2

C-bus (Standard-mode, Fast-mode, and Fast-mode Plus (Fm+)),

3. Applications

 Large arrays of I2C-bus components, e.g., LED displays
 Power management systems
 Game consoles, computers, RAID systems

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R4

002aaf367

I2C-BUS

CONTROL

5

7

10

12

4

6

9

11

SC0

SC1

SC2

SC3

SD0

SD1

SD2

SD3

R3 R5 R6 R7 R8 R9 R10

V

DD

16

FILTER

1 A0
2 A1

13 A2

14

15

3

SCL

SDA

RESET

R2R1

2.7 V to 5.5 V

PCA9646

V

SS

8

4. Ordering information

PCA9646

Buffered 4-channel 2-wire bus switch

mark

Package
Name Description Version

Table 1. Ordering information

Type number Topside

PCA9646D PCA9646 SO16 plastic small outline package; 16 leads; body width3.9 mm SOT109-1
PCA9646PW PCA9646 TSSOP16 plastic thin shrink small outline package; 16 leads;

SOT403-1

body width 4.4 mm

5. Block diagram

Fig 1. Simplified block diagram of PCA9646

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Product data sheet Rev. 1 — 1 March 2011 2 of 22

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PCA9646D

A0 V

DD

A1 SDA

RESET SCL

SD0 A2

SC0 SC3

SD1 SD3

SC1 SC2

V

SS

SD2

002aaf364

1

2

3

4

5

6

7

8

10

9

12

11

14

13

16

15

PCA9646PW

002aaf366

1
2
3
4
5
6
7
8

10

9

12
11

14
13

16
15

A0 V

DD

A1 SDA

RESET SCL

SD0 A2
SC0 SC3
SD1 SD3
SC1 SC2

V

SS

SD2

6. Pinning information

6.1 Pinning

PCA9646

Buffered 4-channel 2-wire bus switch

Fig 2. Pin configuration for SO16 Fig 3. Pin configuration for TSSOP16

6.2 Pin description

Table 2. Pin description

Symbol Pin Description

A0 1 address input 0
A1 2 address input 1
RESET
SD0 4 serial data 0
SC0 5 serial clock 0
SD1 6 serial data 1
SC1 7 serial clock 1
V

SS

SD2 9 serial data 2
SC2 10 serial clock 2
SD3 11 serial data 3
SC3 12 serial clock 3
A2 13 address input 2
SCL 14 serial clock line (normally input)
SDA 15 serial data line
V

DD

3 active LOW reset input

8 negative supply (ground)

16 positive supply

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Product data sheet Rev. 1 — 1 March 2011 3 of 22

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7. Functional description

Refer to Figure 1 “Simplified block diagram of PCA9646”.

7.1 VDD, VSS — DC supply pins

The power supply voltage for the PCA9646 may be any voltage in the range 2.7 V to

5.5 V. The IC supply must be common with the supply for the bus. Hysteresis on the port s
are a percentage of the IC’s power supply, hence noise margin considerations should be
taken into account when selecting an operating voltage.

7.2 SCL — clock signal input

The clock signal buffer is unidirectional, with this pin acting as the default input. However,
the clock signal direction may be reversed by setting the MSB of the Control register
HIGH. In normal I
signal to the slave. For lowest cost the PCA9646 combines unidirectional buffering of the
clock signal with a bidirectional buffer for the data signal. Clock stretching is therefore not
supported and slave devices that may require clock stretching must be accommodated by
the master adopting an appropriate clocking when communicating with them.

PCA9646

Buffered 4-channel 2-wire bus switch

2

C-bus operations the master device generates a unidirectional clock

The buffer includes hysteresis to ensure clean switching signals are output, especially
with slow rise times on high capacitively loaded buses.

7.3 SC0, SC1, SC2 , SC3 — clock signal outputs

The clock signal from SCL is buffered through four independent buffers, and the signal is
presented at the four SC0 to SC3 ports. Ports are open-drain type and require external
pull-up resistors.

When the MSB of the control register is set HIGH, the port direction is reversed. The
ANDed result of the selected SC0 to SC3 lines is then used to drive the open-dr ain output
of the SCL pin.

7.4 SDA, SD0, SD1, SD2, SD3 — data signal inputs/outputs

The data signal buffers are bidir ectional. The port ( SDA, or any one of SD0 to SD3) which
first falls LOW, will decide the direction of this buf fer and ‘lock out’ signals coming from the
opposite side. As the ‘input’ signal continues to fall, it will then drive the open-drain of the
‘output’ side LOW. Again, hysteresis is applied to the buffer to minimize the effects of
noise. Ports are open-drain type and require external pull-up resistors.

At some points during the communication, the data direction will reverse—for example,
when the slave transmits an acknowledge (ACK) or responds with its register contents.
During these times, the controlling ‘input’ side will have to rise to V
the ‘lock’, which then allows the ‘output’ side to gain control, and pull (what was) the ‘input’
side LOW again. This will cause a ‘pulse’ on the ‘input’ side, which can be quite long
duration in high capacitance buses. However, this pulse will not interfere with the actual
data transmission, as it should not occur during times of clock line transition (during
normal I
still met.

2

C-bus and SMBus protocols), and thus data signal set-up time requ irem ents are

before it releases

unlock

PCA9646 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.

Product data sheet Rev. 1 — 1 March 2011 4 of 22

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002aaf368

1 1 1 0 A2 A1 A0 R/W

fixed externally

selectable

read = 1
write = 0

002aaf369

B7 X X X B3 B2 B1 B0

output channel

enable bits

MSB LSB

SCL direction

0: SCL → SC0 to SC3
1: SC0 to SC3 → SCL

SC0/SD0 enable
SC1/SD1 enable
SC2/SD2 enable
SC3/SD3 enable

7.5 RESET — reset IC to default state

The active LOW RESET input is used to disable the buffer, and reset it to its default state.
The IC should only be disabled when the bus is idle to avoid truncation of commands
which may confuse other devices on the bus.

PCA9646

Buffered 4-channel 2-wire bus switch

The RESET
disabling all output lines SC[0:3] and SD[0:3]. It is the nature of the I

signal will clear the contents of the Control register, which has the effect of

2

C-bus protocol that
devices may become ‘stuck’. T o help in the clearin g of this condition, the PCA9646 can be
reset, and each port brought on-line successively to find the component holding the bus
LOW.

7.6 Power-On Reset (POR)

During power-on, the PCA9646 is internally held in the reset condition for a maximum of
t

= 500 ns. The default condition after reset is for the Control register to be erased

rst

(all zeros), resulting in all output channels being disabled.

7.7 A0, A1, A2 — address lines

The slave address of the PCA9646 is shown in Figure 4. The address pins (A2, A1, A0)
must be driven to a HIGH or LOW level—they are not internally pulled to a default state.

Fig 4. Slave address

The read/write bit must be set LOW to enable a write to the Control register, or HIGH to
read from the Control register.

7.8 Control register

The Control register of the PCA9646 is shown in Figure 5. Each of the four output
channels (SCn/SDn pairs) can be enabled independently, and the direction of the clock
signal can be reversed.

PCA9646 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.

Product data sheet Rev. 1 — 1 March 2011 5 of 22

Fig 5. Control register

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002aaf370

S 1 1 1 0 A2 A1 A0

slave address

0 A B7 X X X B3 B2 B1 B0 A P

Control register

START
condition

R/W acknowledge

from slave

acknowledge

from slave

STOP
condition

002aaf371

S 1 1 1 0 A2 A1 A0

slave address

1 A B7 0 0 0 B3 B2 B1 B0 NA P

Control register

START
condition

R/W acknowledge

from slave

not acknowledge

from master

STOP
condition

A LOW or ‘zero’ bit (B[3:0]) indicates that the respective channel (SC[3:0], SD[3:0]) is
disabled. The default reset condition of the register is all zeros, all channels disabled,
forward direction. A HIGH or ‘one’ bit indicates the respective channel is enabled.

Example: B3 = 1, B2 = 0, B1 = 1, B0 = 0 means channel 3 (SC3/SD3) and channel 1
(SC1/SD1) are enabled, and channel 2 (SC2/SD2) and channel 0 (SC0/SD0) are
disabled.

As each channel is individually buffered, the loads on each are isolated, and therefore
there is no special requirement to keep the sum of the collective capacitances below the
maximum bus capacitance. Instead, each line may have up to the maximum bus
capacitance and be enabled or disabled without affecting the performance of the other
channels.

The Most Significant Bit (MSB) B7 is used to set the direction of the SCL (clock) signal.
The default state is LOW (zero). In this state, the SCL port will act as the input, and the IC
will supply a buffered signal to any of the four output channels (SC0 to SC3) which are
enabled. When B7 is set HIGH (one), the clock signal direction is reversed. The ports
SC0 to SC3 act as inputs, the ANDed combination of the selected signals is buffered and
output on the SCL pin.

PCA9646

Buffered 4-channel 2-wire bus switch

The PCA9646 is always addressable from the SCL/SDA side, regardless of the state of
B7. Any device which can communicate data to the SCL/SDA pins, either by being directly
attached to those pins or by transmitting through the PCA9646 (when B7 = 1), may
address the device and change the control register’s contents. The Control register is only
updated upon receipt of the STOP condition.

8. Bus transaction

A typical I2C-bus write transaction to the PCA9646 is shown in Figure 6. A typical read
transaction is shown in Figure 7

Fig 6. PCA9646 write transaction to Control register

.

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Product data sheet Rev. 1 — 1 March 2011 6 of 22

Fig 7. PCA9646 read transaction from Control register

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9. Limiting values

PCA9646

Buffered 4-channel 2-wire bus switch

Table 3. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol Parameter Conditions Min Max Unit

V

DD

V

I/O

V

I

supply voltage
voltage on an input/output pin pins SDx, SCx
input voltage RESET pin

address pins A2, A1, A0

I

I

input current pins other than SCx/SDx - 20 mA

[1]

0.3 +7 V

[1]

VSS 0.5 +7 V

[1]

VSS 0.5 VDD+0.5 V

[1]

VSS 0.5 VDD+0.5 V

all SCx and SDx - 40 mA

I

SS

P

tot

T

stg

T

amb

[1] Voltages are specified with respect to pin 8 (VSS).

ground supply current - 280 mA
total power dissipation - 300 mW

storage temperature 55 +125 C
ambient temperature operating 40 +85 C

10. Characteristics

Table 4. Characteristics

=40C to +85C; voltages are specified with respect to ground (VSS); VDD= 5.5 V unl ess oth erwise specified.

T

amb

Symbol Parameter Conditions Min Typ Max Unit

Power supply

V

DD

I

DD

2

C-bus ports (SCL, SDA, SC[3:0], SD[3:0])

I

V

I2C-bus

V

IL

V

IH

V

I(hys)

I

LI

I

O(sink)

V

OL

supply voltage operating 2.7 - 5.5 V
supply current quiescent; VI(RESET pin)=0V--1 A

I2C-bus voltage SDx, SCx - - 5.5 V
LOW-level input voltage VDD=2.7V

HIGH-level input voltage VDD=2.7V

hysteresis of input voltage VDD=2.7V

input leakage current pin at VDDor V
output sink current LOW-level; V
LOW-level output voltage IOL=30mA; VDD= 2.7 V - 260 450 mV

Pins SDA, SD0, SD1, SD2, SD3

V

V

lock

unlock

direction lock voltage VDD=2.7V

direction unlock voltage VDD=2.7V

[1]

--0.4V

=5.5V

V

DD

=5.5V

V

DD

=5.5V

V

DD

SS

input < V

Sxx

=30mA; VDD= 5.5 V - 140 275 mV

I

OL

=5.5V

V

DD

=5.5V

V

DD

IL

[1]

--0.5V

[1]

1.2 - - V

[1]

2.0 - - V

[1]

80 - - mV

[1]

200 - - mV
1- +1 A
30 - - mA

[1]

--1.3V

[1]

--3.0V

[1]

2.0 - - V

[1]

4.8 - - V

PCA9646 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.

Product data sheet Rev. 1 — 1 March 2011 7 of 22