NXP PCA9621 Technical data

PCA9621

65 mA 8-bit 2-wire bus output port

Rev. 1 — 9 March 2011 Product data sheet

1. General description

The PCA9621 is a monolithic CMOS integrated circuit for general purpose output drive
configurable from a 2-wire bus interface (including I
systems based on similar principles). Output ports have a 65 mA sink capability, making
them ideal for driving LEDs.

The state of the outputs is determined by a programmable 8-bit register which can be read
and written via signals from the 2-wire bus (e.g., I

The 2-wire bus interface also has 30 mA Fast-mode Plus (Fm+) capability, and
consequently can be run in excess of 1 MHz or up to 4000 pF capacitance. As such, the
PCA9621 can be connected to other 2-wire devices across long cable connections.

It can be mixed with other Fast-mode Plus slaves in systems driven by Fm+ buffers or by
the PCA9646 (fully buffered 4-channel bus switch) to build large scale systems with
high-speed or high-capacitance drive capability, for example large scale LED displays or
controlled lighting.

2. Features and benefits

 8 individually selectable open-drain output ports
 65 mA static sink capability on all output ports
 Ports may be paralleled for up to 500mA drive
 Ideal for simple LED or general purpose output drive
 Fast-mode Plus (30 mA, 4000 pF) 2-wire bus capability
 Works with I

(standard and high power mode), and PMBus

 Fast switching times allow operation in excess of 1 MHz
 Operating voltages from 2.7 V to 5.5 V

2

C-bus, SMBus, PMBus, and other

2

C-bus or similar).

2

C-bus (Standard-mode, Fast-mode, and Fast-mode Plus), SMBus

3. Applications

 LED and 7-segment displays
 Simple high-power (500 mA) LED dimming
 General purpose output
 Instrumentation indicators

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9

4. Ordering information

PCA9621

65 mA 8-bit 2-wire bus output port

mark

Package
Name Description Version

Table 1. Ordering information

T

=−40 to +85°C.

amb

Type number Topside

PCA9621D PCA9621 SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1
PCA9621PW PCA9621 TSSOP16 plastic thin shrink small outline package; 16 leads;

SOT403-1

body width 4.4 mm

5. Block diagram

2.7 V to 5.5 V

V

R2R1

SCL

SDA

RESET 3

A0 1

PCA9621

14

15

FILTER

DD

16

I2C-BUS SLAVE
TRANSCEIVER

4P0

5P1

6P2

7P3

9P4

R4

R3 R5 R6

LED

LED

high
current
LED

R7

R8

R9

A1 2

A2 13

Fig 1. Block diagram of PCA9621

10 P5

11 P6

12 P7

8

V

SS

R10

output

output

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PCA9621 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.

Product data sheet Rev. 1 — 9 March 2011 2 of 18

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6. Pinning information

6.1 Pinning

PCA9621

65 mA 8-bit 2-wire bus output port

1

A0 V

2

A1 SDA

RESET SCL

3

4

P0 A2

PCA9621D

5

P1 P7

6

P2 P6

7

P3 P5

8

V

SS

Fig 2. Pin configuration for SO16 Fig 3. Pin configuration for TSSOP16

6.2 Pin description

Table 2. Pin description

Symbol Pin Description

A0 1 address input 0
A1 2 address input 1
RESET
P0 4 output port 0
P1 5 output port 1
P2 6 output port 2
P3 7 output port 3
V

SS

P4 9 output port 4
P5 10 output port 5
P6 11 output port 6
P7 12 output port 7
A2 13 address input 2
SCL 14 serial clock line
SDA 15 serial data line
V

DD

3 active LOW reset input

8 negative supply (ground)

16 positive supply

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16

DD

15

14

13

12

11

10

9

P4

RESET SCL

1

A0 V

2

A1 SDA

3

4

P0 A2

P1 P7

P2 P6

P3 P5

V

SS

5

6

7

8

PCA9621PW

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16

15

14

13

12

11

10

9

DD

P4

PCA9621 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.

Product data sheet Rev. 1 — 9 March 2011 3 of 18

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7. Functional description

Refer to Figure 1 “Block diagram of PCA9621”.

7.1 VDD, VSS — DC supply pins

The power supply voltage for the PCA9621 may be any voltage in the range 2.7 V to

5.5 V. All other I/Os are clamped to V

7.2 SCL, SDA — 2-wire bus interface

PCA9621

65 mA 8-bit 2-wire bus output port

and VSS through ESD protection diodes.

DD

The state of the output ports is determined by the Control register, which is set and read
via a 2-wire bus interface using I
(Fm+) I

2

C-bus compatible, though the ports contain ESD protection diodes to the posi tive
and negative supplies. Consequently, V
within the V

and VSS supply levels.

DD

2

C-bus style signalling. The interface is Fast-mode Plus

(voltage at SCL and SDA) must remain

I2C-bus

7.3 P0 to P7 — output ports

There are eight open-drain output ports whose state is de termined by the Con trol register.
Programming a ‘1’ or HIGH to the relevant register bit will turn on the corresponding port,
resulting at a LOW or ‘0’ at the port. In the case of LED driving, this would result in the
LED turning ON.

Programming a ‘0’ or LOW in the register turns off the open-drain port, placing it in a
high-impedance mode.

The ports are protected by ESD diodes to the supplies so they must not be driven above
the V

or below the VSS levels.

DD

7.4 RESET — reset IC to default state

The active LOW RESET input is used to disable the buffer and reset it to its default state.
The RESET
ports, and resetting the state of the I

signal will clear the contents of the Control register, turning off all output

2

C-bus slave transceiver block.

7.5 Power-On Reset (POR)

During power-on, the PCA9621 is internally held in the reset condition for a maximum of
t

= 500 ns. The default condition after reset is for the Control register to be erased

rst

(all zeros), resulting in all output ports being off (high-impedance).

PCA9621 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.

Product data sheet Rev. 1 — 9 March 2011 4 of 18

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3

84

7.6 A0, A1, A2 — address lines

The slave address of the PCA9621 is shown in Figure 4. The address pins (A2, A1, A0)
must be driven to a HIGH or LOW level—they are not internally pulled to a default state.

PCA9621

65 mA 8-bit 2-wire bus output port

1 1 0 0 A2 A1 A0 R/W

fixed externally

selectable

read = 1
write = 0

002aaf38

Fig 4. Slave address

The read/write bit must be set LOW to enable a write to the Control register, or HIGH to
read from the Control register.

7.7 Control register

The Control register of the PCA9621 is shown in Figure 5. Each of the four output ports
can be activated independently by setting the appropriate bit in the Control register.

P7 P6 P5 P4 P3 P2 P1 P0MSB LSB

002aaf3

1 = ON (sinking)
0 = OFF (high-impedance)

Fig 5. Control register

A LOW or ‘zero’ bit indicates that the respective channel (P7 to P0) is disabled
(high-impedance). The default reset condition of the register is all zeros, all ports
high-impedance. A HIGH or ‘one’ bit indicates the respective channel is active (sinking).

Example: Programming C1h (1100 0001b) into the Control register results in port s P0, P6
and P7 being ON (sinking) and the remaining ports being OFF (high-impedance).

PCA9621 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.

Product data sheet Rev. 1 — 9 March 2011 5 of 18

NXP Semiconductors

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6

8. Bus transaction

A typical I2C-bus write transaction to the PCA9621 is shown in Figure 6. During a write
transaction, the output ports (P0 to P7) of the PCA9621 are updated upon receipt of the
STOP condition.

PCA9621

65 mA 8-bit 2-wire bus output port

Fig 6. PCA9621 write transaction to Control register

A typical read transaction is shown in Figure 7.

Fig 7. PCA9621 read transaction from Control register

9. Limiting values

slave address

S 1 1 0 0 A2 A1 A0

START
condition

slave address

S 1 1 0 0 A2 A1 A0

START
condition

Control register

0 A P7 P6 P5 P4 P3 P2 P1 P0 A P

R/W acknowledge

from slave

Control register

1 A P7 P6 P5 P4 P3 P2 P1 P0 NA P

R/W acknowledge

from slave

acknowledge

from slave

not acknowledge

from master

STOP
condition

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STOP
condition

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Table 3. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol Parameter Conditions Min Max Unit

V

DD

V

n

I

I

supply voltage
voltage on any other pin
input current output ports (P0 to P7)

[1]

−0.3 +7 V

[1]

VSS− 0.5 VDD+0.5 V

[2]

-100mA
SDA, SCL pins - 40 mA
address pins A0 to A2; RESET

I

SS

P

tot

T

stg

T

amb

[1] Voltages are specified with respect to pin 8 (VSS).
[2] 100 mA for one pin only in the group P0 to P3, and one pin only in the group P4 to P7. Otherwise 70 mA maximum, any pin.

PCA9621 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.

Product data sheet Rev. 1 — 9 March 2011 6 of 18

ground supply current - 550 mA
total power dissipation - 300 mW
storage temperature −55 +125 °C
ambient temperature operating −40 +85 °C

pin - 20 mA