NXP PCA 9600 D Datasheet

PCA9600

Dual bidirectional bus buffer

Rev. 5 — 5 May 2011 Product data sheet

1. General description

The PCA9600 is designed to isolate I2C-bus capacitance, allowing long buses to be driven in point-to-point or multipoint applications of up to 4000 pF. The PCA9600 is a higher-speed version of the P82B96. It creates a non-latching , bidirectional, logic interface between a normal I bus configurations. It can operate at speeds up to at least 1 MHz, and the high drive side is compatible with the Fast-mode Plus (Fm+) specifications.

C-bus and a range of other higher capacitance or different voltage

The PCA9600 features temperature-stabilized logic voltage levels at its SX/SY interface making it suitable for interfacing with buses that have non I such as SMBus, PMBus, or with microprocessors that use those same TTL logic levels.

The separation of the bidirectional I enables the SDA and SCL signals to be transmitted via balanced transmission lines (twisted pairs), or with galvanic isolation using opto or magnetic coupling. The TX and RX signals may be connected together to provide a normal bidirectional signal.

2. Features and benefits

 Bidirectional data transfer of I2C-bus signals  Isolates capacitance allowing 400 pF on SX/SY side and 4000 pF on TX/TY side  TX/TY outputs have 60 mA sink capability for driving low-impedance or high-capacitive

buses

 1 MHz operation on up to 20 meters of wire (see AN10658)  Supply voltage range of 2.5 V to 15 V with I

independent of supply voltage

 Splits I

 Low power supply current  ESD protection exceeds 4500 V HBM per JESD22-A114 and 1400 V CDM per

 Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA  Packages offered: SO8 and TSSOP8 (MSOP8)

C-bus signal into pairs of forward/reverse TX/RX, TY/RY signals for interface with opto-electrical isolators and similar devices that need unidirectional input and output signal paths

JESD22-C101

C-bus-compliant logic levels

C-bus signals into unidirectional TX and RX signals

C-bus logic levels on SX/SY side

NXP Semiconductors

3. Applications

 Interface between I2C-buses operating at different logic levels (for example, 5 V and

3V or 15V)

 Interface between I  Simple conversion of I

hardware, for example, via compatible PCA82C250

 Interfaces with opto-couplers to provide opto-isolation between I

1MHz

 Long distance point-to-point or multipoint architectures

4. Ordering information

Table 1. Ordering information

Type number Package

PCA9600D SO8 plastic small outline package; 8 leads;

PCA9600DP TSSOP8 plastic thin shrink small outline package; 8 leads;

PCA9600

Dual bidirectional bus buffer

C-bus and SMBus (350 μA) standard or Fm+ standard

C-bus SDA or SCL signals to multi-drop differential bus

C-bus nodes up to

Name Description Version

SOT96-1

body width 3.9 mm

SOT505-1

body width 3 mm

4.1 Ordering options

Table 2. Ordering options

Type number Topside mark Temperature range

PCA9600D PCA9600 −40 °C to +85 °C PCA9600DP 9600 −40 °C to +85 °C

5. Block diagram

SX (SDA)

SY (SCL)

VCC (2.5 V to 15 V)

PCA9600

GND

TX (TxD, SDA)

RX (RxD, SDA)

TY (TxD, SCL)

RY (RxD, SCL)

002aac835

Fig 1. Block diagram of PCA9600

Product data sheet Rev. 5 — 5 May 2011 2 of 31

NXP Semiconductors

6. Pinning information

6.1 Pinning

PCA9600

Dual bidirectional bus buffer

SX V

RX SY

GND TY

PCA9600D

002aac836

Fig 2. Pin configuration for SO8 Fig 3. Pin configuration for TSSOP8

6.2 Pin description

Table 3. Pin description

Symbol Pin Description

SX 1 I RX 2 receive signal TX 3 transmit signal GND 4 negative supply voltage TY 5 transmit signal RY 6 receive signal SY 7 I V

8 positive supply voltage

C-bus (SDA or SCL)

SX V

RX SY

TX RY

GND TY

PCA9600DP

002aac837

(MSOP8)

7. Functional description

Refer to Figure 1 “Block diagram of PCA9600”. The PCA9600 has two identical buffers allowing buffering of SDA and SCL I

signals. Each buffer is made up of two logic signal paths, a forwar d path from the I interface, pins SX and SY which drive the buffer ed bus, and a reverse sig nal path from the buffered bus input, pins RX and RY to drive the I

• sense the voltage state of I

C-bus pins SX (and SY) and transmit this state to pin TX

C-bus interface. These paths:

(and TY respectively), and

• sense the state of pins RX and RY and pull the I

C-bus pin LOW whenever pin RX or

pin RY is LOW.

The rest of this discussion will address only the ‘X’ side of the buffer; the ‘Y’ side is identical.

C-bus pin SX is specified to allow interfacing with Fast-mode, Fm+ and TTL-based

The I systems.

Product data sheet Rev. 5 — 5 May 2011 3 of 31

C-bus

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The logic threshold voltage levels at SX on this I2C-bus are independent of the IC supply voltage V

When interfacing with Fast-mode systems, the SX pin is guaranteed to sink the normal 3 mA with a V

C-bus specification for all I2C-bus voltages greater than 3 V, as well as compliance with

SMBus or other systems that use TTL switching levels. SX is guaranteed to sink an external 3 mA in addition to its internally sourced pull-up of

typically 300 μA (maximum 1 mA at −40 °C). When selecting the pull-up for the bus at SX, the sink capability of other connected drivers should be taken into account. Most TTL devices are specified to sink at least 4 mA so then the pull-up is limited to 3 mA by the requirement to ensure the 0.8 V TTL LOW.

. The maximum I2C-bus supply voltage is 15 V.

of 0.74 V maximum. That guarantees compliance with the Fast-mode

PCA9600

Dual bidirectional bus buffer

For Fast-mode I

C-bus operation, the other connecte d I2C-bus parts ma y have the minimum sink capability of 3 mA. SX sources typically 300 μA (maximum 1 mA at −40 °C), which forms part of the external driver loading. When selecting the pull-up it is necessary to subtract the SX pin pull-up current, so, worst-case at −40 °C, the allowed pull-up can be limited (by external drivers) to 2 mA.

When the interface at SX is an Fm+ bus with a voltage greater than 4 V, its higher specified sink capability may be used. PCA9600 has a guaranteed sink capability of 7 mA at V

= 1 V maximum. That 1 V complies with the bus LOW requirement (0.25V

bus

) of any Fm+ bus operating at 4 V or greater. Since the other connected Fm+ devices have a drive capability greater than 20 mA, the pull-up may be selected for 7 mA sink current at V

= 1 V. For a nominal 5 V bus (5.5 V maximum) the allowed pull-up is

(5.5 V − 1V)/7mA=643Ω. With 680 Ω pull-up, the Fm+ rise time of 120 ns maximum can be met with total bus loading up to 200 pF.

The logic level on RX is determined from the power supply voltage V LOW is below 40 % of V threshold just slightly below half V

, and logic HIGH is above 55 % of VCC (with a typical switching

TX is an open-collector output without ESD protection diodes to V via a pull-up resistor to a supply voltage in excess of V

, as long as the 15 V rating is not

exceeded. It has a larger current sinking capability than a normal I

of the chip. Logic

. It may be connected

C-bus device, being able to sink a static current of greater than 30 mA, and typical 100 mA dynamic pull-down capability as well.

A logic LOW is transmitted to TX when the voltage at I logic LOW at RX will cause I

with I

C-bus requirements (maximum 1.5 V in 5 V applications) but not low enough to be

C-bus pin SX to be pulled to a logic LOW level in a ccordance

C-bus pin SX is below 0.425 V. A

looped back to the TX output and cause the buffer to latch LOW.

The LOW level this chip can achieve on the I

C-bus by a LOW at RX is typically 0.64 V

when sinking 1 mA. If the supply voltage V

fails, then neither the I2C-bus nor the TX output will be held

LOW. Their open-collector configuration allows them to be pulled up to the rated maximum of 15 V even without V presents no loading of external signals when V

present. The input configuration on SX and RX also

is not present.

The effective input capacitance of an y signal pin, measured by its effect on bus rise times, is less than 10 pF for all bus voltages and supply voltages including V

Product data sheet Rev. 5 — 5 May 2011 4 of 31

=0V.

NXP Semiconductors

PCA9600

Dual bidirectional bus buffer

Remark: Two or more SX or SY I/Os must not be interconnected. The PCA9600 design

does not support this configuration. Bidirectional I

C-bus signals do not allow any direction control pin so, instead, slightly different logic LOW voltage levels are used at SX/SY to avoid latching of this buffer. A ‘regular I

C-bus LOW’ applied at the RX/RY of a PCA9600 will be propagated to SX/SY as a ‘buffered LOW’ with a slightly higher voltage level. If this special ‘buffered LOW’ is applied to the SX/SY of another PCA9600, that second PCA9600 will not recognize it as a ‘regular I

C-bus LOW’ and will not propagate it to its TX/TY output. The SX/SY side of PCA9600 may not be connected to similar buffers that rely on special logic thresholds for their operation, for example P82B96, PCA9511A, PCA9515A, ‘B’ side of PCA9517, etc. The SX/SY side is only intended for, and compatib le with, the normal I

C-bus logic voltage levels of I2C-bus master and slave chips, or even TX/RX signals of a second PCA9600 or P82B96 if required. The TX/RX and TY/RY I/O pins use the standard I

C-bus logic voltage levels of all I2C-bus parts. There are no restrictions on the interconnection of the TX/RX and TY/RY I/O pins to other PCA9600s, for example in a star or multipoint configurat ion with the TX/RX and TY/R Y I/O pins on the common bus and the SX/SY side connected to the line card slave devices. For more details see Application Note AN10658, “Sending I

C-bus signals via long communication

cables”.

The PCA9600 is a direct upgrade of the P82B96 with the significant differences summarized in Table 4

Table 4. PCA9600 versus P82B96

Detail PCA9600 P82B96

Supply voltage (V Maximum operating bus voltage

(independent of V Typical operating supply current: 5 mA 1 mA Typical LOW-level input voltage on I

(SX/SY side): LOW-level output voltage on I

(SX/SY side; 3 mA sink): LOW-level output voltage on Fm+ I

(SX/SY side; 7 mA sink): Temperature coefficient of V Logic voltage levels on SX/SY bus

(independent of V Typical propagation delays: < 100 ns <200 ns TX/RX switching specifications (I

compliant): RX logic levels with tighter control than

C-bus limit of 30 % to 70 %:

I Maximum bus speed: > 1 MHz > 400 kHz ESD rating HBM per JESD22-A114: > 4500 V > 3500 V Package: SO8, TSSOP8 (MSOP8) DIP8, SO8, TSSOP8 (MSOP8)

) range: 2.5 V to 15 V 2 V to 15 V

C-bus

:0mV/°C −2mV/°C

IL/VOL

C-bus

15 V 15 V

0.5 V over −40 °C to +85 °C 0.65 V at 25 °C

0.74 V (max.) over −40 °C to +85 °C 0.88 V (typ.) at 25 °C

1 V (max.) n/a

compatible with I buses using TTL levels (SMBus, etc.)

yes, all classes including 1 MHz Fm+ yes, all classes including Fm+

yes, 40 % to 55 % (48 % nominal) yes, 42 % to 58 % (50 % nominal)

C-bus and similar

compatible with I2C-bus and similar buses using TTL levels (SMBus, etc.)

Product data sheet Rev. 5 — 5 May 2011 5 of 31

NXP Semiconductors

When the device driving the PCA9600 is an I2C-bus compatible device, then the PCA9600 is an improvement on the P82B96 as shown in Table 4 exceptions however, and if the device driving the bus buffer is not I (e.g., you need to use the micro already in the system and bit-bang using two GPIO pins) then here are some considerations that would point to using the P82B96 instead:

• When the pull-up must be the weakest one possible. The spec is 200 μA for P82B96,

• When the lower operating temperature range is restricted (say 0 °C). The P82B96

• When the operating temperature range is restricted at both limits. An I

PCA9600

Dual bidirectional bus buffer

. There will always be

C-bus compatible

but it typically works even below that. And if designing for a temperature range −40°C up to +60 °C, then the driver when sinking 200 μA only needs to drive a guaranteed low of 0.55 V. For th e PCA9600, over that same temper ature r ange and when sinking

1.3 mA (at −40 °C), the device driving the bus buffer must provide the required low of

0.425 V.

larger SX voltage levels then make a better typical match with the driver, even when the supply is as low as 3.3 V.

For an I low that is below 0.83 V. P82B96 guarantees that with a 200 μA pull-up.

typical output is well below 0.4 V and the P82B96 typically requires 0.6 V input even at +60 °C, so there is a reasonable margin. The PCA9600 requires a typical input low of 0.5 V so its typical margin is smaller. At 0 °C the driver requires a typical input low of 1.16 V and P82B96 provides 0.75 V, so again the typical margin is already quite big and even though PCA9600 is better, providing 0.7 V, that difference is not big.

C-bus compliant driver on 3.3 V the P82B96 is required to guarantee a bus

C driver's

8. Limiting values

Table 5. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages with respect to pin GND.

Symbol Parameter Conditions Min Max Unit

I2C-bus

tot

stg

amb

[1] See also Section 10.2 “Negative undershoot below absolute minimum value”.

supply voltage VCC to GND −0.3 +18 V I2C-bus voltage SX and SY;

output voltage TX and TY;

input voltage RX and RY;

I2C-bus current SX and SY;

total power dissipation - 300 mW junction temperature operating range −40 +125 °C storage temperature −55 +125 °C ambient temperature operating −40 +85 °C

C-bus SDA or SCL

buffered output

receive input

C-bus SDA or SCL

−0.3 +18 V

[1]

−0.3 +18 V

[1]

−0.3 +18 V

- 250 mA

Product data sheet Rev. 5 — 5 May 2011 6 of 31

NXP Semiconductors

9. Characteristics

PCA9600

Dual bidirectional bus buffer

Table 6. Characteristics

=−40°C to +85°C unless otherwise specified; voltages are specified with respect to GND with VCC= 2.5 V to 15 V

amb

unless otherwise specified. Typical values are measured at V

= 5 V and T

amb

=25°C.

Symbol Parameter Conditions Min Typ Max Unit

Power supply

V I

ΔI

supply voltage operating 2.5 - 15 V supply current VCC= 5 V; buses HIGH - 5.2 6.75 mA

= 15 V; buses HIGH - 5.5 7.3 mA

additional supply current per TX/TY output driven LOW;

=5.5V

-1.43.0mA

Bus pull-up (load) voltages and currents

Pins SX and SY; I

O(sink)

input voltage open-collector; RX and RY HIGH - - 15 V output voltage open-collector; RX and RY HIGH - - 15 V output current static; VSX = VSY = 0.4 V output sink current dynamic; VSX = VSY = 1 V;

C-bus

[1]

0.3 - 2 mA 715- mA

RX and RY LOW

leakage current VSX = VSY = 15 V;

--10μA

RX and RY HIGH

Pins TX and TY

V I

load

output voltage open-collector - - 15 V load current maximum recommended on

--30mA buffered bus; VTX=VTY=0.4V; SX and SY LOW on

C-bus = 0.4 V

output current from buffered bus;

60 130 - mA

VTX=VTY= 1 V; SX and SY LOW

C-bus = 0.4 V

on I

leakage current on buffered bus;

--10μA VTX=VTY=VCC= 15 V; SX and SY HIGH

Input currents

input current from I2C-bus on SX and SY

RX and RY HIGH or LOW;

[1]

- −0.3 −1mA

SX and SY LOW ≤ 1V RX and RY HIGH; SX and

[1]

--10μA

SY HIGH > 1.4 V

[2]

from buffered bus on RX and RY;

- −1.5 −10 μA SX and SY HIGH or LOW; V

RX=VRY

leakage current on buffered bus input on RX and

=0.4V

--10μA RY; VRX = VRY=15V

Product data sheet Rev. 5 — 5 May 2011 7 of 31

NXP Semiconductors

PCA9600

Dual bidirectional bus buffer

Table 6. Characteristics

=−40°C to +85°C unless otherwise specified; voltages are specified with respect to GND with VCC= 2.5 V to 15 V

amb

unless otherwise specified. Typical values are measured at VCC= 5 V and T

…continued

amb

=25°C.

Symbol Parameter Conditions Min Typ Max Unit

Output logic LOW level

Pins SX and SY

LOW-level output voltage on Standard-mode or Fast-mode

I2C-bus

= 3 mA; Figure 6 - 0.7 0.74 V = 0.3 mA; Figure 5 - 0.6 0.65 V

C-bus

= 7mA --1V

= 0.3mAto3mA - 0 - %/K

ΔV/ΔT voltage variation with temperature I

SX=ISY

on 5 V Fm+ I

SX=ISY

Input logic switching threshold voltages

Pins SX and SY

V V

IL th(IH)

LOW-level input voltage on normal I2C-bus; Figure 7 HIGH-level input threshold voltage on normal I2C-bus; Figure 8 580--mV

[3]

--425mV

ΔV/ΔT voltage variation with temperature - 0 - %/K

Pins RX and RY

th(i)

HIGH-level input voltage fraction of applied V input threshold voltage fraction of applied V LOW-level input voltage fra c tion of applied V

CC CC CC

0.55VCC--V

-0.48V

-V

--0.4VCCV

Logic level threshold difference

[4]

ΔV voltage difference SX and SY; SX output LOW at

50--mV

0.3 mA to SX input HIGH maximum

Thermal resistance

th(j-pcb)

thermal resistance from junction to printed-circuit board

Bus release on V

supply voltage SX, SY, TX and TY; voltage at

failure

SOT96-1 (SO8); average lead temperature at board interface

-127-K/W

--1V which all buses are to be released at 25 °C

ΔV/ΔT voltage variation with temperature Figure 9

- −4- %/K

Product data sheet Rev. 5 — 5 May 2011 8 of 31

NXP Semiconductors

PCA9600

Dual bidirectional bus buffer

Table 6. Characteristics

=−40°C to +85°C unless otherwise specified; voltages are specified with respect to GND with VCC= 2.5 V to 15 V

amb

unless otherwise specified. Typical values are measured at VCC= 5 V and T

…continued

amb

=25°C.

Symbol Parameter Conditions Min Typ Max Unit

Buffer response time

[5]

VCC = 5 V; pin TX pull-up resistor = 160 Ω; pin SX pull-up resistor = 2.2 kΩ; no capacitive load

delay time VSX to VTX, VSY to VTY; on falling

-50-ns input between VSX= input

-60-ns

switching threshold, and V output falling to 50 % V

to VTX, VSY to VTY; on rising

input between VSX= input

-100-ns

switching threshold, and V output reaching 50 % V

to VSX, VRY to VSY; on falling

input between VRX= input

-95-ns

switching threshold, and V output falling to 50 % V

to VSX, VRY to VSY; on rising

input between VRX= input

switching threshold, and V output reaching 50 % V

Input capacit a nce

input capacitance effective input capacitance of any

--10pF signal pin measured by incremental bus rise times; guaranteed by design, not production tested

[1] This bus pull-up current specification is intended to assist design of the bus pull-up resistor. It is not a specification of the sink cap ability

(see V PCA9600 is guaranteed to sink 3 mA at SX/SY when its pins are holding the bus LOW. However, when an external device pulls the SX/SY pins below 1.4 V, the PCA9600 may source a current between 0 mA and 1 mA maximum. When that other external device is driving LOW it will pull the bus connected to SX or SY down to, or below, the 0.4 V level referenced in the I these test conditions. Then that device must be able to sink up to 1 mA coming from SX/SY plus the usual pull-up current. Therefore the external pull-up used at SX/SY should be limited to 2 mA. The typical and maximum currents sourced by SX/SY as a function of junction

temperature are shown in Figure 10 [2] Valid over temperature for V [3] The input logic threshold is independent of the supply voltage. [4] The minimum value requirement for pull-up current, 0.3 mA, guarantees that the minimum value for V

the maximum V

IC. While the tolerances on absolute levels allow a small probability, the LOW from one SX output is recognized by an SX input of

another PCA9600, this has no consequences for normal applications. In any design the SX pins of different ICs should never be linked

because the resulting system would be very susceptible to induced noise and would not support all I [5] The fall time of V

The fall time of V

The rise time of V

under sub-section “Output logic LOW level”). The maximum static sink current for a Standard/Fast-mode I2C-bus is 3 mA and

C-bus specification and in

, and the equivalent circuit at the SX/SY interface is shown in Figure 4.

≤ 5 V. At higher VCC, this current may increase to maximum −20 μA at VCC=15V.

output LOW will always exceed

input HIGH level to eliminate any possibility of latching. The specified difference is guaranteed by design within any

from 5 V to 2.5 V in the test is approximately 10 ns.

from 5 V to 2.5 V in the test is approximately 20 ns.

from 0 V to 2.5 V in the test is approximately 15 ns.

from 0.7 V to 2.5 V in the test is approximately 25 ns.

C-bus operating modes.

Product data sheet Rev. 5 — 5 May 2011 9 of 31

NXP Semiconductors

002aac839

002aac840

PCA9600

Dual bidirectional bus buffer

≤ 1 mA

Fig 4. Equivalent circuit at SX/SY

800

(mV)

700

600

500

400

−50 1251007550250−25

(1)

(2)

(°C)

VOL at SX typical and limits over temperature. (1) Maximum. (2) Typical.

Fig 5. VOL as a function of junction temperature

=0.3mA)

ref

Fig 6. V

800

(mV)

(1)

(2)

700

600

500

400

−50 1251007550250−25

at SX typical and limits over temperature.

(1) Maximum. (2) Typical.

as a function of junction temperature

=3mA)

SX (SY)

002aac83

(°C)

600

(mV)

typical

500

maximum

400

300

200

−50 1251007550250−25

VIL at SX changes over temperature range. VIH at SX changes over temperature range.

Fig 7. VIL as a function of junction temperature;

maximum and typical values

002aag005

(°C)

600

500

400

300

200

−50 1251007550250−25

minimum

typical

(mV)

Fig 8. VIH as a function of junction temperature;

minimum and typical values

002aag006

(°C)

Product data sheet Rev. 5 — 5 May 2011 10 of 31

NXP Semiconductors

PCA9600

Dual bidirectional bus buffer

002aac075

(°C)

CC(max)

(mV)

1400

1200

1000

800

600

400

−50 1251007550250−25

Fig 9. VCC bus release limit over temperature;

maximum values

001aai062

(°C)

(μA)

1000

800

600

400

200

(1)

(2)

−50 1251007550250−25

(1) Maximum. (2) Typical.

Fig 10. Current sourced out of SX/SY as a function of

junction temperature if these pins are externally pulled to 0.4 V or lower

Product data sheet Rev. 5 — 5 May 2011 11 of 31

NXP Semiconductors

10. Application information

Refer to PCA9600 data sheet and application notes AN10658 and AN255 for more detailed application information.

I2C-bus

SDA

5 V

VCC (2.5 V to 15 V)

TX (SDA)

RX (SDA)

PCA9600

Dual bidirectional bus buffer

'SDA' (new levels)

PCA9600

001aai06

Fig 11. Interfacing a standard 3 mA I2C-bus or one with TTL levels (e.g. SMBus) to

higher voltage or higher current sink (e.g. Fast-mode Plus) devices

I2C-bus

SDA

5 V

(SDA)

TX (SDA)

PCA9600

CC1

I2C-bus SDA

001aai06

This simple example may be limited, if using lowest-cost couplers, to speeds as low as 5 kHz. Refer to application notes for schematics suitable for operation to 400 kHz or higher.

Fig 12. Galvanic isolation of I2C-bus nodes via opto-couplers

SDA

SCL

main enclosure

3.3 V to 5 V 12 V

long cables

12 V3.3 V to 5 V

PCA9600

remote control enclosure

3.3 V to 5 V

12 V

3.3 V to 5 V

PCA9600

SDA

SCL

002aac84

Fig 13. Long distance I2C-bus communication

Product data sheet Rev. 5 — 5 May 2011 12 of 31

NXP Semiconductors

PCA9600

Dual bidirectional bus buffer

CC1

I2C-BUS MASTER

GND

SCL

SDA

+V cable drive

R1 R1

cable

R1 R1

PCA9600

C2C2

BAT54A

propagation

delay ≈ 5 ns/m

BAT54A

PCA9600

SCL

SDA

C2C2

CC2

C-BUS

SLAVE(S)

GND

002aac85

Fig 14. Driving ribbon or flat telephone cables

CC2

(Ω)

(kΩ)

(pF)

Cable length (m)

Cable capacitance

Cable delay

Set master nominal SCL

HIGH period (ns)

LOW period (ns)

Effective bus clock speed (kHz)

Max. slave response delay

1.25 μs 600 3850 125 normal

(delay based)

specification

Table 7. Examples of bus capability

Refer to Figure 14

V (V)

CC1

+V cable

V (V)

(V)

5 12 5 750 2.2 400 250 n/a

400 kHz parts

5 12 5 750 2.2 220 100 n/a

(delay based)

500 ns 600 2450 195 normal

specification 400 kHz parts

3.3 5 3.3 330 1 220 25 1 nF 125 ns 260 770 620 meets Fm+ specification

3.3 5 3.3 330 1 100 3 120 pF 15 ns 260 720 690 meets Fm+ specification

For more examples of faster alternatives for driving over longer cables such as Cat5 communication cable, see AN10658. Communication at 1 MHz is possible over short cables and > 40 0 kHz is possible over 50 m of cable.

Product data sheet Rev. 5 — 5 May 2011 13 of 31

NXP Semiconductors

10.1 Calculating system delays and bus clock frequency

PCA9600

Dual bidirectional bus buffer

local master bus

CCM

MASTER

C-BUS

SCL

GND (0 V)

Effective delay of SCL at slave: 120 + 17V

CCB

master bus capacitance

PCA9600 PCA9600

buffered expansion bus

Rb Rs

TX/RX

+(2.5+4× 109× Cb) × V

CCM

TX/RX SX

buffered bus wiring capacitance

CCB

+ 10V

CCS

(ns).

C=F; V=V.

Fig 15. Falling edge of SCL at master is delayed by the buffers and bus fall times

CCM

local master bus

CCB

buffered expansion bus

remote slave bus

SCL

slave bus capacitance

SLAVE

I2C-BUS

002aac8

CCS

MASTER

C-BUS

SCL

GND (0 V)

master bus capacitance

PCA9600

TX/RX

buffered bus wiring capacitance

002aac8

Effective delay of SCL at master: 115 + (Rm × Cm) + (0.7 × Rb × Cb) (ns). C=F; R=Ω.

Fig 16. Rising edge of SCL at master is delayed (clock stretch) by buffer and bus rise times

Product data sheet Rev. 5 — 5 May 2011 14 of 31

NXP Semiconductors

PCA9600

Dual bidirectional bus buffer

local master bus

CCM

MASTER

C-BUS

Effective delay of SDA at master: 115 + 0.2(Rs × Cs) + 0.7[(Rb × Cb) + (Rm × Cm)] (ns). C=F; R=Ω.

SDA

GND (0 V)

CCB

master bus capacitance

PCA9600 PCA9600

buffered expansion bus

Rb Rs

TX/RX

TX/RX SX

buffered bus wiring capacitance

Fig 17. Rising edge of SDA at slave is delayed by the buffers and bus rise times

Figure 15, Figure 16, and Figure 17 show the PCA9600 used to drive extended bus wir ing

with relatively large capacitances linking two I

C-bus nodes. It includes simplified expressions for making the relevant timing calculations for 3.3 V or 5 V operation. Because the buffers and the wiring introduce timing delays, it may be necessary to decrease the nominal SCL frequency. In most cases the actual bus frequency will be lower than the nominal Master timing due to bit-wise stretching of the clock periods.

remote slave bus

SDA

slave bus capacitance

SLAVE

I2C-BUS

001aai1

CCS

The delay factors involved in calculation of the allowed bus speed are: A — The propagation delay of the master signal through the buffers and wiring to the

slave. The important delay is that of the falling edge of SCL because this edge ‘requests’ the data or acknowledge from a slave. See Figure 15

B — The effective stretching of the nominal LOW period of SCL at the master caused by the buffer and bus rise times. See Figure 16

C — The propagation delay of the slave's response signal through the buffers and wiring back to the master. The important delay is that of a rising edge in the SDA signal. Rising edges are always slower and are therefore delayed by a longer time than falling edges. (The rising edges are limited by the passive pull-up while falling edges are actively driven); see Figure 17

The timing requirement in any I

C-bus system is that a slave's data response (which is provided in response to a falling edge of SCL) must be received at the master before the end of the corresponding LOW period of SCL as appears on the bus wirin g a t th e m aster. Since all slaves will, as a minimum, satisfy the worst case timing requirements of their speed class (Fast-mode, Fm+, etc.), they must provide their response, allowing for the set-up time, within the minimum allowed clock LOW period, e.g., 450 ns (max.) for Fm+ parts. In systems that introduce additional delays it may be necessary to extend the minimum clock LOW period to accommodate the ‘effective’ delay of the slave's response. The effective delay of the slave’s response equals the total delays in SCL falling edge

Product data sheet Rev. 5 — 5 May 2011 15 of 31

NXP Semiconductors

from the master reaching the slave (Figure 15) minus the effective delay (stretch) of the SCL rising edge (Figure 16 SDA, reaching the master (Figure 17

The master microcontroller should be programmed to produce a nominal SCL LOW period as follows:

PCA9600

Dual bidirectional bus buffer

) plus total delays in the slave's response data, carried on

SCL LOW slave response delay to valid data on its SDA A B C data set-up time++–+( )≥ ns

The actual LOW period will become (the programmed value + the stretching time B). When this actual LOW period is then less than the specified minimum, the specified minimum should be used.

Example 1:

It is required to connect an Fm+ slave, with Rs × Cs produc t of 100 ns, to a 5 V Fast-mode system also having 100 ns Rm × Cm using two PCA9600’s to buffer a 5 V bus with 4 nF loading and 160 Ω pull-up.

Calculate the allowed bus speed:

Delay A = 120 + 85 + (2.5 + [4 × 4]) × 5 + 50 = 347.5 ns Delay B = 115 + 100 + 70 = 285 ns Delay C = 115 + 20 + 0.7(100 + 100) = 275 ns

The maximum Fm+ slave response delay must be < 450 ns so the programmed LOW period is calculated as:

LOW ≥ 450 + 347.5 − 285 + 275 + 100 = 887.5 ns

The actual LOW period will be 887.5 + 285 = 1173 ns, which is below the Fast-mode minimum, so the programmed LOW period must be increased to (1300 − 285) = 1015 ns, so the actual LOW equals the 1300 ns requirement and this shows that this Fast-mode system may be safely run to its limit of 400 kHz.

(1)

Example 2:

It is required to buffer a Master with Fm+ speed capability, but only 3 mA sink capability, to an Fm+ bus. All the system operates at 3.3 V . The Master Rm× Cm product is 50 ns. Only one PCA9600 is used. The Fm+ bus becomes the bu f fered bu s. The Fm+ bus ha s 200 pF loading and 150 Ω pull-up, so its Rb × Cb product is 30 ns. The Fm+ slave has a specified data valid time t

Calculate the allowed maximum system bus speed. (Note that the fixed values in the delay equations represent the internal propagation delays of the PCA9600. Only on e PCA9600 is used here, so those fixed values used below are taken from the characteristics.)

The delays are:

Delay A = 40 + 56 + (2.5 + [4 × 0.2]) × 3.3 = 107 ns Delay B = 115 + 50 + 21 = 186 ns Delay C = 70 + 0.7(50 + 30) = 126 ns

The programmed LOW period is calculated as:

SCL LOW ≥ 300 + 117 − 186 + 126 + 50 = 407 ns

Product data sheet Rev. 5 — 5 May 2011 16 of 31

maximum of 300 ns.

VD;DAT

NXP Semiconductors

The actual LOW period will be 407 + 126 = 533 ns, which exceeds the minimum Fm+ 500 ns requirement. This system requires the bus LOW period, and therefore cycle time, to be increased by 33 ns so the system must run slightly below the 1 MHz limit.

The possible maximum speed has a cycle perio d of 1033 ns or 968 kHz.

PCA9600

Dual bidirectional bus buffer

SDA

SCL

12 V

3.3 V to 5 V

12 V

PCA9600

Fig 18. I2C-bus multipoint application

There is an Excel calculator which makes it easy to determine the maximum I2C-bus clock speed when using the PCA9600. The calculator and instructions can be found at

www.nxp.com/clockspeedcalculator

PCA9600

SX SY

SCL/SDA

no limit to the number of connected bus devices

PCA9600

SX SY

SCL/SDA

PCA9600

SX SY

SCL/SDA

PCA9600

twisted-pair telephone wires, USB, or flat ribbon cables; up to 15 V logic levels, include V

3.3 V 3.3 V

and GND

SY SDA

SX SCL

001aai06

Product data sheet Rev. 5 — 5 May 2011 17 of 31

NXP Semiconductors

002aac932

002aac933

PCA9600

Dual bidirectional bus buffer

(V)

−1 0 900

(1)

(2)

200100 300 400 500 600 700 800

time (ns)

(1)

(2)

(1) TX output. (2) SX input.

Fig 19. Propagation SX to TX with VRX=VCC=3.3V

(SX pull-up to 3.3 V; TX pull-up to 5.7 V)

(V)

−1 0 900

(1)

200100 300 400 500 600 700 800

(V)

−1 0 900

(1)

(2)

200100 300 400 500 600 700 800

(1) TX/RX output. (2) SX input.

Fig 20. Propagation SX to TX with RX tied to TX;

VCC= 3.3 V (SX pull-up to 3.3 V; TX pull-up to

5.7 V)

002aac934

(2)

(1)

time (ns)

(1)

(2)

time (ns)

(1) RX input. (2) SX output.

Fig 21. Propagation RX to SX (SX pull-up to 3.3 V; VCC= 3.3 V; RX pull-up to 4.6 V)

10.2 Negative undershoot below absolute minimum value

The reason why the IC pin reverse voltage on pins TX and RX in Table 5 “Limiting values” is specified at such a low value, −0.3 V, is not that applying larger voltages is likely to cause damage but that it is expected that, in normal applications, there is no reason why larger DC voltages will be applied. This ‘absolute maximum’ specification is intended to be a DC or continuous ratings and the nominal DC I even reach 0 V. Inside PCA9600 at every pin there is a large protective diode connected to the GND pin and that diode will start to conduct when the pin voltage is more than about

−0.55 V with respect to GND at 25 °C ambient.

Figure 22

shows the measured characteristic for one of those diodes inside PCA9600. The plot was made using a curve tracer that applies 50 Hz mains voltage via a series resistor, so the pulse durations are long duration (several milliseconds) and are reaching peaks of over 2 A when more than −1.5 V is applied. The IC becomes very hot during this

Product data sheet Rev. 5 — 5 May 2011 18 of 31

C-bus voltage LOW usually does not

NXP Semiconductors

testing but it was not damaged. Whenever there is current flowi ng in any of these d iodes it is possible that there can be faulty operation of any IC. For that rea s o n we pu t a specification on the negative voltage that is allowed to be applied. It is selected so that, at the highest allowed junction temperature, there will be a big safety factor that guarantees the diode will not conduct and then we do not need to make any 100 % production tests to guarantee the published specification.

For the PCA9600, in specific applications, there will always be transient overshoot and ringing on the wiring that can cause these diodes to conduct. Therefore we designed the IC to withstand those transients and as a part of the qualification procedure we made tests, using DC currents to more than twice the normal bus sink currents, to be sure that the IC was not affected by those currents. For exam ple, the TX/TY and RX/RY pins were tested to at least −80 mA which, from Figure 22 functioning of the PCA9600 is not affected even by those large currents. The Absolute Maximum (DC) ratings are not intended to apply to transients but to steady state conditions. This explains why you will never see any problems in practice even if, during transients, more than −0.3 V is applied to the bus interface pins of PCA9600.

PCA9600

Dual bidirectional bus buffer

, would be more than −0.8 V. The correct

Figure 22 “

Diode characteristic curve” also explains how the general Absolute Maximum

DC specification was selected. The current at 25 °C is near zero at −0.55 V. The PCA9600 is allowed to operate with +125 °C junction and that would cause this diode voltage to decrease by 100 × 2 mV = 200 mV. So for zero current we need to specify

−0.35 V and we publish −0.3 V just to have some extra margin. Remark: You should not be concerned about the transients generated on the wiring by a

PCA9600 in normal applications and that is input to the TX/RX or TY/RY pins of another PCA9600. Because not all ICs that may be driven by PCA9600 are designed to tolerate negative transients, in Section 10.2.1 “

Example with questions and answers” we show

they can be managed if required.

diode current

(mA)

−1

−10

−1

−10

002aaf063

−10

−2.0 0−0.5−1.5 −1.0

voltage (V)

Fig 22. Diode characteristic curve

Product data sheet Rev. 5 — 5 May 2011 19 of 31

NXP Semiconductors

10.2.1 Example with questions and answers

Question: On a falling edge of TX we measure undershoot at −800 mV at the linked

TX, RX pins of the PCA9600 that is generating the LOW, but the PCA9600 data sheet specifies minimum −0.3 V. Does this mean that we violate the data sheet absolute value?

Answer: For PCA9600 the −0.3 V Absolute Maximum rating is not intended to apply to transients, it is a DC rating. As shown in Figure 23 undershoot at the IC that is driving the bus LOW and no significant undershoot should be observed when using reasonable care with the grou nd co nnectio n of th e ‘scope. It is more likely that undershoot observed at a driving PCA9600 is caused by local stray inductance and capacitance in the circuit and by the oscilloscope connections. As shown, undershoot will be generated by PCB traces, wiring, or cables driven by a PCA9600 because the allowed value of the I than that required to correctly terminate the wiring. In this example, with no IC connected at the end of the wiring, the undershoot is about 2 V.

voltage

(V)

PCA9600

Dual bidirectional bus buffer

, there is no theoretical reason for any

C-bus pull-up resistor generally is larger

send

−2 horizontal scale = 62.5 ns/div

5 V

PCA9600

5 V

300 Ω

send

Fig 23. Transients generated by the bus wiring

receive

2 meter

cable

time (ns)

5 V

300 Ω

receive

GND

002aaf081

Product data sheet Rev. 5 — 5 May 2011 20 of 31

NXP Semiconductors

Question: We have 2 meters of cable in a bus that joins the TX/RX sides of two

PCA9600 devices. When one TX drives LOW the other PCA9600 TX/RX is driven to

−0.8 V for over 50 ns. What is the expected value and the theoretically allowed value of undershoot?

Answer: Because the cable joining the two PCA9600s is a ‘transmission line’ that will have a characteristic impedance around 100 Ω and it will be terminated by pull-up resistors that are larger than that characteristic impedance there will always be negative undershoot generated. The duration of the undershoot is a function of the cable length and the input impedance of the connected IC. As shown in Figure 24 undershoot will be limited, by the diodes inside PCA9600, to around −0.8 V and that will not cause problems for PCA9600. Those transients will not be passed inside the IC to the SX/SY side of the IC.

PCA9600

Dual bidirectional bus buffer

, the transient

voltage

(V)

cable

receive

5 V

time (ns)

300 Ω

receive

GND

5 V

002aaf082

send

−2 horizontal scale = 62.5 ns/div

5 V

PCA9600

5 V

300 Ω

send

2 meter

Fig 24. Wiring transients limited by the diodes in PCA9600

Question: If we input 800 mV undershoot at TX, RX pins, what kind of problem is

expected? Answer: When that undershoot is generated by another PCA9600 and is simply the

result of the system wiring, then there will be no problems.

Question: Will we have any functional problem or reliability problem? Answer: No.

Product data sheet Rev. 5 — 5 May 2011 21 of 31

NXP Semiconductors

Question: If we add 100 Ω to 200 Ω at signal line, the overshoot becomes slightly

smaller. Is this a good idea? Answer: No, it is not necessary to add any resista nce. When the logic sign al generated

by TX or TY of PCA9600 drives long traces or wiring with ICs other than PCA9600 being driven, then adding a Schottky diode (BAT54A) as shown in Figure 25 the wiring undershoot to a value that will not cause conduction of the IC’s internal diodes.

PCA9600

Dual bidirectional bus buffer

will clamp

voltage

(V)

send

receive

−2 horizontal scale = 62.5 ns/div

5 V

PCA9600

send

5 V

300 Ω

2 meter

cable

5 V

300 Ω

receive

/2 BAT54A

Fig 25. Wiring transients limited by a Schottky diode

time (ns)

RX TX

GND

002aaf083

5 V

Product data sheet Rev. 5 — 5 May 2011 22 of 31

NXP Semiconductors

-1

11. Package outline

PCA9600

Dual bidirectional bus buffer

O8: plastic small outline package; 8 leads; body width 3.9 mm

pin 1 index

w M

detail X

v M

(A )

SOT96

0 2.5 5 mm

scale

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

OUTLINE VERSION

SOT96-1

A1A2A3b

max.

0.25

1.75

0.10

0.010

0.069

0.004

1.45

1.25

0.057

0.049

IEC JEDEC JEITA

076E03 MS-012

0.25

0.01

0.49

0.36

0.019

0.014

0.0100

0.0075

UNIT

inches

Notes

1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.

2. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.

0.25

5.0

0.19

4.8

0.20

0.19

REFERENCES

(1)E(2)

4.0

3.8

0.16

0.15

eHELLpQZywv θ

6.2

1.27

5.8

0.244

0.05

0.228

1.05

1.0

0.4

0.039

0.016

0.7

0.6

0.028

0.024

0.25 0.10.25

0.010.010.041 0.004

EUROPEAN

PROJECTION

(1)

0.7

0.3

0.028

0.012

ISSUE DATE

99-12-27 03-02-18

Fig 26. Package outline SOT96-1 (SO8)

Product data sheet Rev. 5 — 5 May 2011 23 of 31

NXP Semiconductors

-1

PCA9600

Dual bidirectional bus buffer

TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm

pin 1 index

w M

detail X

SOT505

(A3)

v M

2.5 5 mm0

scale

DIMENSIONS (mm are the original dimensions)

UNIT

max.

1.1

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

OUTLINE

VERSION

SOT505-1

0.15

0.05

A2A3b

0.95

0.25

0.80

IEC JEDEC JEITA

0.45

0.25

ceD

0.28

0.15

REFERENCES

(1)E(2)

3.1

2.9

3.1

2.9

0.65

5.1

4.7

0.7

0.4

wyv

0.1 0.10.10.94

EUROPEAN

PROJECTION

(1)

0.70

0.35

ISSUE DATE

6° 0°

99-04-09 03-02-18

Fig 27. Package outline SOT505-1 (TSSOP8)

Product data sheet Rev. 5 — 5 May 2011 24 of 31

NXP Semiconductors

12. Soldering of SMD packages

This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description”.

12.1 Introduction to soldering

Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization.

12.2 Wave and reflow soldering

Wave soldering is a joining technology in which the joints are made by so lder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following:

PCA9600

Dual bidirectional bus buffer

• Through-hole components

• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board

Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging.

The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable.

Key characteristics in both wave and reflow soldering are:

• Board specifications, including the board finish, solder masks and vias

• Package footprints, including solder thieves and orientation

• The moisture sensitivity level of the packages

• Package placement

• Inspection and repair

• Lead-free soldering versus SnPb soldering

12.3 Wave soldering

Key characteristics in wave soldering are:

• Process issues, such as application of adhesive and flux, clinching of leads, board

transport, the solder wave parameters, and the time during which components are exposed to the wave

• Solder bath specifications, including temperature and impurities

Product data sheet Rev. 5 — 5 May 2011 25 of 31

NXP Semiconductors

12.4 Reflow soldering

Key characteristics in reflow soldering are:

• Lead-free versus SnPb soldering; note that a lead-free reflow process usually lea ds to

• Solder paste printing issues including smearing, release, and adjusting the process

• Reflow temperature profile; this profile includes preheat, reflow (in which the board is

Table 8. SnPb eutectic process (from J-STD-020C)

Package thickness (mm) Package reflow temperature (°C)

< 2.5 235 220 ≥ 2.5 220 220

PCA9600

Dual bidirectional bus buffer

higher minimum peak temperatures (see Figure 28 reducing the process window

window for a mix of large and small components on one board

heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joint s (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with

Table 8

and 9

Volume (mm3) < 350 ≥ 350

) than a SnPb process, thus

Table 9. Lead-free process (from J-STD-020C)

Package thickness (mm) Package reflow temperature (°C)

Volume (mm3) < 350 350 to 2000 > 2000

< 1.6 260 260 260

1.6 to 2.5 260 250 245 > 2.5 250 245 245

Moisture sensitivity precautions, as indicated on the packing, must be respected at all times.

Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 28

Product data sheet Rev. 5 — 5 May 2011 26 of 31

NXP Semiconductors

Fig 28. Temperature profiles for large and small components

maximum peak temperature

temperature

MSL: Moisture Sensitivity Level

= MSL limit, damage level

minimum peak temperature

= minimum soldering temperature

PCA9600

Dual bidirectional bus buffer

peak

temperature

time

001aac84

For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”.

13. Abbreviations

Table 10. Abbreviations

Acronym Description

CDM Charged-Device Model ESD ElectroStatic Discharge HBM Human Body Model

C-bus Inter-Integrated Circuit bus

I I/O Input/Output IC Integrated Circuit PMBus Power Management Bus SMBus System Management Bus TTL Transistor-Transi sto r Lo g i c

Product data sheet Rev. 5 — 5 May 2011 27 of 31

NXP Semiconductors

PCA9600

Dual bidirectional bus buffer

14. Revision history

Table 11. Revision history

Document ID Release date Data sheet statu s Change notice Supersedes

PCA9600 v.5 20110505 Product data sheet - PCA9600 v.4 Modifications:

PCA9600 v.4 20091111 Product data sheet - PCA9600 v.3 PCA9600 v.3 20090903 Product data sheet - PCA9600 v.2 PCA9600 v.2 20080813 Product data sheet - PCA9600 v.1 PCA9600 v.1 20080602 Product data sheet - -

• Section 2 “Features and benefits”, eighth bullet item: deleted phrase “450 V MM per

JESD22-A115”

• Table 6 “Characteristics”, sub-section “Output logic LOW level, Pins SX and SY”:

– Unit for V

, condition ISX = ISY = 0.3 mA is corrected from “mV” to “V”.

• Table 6 “Characteristics”, sub-section “Input logic switching threshold voltages, Pins SX and SY”:

– Changed V – Changed V – Changed V – Changed V – Changed V – Changed V

Min value from “425 mV” to “-”.

Typ value from “500 mV” to “-”.

Max value from “-” to “425 mV”.

Min value from “-” to “580 mV”.

th(IH)

Typ value from “500 mV” to “-”.

th(IH)

Max value from “580 mV” to “-”.

th(IH)

• Table 6 “Characteristics”, sub-section “Input logic switching threshold voltages, Pins TX and TY”:

– Under Conditions for I

, output current: deleted word “dynamic”.

• Table 6 “Characteristics”: Table note [1] re-written.

• Figure 7 modified to add “typical” curve.

• Figure 8 modified to add “typical” curve.

Product data sheet Rev. 5 — 5 May 2011 28 of 31

NXP Semiconductors

PCA9600

Dual bidirectional bus buffer

15. Legal information

15.1 Data sheet status

Document status

Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification.

[1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) d escribed i n this docume nt may have changed since this docume nt was publis hed and ma y dif fer in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

[1][2]

Product status

[3]

Definition

15.2 Definitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied u pon to co nt ain det ailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.

Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet.

15.3 Disclaimers

Limited warranty and liability — Information in this document is believed to

be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information.

In no event shall NXP Semiconductors be lia ble for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory.

Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semi conductors’ aggregat e and cumulative liabil ity towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors.

Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof.

Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonabl y be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk.

Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification.

Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products.

NXP Semiconductors does not accept any liability related to any default , damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third part y customer(s). NXP does not accept any liability in this respect.

Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device.

Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer.

No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell product s that is ope n for accept ance or the gr ant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights.

Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities.

, unless otherwise

Product data sheet Rev. 5 — 5 May 2011 29 of 31

NXP Semiconductors

PCA9600

Dual bidirectional bus buffer

Non-automotive qualified products — Unless this data sheet expressly

states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It i s neither qua lif ied nor test ed in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equ ipment or applications.

In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s

own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, da mages or failed produ ct cl aims resulting from custome r design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications.

15.4 Trademarks

Notice: All referenced brands, prod uct names, service names and trad emarks are the property of their respective owners.

C-bus — logo is a trademark of NXP B.V.

16. Contact information

For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com

Product data sheet Rev. 5 — 5 May 2011 30 of 31

NXP Semiconductors

17. Contents

1 General description . . . . . . . . . . . . . . . . . . . . . . 1

2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1

3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

4 Ordering information. . . . . . . . . . . . . . . . . . . . . 2

4.1 Ordering options. . . . . . . . . . . . . . . . . . . . . . . . 2

5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2

6 Pinning information. . . . . . . . . . . . . . . . . . . . . . 3

6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3

7 Functional description . . . . . . . . . . . . . . . . . . . 3

8 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 6

9 Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 7

10 Application information. . . . . . . . . . . . . . . . . . 12

10.1 Calculating system delays and bus clock

frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

10.2 Negative undershoot below absolute

minimum value . . . . . . . . . . . . . . . . . . . . . . . . 18

10.2.1 Example with questions and answers. . . . . . . 20

11 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 23

12 Soldering of SMD packages . . . . . . . . . . . . . . 25

12.1 Introduction to soldering . . . . . . . . . . . . . . . . . 25

12.2 Wave and reflow soldering . . . . . . . . . . . . . . . 25

12.3 Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 25

12.4 Reflow soldering. . . . . . . . . . . . . . . . . . . . . . . 26

13 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 27

14 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 28

15 Legal information. . . . . . . . . . . . . . . . . . . . . . . 29

15.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 29

15.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

15.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 29

15.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 30

16 Contact information. . . . . . . . . . . . . . . . . . . . . 30

17 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

PCA9600

Dual bidirectional bus buffer

Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 5 May 2011

Document identifier: PCA9600

NXP PCA 9600 D Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual

1. General description

2. Features and benefits

3. Applications

4. Ordering information

4.1 Ordering options

5. Block diagram

6. Pinning information

6.1 Pinning

6.2 Pin description

7. Functional description

8. Limiting values

9. Characteristics

10. Application information

10.1 Calculating system delays and bus clock frequency

10.2 Negative undershoot below absolute minimum value

10.2.1 Example with questions and answers

11. Package outline

12. Soldering of SMD packages

12.1 Introduction to soldering

12.2 Wave and reflow soldering

12.3 Wave soldering

12.4 Reflow soldering

13. Abbreviations

14. Revision history

15. Legal information

15.1 Data sheet status

15.2 Definitions

15.3 Disclaimers

15.4 Trademarks

16. Contact information

17. Contents