NXP PCA 9600 D Datasheet

PCA9600

Dual bidirectional bus buffer

Rev. 5 — 5 May 2011 Product data sheet

1. General description

The PCA9600 is designed to isolate I2C-bus capacitance, allowing long buses to be driven in point-to-point or multipoint applications of up to 4000 pF. The PCA9600 is a higher-speed version of the P82B96. It creates a non-latching , bidirectional, logic interface between a normal I bus configurations. It can operate at speeds up to at least 1 MHz, and the high drive side is compatible with the Fast-mode Plus (Fm+) specifications.

C-bus and a range of other higher capacitance or different voltage

The PCA9600 features temperature-stabilized logic voltage levels at its SX/SY interface making it suitable for interfacing with buses that have non I such as SMBus, PMBus, or with microprocessors that use those same TTL logic levels.

The separation of the bidirectional I enables the SDA and SCL signals to be transmitted via balanced transmission lines (twisted pairs), or with galvanic isolation using opto or magnetic coupling. The TX and RX signals may be connected together to provide a normal bidirectional signal.

2. Features and benefits

 Bidirectional data transfer of I2C-bus signals  Isolates capacitance allowing 400 pF on SX/SY side and 4000 pF on TX/TY side  TX/TY outputs have 60 mA sink capability for driving low-impedance or high-capacitive

buses

 1 MHz operation on up to 20 meters of wire (see AN10658)  Supply voltage range of 2.5 V to 15 V with I

independent of supply voltage

 Splits I

 Low power supply current  ESD protection exceeds 4500 V HBM per JESD22-A114 and 1400 V CDM per

 Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA  Packages offered: SO8 and TSSOP8 (MSOP8)

C-bus signal into pairs of forward/reverse TX/RX, TY/RY signals for interface with opto-electrical isolators and similar devices that need unidirectional input and output signal paths

JESD22-C101

C-bus-compliant logic levels

C-bus signals into unidirectional TX and RX signals

C-bus logic levels on SX/SY side

NXP Semiconductors

3. Applications

 Interface between I2C-buses operating at different logic levels (for example, 5 V and

3V or 15V)

 Interface between I  Simple conversion of I

hardware, for example, via compatible PCA82C250

 Interfaces with opto-couplers to provide opto-isolation between I

1MHz

 Long distance point-to-point or multipoint architectures

4. Ordering information

Table 1. Ordering information

Type number Package

PCA9600D SO8 plastic small outline package; 8 leads;

PCA9600DP TSSOP8 plastic thin shrink small outline package; 8 leads;

PCA9600

Dual bidirectional bus buffer

C-bus and SMBus (350 μA) standard or Fm+ standard

C-bus SDA or SCL signals to multi-drop differential bus

C-bus nodes up to

Name Description Version

SOT96-1

body width 3.9 mm

SOT505-1

body width 3 mm

4.1 Ordering options

Table 2. Ordering options

Type number Topside mark Temperature range

PCA9600D PCA9600 −40 °C to +85 °C PCA9600DP 9600 −40 °C to +85 °C

5. Block diagram

SX (SDA)

SY (SCL)

VCC (2.5 V to 15 V)

PCA9600

GND

TX (TxD, SDA)

RX (RxD, SDA)

TY (TxD, SCL)

RY (RxD, SCL)

002aac835

Fig 1. Block diagram of PCA9600

Product data sheet Rev. 5 — 5 May 2011 2 of 31

NXP Semiconductors

6. Pinning information

6.1 Pinning

PCA9600

Dual bidirectional bus buffer

SX V

RX SY

GND TY

PCA9600D

002aac836

Fig 2. Pin configuration for SO8 Fig 3. Pin configuration for TSSOP8

6.2 Pin description

Table 3. Pin description

Symbol Pin Description

SX 1 I RX 2 receive signal TX 3 transmit signal GND 4 negative supply voltage TY 5 transmit signal RY 6 receive signal SY 7 I V

8 positive supply voltage

C-bus (SDA or SCL)

SX V

RX SY

TX RY

GND TY

PCA9600DP

002aac837

(MSOP8)

7. Functional description

Refer to Figure 1 “Block diagram of PCA9600”. The PCA9600 has two identical buffers allowing buffering of SDA and SCL I

signals. Each buffer is made up of two logic signal paths, a forwar d path from the I interface, pins SX and SY which drive the buffer ed bus, and a reverse sig nal path from the buffered bus input, pins RX and RY to drive the I

• sense the voltage state of I

C-bus pins SX (and SY) and transmit this state to pin TX

C-bus interface. These paths:

(and TY respectively), and

• sense the state of pins RX and RY and pull the I

C-bus pin LOW whenever pin RX or

pin RY is LOW.

The rest of this discussion will address only the ‘X’ side of the buffer; the ‘Y’ side is identical.

C-bus pin SX is specified to allow interfacing with Fast-mode, Fm+ and TTL-based

The I systems.

Product data sheet Rev. 5 — 5 May 2011 3 of 31

C-bus

NXP Semiconductors

The logic threshold voltage levels at SX on this I2C-bus are independent of the IC supply voltage V

When interfacing with Fast-mode systems, the SX pin is guaranteed to sink the normal 3 mA with a V

C-bus specification for all I2C-bus voltages greater than 3 V, as well as compliance with

SMBus or other systems that use TTL switching levels. SX is guaranteed to sink an external 3 mA in addition to its internally sourced pull-up of

typically 300 μA (maximum 1 mA at −40 °C). When selecting the pull-up for the bus at SX, the sink capability of other connected drivers should be taken into account. Most TTL devices are specified to sink at least 4 mA so then the pull-up is limited to 3 mA by the requirement to ensure the 0.8 V TTL LOW.

. The maximum I2C-bus supply voltage is 15 V.

of 0.74 V maximum. That guarantees compliance with the Fast-mode

PCA9600

Dual bidirectional bus buffer

For Fast-mode I

C-bus operation, the other connecte d I2C-bus parts ma y have the minimum sink capability of 3 mA. SX sources typically 300 μA (maximum 1 mA at −40 °C), which forms part of the external driver loading. When selecting the pull-up it is necessary to subtract the SX pin pull-up current, so, worst-case at −40 °C, the allowed pull-up can be limited (by external drivers) to 2 mA.

When the interface at SX is an Fm+ bus with a voltage greater than 4 V, its higher specified sink capability may be used. PCA9600 has a guaranteed sink capability of 7 mA at V

= 1 V maximum. That 1 V complies with the bus LOW requirement (0.25V

bus

) of any Fm+ bus operating at 4 V or greater. Since the other connected Fm+ devices have a drive capability greater than 20 mA, the pull-up may be selected for 7 mA sink current at V

= 1 V. For a nominal 5 V bus (5.5 V maximum) the allowed pull-up is

(5.5 V − 1V)/7mA=643Ω. With 680 Ω pull-up, the Fm+ rise time of 120 ns maximum can be met with total bus loading up to 200 pF.

The logic level on RX is determined from the power supply voltage V LOW is below 40 % of V threshold just slightly below half V

, and logic HIGH is above 55 % of VCC (with a typical switching

TX is an open-collector output without ESD protection diodes to V via a pull-up resistor to a supply voltage in excess of V

, as long as the 15 V rating is not

exceeded. It has a larger current sinking capability than a normal I

of the chip. Logic

. It may be connected

C-bus device, being able to sink a static current of greater than 30 mA, and typical 100 mA dynamic pull-down capability as well.

A logic LOW is transmitted to TX when the voltage at I logic LOW at RX will cause I

with I

C-bus requirements (maximum 1.5 V in 5 V applications) but not low enough to be

C-bus pin SX to be pulled to a logic LOW level in a ccordance

C-bus pin SX is below 0.425 V. A

looped back to the TX output and cause the buffer to latch LOW.

The LOW level this chip can achieve on the I

C-bus by a LOW at RX is typically 0.64 V

when sinking 1 mA. If the supply voltage V

fails, then neither the I2C-bus nor the TX output will be held

LOW. Their open-collector configuration allows them to be pulled up to the rated maximum of 15 V even without V presents no loading of external signals when V

present. The input configuration on SX and RX also

is not present.

The effective input capacitance of an y signal pin, measured by its effect on bus rise times, is less than 10 pF for all bus voltages and supply voltages including V

Product data sheet Rev. 5 — 5 May 2011 4 of 31

=0V.

NXP Semiconductors

PCA9600

Dual bidirectional bus buffer

Remark: Two or more SX or SY I/Os must not be interconnected. The PCA9600 design

does not support this configuration. Bidirectional I

C-bus signals do not allow any direction control pin so, instead, slightly different logic LOW voltage levels are used at SX/SY to avoid latching of this buffer. A ‘regular I

C-bus LOW’ applied at the RX/RY of a PCA9600 will be propagated to SX/SY as a ‘buffered LOW’ with a slightly higher voltage level. If this special ‘buffered LOW’ is applied to the SX/SY of another PCA9600, that second PCA9600 will not recognize it as a ‘regular I

C-bus LOW’ and will not propagate it to its TX/TY output. The SX/SY side of PCA9600 may not be connected to similar buffers that rely on special logic thresholds for their operation, for example P82B96, PCA9511A, PCA9515A, ‘B’ side of PCA9517, etc. The SX/SY side is only intended for, and compatib le with, the normal I

C-bus logic voltage levels of I2C-bus master and slave chips, or even TX/RX signals of a second PCA9600 or P82B96 if required. The TX/RX and TY/RY I/O pins use the standard I

C-bus logic voltage levels of all I2C-bus parts. There are no restrictions on the interconnection of the TX/RX and TY/RY I/O pins to other PCA9600s, for example in a star or multipoint configurat ion with the TX/RX and TY/R Y I/O pins on the common bus and the SX/SY side connected to the line card slave devices. For more details see Application Note AN10658, “Sending I

C-bus signals via long communication

cables”.

The PCA9600 is a direct upgrade of the P82B96 with the significant differences summarized in Table 4

Table 4. PCA9600 versus P82B96

Detail PCA9600 P82B96

Supply voltage (V Maximum operating bus voltage

(independent of V Typical operating supply current: 5 mA 1 mA Typical LOW-level input voltage on I

(SX/SY side): LOW-level output voltage on I

(SX/SY side; 3 mA sink): LOW-level output voltage on Fm+ I

(SX/SY side; 7 mA sink): Temperature coefficient of V Logic voltage levels on SX/SY bus

(independent of V Typical propagation delays: < 100 ns <200 ns TX/RX switching specifications (I

compliant): RX logic levels with tighter control than

C-bus limit of 30 % to 70 %:

I Maximum bus speed: > 1 MHz > 400 kHz ESD rating HBM per JESD22-A114: > 4500 V > 3500 V Package: SO8, TSSOP8 (MSOP8) DIP8, SO8, TSSOP8 (MSOP8)

) range: 2.5 V to 15 V 2 V to 15 V

C-bus

:0mV/°C −2mV/°C

IL/VOL

C-bus

15 V 15 V

0.5 V over −40 °C to +85 °C 0.65 V at 25 °C

0.74 V (max.) over −40 °C to +85 °C 0.88 V (typ.) at 25 °C

1 V (max.) n/a

compatible with I buses using TTL levels (SMBus, etc.)

yes, all classes including 1 MHz Fm+ yes, all classes including Fm+

yes, 40 % to 55 % (48 % nominal) yes, 42 % to 58 % (50 % nominal)

C-bus and similar

compatible with I2C-bus and similar buses using TTL levels (SMBus, etc.)

Product data sheet Rev. 5 — 5 May 2011 5 of 31

NXP Semiconductors

When the device driving the PCA9600 is an I2C-bus compatible device, then the PCA9600 is an improvement on the P82B96 as shown in Table 4 exceptions however, and if the device driving the bus buffer is not I (e.g., you need to use the micro already in the system and bit-bang using two GPIO pins) then here are some considerations that would point to using the P82B96 instead:

• When the pull-up must be the weakest one possible. The spec is 200 μA for P82B96,

• When the lower operating temperature range is restricted (say 0 °C). The P82B96

• When the operating temperature range is restricted at both limits. An I

PCA9600

Dual bidirectional bus buffer

. There will always be

C-bus compatible

but it typically works even below that. And if designing for a temperature range −40°C up to +60 °C, then the driver when sinking 200 μA only needs to drive a guaranteed low of 0.55 V. For th e PCA9600, over that same temper ature r ange and when sinking

1.3 mA (at −40 °C), the device driving the bus buffer must provide the required low of

0.425 V.

larger SX voltage levels then make a better typical match with the driver, even when the supply is as low as 3.3 V.

For an I low that is below 0.83 V. P82B96 guarantees that with a 200 μA pull-up.

typical output is well below 0.4 V and the P82B96 typically requires 0.6 V input even at +60 °C, so there is a reasonable margin. The PCA9600 requires a typical input low of 0.5 V so its typical margin is smaller. At 0 °C the driver requires a typical input low of 1.16 V and P82B96 provides 0.75 V, so again the typical margin is already quite big and even though PCA9600 is better, providing 0.7 V, that difference is not big.

C-bus compliant driver on 3.3 V the P82B96 is required to guarantee a bus

C driver's

8. Limiting values

Table 5. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages with respect to pin GND.

Symbol Parameter Conditions Min Max Unit

I2C-bus

tot

stg

amb

[1] See also Section 10.2 “Negative undershoot below absolute minimum value”.

supply voltage VCC to GND −0.3 +18 V I2C-bus voltage SX and SY;

output voltage TX and TY;

input voltage RX and RY;

I2C-bus current SX and SY;

total power dissipation - 300 mW junction temperature operating range −40 +125 °C storage temperature −55 +125 °C ambient temperature operating −40 +85 °C

C-bus SDA or SCL

buffered output

receive input

C-bus SDA or SCL

−0.3 +18 V

[1]

−0.3 +18 V

[1]

−0.3 +18 V

- 250 mA

Product data sheet Rev. 5 — 5 May 2011 6 of 31

NXP Semiconductors

9. Characteristics

PCA9600

Dual bidirectional bus buffer

Table 6. Characteristics

=−40°C to +85°C unless otherwise specified; voltages are specified with respect to GND with VCC= 2.5 V to 15 V

amb

unless otherwise specified. Typical values are measured at V

= 5 V and T

amb

=25°C.

Symbol Parameter Conditions Min Typ Max Unit

Power supply

V I

ΔI

supply voltage operating 2.5 - 15 V supply current VCC= 5 V; buses HIGH - 5.2 6.75 mA

= 15 V; buses HIGH - 5.5 7.3 mA

additional supply current per TX/TY output driven LOW;

=5.5V

-1.43.0mA

Bus pull-up (load) voltages and currents

Pins SX and SY; I

O(sink)

input voltage open-collector; RX and RY HIGH - - 15 V output voltage open-collector; RX and RY HIGH - - 15 V output current static; VSX = VSY = 0.4 V output sink current dynamic; VSX = VSY = 1 V;

C-bus

[1]

0.3 - 2 mA 715- mA

RX and RY LOW

leakage current VSX = VSY = 15 V;

--10μA

RX and RY HIGH

Pins TX and TY

V I

load

output voltage open-collector - - 15 V load current maximum recommended on

--30mA buffered bus; VTX=VTY=0.4V; SX and SY LOW on

C-bus = 0.4 V

output current from buffered bus;

60 130 - mA

VTX=VTY= 1 V; SX and SY LOW

C-bus = 0.4 V

on I

leakage current on buffered bus;

--10μA VTX=VTY=VCC= 15 V; SX and SY HIGH

Input currents

input current from I2C-bus on SX and SY

RX and RY HIGH or LOW;

[1]

- −0.3 −1mA

SX and SY LOW ≤ 1V RX and RY HIGH; SX and

[1]

--10μA

SY HIGH > 1.4 V

[2]

from buffered bus on RX and RY;

- −1.5 −10 μA SX and SY HIGH or LOW; V

RX=VRY

leakage current on buffered bus input on RX and

=0.4V

--10μA RY; VRX = VRY=15V

Product data sheet Rev. 5 — 5 May 2011 7 of 31

NXP Semiconductors

PCA9600

Dual bidirectional bus buffer

Table 6. Characteristics

=−40°C to +85°C unless otherwise specified; voltages are specified with respect to GND with VCC= 2.5 V to 15 V

amb

unless otherwise specified. Typical values are measured at VCC= 5 V and T

…continued

amb

=25°C.

Symbol Parameter Conditions Min Typ Max Unit

Output logic LOW level

Pins SX and SY

LOW-level output voltage on Standard-mode or Fast-mode

I2C-bus

= 3 mA; Figure 6 - 0.7 0.74 V = 0.3 mA; Figure 5 - 0.6 0.65 V

C-bus

= 7mA --1V

= 0.3mAto3mA - 0 - %/K

ΔV/ΔT voltage variation with temperature I

SX=ISY

on 5 V Fm+ I

SX=ISY

Input logic switching threshold voltages

Pins SX and SY

V V

IL th(IH)

LOW-level input voltage on normal I2C-bus; Figure 7 HIGH-level input threshold voltage on normal I2C-bus; Figure 8 580--mV

[3]

--425mV

ΔV/ΔT voltage variation with temperature - 0 - %/K

Pins RX and RY

th(i)

HIGH-level input voltage fraction of applied V input threshold voltage fraction of applied V LOW-level input voltage fra c tion of applied V

CC CC CC

0.55VCC--V

-0.48V

-V

--0.4VCCV

Logic level threshold difference

[4]

ΔV voltage difference SX and SY; SX output LOW at

50--mV

0.3 mA to SX input HIGH maximum

Thermal resistance

th(j-pcb)

thermal resistance from junction to printed-circuit board

Bus release on V

supply voltage SX, SY, TX and TY; voltage at

failure

SOT96-1 (SO8); average lead temperature at board interface

-127-K/W

--1V which all buses are to be released at 25 °C

ΔV/ΔT voltage variation with temperature Figure 9

- −4- %/K

Product data sheet Rev. 5 — 5 May 2011 8 of 31

NXP Semiconductors

PCA9600

Dual bidirectional bus buffer

Table 6. Characteristics

=−40°C to +85°C unless otherwise specified; voltages are specified with respect to GND with VCC= 2.5 V to 15 V

amb

unless otherwise specified. Typical values are measured at VCC= 5 V and T

…continued

amb

=25°C.

Symbol Parameter Conditions Min Typ Max Unit

Buffer response time

[5]

VCC = 5 V; pin TX pull-up resistor = 160 Ω; pin SX pull-up resistor = 2.2 kΩ; no capacitive load

delay time VSX to VTX, VSY to VTY; on falling

-50-ns input between VSX= input

-60-ns

switching threshold, and V output falling to 50 % V

to VTX, VSY to VTY; on rising

input between VSX= input

-100-ns

switching threshold, and V output reaching 50 % V

to VSX, VRY to VSY; on falling

input between VRX= input

-95-ns

switching threshold, and V output falling to 50 % V

to VSX, VRY to VSY; on rising

input between VRX= input

switching threshold, and V output reaching 50 % V

Input capacit a nce

input capacitance effective input capacitance of any

--10pF signal pin measured by incremental bus rise times; guaranteed by design, not production tested

[1] This bus pull-up current specification is intended to assist design of the bus pull-up resistor. It is not a specification of the sink cap ability

(see V PCA9600 is guaranteed to sink 3 mA at SX/SY when its pins are holding the bus LOW. However, when an external device pulls the SX/SY pins below 1.4 V, the PCA9600 may source a current between 0 mA and 1 mA maximum. When that other external device is driving LOW it will pull the bus connected to SX or SY down to, or below, the 0.4 V level referenced in the I these test conditions. Then that device must be able to sink up to 1 mA coming from SX/SY plus the usual pull-up current. Therefore the external pull-up used at SX/SY should be limited to 2 mA. The typical and maximum currents sourced by SX/SY as a function of junction

temperature are shown in Figure 10 [2] Valid over temperature for V [3] The input logic threshold is independent of the supply voltage. [4] The minimum value requirement for pull-up current, 0.3 mA, guarantees that the minimum value for V

the maximum V

IC. While the tolerances on absolute levels allow a small probability, the LOW from one SX output is recognized by an SX input of

another PCA9600, this has no consequences for normal applications. In any design the SX pins of different ICs should never be linked

because the resulting system would be very susceptible to induced noise and would not support all I [5] The fall time of V

The fall time of V

The rise time of V

under sub-section “Output logic LOW level”). The maximum static sink current for a Standard/Fast-mode I2C-bus is 3 mA and

C-bus specification and in

, and the equivalent circuit at the SX/SY interface is shown in Figure 4.

≤ 5 V. At higher VCC, this current may increase to maximum −20 μA at VCC=15V.

output LOW will always exceed

input HIGH level to eliminate any possibility of latching. The specified difference is guaranteed by design within any

from 5 V to 2.5 V in the test is approximately 10 ns.

from 5 V to 2.5 V in the test is approximately 20 ns.

from 0 V to 2.5 V in the test is approximately 15 ns.

from 0.7 V to 2.5 V in the test is approximately 25 ns.

C-bus operating modes.

Product data sheet Rev. 5 — 5 May 2011 9 of 31

NXP Semiconductors

002aac839

002aac840

PCA9600

Dual bidirectional bus buffer

≤ 1 mA

Fig 4. Equivalent circuit at SX/SY

800

(mV)

700

600

500

400

−50 1251007550250−25

(1)

(2)

(°C)

VOL at SX typical and limits over temperature. (1) Maximum. (2) Typical.

Fig 5. VOL as a function of junction temperature

=0.3mA)

ref

Fig 6. V

800

(mV)

(1)

(2)

700

600

500

400

−50 1251007550250−25

at SX typical and limits over temperature.

(1) Maximum. (2) Typical.

as a function of junction temperature

=3mA)

SX (SY)

002aac83

(°C)

600

(mV)

typical

500

maximum

400

300

200

−50 1251007550250−25

VIL at SX changes over temperature range. VIH at SX changes over temperature range.

Fig 7. VIL as a function of junction temperature;

maximum and typical values

002aag005

(°C)

600

500

400

300

200

−50 1251007550250−25

minimum

typical

(mV)

Fig 8. VIH as a function of junction temperature;

minimum and typical values

002aag006

(°C)

Product data sheet Rev. 5 — 5 May 2011 10 of 31

+ 21 hidden pages

NXP PCA 9600 D Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual

1. General description

2. Features and benefits

3. Applications

4. Ordering information

4.1 Ordering options

5. Block diagram

6. Pinning information

6.1 Pinning

6.2 Pin description

7. Functional description

8. Limiting values

9. Characteristics