PCA9530
2-bit I2C-bus LED dimmer
Rev. 03 — 26 February 2009 Product data sheet
1. General description
The PCA9530 is a 2-bit I2C-bus and SMBus I/O expander optimized for dimming LEDs in
256 discrete steps for Red/Green/Blue (RGB) color mixing and backlight applications.
The PCA9530 contains an internal oscillator with two user programmable blink rates and
duty cycles coupled to the output PWM. The LED brightness is controlled by setting the
blink rate high enough (> 100 Hz) that the blinking cannot be seen and then using the
duty cycle to vary the amount of time the LED is on and thus the average current through
the LED.
The initial setup sequence programs the two blink rates/duty cycles for each individual
PWM. From then on, only onecommand from the bus master is required to turn individual
LEDs ON, OFF, BLINK RATE 1 or BLINK RATE 2. Based on the programmed frequency
and duty cycle, BLINK RATE 1 and BLINK RATE 2 will cause the LEDs to appear at a
different brightness or blink at periods up to 1.69 second. The open-drain outputs directly
drive the LEDs with maximum output sink current of 25 mA per bit and 50 mA per
package.
2. Features
To blink LEDs at periods greater than 1.69 second, the bus master (MCU, MPU, DSP,
chip set, etc.) must send repeated commands to turn the LED on and off as is currently
done when using normal I/O Expanders like the NXP Semiconductors PCF8574 or
PCA9554. Any bits not used for controlling the LEDs can be used for General Purpose
parallel Input/Output (GPIO) expansion which provides a simple solution when additional
I/O is needed for ACPI power switches, sensors, push buttons, alarm monitoring, fans,
etc.
The active LOW hardware reset pin (RESET) and Power-On Reset (POR) initialize the
registers to their default state causing the bits to be set HIGH (LED off).
One hardware address pin on the PCA9530 allows two devices to operate on the same
bus.
n 2 LED drivers (on, off, flashing at a programmable rate)
n 2 selectable, fully programmable blink rates (frequency and duty cycle) between
0.591 Hz and 152 Hz (1.69 seconds and 6.58 milliseconds)
n 256 brightness steps
n Input/output not used as LED drivers can be used as regular GPIOs
n Internal oscillator requires no external components
n I2C-bus interface logic compatible with SMBus
n Internal power-on reset
NXP Semiconductors
PCA9530
2-bit I2C-bus LED dimmer
n Noise filter on SCL/SDA inputs
n Active LOW reset input (RESET)
n 2 open-drain outputs directly drive LEDs to 25 mA
n Edge rate control on outputs
n No glitch on power-up
n Supports hot insertion
n Low standby current
n Operating power supply voltage range of 2.3 V to 5.5 V
n 0 Hz to 400 kHz clock frequency
n ESD protection exceeds 2000 V HBM per JESD22-A114, 150 V MM per
JESD22-A115 and 1000 V CDM per JESD22-C101
n Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA
n Packages offered: SO8, TSSOP8 (MSOP8)
3. Ordering information
Table 1. Ordering information
T
=−40°C to +85°C
amb
Type number Topside
mark
PCA9530D PCA9530 SO8 plastic small outline package; 8 leads; body width 3.9 mm SOT96-1
PCA9530DP 9530 TSSOP8
Package
Name Description Version
[1]
plastic thin shrink small outline package; 8 leads; body width 3 mm SOT505-1
[1] Also known as MSOP8.
4. Block diagram
PCA9530
SCL
SDA
V
DD
RESET
V
SS
INPUT
FILTERS
POWER-ON
OSCILLATOR
RESET
A0
I2C-BUS
CONTROL
PRESCALER 0
REGISTER
PRESCALER 1
REGISTER
PWM0
REGISTER
PWM1
REGISTER
REGISTER
LED SELECT (LSn)
REGISTER
0
1
BLINK0
BLINK1
INPUT
LEDn
002aae498
Remark: Only one I/O shown for clarity.
Fig 1. Block diagram
PCA9530_3 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 03 — 26 February 2009 2 of 24
NXP Semiconductors
5. Pinning information
5.1 Pinning
PCA9530
2-bit I2C-bus LED dimmer
1
A0 V
2
LED0 SDA
LED1 SCL
V
SS
3
4
PCA9530D
002aae496
8
7
6
5
DD
RESET
Fig 2. Pin configuration for SO8 Fig 3. Pin configuration for TSSOP8
5.2 Pin description
Table 2. Pin description
Symbol Pin Description
A0 1 address input 0
LED0 2 LED driver 0
LED1 3 LED driver 1
V
SS
RESET 5 active LOW reset input
SCL 6 serial clock line
SDA 7 serial data line
V
DD
4 supply ground
8 supply voltage
1
A0 V
2
LED0 SDA
LED1 SCL
V
SS
PCA9530DP
3
4
002aae497
8
7
6
5
DD
RESET
(MSOP8)
6. Functional description
Refer to Figure 1 “Block diagram”.
6.1 Device addressing
Following a START condition, the bus master must output the address of the slave it is
accessing. The address of the PCA9530 is shown in Figure 4. To conserve power, no
internal pull-up resistor is incorporated on the hardwareselectable address pin and it must
be pulled HIGH or LOW.
slave address
1 1 0 0 0 0 A0 R/W
fixed
Fig 4. Slave address
PCA9530_3 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 03 — 26 February 2009 3 of 24
hardware
selectable
002aae499
NXP Semiconductors
The last bit of the address byte defines the operation to be performed. When set to logic 1
a read is selected, while a logic 0 selects a write operation.
6.2 Control register
Followingthe successful acknowledgement of the slave address, the bus master will send
a byte to the PCA9530, which will be stored in the Control register.
PCA9530
2-bit I2C-bus LED dimmer
0 0 0 AI 0 B2 B1 B0
Reset state: 00h
Fig 5. Control register
The lowest 3 bits are used as a pointer to determine which register will be accessed.
If the Auto-Increment flag is set, the three low order bits of the Control register are
automatically incremented after a read or write. This allows the user to program the
registers sequentially. The contents of these bits will rolloverto ‘000’ after the last register
is accessed.
When Auto-Increment flag is set (AI = 1) and a read sequence is initiated, the sequence
must start by reading a register different from the Input register (B2 B1 B0 ≠ 0 0 0).
Only the 3 least significant bits are affected by the AI flag. Unused bits must be
programmed with zeroes.
6.2.1 Control register definition
Table 3. Register summary
B2 B1 B0 Symbol Access Description
0 0 0 INPUT read only input register
0 0 1 PSC0 read/write frequency prescaler 0
0 1 0 PWM0 read/write PWM register 0
0 1 1 PSC1 read/write frequency prescaler 1
1 0 0 PWM1 read/write PWM register 1
1 0 1 LS0 read/write LED selector
Auto-Increment flag
register address
002aae500
PCA9530_3 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 03 — 26 February 2009 4 of 24
NXP Semiconductors
6.3 Register descriptions
6.3.1 INPUT - Input register
The INPUT register reflects the state of the device pins. Writes to this register will be
acknowledged but will have no effect.
Table 4. INPUT - Input register description
Bit 7 6 5 4 3 2 1 0
Symbol ------LED1 LED0
Default 000000XX
Remark: The default value ‘X’ is determined by the externally applied logic level(normally
logic 1) when used for directly driving LED with pull-up to VDD.
6.3.2 PCS0 - Frequency Prescaler 0
PSC0 is used to program the period of the PWM output.
The period of BLINK0 = (PSC0 + 1) / 152.
PCA9530
2-bit I2C-bus LED dimmer
Table 5. PSC0 - Frequency Prescaler 0 register description
Bit 7 6 5 4 3 2 1 0
Symbol PSC0[7] PSC0[6] PSC0[5] PSC0[4] PSC0[3] PSC0[2] PSC0[1] PSC0[0]
Default 00000000
6.3.3 PWM0 - Pulse Width Modulation 0
The PWM0 register determines the duty cycle of BLINK0. The outputs are LOW (LED on)
when the count is less than the value in PWM0 and HIGH (LED off) when it is greater. If
PWM0 is programmed with 00h, then the PWM0 output is always HIGH (LED off).
The duty cycle of BLINK0 = PWM0 / 256.
Table 6. PWM0 - Pulse Width Modulation 0 register description
Bit 7 6 5 4 3 2 1 0
Symbol PWM0
[7]
Default 10000000
PWM0
[6]
PWM0
[5]
6.3.4 PCS1 - Frequency Prescaler 1
PSC1 is used to program the period of the PWM output.
The period of BLINK1 = (PSC1 + 1) / 152.
PWM0
[4]
PWM0
[3]
PWM0
[2]
PWM0
[1]
PWM0
[0]
Table 7. PSC1 - Frequency Prescaler 1 register description
Bit 7 6 5 4 3 2 1 0
Symbol PSC1[7] PSC1[6] PSC1[5] PSC1[4] PSC1[3] PSC1[2] PSC1[1] PSC1[0]
Default 00000000
PCA9530_3 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 03 — 26 February 2009 5 of 24
NXP Semiconductors
6.3.5 PWM1 - Pulse Width Modulation 1
The PWM1 register determines the duty cycle of BLINK1. The outputs are LOW (LED on)
when the count is less than the value in PWM1 and HIGH (LED off) when it is greater.
If PWM1 is programmed with 00h, then the PWM1 output is always HIGH (LED off).
The duty cycle of BLINK1 = PWM1 / 256.
Table 8. PWM1 - Pulse Width Modulation 1 register description
Bit 7 6 5 4 3 2 1 0
Symbol PWM1
Default 10000000
6.3.6 LS0 - LED selector
The LS0 LED select register determines the source of the LED data.
00 = output is set high-impedance (LED off; default)
01 = output is set LOW (LED on)
10 = output blinks at PWM0 rate
11 = output blinks at PWM1 rate
[7]
PWM1
[6]
PWM1
[5]
PWM1
[4]
PWM1
[3]
PCA9530
2-bit I2C-bus LED dimmer
PWM1
[2]
PWM1
[1]
PWM1
[0]
Table 9. LS0 - LED selector register bit description
Legend: * default value.
Register Bit Value Description
LS0 7:4 1111* reserved
3:2 00* LED1 selected
1:0 00* LED0 selected
6.4 Pins used as GPIOs
LEDn pins not used to control LEDs can be used as General Purpose I/Os (GPIOs).
For use as input, set LEDn to high-impedance (00) and then read the pin state via the
INPUT register.
For use as output, connect external pull-up resistor to the pin and size it according to the
DC recommended operating characteristics. LEDn output pin is HIGH when the output is
programmed as high-impedance, and LOW when the output is programmed LOW through
the ‘LED selector’ register LS0. The output can be pulse-width controlled when PWM0 or
PWM1 are used.
6.5 Power-on reset
When power is applied to VDD, an internal Power-On Reset (POR) holds the PCA9530 in
a reset condition until VDDhas reached V
and the PCA9530 registers are initialized to their default states, all the outputs in the
OFF state. Thereafter, VDD must be lowered below 0.2 V to reset the device.
. At that point, the reset condition is released
POR
PCA9530_3 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 03 — 26 February 2009 6 of 24
NXP Semiconductors
6.6 External RESET
PCA9530
2-bit I2C-bus LED dimmer
A reset can be accomplished by holding the RESET pin LOW for a minimum of t
PCA9530 registers and I2C-bus state machine will be held in their default states until the
RESET input is once again HIGH.
This input requires a pull-up resistor to VDD if no active connection is used.
7. Characteristics of the I2C-bus
The I2C-bus is for 2-way, 2-line communication between different ICs or modules. The two
lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be
connected to a positive supply via a pull-up resistor when connected to the output stages
of a device. Data transfer may be initiated only when the bus is not busy.
7.1 Bit transfer
One data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the HIGH period of the clock pulse as changes in the data line at this time
will be interpreted as control signals (see Figure 6).
SDA
SCL
w(rst)
. The
Fig 6. Bit transfer
7.1.1 START and STOP conditions
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW
transition of the data line while the clock is HIGH is defined as the START condition (S). A
LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP
condition (P) (see Figure 7).
SDA
SCL
S
START condition
Fig 7. Definition of START and STOP conditions
data line
stable;
data valid
change
of data
allowed
mba607
P
STOP condition
mba608
PCA9530_3 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 03 — 26 February 2009 7 of 24
NXP Semiconductors
7.2 System configuration
A device generating a message is a ‘transmitter’; a device receiving is the ‘receiver’. The
device that controls the message is the ‘master’ and the devices which are controlled by
the master are the ‘slaves’ (see Figure 8).
SDA
SCL
PCA9530
2-bit I2C-bus LED dimmer
MASTER
TRANSMITTER/
RECEIVER
Fig 8. System configuration
7.3 Acknowledge
The number of data bytes transferred between the START and the STOP conditions from
transmitter to receiver is not limited. Each byte of eight bits is followed by one
acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter,
whereas the master generates an extra acknowledge related clock pulse.
A slavereceiver which is addressed must generate an acknowledge after the reception of
each byte. Also a master must generate an acknowledge after the reception of each byte
that has been clocked out of the slave transmitter. The device that acknowledges has to
pull down the SDA line during the acknowledge clock pulse, so that the SDA line is stable
LOW during the HIGH period of the acknowledge related clock pulse; set-up and hold
times must be taken into account.
A master receiver must signal an end of data to the transmitter by not generating an
acknowledge on the last byte that has been clocked out of the slave. In this event, the
transmitter must leave the data line HIGH to enable the master to generate a STOP
condition.
SLAVE
RECEIVER
SLAVE
TRANSMITTER/
RECEIVER
MASTER
TRANSMITTER
MASTER
TRANSMITTER/
RECEIVER
SLAVE
I2C-BUS
MULTIPLEXER
002aaa966
data output
by transmitter
not acknowledge
data output
by receiver
acknowledge
SCL from master
S
START
condition
clock pulse for
acknowledgement
9821
002aaa987
Fig 9. Acknowledgement on the I2C-bus
PCA9530_3 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 03 — 26 February 2009 8 of 24
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