P82B96
Dual bidirectional bus buffer
Rev. 08 — 10 November 2009 Product data sheet
1. General description
The P82B96 is a bipolar IC that creates a non-latching, bidirectional, logic interface
between the normal I2C-bus and a range of other bus configurations. It can interface
I2C-bus logic signals to similar buses having different voltage and current levels.
For example, it can interface to the 350 µA SMBus, to 3.3 V logic devices, and to 15 V
levels and/or low-impedance lines to improve noise immunity on longer bus lengths.
It achieves this interface without any restrictions on the normal I2C-bus protocols or clock
speed. The IC adds minimal loading to the I2C-bus node, and loadings of the new bus or
remote I2C-bus nodes are not transmitted or transformed to the local node. Restrictions
on the number of I2C-bus devices in a system, or the physical separation between them,
are virtually eliminated. Transmitting SDA and SCL signals via balanced transmission
lines (twisted pairs) or with galvanic isolation (opto-coupling) is simple because separate
directional Tx and Rx signals are provided. The Tx and Rx signals may be directly
connected, without causing latching, to provide an alternative bidirectional signal line with
I2C-bus properties.
2. Features
n Bidirectional data transfer of I2C-bus signals
n Isolates capacitance allowing 400 pF on Sx/Sy side and 4000 pF on Tx/Ty side
n Tx/Ty outputs have 60 mA sink capability for driving low-impedance or high capacitive
buses
n 400 kHz operation over at least 20 meters of wire (see
n Supply voltage range of 2 V to 15 V with I2C-bus logic levels on Sx/Sy side
independent of supply voltage
n Splits I2C-bus signal into pairs of forward/reverse Tx/Rx, Ty/Ry signals for interface
with opto-electrical isolators and similar devices that need unidirectional input and
output signal paths.
n Low power supply current
n ESD protection exceeds 3500 V HBM per JESD22-A114, 250 V DIP package, 400 V
SO package MM per JESD22-A115, and 1000 V CDM per JESD22-C101
n Latch-up free (bipolar process with no latching structures)
n Packages offered: DIP8, SO8 and TSSOP8
AN10148
)
NXP Semiconductors
3. Applications
n Interface between I2C-buses operating at different logic levels (for example, 5 V and
3 V or 15 V)
n Interface between I2C-bus and SMBus (350 µA) standard
n Simple conversion of I2C-bus SDA or SCL signals to multi-drop differential bus
hardware, for example, via compatible PCA82C250
n Interfaces with opto-couplers to provide opto-isolation between I2C-bus nodes up to
400 kHz
4. Ordering information
Table 1. Ordering information
Type number Package
P82B96DP TSSOP8 plastic thin shrink small outline package; 8 leads;
P82B96PN DIP8 plastic dual in-line package; 8 leads (300 mil) SOT97-1
P82B96TD SO8 plastic small outline package; 8 leads;
P82B96TD/S900 SO8 plastic small outline package; 8 leads;
P82B96
Dual bidirectional bus buffer
Name Description Version
SOT505-1
body width 3 mm
SOT96-1
body width 3.9 mm
SOT96-1
body width 3.9 mm
4.1 Ordering options
Table 2. Ordering options
Type number Topside mark Temperature range
P82B96DP 82B96 −40 °C to +85 °C
P82B96PN P82B96PN −40 °C to +85 °C
P82B96TD P82B96T −40 °C to +85 °C
P82B96TD/S900 P82B96T −40 °C to +125 °C
P82B96_8 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 08 — 10 November 2009 2 of 32
NXP Semiconductors
5. Block diagram
Sx (SDA)
Sy (SCL)
VCC (2 V to 15 V)
8
P82B96
1
7
4
3
2
5
6
P82B96
Dual bidirectional bus buffer
Tx (TxD, SDA)
Rx (RxD, SDA)
Ty (TxD, SCL)
Ry (RxD, SCL)
GND
002aab976
Fig 1. Block diagram of P82B96
6. Pinning information
6.1 Pinning
P82B96TD
P82B96TD/S900
1
1
Sx V
2
Rx Sy
P82B96PN
3
Tx Ry
4
GND Ty
002aab977
8
7
6
5
CC
Sx V
2
Rx Sy
3
Tx Ry
4
GND Ty
002aab978
Fig 2. Pin configuration for DIP8 Fig 3. Pin configuration for SO8 Fig 4. Pin configuration for
6.2 Pin description
8
CC
7
6
5
1
Sx V
2
Rx Sy
Tx Ry
GND Ty
3
4
P82B96DP
002aab979
TSSOP8
8
CC
7
6
5
Table 3. Pin description
Symbol Pin Description
2
Sx 1 I
C-bus (SDA or SCL)
Rx 2 receive signal
Tx 3 transmit signal
GND 4 negative supply
Ty 5 transmit signal
Ry 6 receive signal
2
Sy 7 I
V
CC
P82B96_8 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 08 — 10 November 2009 3 of 32
8 positive supply voltage
C-bus (SDA or SCL)
NXP Semiconductors
7. Functional description
Refer to Figure 1 “Block diagram of P82B96”.
The P82B96 has two identical buffers allowing buffering of both of the I2C-bus (SDA and
SCL) signals. Each buffer is made up of two logic signal paths, a forward path from the
I2C-bus interface pin which drives the buffered bus, and a reverse signal path from the
buffered bus input to drive the I2C-bus interface. Thus these paths are:
P82B96
Dual bidirectional bus buffer
• sense the voltage state of the I
Tx (Ty respectively), and
• sense the state of the pin Rx (Ry) and pull the I
LOW.
The rest of this discussion will address only the ‘x’ side of the buffer; the ‘y’ side is
identical.
The I2C-bus pin (Sx) is designed to interface with a normal I2C-bus.
The logic threshold voltage levels on the I2C-bus are independent of the IC supply VCC.
The maximum I2C-bus supply voltage is 15 V and the guaranteed static sink current is
3 mA.
The logic level of Rx is determined from the power supply voltage VCC of the chip. Logic
LOW is below 42 % of VCC, and logic HIGH is above 58 % of VCC(with a typical switching
threshold of half VCC).
Tx is an open-collector output without ESD protection diodes to VCC. It may be connected
via a pull-up resistor to a supply voltage in excess of VCC, as long as the 15 V rating is not
exceeded. It has a larger current sinking capability than a normal I2C-bus device, being
able to sink a static current of greater than 30 mA, and typical 100 mA dynamic pull-down
capability as well.
A logic LOW is only transmitted to Tx when the voltage at the I2C-bus pin (Sx) is below
0.6 V. A logic LOW at Rx will cause the I2C-bus (Sx) to be pulled to a logic LOW level in
accordance with I2C-bus requirements (maximum 1.5 V in 5 V applications) but not low
enough to be looped back to the Tx output and cause the buffer to latch LOW.
2
C-bus pin Sx (or Sy) and transmit this state to the pin
2
C-bus pin LOW whenever Rx (Ry) is
The minimum LOW level this chip can achieve on the I2C-bus by a LOW at Rx is typically
0.8 V.
If the supply voltageVCCfails,thenneithertheI2C-bus nor the Tx output willbeheldLOW.
Their open-collector configuration allows them to be pulled up to the rated maximum of
15 V even without VCC present. The input configuration on Sx and Rx also present no
loading of external signals even when VCC is not present.
The effectiveinput capacitance of any signal pin, measured by its effectonbusrise times,
is less than 7 pF for all bus voltages and supply voltages including VCC=0V.
Remark: Two or more Sx or Sy I/Os must not be interconnected. The P82B96 design
does not support this configuration. Bidirectional I2C-bus signals do not allow any
direction control pin so,instead,slightlydifferent logic low voltage levels are used at Sx/Sy
to avoid latching of this buffer. A ‘regular I2C-bus LOW’ applied at the Rx/Ry of a P82B96
will be propagated to Sx/Sy as a ‘buffered LOW’ with a slightly higher voltage level. If this
P82B96_8 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 08 — 10 November 2009 4 of 32
NXP Semiconductors
special ‘buffered LOW’ is applied to the Sx/Sy of another P82B96 that second P82B96 will
not recognize it as a ‘regular I2C-bus LOW’ and will not propagate it to its Tx/Ty output.
The Sx/Sy side of P82B96 may not be connected to similar buffers that rely on special
logic thresholds for their operation, for example PCA9511, PCA9515, or PCA9518. The
Sx/Sy side is only intended for, and compatible with, the normal I2C-bus logic voltage
levels of I2C-bus master and slave chips, or even Tx/Rx signals of a second P82B96 if
required. The Tx/Rx and Ty/Ry I/O pins use the standard I2C-bus logic voltage levels of all
I2C-bus parts. There are no restrictions on the interconnection of the Tx/Rx and Ty/Ry I/O
pins to other P82B96s, for example in a star or multipoint configuration with the Tx/Rx and
Ty/Ry I/O pins on the common bus and the Sx/Sy side connected to the line card slave
devices. For more details see
8. Limiting values
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Voltages with respect to pin GND.
Symbol Parameter Conditions Min Max Unit
V
CC
V
Sx
V
Tx
V
Rx
I
n
P
tot
T
j
T
stg
T
amb
[1] See also Section 10.2 “Negative undershoot below absolute minimum value”.
P82B96
Dual bidirectional bus buffer
Application Note AN255
supply voltage VCC to GND −0.3 +18 V
voltage on pin Sx I2C-bus SDA or SCL −0.3 +18 V
voltage on pin Tx buffered output
voltage on pin Rx receive input
current on any pin - 250 mA
total power dissipation - 300 mW
junction temperature operating range
P82B96TD/S900
storage temperature −55 +125 °C
ambient temperature operating −40 +85 °C
.
[1]
−0.3 +18 V
[1]
−0.3 +18 V
−40 +125 °C
P82B96_8 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 08 — 10 November 2009 5 of 32
NXP Semiconductors
9. Characteristics
Table 5. Characteristics
T
= +25°C; voltages are specified with respect to GND with VCC= 5 V, unless otherwise specified.
amb
Symbol Parameter Conditions T
Min Typ Max Min Max
Power supply
V
CC
I
CC
supply voltage operating 2.0 - 15 2.0 15 V
supply current buses HIGH - 0.9 1.8 - 3 mA
=15V;
V
CC
buses HIGH
∆I
CC
additional quiescent
per Tx or Ty LOW - 1.7 3.5 - 3.5 mA
supply current
Bus pull-up (load) voltages and currents
, V
V
Sx
maximum input/output
Sy
voltage
open-collector;
2
I
C-busandVRx,VRy=
HIGH
, I
I
Sx
Sy
, I
I
Sx
Sy
, I
I
Sx
Sy
, V
V
Tx
static output loading on
2
I
C-bus
dynamic output sink
capability on I
leakage current on
2
I
C-bus
maximumoutputvoltage
Ty
2
C-bus
, VSy= 1.0 V;
V
Sx
V
Rx,VRy
V
Sx
V
Rx,VRy
V
Sx
V
Rx,VRy
V
Sx
V
Rx,VRy
=LOW
, VSy=2V;
=LOW
, VSy=5V;
= HIGH
, VSy=15V;
= HIGH
open-collector - - 15 - 15 V
[2]
0.2 - 3 0.2 3 mA
718- 7 -mA
level
, I
I
Tx
Ty
, I
I
Tx
Ty
, I
I
Tx
Ty
static output loading on
buffered bus
dynamic output sink
capability, buffered bus
leakage current on
buffered bus
VTx, VTy= 0.4 V;
V
2
I
= LOW on
Sx,VSy
C-bus = 0.4 V
VTx, VTy>1V;
V
2
I
= LOW on
Sx,VSy
C-bus = 0.4 V
VTx, VTy=VCC=15V;
V
, VSy= HIGH
Sx
60 100 - 60 - mA
Input currents
, I
I
Sx
Sy
, I
I
Rx
Ry
, I
I
Rx
Ry
input current from
2
I
C-bus
input current from
buffered bus
leakage current on
bus LOW;
VRx,VRy= HIGH
bus LOW;
V
Rx,VRy
VRx, VRy=V
= 0.4 V
CC
buffered bus input
Output logic LOW level
V
dV
dV
, V
Sx
Sx
Sy
output logic level LOW
Sy
on normal I
/dT,
temperature coefficient
/dT
of output LOW levels
2
C-bus
, ISy=3mA
I
Sx
, ISy= 0.2 mA
I
Sx
, ISy= 0.2 mA
I
Sx
[3]
0.8 0.88 1.0 (see Figure 6)V
[3]
670 730 790 (see Figure 5)mV
[3]
= +25 °C T
amb
- 1.1 2.5 - 4 mA
--15-15V
--1 -10µA
-1- - 10µA
- - 30 - 30 mA
-1- - 10µA
- −1- - −10 µA
- −1- - −10 µA
-1- - 10µA
- −1.8 - - - mV/K
P82B96
Dual bidirectional bus buffer
= −40 °C to
amb
+125 °C
[1]
Unit
P82B96_8 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 08 — 10 November 2009 6 of 32
NXP Semiconductors
P82B96
Dual bidirectional bus buffer
Table 5. Characteristics
T
= +25°C; voltages are specified with respect to GND with VCC= 5 V, unless otherwise specified.
amb
Symbol Parameter Conditions T
…continued
= +25 °C T
amb
Min Typ Max Min Max
Input logic switching threshold voltages
, V
V
Sx
, V
V
Sx
input logic voltage LOW on normal I2C-bus
Sy
input logic level HIGH
Sy
on normal I2C-bus
[4]
- 640 600 (see Figure 7)mV
[4]
700 650 - (see Figure 8)mV
threshold
/dT,
dV
dV
V
V
V
Rx
Rx
Rx
Sx
Sy
, V
, V
, V
temperature coefficient
/dT
of input thresholds
input logic HIGH level fraction of applied V
Ry
input threshold fraction of applied V
Ry
input logic LOW level fraction of applied V
Ry
CC
CC
CC
- −2 - - - mV/K
0.58V
- 0.5V
- - 0.58V
CC
CC
- - 0.42V
Logic level threshold difference
, V
V
Sx
input/output logic level
Sy
difference
VSx output LOW at
0.2 mA − V
Sx
input
[2]
50 85 - 50 - mV
HIGH maximum
Thermal resistance
R
th(j-pcb)
thermal resistance from
junctiontoprinted-circuit
board
SOT96-1 (SO8);
average lead
temperature at board
- 127 - - - K/W
interface
Bus release on V
V
V
Sx
Tx
, VSy,
, V
VCC voltage at which all
busesare guaranteed to
Ty
failure
CC
- - 1 (see Figure 9)V
be released
dV/dT temperature coefficient
- −4 - - - mV/K
of guaranteed release
voltage
Buffer response time
T
fall delay
VSxtoVTx,
V
to V
Sy
buffer time delay on
falling input between
V
Ty
Sx
threshold, and V
[5]
= input switching
Tx
R
pull-up = 160 Ω;
Tx
no capacitive load;
V
=5V
CC
-70- - -ns
output falling 50 %
T
rise delay
VSxtoVTx,
V
to V
Sy
Ty
buffer time delay on
rising input between
V
= input switching
Sx
threshold, and V
Tx
RTx pull-up = 160 Ω;
no capacitive load;
V
=5V
CC
-90- - -ns
output reaching 50 %
V
CC
= −40 °C to
amb
+125 °C
CC
[1]
Unit
-V
---V
CC
- 0.42VCCV
P82B96_8 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 08 — 10 November 2009 7 of 32
NXP Semiconductors
P82B96
Dual bidirectional bus buffer
Table 5. Characteristics
T
= +25°C; voltages are specified with respect to GND with VCC= 5 V, unless otherwise specified.
amb
Symbol Parameter Conditions T
…continued
= +25 °C T
amb
= −40 °C to
amb
+125 °C
[1]
Unit
Min Typ Max Min Max
T
fall delay
VRx to
V
, V
Sx
to V
Sy
buffer time delay on
falling input between
V
Ry
= input switching
Rx
threshold, and V
Sx
R
pull-up = 1500 Ω;
Sx
no capacitive load;
V
=5V
CC
- 250 - - - ns
output falling 50 %
T
rise delay
VRx to
V
, V
Sx
to V
Sy
buffer time delay on
rising input between
V
Ry
= input switching
Rx
threshold, and V
RSx pull-up = 1500 Ω;
- 270 - - - ns
no capacitive load;
V
=5V
CC
Sx
output reaching 50 %
V
CC
Input capacitance
C
i
input capacitance effective input
--7 - 7pF
capacitance of any
signal pin measured
by incremental bus
rise times
[1] Limit data for +125 °C applies to P82B96TD/S900 version. It is guaranteed by design/characterization, but not by 100 % test.
[2] The minimum value requirement for pull-up current, 200 µA, guarantees that the minimum value for VSxoutput LOW will always exceed
the minimum VSxinput HIGH level to eliminate any possibility of latching. The specified difference is guaranteed by design within any IC.
While the tolerances on absolute levels allow a small probability the LOW from one Sx output is recognized by an Sx input of another
P82B96, this has no consequences for normal applications. In any design the Sx pins of different ICs should never be linked because
the resulting system would be very susceptible to induced noise and would not support all I2C-bus operating modes.
[3] The output logic LOW depends on the sink current. For scaling, see
[4] The input logic threshold is independent of the supply voltage.
[5] The fall time of VTx from 5 V to 2.5 V in the test is approximately 15 ns.
The fall time of VSx from 5 V to 2.5 V in the test is approximately 50 ns.
The rise time of VTx from 0 V to 2.5 V in the test is approximately 20 ns.
The rise time of VSx from 0.9 V to 2.5 V in the test is approximately 70 ns.
Application Note AN255
.
P82B96_8 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 08 — 10 November 2009 8 of 32
NXP Semiconductors
P82B96
Dual bidirectional bus buffer
1000
V
OL
(mV)
800
600
400
−50 1251007550250−25
002aac069
(1)
(2)
(3)
T
(°C)
j
VOL at Sx typical and limits over temperature
(1) Maximum
(2) Typical
(3) Minimum
Fig 5. VOL as a function of junction temperature
(I
= 0.2 mA)
OL
1000
V
IL(max)
(mV)
800
002aac071
1200
V
OL
(mV)
1000
800
600
400
−50 1251007550250−25
(1) Maximum
(2) Typical
(3) Minimum
Fig 6. V
1000
V
IH(min)
(mV)
800
002aac070
T
(°C)
j
VOL at Sx typical and limits over temperature
as a function of junction temperature
OL
(I
= 3 mA)
OL
002aac072
(1)
(2)
(3)
600
400
200
−50 1251007550250−25
Fig 7. V
T
(°C)
j
V
at Sx changes over temperature range V
IL(max)
as a function of junction temperature Fig 8. V
IL(max)
1400
V
CC(max)
(mV)
1200
1000
800
600
400
−50 1251007550250−25
600
400
200
−50 1251007550250−25
at Sx changes over temperature range
IH(min)
as a function of junction temperature
IH(min)
002aac075
T
(°C)
j
T
(°C)
j
Fig 9. V
P82B96_8 © NXP B.V. 2009. All rights reserved.
that guarantees bus release limit over temperature
CC(max)
Product data sheet Rev. 08 — 10 November 2009 9 of 32
NXP Semiconductors
10. Application information
P82B96
Dual bidirectional bus buffer
Refer to
AN460
and
AN255
I2C-bus
SDA
for more application detail.
+VCC (2 V to 15 V)
+5 V
Tx
(SDA)
Rx
(SDA)
1
/
P82B96
2
R1
'SDA' (new levels)
Fig 10. Interfacing an ‘I2C’ type of bus with different logic levels
I2C-bus
SDA
R1
+5 V
1
/
P82B96
2
R2
Rx
(SDA)
Tx
(SDA)
+V
CC
R3
+V
R4
002aab986
CC1
R5
I2C-bus
SDA
002aab987
2
Fig 11. Galvanic isolation of I
main enclosure
3.3 V to 5 V
SDA
SCL
Fig 12. Long distance I
P82B96_8 © NXP B.V. 2009. All rights reserved.
12 V
P82B96
2
C-bus nodes via opto-couplers
long cables
12 V3.3 V to 5 V
C-bus communications
remote control enclosure
3.3 V to 5 V
12 V
3.3 V to 5 V
P82B96
SDA
SCL
002aab988
Product data sheet Rev. 08 — 10 November 2009 10 of 32
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