P82B715
I2C-bus extender
Rev. 08 — 9 November 2009 Product data sheet
1. General description
The P82B715 is a bipolar IC intended for application in I2C-bus and derivative bus
systems. While retaining all the operating modes and features of the I2C-bus it permits
extension of the practical separation distance between components on the I2C-bus by
buffering both the data (SDA) and the clock (SCL) lines.
The I2C-bus capacitance limit of 400 pF restricts practical communication distances to a
few meters. Using one P82B715 at each end of a long cable (connecting Lx/Ly to Lx/Ly)
reduces that cable’s loading on the linked I2C-buses by a factor of 10 and allows the total
system capacitance load (all devices,cable, connectors,andtracesor wires connected to
the I2C-bus) to be around 3000 pF while the loading on each I2C-bus on the Sx/Sy sides
remains below 400 pF. Longer cables or low-cost, general-purpose wiring may be used to
link I2C-bus based modules without degrading noise margins. Multiple P82B715s can be
connected together, linking their Lx/Ly ports, in a star or multi-point architecture as long as
the total capacitance of the system is less than about 3000 pF and each bus at an Sx/Sy
connection is well below 400 pF. This configuration, with the master and/or slave devices
attached to the Sx/Sy port of each P82B715, has full multi-master communication
capability. The P82B715 alone does not support voltage level translation, but it can be
simply implemented using low cost transistors when required. There is no restriction on
interconnecting the Sx/Sy I/Os, and, because the device output levels are always held
within 100 mV of input drive levels, P82B715 is compatible with bus buffers that use
voltage level offsets, e.g., PCA9511A, PCA9517, Sx/Sy side of P82B96.
2. Features
The lower VOL level and ability to operate with any master, slave or bus buffer is the
primary advantage of the using the P82B715 for long distance buses at the disadvantage
of not isolating bus capacitance like the P82B96 or PCA9600 are able to do. The primary
disadvantage of the P82B96 and PCA9600 is that the static level offset needed to isolate
bus capacitance does not allow these devices to operate with other bus buffers with
special offset levels or with master/slaves that require a VIL lower than 0.8 V with noise
margin. A proven quick design-in point-to-point/multi-point circuit (Figure 9) is included in
Section 8.2 to allow rapid use of the P82B715 along with comparison waveforms so that
the designer can clearly see the trade-offs between the P82B715 and the
P82B96/PCA9600 and choose the type of device that is best for their application.
n Dual, bidirectional, unity voltage gain buffer with no external directional control
required
n Compatible with I2C-bus and its derivatives SMBus, PMBus, DDC, etc.
n Logic signal levels may include (but not exceed) both supply and ground
n Logic signal input voltage levelsare output without change and are independent of V
n ×10 impedance transformation, but does not change logic voltage levels
CC
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n Supply voltage range 3 V to 12 V
n Clock speeds to at least 100 kHz and 400 kHz when other system delays permit
n ESD protection exceeds 2500 V HBM per Mil. Std 883C-3015.7 and 400 V MM per
JESD22-A115 (I/Os have diodes to VCC and GND)
n Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA
3. Applications
n Increase the total connected capacitance of an I2C-bus system to around 3000 pF
n Drive I2C-bus signals over long cables to approximately 50 meters or 3000 pF
n Drives ×10 lower impedance bus wiring for improved noise immunity
n Multi-drop distribution of I2C-bus signals using low cost twisted-pair cables
n AdvancedTCA radial IPMB architecture
n Driving 30 mA Fm+ devices from standard 3 mA parts
4. Ordering information
P82B715
I2C-bus extender
Table 1. Ordering information
Type number Package
Name Description Version
P82B715PN DIP8 plastic dual in-line package; 8leads (300 mil) SOT97-1
P82B715TD SO8 plastic small outline package; 8 leads; body width 3.9 mm SOT96-1
[1] For applications requiring lower voltage operation, or additional buffer performance, see application notes
AN255, “I2C/SMBus repeaters, hubs and expanders”
P82B715 I2C-bus extender”
[1]
and
AN10710, “Features and applications of the
.
4.1 Ordering options
Table 2. Ordering options
Type number Topside mark Temperature range
P82B715PN P82B715PN −40 °C to +85 °C
P82B715TD P82B715 −40 °C to +85 °C
P82B715_8 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 08 — 9 November 2009 2 of 23
NXP Semiconductors
5. Block diagram
P82B715
P82B715
I2C-bus extender
V
CC
Fig 1. Block diagram of P82B715
6. Pinning information
6.1 Pinning
n.c. V
GND n.c.
SDA LDA
SCL
P82B715PN
1
2
Lx Ly
3
Sx Sy
4
002aad686
8
CC
7
6
5
BUFFER
BUFFER
GND
002aad689
P82B715TD
1
n.c. V
2
Lx Ly
3
Sx Sy
4
GND n.c.
002aad687
LCL
8
7
6
5
CC
Fig 2. Pin configuration for DIP8 Fig 3. Pin configuration for SO8
6.2 Pin description
Table 3. Pin description
Symbol Pin Description
n.c. 1 not connected
Lx 2 buffered bus, LDA or LCL
2
Sx 3 I
GND 4 negative supply
n.c. 5 not connected
Sy 6 I
Ly 7 buffered bus, LCL or LDA
V
CC
P82B715_8 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 08 — 9 November 2009 3 of 23
8 positive supply
C-bus, SDA or SCL
2
C-bus, SCL or SDA
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7. Functional description
The P82B715 is a dual bidirectional logic signal device having unity voltage gain in both
directions, but ×10 current amplification in one direction that allows increasing the
allowableI2C-bus system capacitance. It contains identical circuits for each I2C-bus signal
and requires no external directional control. It uses unidirectional analog current
amplification to increase the current sink capability of I2C-bus chips by a factor of 10 and
to change the I2C-bus specification limit of 400 pF to a 4 nF system limit. This allows
I2C-bus, or similar bus systems, to be extended over long distances using conventional
cables and without degradation of system performance.
P82B715 provides current amplification from its I2C-bus to its low-impedance or buffered
bus. Whenever current is flowing out of Sx, into an I2C-bus chip driving the I2C-bus LOW,
P82B715 will sink ten times that current into Lx to drive the buffered bus LOW (see
Figure 4).
To minimize interference and ensure stability, the current rise and fall times of the Lx drive
amplifier are internally controlled.
The P82B715 does not amplify signal currents flowing in the other direction, i.e., into Sx
from the I2C-bus.The Sx pin is driven LOW by current flowing out of Lx to the driver of that
buffered side.
P82B715
I2C-bus extender
The buffered bus logic LOW voltage at Lx simply drives the I2C-bus at Sx LOW via the
internal 30 Ω resistor. The buffer’s offset voltage (the difference between Sx and Lx)
depends on the current flowing in the sense resistor so it will be very small when the bus
currents are small, but it is guaranteed not to exceed 100 mV in either direction with full
static I2C-bus loading.
The unity voltage gain, with signal current amplification dependent on direction, preserves
the multi-master, bidirectional, open-collector/open-drain, characteristic of any connected
I2C-bus lines and provides these characteristics to the new low-impedance bus. Bus logic
signal voltage levels will be clamped at (VCC+ 0.7 V), but otherwise are independent of
the supply voltage VCC.
= I
I
Sx
Lx
I
Sx
9 × I
I
= 10 × I
Lx
Sx
Sx
Lx buffered bus
002aad688
I2C-bus Sx
V
CC
GND
I
Sx
CURRENT
SENSE
30 Ω
Fig 4. Equivalent circuit: one-half P82B715
7.1 Sx, Sy: I2C-bus SDA or SCL
On the normal side, because the two buffer circuits in the P82B715 are identical, either
the Sx or Sy input pins can be used as the I2C-bus SDA data line, or the SCL clock line.
P82B715_8 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 08 — 9 November 2009 4 of 23
NXP Semiconductors
7.2 Lx, Ly: buffered bus LDA or LCL
On the special low-impedance or buffered line side, the corresponding output at the Lx or
Ly pins becomes the LDA data line or LCL clock line.
7.3 VCC, GND: positive and negative supply pins
The power supply voltages at each P82B715 used in a system are normally nominally the
same. If they differ by a significant amount, noise margin may be sacrificed as the bus
HIGH level should not exceed the lowest of those supplies.
8. Application design-in information
By using two (or more) P82B715 ICs, a sub-system can be built that retains the interface
characteristics of a normal I2C-bus device so that the sub-system may be included in, or
added onto, any I2C-bus or related system.
The sub-system shown in Figure 5 features a low-impedance or buffered bus, capable of
driving large wiring capacitance.
P82B715
I2C-bus extender
The P82B715 will operate with a supply voltage from 3 V to 12.5 V but the logic signal
levels at Sx/Lx are independent of the chip’s supply. They remain at the levels presented
to the chip by the attached ICs. The maximum static I2C-bus sink current, 3 mA, flowing in
either direction in the internal current sense resistor,causes a difference, or offset voltage,
less than 100 mV between the bus logic LOW levels at Sx and Lx. This makes P82B715
fully compatible with all logic signal drivers, including TTL. The P82B715 cannot modify
the bus logic signal voltage levelsbut it contains internal diodes connected between Lx/Sx
and VCC that will conduct and limit the logic signal swing if the applied logic levels would
have exceeded the supply voltage by more than 0.7 V. In normal applications external
pull-up resistors will pull the connected buses up to the desired voltage HIGH level.
Usually this will be the chip supply, VCC, but for very low logic voltages it is necessary to
use a VCC of at least 3.3 V and preferably even higher. Note that full performance over
temperature is only guaranteed from 4.5 V. Specification de-ratings apply when its supply
voltage is reduced below 4.5 V. The absolute minimum VCC is 3 V.
SDA
SCL
P82B715
1/2
1/2
V
CC
V
CC
long
cable
LDA
LCL
V
V
CC
CC
P82B715
SDA
1/2
I2C-BUS
DEVICE
SCL
1/2
standard
2
C-bus
I
special
buffered bus
special
buffered bus
standard
2
C-bus
I
002aad690
Fig 5. Minimum sub-system with P82B715
P82B715_8 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 08 — 9 November 2009 5 of 23
NXP Semiconductors
8.1 I2C-bus systems
As in standard I2C-bus systems, pull-up resistors are required to provide the logic HIGH
levels on the buffered bus. (The standard open-collector configuration is retained.) The
value and number of pull-up resistors used is flexible and depends on the system
requirements and designer preferences.
If P82B715 ICs are to be permanently connected into a system it could be configured with
only one pull-up resistor on the buffered bus and none on the I2C-buses, but the system
design will be simplified, and performance improved, by fitting separate pull-ups on each
section of the bus. When a sub-system using P82B715 may be optionally connected to an
existing I2C-bus system that already has a pull-up, then the effects of the sub-system
pull-ups acting in parallel with the existing I2C-bus pull-up must be considered.
8.1.1 Pull-up resistance calculation
When calculating the pull-up resistance values, the gain of the buffer introduces scaling
factors which must be applied to the system components. In practical systems the pull-up
resistance value is usually calculated to achieve the rise time requirement of the system.
As an approximation, this requirement will be satisfied for a standard 100 kHz system if
the time constant of the total system (product of the net resistance and net capacitance) is
set to 1 microsecond or less.
P82B715
I2C-bus extender
In systems using P82B715s, the most convenient way to achieve the total system
rise time requirement is by considering each bus node separately. Each of the I2C-bus
nodes, and the buffered bus node, is designed by selecting its pull-up resistor to provide
the required rise time by setting its time constant (product of the pull-up resistance and
load capacitance) equal to the I2C-bus rise time requirement. If each node complies, then
the system requirement will also be met with a small safety margin.
This arrangement, using multiple pull-ups as in Figure 6, provides the best system
performance and allows stand-alone operation of individual I2C-buses if parts of the
extended system are disconnected or re-connected. For each bus section the pull-up
resistor for a Standard-mode system is calculated as shown in Equation 1:
R
=
-----------------------------------------------------
C device C wiring+
Where: C device = sum of any connected device capacitances, and C wiring = total wiring
and stray capacitance on the bus section.
Remark: The 1 µs is an approximation, with a safety factor, to the theoretical
time-constant necessary to meet the Standard-mode 1 µs bus rise time specification in a
system with variable logic thresholds where the CMOS limits of 30 % and 70 % of V
apply. The actual RC requirement can be shown to be 1.18 µs. For a Fast-mode system,
and the same safety margin, replace the 1 µs with its 300 ns requirement.
If these capacitances cannot be measured or calculated then an approximation can be
made by assuming that each device presents 10 pF of load capacitance and 10 pF of
trace capacitance and that cables range from 50 pF to 100 pF per meter.
1 µs
(1)
CC
If only a single pull-up must be used then it must be placed on the buffered bus (as R2 in
Figure 6) and the associated total system capacitance calculated by combining the
individual bus capacitances into an equivalent capacitive loading on the buffered bus.
P82B715_8 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 08 — 9 November 2009 6 of 23
NXP Semiconductors
This equivalent capacitance is the sum of the capacitance on the buffered bus plus
10 times the sum of the capacitances on all the connected I2C-bus nodes. The calculated
value should not exceed 4 nF. The single buffered bus pull-up resistor is then calculated to
achievethe rise time requirement and it then provides the pull-up for the buffered bus and
for all other connected I2C-bus nodes included in the calculation.
2
C-bus 1
I
P82B715
I2C-bus extender
V
= 5 V
CC
R3
SDA
I2C-bus 2
SCL
VCC = 5 V
R4
SDA
I2C-bus 3
SCL
SDA
SCL
R1
Sx
Sy
Lx
Ly
R2
buffered bus
Lx
Ly
Lx
Ly
Sx
Sy
Sx
Sy
Fig 6. Single pull-up on buffered bus and multiple pull-up option
8.1.2 Calculating static bus drive currents
Figure 6 shows three P82B715s connected to a common buffered bus. The associated
bus capacitances are omitted for clarity and we assume the pull-up resistors have been
selected to give RC products equal to the bus rise time requirement. An I2C-bus chip
connected at I2C-bus 1 and holding the SDA bus LOW must sink the current flowing in its
local pull-up R1 plus, with assistance from the P82B715, the currents in R2, R3 and R4.
When I2C-bus 1 is LOW, the resistors R3 and R4 act to pull the bus nodes I2C-bus 2 and
I2C-bus 3, and their corresponding Sx pins, to a voltage higher than the voltage at their Lx
pins (which are LOW) so their buffer amplifiers will be inactive.The SDA at Sx of I2C-bus 2
and I2C-bus 3 is pulled LOW by the LOW at Lx via the internal 30 Ω resistor that links Lx
to Sx. So the effective current that must be sunk by the P82B715 bufferon I2C-bus 1, at its
Lx pin, is the sum of the currents in R2, R3 and R4. The Sx current that must be sunk by
an I2C-bus chip at I2C-bus 1, due to the buffer gain action, is1⁄10of the Lx current. So the
effectivepull-up, determining the current to be sunk by an I2C-bus chip at I2C-bus 1, is R1
in parallel with resistors 10 times the values of R2, R3 and R4. If R1 = R3 = R4 = 10 kΩ,
and R2=1kΩ, the effective pull-up load at I2C-bus 1 is
10 kΩ||10 kΩ||100 kΩ||100 kΩ = 4.55 kΩ. (‘||’ means ‘in parallel with’.)
The same calculation applies for I2C-bus 2 or I2C-bus 3.
002aad691
To calculate the current sunk by the Lx pin of the buffer at I2C-bus 1, note that the current
in R1 is sunk directly by the IC at I2C-bus 1. The buffer therefore sinks only the currents
flowing in R2, R3, and R4 so the effective pull-up is R2 in parallel with R3 and R4.
In this example that is 1 kΩ||10 kΩ||10 kΩ = 833 Ω. For a 5.5 V supply and 0.4 V LOW,
that means the buffer is sinking 16.3 mA.
P82B715_8 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 08 — 9 November 2009 7 of 23
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