NXP UM11227, NTM88 User Manual

UM11227

NTM88 family of tire pressure monitor sensors

Rev. 7 — 29 March 2021 User manual

Document information

Information Content

Keywords NTM88, features, architecture, programming model, 8-bit microcontroller

(MCU), pressure sensor, accelerometer, programmable RF transmitter and flexible LF receiver

Abstract This user manual describes the features, architecture, and programming

model of the NTM88 family of devices.

NXP Semiconductors

UM11227

NTM88 family of tire pressure monitor sensors

Revision history

Document ID Release

date

UM11227 v.7 20210329 • Global changes as follows:

UM11227 v.6 20200424 • Section 3, revised second bullet for "Optional accelerometer ranges" and added a footnote.

Description

– Performed minor grammatical, content and tyopgraphic revisions throughout. – Revised "SRS" to "SIMRS" in six locations.

• Inserted new document information table on the first page of the data sheet.

• Section 1, relocated the revision history to the front of the document to comply with NXP

content guidelines for user manuals.

• Section 3, revised as follows: – Revised "Pressure range: 90 kPa to 930 kPa" to "Optional pressure ranges". – Removed "Optional accelerometer range: See Section 4." – Revised "Slave SPI to support..." to "Client SPI to support..."

• Section 4, Table 1, revised the "Type number" from "NTM88Hxx5" to "NTM88Hxxx" and

"NTM88Jxxx".

• Section 4.5, revised "At address $FC00, 1024 bytes..." to "At address $FC00, 512 bytes..."

• Section 5.1 revised as follows: – Step 1: revised the content. – Table 3: revised the part number from "NTM88H05xT1" to "NTM88xxxxT1", the pressure

value from "H" to "y" and updated footnote 3.

• Section 9.1, revised the first paragraph adding a statement to visit the NXP website for

user guides, application notes and evaluation hardware collateral.

• Section 10.19.1.3, Figure 47, revised the title.

• Section 10.19.2.4, revised the note below Table 155.

• Section 11, Figure 60, revised the title.

• Section 5.1, revised as follows: – Table 3, revised tables notes 1, 3, 4, and 5. – Table 4, revised table note 1

• Section 10.1.1, deleted rows for register map addresses $E7E0 through $E7FF.

• Section 10.2.2, deleted the last paragraph starting with "The LF, SMI, and ADU user...."

• Section 10.3, Table 17, revised vector priority 8 removing "reserved" and providing values.

• Section 10.12.1, revised as follows: – Moved the figure titled "KBI block diagram" to Section 10.12.2.1 prior to Table 36. – Moved the figure titled "External interrupt logic" to Section 10.12.2.4 prior to Table 42. – Figure 14, revised image. – Table 23, in the "Pull enable" row, revised the "x" in the "KBI pin enable" column to "0".

• Section 10.12.1.1, revised as follows: – Removed second paragraph starting with "PTA[4:0] pins are shared with on-chip

peripheral functions."

– Removed redundant Figures titled "General purpose I/O block diagram" and "General

purpose I/O logic".

– Removed redundant Table titled "Truth table for pullup and pulldown resistors". – Table 37, revised the "Description" for "KBACK".

• Section 10.12.2.4, Table 43, revised the "Description" for "IRQACK".

• Section 10.14.1.1, Table 63, revised the "Description" for "WUFACK" and "PRFACK".

• Section 10.15.17.5, Table 84, revised the "Description" for "LFIAK".

• Section 10.16.11.8, Table 118, revised the "Description" for "RFIAK".

• Section 10.19.2.1, Table 147, revised the "Description" for "SMIFAK".

• Section 10.19.2.3, Table 151, revised the description for 1:0, FILT[1:0]

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UM11227

NTM88 family of tire pressure monitor sensors

Revision history...continued

Document ID Release

date

UM11227 v.5 20200124 • Section 10.19, revised entire section.

UM11227 v.4 20191004 • Section 3: Revised third bullet under "Transducer measurement interfaces" from "12-bit

UM11227 v.3 20190822 • Section 2, revised the general description paragraph.

Description

UM11227 v.6 (Continued)

• Section 10.23.3.1, Table 175, revised and unmerged the Bit 6 cell for "R" and "W", inserting

"0" in Bit 6 for "R" and revised the "Description" for "RTIACK" in Table 176.

• Section 10.23.3.2, Table 177, revised and unmerged the Bit 6 cell for "R" and "W", inserting

"0" in Bit 6 for "R" and revised the "Description" for "LVDACK" in Table 178.

• Section 10.23.3.3, Table 179, revised and unmerged the Bit 2 cell for "R" and "W", inserting

"0" in Bit 2 for "R" and revised the "Description" for "PPDACK" in Table 180.

• Section 10.25, inserted a new first bullet, revised the second bullet, and inserted a new

bullet before the last bullet.

• Section 10.26, Added new first paragraph.

• Section 10.26.6, revised the first sentence and the figure title for Figure 59.

• Section 11, revised the paragaph starting with "A gel is used to provide media protection...",

adding two new sentences at the end of the paragraph.

compensated..." to "8-bit compensated...."

• Section 4.1: Revised the first bullet adding "For devices programmed by NXP with an

embedded firmware..." and added new paragraph beginning with "Prototype samples...."

• Section 4.4, revised the second paragraph.

• Section 7.3, Figure 4: Revised Figure 4.

• Section 10.1.1, Table 15, revised rows $1860, $1861 and $FD66:$FDFA.

• Section 10.8.5.2, Table 20: Removed "Normal Temperature Restart" row.

• Section 10.8.5.4: Removed section titled "Temperature restart" that followed

Section 10.8.5.4.14.

• Section 10.9.1, Table 21, revised as follows: – Start Address $FC00, revised the "End Address" from "$FD65" to "$FD3F" and updated

the "Block description".

– Start Address $FD40, revised "Start Address "from $FD66" to "$FD40" and updated the

"Block description".

– Start Address $FFC0, revised "End address" from "$FFDB" to "$FFDF" and updated the

"Block description".

– Start Address $FFDC, removed entire row.

• Section 10.16.11.1, Table 104: Added new table.

• Section 10.16.11.3, Table 108: Revised the description for "4:0, PWR[4:0]".

• Section 10.16.11.9, Table 123: Revised the description for "15:3, AFREQ[12:0]".

• Section 10.16.11.11: Revised "RFCR8" to "EPR" in three locations.

• Section 10.16.11.12: Revised "RFCR9" to "RFPRECHARGE" in three locations.

• Section 10.19.2.3, Table 151, added "Recommend adjusting to 500 Hz or higher when

either or both ISD[3:0] / SP[3:0] are configured for times < 1024 ms." to the description for FILT[1:0] for the case of "0 0 = 250 Hz".

• Section 11, Figure 60: revised the image.

• Section 3, revised as follows: – Revised the supporting bulleted items of the bullet "Transducer measurement interfaces

with low-power AFE."

– Revised "16k bytes flash memory" to "16 kB flash memory" below "8-bit S08 compact

instruction set controller."

• Section 4, Table 1: revised the description.

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UM11227

NTM88 family of tire pressure monitor sensors

Revision history...continued

Document ID Release

date

UM11227 v.2 20190516 • The format of this document has been redesigned to comply with the identity guidelines of

NTM88RM v.1 20181214 • Initial release

Description

UM11227 v.3 Modifications (Continued.)

• Section 4.1, replaced table titled "CodeF - tolerance and firmware configuration encoding"

with a paragraph and bullets.

• Section 4.2, replaced table titled "CodeH - hardware configuration encoding" with a

paragraph and bullets.

• Section 4.3: revised as follows: – Table 2, bits 7 through 0, removed table 2 reference for CODEF, removed table 3

reference for CODEH and replaced references with "Consult the appropriate NTM88 product data sheet for a description."

– Revised "ID27 — 0 to identify NTM88 family" to "ID27 — 1 to identify NTM88 family."

• Section 5.1, Table 3: Revised footnote 5.

• Section 6: revised the first paragraph.

• Section 6, Figure 2, revised the figure caption.

• Section 7, added introductory paragraph.

• Section 7.1: Revised the image in Figure 3.

• Section 7.2, Table 5: Revised the symbols for pins 1 through 6 from "NC" to "n.c." to

support changes made to the image in Figure 3.

• Section 10.1.1, Table 15, revised as follows – Address $0008, revised all entries to "reserved." – Address $1809, revised Bit1 to "reserved." – Address $180C, revised Bit3, Bit2, and Bit0 to "reserved." – Address $FDFF, revised Bit7 to "ID31," Bit6 to "ID30," Bit5 to "ID29," and Bit4 to "ID28."

• Removed the section titled "Port input filter enable register (PORTIFE)" that followed

Section 10.12.1.7.

• Section 10.16.9, Figure 38: revised the figure.

• Section 10.16.11.12, revised as follows: – Table 128, revised "Reset ($00)" to "Reset ($40) and the "TIMEOUT0" bit from "0" to "1". – Table 129, revised the description for 7:6.

• Section 10.19, Figure 44: revised the figure.

• Section 10.19.1: revised as follows: – Revised the last sentence before Table 145. – Table 145: Added "Stop4 entry not recommended." to the "Comments" for "Direct"

• Section 10.19.1.2: Revised 5th paragraph, 2nd sentence.

• Section 10.23.3.2, Table 177, removed "BGBDS" from Bit1

• Section 10.23.3.2, Table 178, removed "BGBDS" row from table.

• Section 10.23.3.4, Table 181, removed "HVWF" from Bit3, "HVWACK" from Bit2, and

"HVWE" from Bit 0.

• Section 10.23.3.4, Table 182, removed rows for "HVWF", "HVWACK," and "HVWE."

• Section 11: Added new paragraph before Figure 60.

NXP Semiconductors.

• Legal texts have been adapted to the new company name where appropriate.

• Revised document number from "NTM88RM" to "UM11227".

• UM11227 v.2 supercedes NTM88RM v.1.

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1 Introduction

1.1 Purpose

This user manual describes the features, architecture, and programming model of the NTM88 family of devices.

1.2 Audience

This document is primarily for system architects and software application developers who are using or considering the use of the NTM88 in a system.

2 General description

The NTM88 is a small (4 mm x 4 mm x 1.98 mm), fully integrated tire pressure monitoring sensor (TPMS). It also provides low transmitting power consumption, large customer memory size, and a choice of either dual- or single-axis accelerometer architecture. The NTM88 TPMS solution integrates an 8-bit microcontroller (MCU), pressure sensor, accelerometer, and RF transmitter.

UM11227

NTM88 family of tire pressure monitor sensors

3 Features and benefits

• Optional pressure ranges

• Optional single- or dual-axis accelerometer ranges

• Transducer measurement interfaces with low-power AFE: – 10-bit compensated pressure sense element – 10-bit compensated accelerometers – 8-bit compensated internal device temperature measurement – 8-bit compensated internal device voltage measurement – Two I/O pins can be used for external signals

• 8-bit S08 compact instruction set controller: – 64 bytes low-power “always on“ NVM parameter registers – 512 bytes SRAM – 16 kB flash memory (512 bytes reserved for NXP coefficients) – Family of NXP firmware libraries available via royalty-free license

• Programmable RF transmitter – Characterized for RF carrier typical of 315 MHz or 434 MHz – Characterized for FSK in ~3 kHz increments or OOK modulation – Characterized for baud rate examples of 9.6 kbp/s, 19.2 kbp/s, and 38.4 kbp/s

• Flexible 125 kHz LF receiver: – Capability for ASK or OOK demodulation – Automated Manchester decoding

• Two channel timer / pulse-width module

• Client SPI to support host access to internal peripherals, registers, and memory

• Seven GPIOs with programmable multiplexing to support software development,

external ADC input, timer, SPI, and wake-up

• Qualified in compliance with AEC-Q100, Rev. H

1 Consult NXP sales for details or specific requests.

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• Long battery service life

• Temperature sensor

• Voltage reference measured by ADC10

• Six-channel, 10-bit analog-to-digital converter (ADC10) with two external I/O inputs

• Internal 315-/434-M Hz RF transmitter – External crystal oscillator – PLL-based output with fractional-n divider – OOK and FSK modulation capability – Programmable data rate generator – Manchester, Bi-Phase, or NRZ data encoding – 256-bit RF data buffer variable length interrupt – Direct access to RF transmitter from MCU for unique formats – Low-power consumption

• Differential input LF detector/decoder on independent signal pins

• Real-time Interrupt driven by LFO with intervals of 2, 4, 8, 16, 32, 64, or 128 ms

• Free-running counter, low-power, wake up timer and periodic reset driven by LFO

• Watchdog timeout with selectable times and clock sources

• Two-channel general-purpose timer/PWM module (TPM1)

• Internal oscillators – MCU bus clock of 0.5, 1, 2, and 4 MHz (1, 2, 4, and 8 MHz HFO) – Low frequency, low-power time clock (LFO) with 1 ms period – Medium frequency, controller clock (MFO) of 8 μs period

• Low-voltage detection

UM11227

NTM88 family of tire pressure monitor sensors

4 Configuration options

Table 1. Ordering information

PackageType number

Name Description Version

NTM88Hxxx NTM88Jxxx

HQFN24 Plastic thermal enhanced quad flat package; no leads, 0.1 dimple wettable

flank; 24 terminals; 0.5 mm pitch, 4 mm x 4 mm x 1.98 mm body

4.1 Electronic encoding - "CodeF"

Consult the appropriate NTM88 product data sheet for a description of the CodeF traceability which allows the user to extract:

• For devices programmed by NXP with an embedded firmware, configuration values holding the firmware library used for final test

• Accelerometer variant type

Prototype samples may be configured and delivered with the firmware remaining in the flash memory upon special request. The series production process will erase the firmware from flash memory to facilitate customers choice of the firmware routines, while excluding specific firmware routines the application software does not require. Consult the appropriate NTM88 firmware user guide for a description of the available firmware routines, either as firmware in flash, or as library releases.

SOT1931-1(D)

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UM11227

NTM88 family of tire pressure monitor sensors

4.2 Electronic encoding - "CodeH"

Consult the appropriate NTM88 product data sheet for a description of the CodeH traceability which allows users to extract:

• configuration values holding the assembly revision

• final test pressure

• accelerometer calibrations

4.3 Device identification

The bytes assigned to identify the device and its options are described below. This data can be read using the TPMS_READ_ID routine.

Table 2. Device ID coding summary

ID Address

00 CODEF Consult the appropriate NTM88 product data sheet for a description.

01 CODEH Consult the appropriate NTM88 product data sheet for a description.

02 CODE2 ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0

03 CODE3 ID15 ID14 ID13 ID12 ID11 ID10 ID9 ID8

04 CODE4 ID23 ID22 ID21 ID20 ID19 ID18 ID17 ID16

05 CODE5 ID31 ID30 ID29 ID28 ID27 ID26 ID25 ID24

Name

7 6 5 4 3 2 1 0

BIT

ID13:0 — Device ID within each assembly lot - 16k devices in each lot

ID26:14 — Lower 13 bits of assembly lot ID - 32k lots

ID27 — 1 to identify NTM88 family

ID28:29 — Upper 2 bits of assembly lot ID

ID30 — 0x1 to identify sub-con B, 0x0 to identify sub-con A

ID31 — 0x1 to identify NXP as device supplier

Note: Prior to erasing the flash memory, users are advised to first copy the contents of the CODEF through CODE5 data into a secure and retrievable database when using, for example, a custom gang programmer in lieu of the CodeWarrior IDE tool. The contents of CODEF through CODE5 are unique to each part number, configuration of pressure and accelerometer ranges, and serial numbers, and must be replaced as part of the user flash programming processes.

4.4 Definition of signal ranges

Each measured parameter (pressure, voltage, temperature, acceleration) results from an ADC10 conversion of an analog signal. This ADC10 result may then be passed by the firmware to the application software as either the raw ADC10 result or further compensated and scaled for an output between one and the maximum digital value minus one. The minimum digital value of zero and the maximum digital value are reserved as error codes.

The signal ranges and their significant data points are shown in Figure 1. In this definition, the signal source would normally output a signal between S

User manual Rev. 7 — 29 March 2021

INLO

and S

INHI

. Due

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NXP Semiconductors

SENSOR ANALOG

VOLTAGE

ADC10 RAW

DIGITAL

(10-BIT CONVERSION)

CALCULATED

DIGITAL

(9-BIT EXAMPLE)

SIGNAL

SOURCE

ADC10

FIRMWARE

ROUTINE

511 510

256

1023

512

VDD/2

VDD

SINMAX

SINHI

SINMIN

SINLO

DINMAX

DINHI

DINLO

DINMIN

NORMAL CASE

UNDERFLOW

LOWER ERROR CASE

CASE

OVERFLOW

CASE

FORCE OUTPUT TO 511

FORCE OUTPUT TO ZERO

UPPER ERROR CASE

aaa-028041

to process, temperature, and voltage variations, this signal may increase its range to S

INMIN

the signal is between the supply rails, so that the ADC10 converts it to a range of digital numbers between 0 and 1023. These digital numbers have corresponding D D

INHI

and scaled to give the required output code range.

to S

, D

UM11227

NTM88 family of tire pressure monitor sensors

. In the example case of 10-bit raw conversions and 9-bit compensation,

INMAX

INMIN

values. The ADC10 digital value is taken by the firmware and compensated

INMAX

, D

INLO

Figure 1. Measurement signal range definitions

Digital input values below D

and above D

INMIN

are immediately flagged as being out

INMAX

of range and generate error bits and the output is forced to the 0 value.

and D

) or above D

INMIN

will normally produce an output between 1 to

INHI

(but not D

INHI

INMAX

) will most

Digital values below D likely cause an output that would be less than 1 or greater than 510, respectively. These cases are considered underflow or overflow, respectively. Underflow results will be forced to a value of 1. Overflow results will be forced to a value of 510.

Digital values between D 510 (for a 9-bit result). In some isolated cases due to compensation calculations and rounding, the result may be less than 1 or greater than 510, in which case the underflow

(but above D

INLO

and overflow rule mentioned above is used.

User manual Rev. 7 — 29 March 2021

4.5 Memory resource usage

At address $FC00, 512 bytes are protected from erasure, containing the sensitivity and offset coefficients for the transducers and clocks.

The firmware uses no specific bytes of the RAM but will cause additional stacking of temporary values.

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The firmware uses 2 bytes ($008E and $008F) of the Parameter Registers for global flags for all routines.

5 Marking

5.1 Exterior markings

The marking2 on the NTM88 family contain three lines of text, described as follows:

1. Line 1 identifies the location of pin 1 and, when appropriate, shows the corporate logo

2. Line 2 identifies part marking information, see Table 3 for details on the NTM88

3. Line 3 is the trace code. See Table 4 for trace code definitions.

Table 3. Example Exterior Marking

Part Number Company

NTM88xxxxT1 N 8 y a a x

markings.

[1]

Family

UM11227

NTM88 family of tire pressure monitor sensors

Marking

[2]

Pressure

[3]

Accelerometer

[4]

Mechanical

[5]

[1] Company column: N = qualified. [2] Family column: Always "8". [3] Pressure column: Where "y" is a letter representing the pressure configuration. [4] Accelerometer columns: Where "a a" are two letters representing the accelerometer configuration. [5] Mechanical column: Where "x" is a letter representing the mechanical configuration.

Table 4. Trace code definitions

Trace code Definition

A Assembly site

[1]

L Wafer lot

YW Year and work week

Z Assembly lot split

[1] "X" for site #1; additional letters for other assembly sites as needed. [2] “Z” can be up to two characters "ZZ" when the number of subassembly lots > 26

[2]

2 Subject to change by NXP without notice.

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BDM

CONTROLLER

S08

8b CPU

BUS

ARB.

MUX

A TO D MUX

C TO V MUX

INTERRUPT

CONTROLLER

SPIPADMUX

GPIO

IRQ

BKGD

SPI TPM ADC ETC.

NV RAM

64 x 8

PWR. MODE

CONTROLLER

RESET

CNTL. MOD.

KEYBD

INTERRUPT

LF RX

REG. FILE

FREE

RUN CNTR .

peripheral bus

2chTPM

LF RX

SMI

LPFBUFFER

aaa- 031049

SYSTEM

INT. MOD.

RF TX

REG. FILE

TX PLL

DIGITAL

SUB GHz

DE-

CODE

AZ, RECT.

GAIN, SLICE

TX PA

125 kHz

AFE

P-CELL SENSE

P-CELL

REF.

G-CELL NORTH

G-CELL SOUTH

off- chip 26 MHz

off-c hip LF coil

off-c hip antenna

OSC

RF TX

INT. CLKS

SYS

COP

TIMER

PWU/RTI

TIMER

GAIN, OFFSET

AND COEFF.

GAIN, OFFSET

AMPS

SAR ADC

Offset

DAC

C TO V

CONVERTER

bandgap

temp sensor

ext. A2D V0

ext. A2D V1

SYS RAM

512 x 8

FLASH

CONTROLLER

FLASH N VM

16 k x 8

PTA0 - 4

PTB0 - 1

6 Block diagram

Figure 2 presents the device's main blocks and their signal interactions. Power

management controls and bus control signals are not shown in this block diagram for clarity.

UM11227

NTM88 family of tire pressure monitor sensors

Figure 2. Block diagram

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aaa- 031048

RFOUT

Transparent top view

Pin 1 index area

RFGND

PTA1

PTA2

PTA3

PTB0

n.c. 1

n.c.

n.c. 3

n.c.

n.c. 5

n.c. 6

PTA4 7

RSTB

VDDA 9

GND

VDD 11

VREG 12

7 Pinning information

This section describes the pin layout and general function of each pin.

7.1 Pinout

UM11227

NTM88 family of tire pressure monitor sensors

Figure 3. NTM88 QFN package pinout

7.2 Pin description

Table 5. Pin description

Symbol Pin Function Description

n.c. 1 — Do not connect electrical signals to this pin; solder joint only.

n.c. 2 — Do not connect electrical signals to this pin; solder joint only.

n.c. 3 — Do not connect electrical signals to this pin; solder joint only.

n.c. 4 — Do not connect electrical signals to this pin; solder joint only.

n.c. 5 — Do not connect electrical signals to this pin; solder joint only.

n.c. 6 — Do not connect electrical signals to this pin; solder joint only.

PTA4 7 PTA4 / BKGD PTA4 Pin - The PTA4 pin places the device in the BACKGROUND DEBUG

mode (BDM) to evaluate MCU code and transfer data to/from the internal memory. If the BKGD/PTA4 pin is held low when the device comes out of a power-on-reset (POR), the device switches into the ACTIVE BACKGROUND DEBUG mode (BDM).

The BKGD/PTA4 pin has an internal pullup device or can be connected to

User manual Rev. 7 — 29 March 2021

VDD in the application, unless there is a need to enter BDM operation after the device as been soldered into the PWB. If in-circuit BDM is desired, the BKGD/PTA4 pin should be connected to VDD through a resistor (~10 kΩ or greater) which can be over-driven by an external signal. This resistor reduces the possibility of inadvertently activating the debug mode in the application due to an EMC event.

When the application programs port A to GPIOs, PTA4 becomes output-only.

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Table 5. Pin description...continued

Symbol Pin Function Description

RST_B 8 Reset / V

programming voltage

VDDA 9 Analog supply The analog circuits operate from a single power supply connected to the unit

GND 10 Digital and analog

ground

VDD 11 Digital supply The digital circuits operate from a single power supply connected to the unit

VREG 12 1.8 V regulation The internal regulator for the RF analog circuits requires an external

PTB0 13 PTB0 / TPMCH0 /

AD3

PTA3 14 PTA3 / KBI3 / MOSI The PTA[3] pin is a general-purpose I/O pin. The pulldown devices can only

PTA2 15 PTA2 / KBI2 / MISO The PTA[2] pin is a general-purpose I/O pin. The pulldown devices can only

The RST_B pin is used for test and establishing the BDM condition and providing the programming voltage source to the internal FLASH memory. This pin can also be used to direct to the MCU to the reset vector.

The RST_B pin has an internal pullup device and can be connected to VDD in the application unless there is a need to enter BDM operation after the device as been soldered to the PWB. If in-circuit BDM is desired, the RST_B pin can be left unconnected; but should be connected to VDD through a low impedance resistor (<10 kΩ) which can be over-driven by an external signal. This low impedance resistor reduces the possibility of getting into the debug mode in the application due to an EMC event.

Activation of the external reset function occurs when the voltage on the RST_B pin goes below 0.3 × VDD for at least 100 ns before rising above

0.7 × VDD.

through the VDDA pin. VDDA is the positive supply and GND is the ground. The conductors to the power supply should be connected to the VDDA and GND pins and locally decoupled.

Care should be taken to reduce measurement signal noise by separating the VDD, GND, VDDA, and RFGND pins using a “star” connection such that each metal trace does not share any load currents with other external devices.

The digital circuits operate from a single power supply connected to the unit through the VDD and GND pins. GND is the ground. Care should be taken to reduce measurement signal noise by separating the GND and RFGND pins using a “star” connection such that each metal trace does not share any load currents with other external devices.

through the VDD and GND pins. VDD is the positive supply. The conductors to the power supply should be connected to the VDD and GND pins and locally decoupled.

stabilization capacitor to GND.

The PTB[0] pin is a general-purpose I/O pin. This pin can be configured as a nominal bidirectional I/O pin with programmable pullup devices. User software must configure the general-purpose I/O pin (PTB[1:0]) so that they do not result in “floating” inputs. PTB0 can be mapped to TPM channel 0, or to ADC channel 3.

be activated if the wake-up interrupt capability is enabled. User software must configure the general-purpose I/O pins so that they do not result in “floating” inputs. PTA[3] maps to keyboard interrupt function bit [3]. When SPI is enabled, PTA[3] serves as MOSI.

be activated if the wake-up interrupt capability is enabled. User software must configure the general-purpose I/O pins so that they do not result in “floating” inputs. PTA[2] maps to keyboard interrupt function bit [2]. When SPI is enabled, PTA[2] serves as MISO.

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NTM88 family of tire pressure monitor sensors

Table 5. Pin description...continued

Symbol Pin Function Description

PTA1 16 PTA1 / KBI1 / SCLK The PTA[1] pin is a general-purpose I/O pin. The pulldown devices can only

be activated if the wake-up interrupt capability is enabled. User software must configure the general-purpose I/O pins so that they do not result in “floating” inputs. PTA[1] maps to keyboard interrupt function bit [1]. When SPI is enabled, PTA[1] serves as SCLK

RFGND 17 RF ground Power in the RF output amplifier is returned to the supply through the

RFGND pin. This conductor should be connected to the power supply using a “star” connection such that each metal trace does not share any load currents with other supply pins.

RFOUT 18 RF output The RFOUT pin is the RF energy data supplied by the unit to an external

antenna.

PTA0 19 PTA0 / KBI0 / SS_B /

IRQ

X1 20 RF crystal input The X1 pin is for an external 26 MHz crystal to be used by the internal PLL

X0 21 RF crystal output The X0 pin is for an external 26 MHz crystal to be used by the internal PLL

PTB1 22 PTB1 / TPMCH1 /

AD4

LFB 23 LF input '-' The LF[A:B] pins can be used by the LF receiver (LFR) as one differential

LFA 24 LF input '+' The LF[A:B] pins can be used by the LF receiver (LFR) as one differential

The PTA[0] pin is a general-purpose I/O pin. PTA[0] can be configured as a normal bidirectional I/O pin with programmable pullup or pulldown devices and/or wake-up interrupt capability. PTA[0] can be configured for external interrupt (IRQ). The pulldown devices can only be activated if the wake-up interrupt capability is enabled. User software must configure the generalpurpose I/O pins so that they do not result in “floating” inputs. PTA[0] maps to keyboard interrupt function bit [0]. When SPI is enabled, PTA0 serves as SS_B.

for creating the carrier frequencies and data rates for the RF pin.

The PTB[1] pin is a general-purpose I/O pin. This pin can be configured as a nominal bidirectional I/O pin with programmable pullup devices. User software must configure the general-purpose I/O pins (PTB[1:0]) so that they do not result in “floating” inputs. PTB1 can be mapped to TPM channel 1, or to ADC channel 4.

input channel for sensing low-level signals from an external low frequency (LF) coil. The external LF coil should be connected between the LF[A] and the LF[B] pins.

Signaling into the LFR pins can place the unit into various diagnostic or operational modes. The LFR is comprised of the detector and the decoder. Each LF[A:B] pin always has an impedance of approximately 500 kΩ to GND due to the LFR input circuitry.

The LFA/LFB pins are used by the LFR when the LFEN control bit is set and are not functional when the LFEN control bit is clear.

input channel for sensing low-level signals from an external low frequency (LF) coil. The external LF coil should be connected between the LF[A] and the LF[B] pins.

The LFA/LFB pins are used by the LFR when the LFEN control bit is set and are not functional when the LFEN control bit is clear.

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Gravity

7.3 Orientation

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Figure 4. NTM88 orientation at rest.

8 Central processing unit

8.1 Introduction

This section provides summary information about the registers, addressing modes, and instruction set of the CPU of the HCS08 Family. For a more detailed discussion, refer to the HCS08 Family Reference Manual, volume 1, NXP Semiconductor document order number HCS08RMV1/D.

The HCS08 CPU is fully source- and object-code-compatible with the M68HC08 CPU. Several instructions and enhanced addressing modes were added to improve C compiler efficiency and to support a new BACKGROUND DEBUG system which replaces the monitor mode of earlier M68HC08 microcontrollers (MCU).

8.2 Features

Features of the HCS08 CPU include:

• Object code fully upward compatible with M68HC05 and M68HC08 Families

• All registers and memory are mapped to a single 64 kB address space

• 16-bit stack pointer (any size stack anywhere in 64 kB address space)

• 16-bit index register (H:X) with powerful indexed addressing modes

• 8-bit accumulator (A)

• Many instructions treat X as a second general-purpose 8-bit register

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aaa-028004

accumulator

index register (low)index register (high)

16-bit index register H:X

stack pointer

condition code register

V 1 1 H I N Z C

CCR

Carry Zero

Interrupt mask

Two's complement overflow

Half-carry (from bit 3)

Negative

program counter pointer

• Seven addressing modes: – Inherent — Operands in internal registers – Relative — 8-bit signed offset to branch destination – Immediate — Operand in next object code byte(s) – Direct — Operand in memory at 0x0000–0x00FF – Extended — Operand anywhere in 64 kB address space – Indexed relative to H:X — Five submodes including auto-increment – Indexed relative to SP — Improves C efficiency dramatically

• Memory-to-memory data move instructions with four address mode combinations

• Overflow, half-carry, negative, zero, and carry condition codes support conditional

branching on the results of signed, unsigned, and binary-coded decimal (BCD) operations

• Efficient bit manipulation instructions

• Fast 8-bit by 8-bit multiply and 16-bit by 8-bit divide instructions

• STOP and WAIT instructions to invoke low-power operating modes

8.3 Programmer’s model and CPU registers

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Figure 5 shows the five CPU registers. CPU registers are not part of the memory map.

Figure 5. CPU registers

8.3.1 Accumulator (A)

The A accumulator is a general-purpose 8-bit register. One operand input to the arithmetic logic unit (ALU) is connected to the accumulator and the ALU results are often stored into the A accumulator after arithmetic and logical operations. The accumulator can be loaded from memory using various addressing modes to specify the address

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where the loaded data comes from, or the contents of A can be stored to memory using various addressing modes to specify the address where data from A will be stored.

Reset has no effect on the contents of the A accumulator.

8.3.2 Index register (H:X)

This 16-bit register is actually two separate 8-bit registers (H and X), which often work together as a 16-bit address pointer where H holds the upper byte of an address and X holds the lower byte of the address. All indexed addressing mode instructions use the full 16-bit value in H:X as an index reference pointer; however, for compatibility with the earlier M68HC05 Family, some instructions operate only on the low-order 8-bit half (X).

Many instructions treat X as a second general-purpose 8-bit register that can be used to hold 8-bit data values. X can be cleared, incremented, decremented, complemented, negated, shifted, or rotated. Transfer instructions allow data to be transferred from A or transferred to A where arithmetic and logical operations can then be performed.

For compatibility with the earlier M68HC05 Family, H is forced to 0x00 during reset. Reset has no effect on the contents of X.

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8.3.3 Stack pointer (SP)

This 16-bit address pointer register points at the next available location on the automatic last-in-first-out (LIFO) stack. The stack may be located anywhere in the 64 kB address space that has RAM and can be any size up to the amount of available RAM. The stack is used to automatically save the return address for subroutine calls, the return address and CPU registers during interrupts, and for local variables. The AIS (add immediate to stack pointer) instruction adds an 8-bit signed immediate value to SP. This is most often used to allocate or deallocate space for local variables on the stack.

SP is forced to 0x00FF at reset for compatibility with the earlier M68HC05 Family. HCS08 programs normally change the value in SP to the address of the last location (highest address) in on-chip RAM during reset initialization to free up direct page RAM (from the end of the on-chip registers to 0x00FF).

The RSP (reset stack pointer) instruction was included for compatibility with the M68HC05 Family and is seldom used in new HCS08 programs because it only affects the low-order half of the stack pointer.

8.3.4 Program counter (PC)

The program counter is a 16-bit register that contains the address of the next instruction or operand to be fetched.

During normal program execution, the program counter automatically increments to the next sequential memory location every time an instruction or operand is fetched. Jump, branch, interrupt, and return operations load the program counter with an address other than that of the next sequential location. This is called a change-of-flow.

During reset, the program counter is loaded with the reset vector that is located at 0xFFFE and 0xFFFF. The vector stored there is the address of the first instruction that will be executed after exiting the reset state.

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condition code register

V 1 1 H I N Z C

CCR

Carry Zero

Interrupt mask

Two's complement overflow

Half-carry (from bit 3)

Negative

8.3.5 Condition code register (CCR)

The 8-bit condition code register contains the interrupt mask (I) and five flags that indicate the results of the instruction just executed. Bits 6 and 5 are set permanently to

1. The following paragraphs describe the functions of the condition code bits in general

terms. For a more detailed explanation of how each instruction sets the CCR bits, refer to the HCS08 Family Reference Manual, volume 1, NXP Semiconductors document order number HCS08RMv1.

Figure 6. Condition code register

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Table 6. CCR register field descriptions

Field Description

Two’s Complement Overflow Flag — The CPU sets the overflow flag when a two’s

7 V

complement overflow occurs. The signed branch instructions BGT, BGE, BLE, and BLT use the overflow flag.

0 No overflow 1 Overflow

Half-Carry Flag — The CPU sets the half-carry flag when a carry occurs between accumulator bits 3 and 4 during an add-without-carry (ADD) or add-with-carry (ADC) operation. The half-carry flag is required for binary-coded decimal (BCD)

arithmetic operations. The DAA instruction uses the states of the H and C condition code bits to automatically add a correction value to the result from a previous ADD or ADC on BCD operands to correct the result to a valid BCD value.

0 No carry between bits 3 and 4 1 Carry between bits 3 and 4

Interrupt Mask Bit — When the interrupt mask is set, all maskable CPU interrupts are disabled. CPU interrupts are enabled when the interrupt mask is cleared. When a CPU interrupt occurs, the interrupt mask is set automatically after the CPU registers are saved on the stack, but before the first instruction of the interrupt

service routine is executed. Interrupts are not recognized at the instruction boundary after any instruction that

clears I (CLI or TAP). This ensures that the next instruction after a CLI or TAP will always be executed without the possibility of an intervening interrupt, provided I was set.

0 Interrupts enabled 1 Interrupts disabled

Negative Flag — The CPU sets the negative flag when an arithmetic operation, logic operation, or data manipulation produces a negative result, setting bit 7 of the

result. Simply loading or storing an 8-bit, or 16-bit value causes N to be set if the most significant bit of the loaded or stored value was 1.

0 Non-negative result 1 Negative result

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Table 6. CCR register field descriptions...continued

8.4 Addressing modes

Addressing modes define the way the CPU accesses operands and data. In the HCS08, all memory, status and control registers, and input/output (I/O) ports share a single 64 kB linear address space so a 16-bit binary address can uniquely identify any memory location. This arrangement means that the same instructions that access variables in RAM can also be used to access I/O and control registers or nonvolatile program space.

Field Description

Zero Flag — The CPU sets the zero flag when an arithmetic operation, logic

operation, or data manipulation produces a result of 0x00 or 0x0000. Simply 1 Z

loading or storing an 8-bit, or 16-bit value causes Z to be set if the loaded or stored

value was all 0s.

0 Non-zero result

1 Zero result

Carry/Borrow Flag — The CPU sets the carry/borrow flag when an addition

operation produces a carry out of bit 7 of the accumulator or when a subtraction

operation requires a borrow. Some instructions — such as bit test and branch,

shift, and rotate — also clear or set the carry/borrow flag.

0 No carry out of bit 7

1 Carry out of bit 7

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Some instructions use more than one addressing mode. For instance, move instructions use one addressing mode to specify the source operand and a second addressing mode to specify the destination address. Instructions such as BRCLR, BRSET, CBEQ, and DBNZ use one addressing mode to specify the location of an operand for a test and then use relative addressing mode to specify the branch destination address when the tested condition is true. For BRCLR, BRSET, CBEQ, and DBNZ, the addressing mode listed in the instruction set tables is the addressing mode needed to access the operand to be tested, and relative addressing mode is implied for the branch destination.

8.4.1 Inherent addressing mode (INH)

In this addressing mode, operands needed to complete the instruction (if any) are located within CPU registers so the CPU does not need to access memory to get any operands.

8.4.2 Relative addressing mode (REL)

Relative addressing mode is used to specify the destination location for branch instructions. A signed 8-bit offset value is located in the memory location immediately following the opcode. During execution, if the branch condition is true, the signed offset is sign-extended to a 16-bit value and is added to the current contents of the program counter, which causes program execution to continue at the branch destination address.

8.4.3 Immediate addressing mode (IMM)

In immediate addressing mode, the operand needed to complete the instruction is included in the object code immediately following the instruction opcode in memory. In the case of a 16-bit immediate operand, the high-order byte is located in the next memory location after the opcode, and the low-order byte is located in the next memory location after that.

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8.4.4 Direct addressing mode (DIR)

In direct addressing mode, the instruction includes the low-order 8 bits of an address in the direct page (0x0000–0x00FF). During execution, a 16-bit address is formed by concatenating an implied 0x00 for the high-order half of the address and the direct address from the instruction to get the 16-bit address where the desired operand is located. DIR is faster and more memory efficient than specifying a complete 16-bit address for the operand.

8.4.5 Extended addressing mode (EXT)

In extended addressing mode, the full 16-bit address of the operand is located in the next 2 bytes of program memory after the opcode (high byte first).

8.4.6 Indexed addressing mode

Indexed addressing mode has seven variations including five that use the 16-bit H:X index register pair and two that use the stack pointer as the base reference.

8.4.6.1 Indexed, no offset (IX)

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This variation of indexed addressing uses the 16-bit value in the H:X index register pair as the address of the operand needed to complete the instruction.

8.4.6.2 Indexed, no offset with post increment (IX+)

This variation of indexed addressing uses the 16-bit value in the H:X index register pair as the address of the operand needed to complete the instruction. The index register pair is then incremented (H:X = H:X + 0x0001) after the operand has been fetched. This addressing mode is only used for MOV and CBEQ instructions.

8.4.6.3 Indexed, 8-bit offset (IX1)

8.4.6.4 Indexed, 8-bit offset with post increment (IX1+)

This variation of indexed addressing uses the 16-bit value in the H:X index register pair plus an unsigned 8-bit offset included in the instruction as the address of the operand needed to complete the instruction. The index register pair is then incremented (H:X = H:X + 0x0001) after the operand has been fetched. This addressing mode is used only for the CBEQ instruction.

8.4.6.5 Indexed, 16-bit offset (IX2)

This variation of indexed addressing uses the 16-bit value in the H:X index register pair plus a 16-bit offset included in the instruction as the address of the operand needed to complete the instruction.

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8.4.6.6 SP-Relative, 8-bit offset (SP1)

This variation of indexed addressing uses the 16-bit value in the stack pointer (SP) plus an unsigned 8-bit offset included in the instruction as the address of the operand needed to complete the instruction.

8.4.6.7 SP-Relative, 16-bit offset (SP2)

This variation of indexed addressing uses the 16-bit value in the stack pointer (SP) plus a 16-bit offset included in the instruction as the address of the operand needed to complete the instruction.

8.5 Special operations

The CPU performs a few special operations that are similar to instructions but do not have opcodes like other CPU instructions. In addition, a few instructions such as STOP and WAIT directly affect other MCU circuitry. This section provides additional information about these operations.

8.5.1 Reset sequence

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Reset can be caused by a power-on-reset (POR) event, internal conditions such as the COP (computer operating properly) watchdog, or by assertion of an external active-low reset pin. When a reset event occurs, the CPU immediately stops whatever it is doing (the MCU does not wait for an instruction boundary before responding to a reset event). For a more detailed discussion about how the MCU recognizes resets and determines the source, see Section 10.11 "Reset, interrupts and system configuration".

The reset event is considered concluded when the sequence to determine whether the reset came from an internal source is done and when the reset pin is no longer asserted. At the conclusion of a reset event, the CPU performs a 6-cycle sequence to fetch the reset vector from 0xFFFE and 0xFFFF and to fill the instruction queue in preparation for execution of the first program instruction.

8.5.2 Interrupt sequence

When an interrupt is requested, the CPU completes the current instruction before responding to the interrupt. At this point, the program counter is pointing at the start of the next instruction, which is where the CPU should return after servicing the interrupt. The CPU responds to an interrupt by performing the same sequence of operations as for a software interrupt (SWI) instruction, except the address used for the vector fetch is determined by the highest priority interrupt that is pending when the interrupt sequence started.

The CPU sequence for an interrupt is:

1. Store the contents of PCL, PCH, X, A, and CCR on the stack, in that order.

2. Set the I bit in the CCR.

3. Fetch the high-order half of the interrupt vector.

4. Fetch the low-order half of the interrupt vector.

5. Delay for one free bus cycle.

6. Fetch 3 bytes of program information, starting at the address indicated by the interrupt vector, to fill the instruction queue in preparation for execution of the first instruction in the interrupt service routine.

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After the CCR contents are pushed onto the stack, the I bit in the CCR is set to prevent other interrupts while in the interrupt service routine. Although it is possible to clear the I bit with an instruction in the interrupt service routine, this would allow nesting of interrupts (which is not recommended because it leads to programs that are difficult to debug and maintain).

For compatibility with the earlier M68HC05 MCUs, the high-order half of the H:X index register pair (H) is not saved on the stack as part of the interrupt sequence. The user must use a PSHH instruction at the beginning of the service routine to save H and then use a PULH instruction just before the RTI that ends the interrupt service routine. It is not necessary to save H if you are certain that the interrupt service routine does not use any instructions or auto-increment addressing modes that might change the value of H.

The software interrupt (SWI) instruction is like a hardware interrupt except that it is not masked by the global I bit in the CCR and it is associated with an instruction opcode within the program so it is not asynchronous to program execution.

8.5.3 WAIT mode operation

The WAIT instruction enables interrupts by clearing the I bit in the CCR. It then halts the clocks to the CPU to reduce overall power consumption while the CPU is waiting for the interrupt or reset event that will wake the CPU from WAIT mode. When an interrupt or reset event occurs, the CPU clocks resume and the interrupt or reset event are processed normally.

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If a serial BACKGROUND command is issued to the MCU through the BACKGROUND DEBUG interface while the CPU is in WAIT mode, CPU clocks resume and the CPU enters ACTIVE BACKGROUND mode where other serial BACKGROUND commands can be processed. This ensures that a host development system can still gain access to a target MCU even if it is in WAIT mode.

8.5.4 STOP mode operation

Usually, all system clocks, including the crystal oscillator (when used), are halted during STOP mode to minimize power consumption. In such systems, external circuitry is needed to control the time spent in STOP mode and to issue a signal to wake up the target MCU when it is time to resume processing. Unlike the earlier M68HC05 and M68HC08 MCUs, the HCS08 can be configured to keep a minimum set of clocks running in STOP mode. This optionally allows an internal periodic signal to wake the target MCU from STOP mode.

When a host debug system is connected to the BACKGROUND DEBUG pin (BKGD) and the ENBDM control bit has been set by a serial command through the BACKGROUND interface (or because the MCU was reset into ACTIVE BACKGROUND mode), the oscillator is forced to remain active when the MCU enters STOP mode. In this case, if a serial BACKGROUND command is issued to the MCU through the BACKGROUND DEBUG interface while the CPU is in STOP mode, CPU clocks resume and the CPU enters ACTIVE BACKGROUND mode where other serial BACKGROUND commands can be processed. This ensures that a host development system can still gain access to a target MCU even if it is in STOP mode.

Recovery from STOP mode depends on the particular HCS08 and whether the oscillator was stopped in STOP mode. See Section 10.8 "Modes of operation" for more details.

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8.5.5 BGND instruction

The BGND instruction is new to the HCS08 compared to the M68HC08. BGND would not be used in normal user programs because it forces the CPU to stop processing user instructions and enter the ACTIVE BACKGROUND mode. The only way to resume execution of the user program is through reset or by a host debug system issuing a GO, TRACE1, or TAGGO serial command through the BACKGROUND DEBUG interface.

Software-based breakpoints can be set by replacing an opcode at the desired breakpoint address with the BGND opcode. When the program reaches this breakpoint address, the CPU is forced to ACTIVE BACKGROUND mode rather than continuing the user program.

8.6 HCS08 instruction set summary

8.6.1 Instruction set summary nomenclature

The nomenclature listed here is used in the instruction descriptions in Table 7.

8.6.2 Operators

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( ) = Contents of register or memory location shown inside parentheses

← = Is loaded with (read: "gets")

& = Boolean AND

| = Boolean OR

= Boolean exclusive-OR

⊕

× = Multiply

÷ = Divide

: = Concatenate

+ = Add

– = Negate (two’s complement)

8.6.3 CPU registers

A = Accumulator

CCR = Condition code register

H = Index register, higher order (most significant) 8 bits

X = Index register, lower order (least significant) 8 bits

PC = Program counter

PCH = Program counter, higher order (most significant) 8 bits

PCL = Program counter, lower order (least significant) 8 bits

SP = Stack pointer

8.6.4 Memory and addressing

M = A memory location or absolute data, depending on addressing mode

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M:M + 0x0001 = A 16-bit value in two consecutive memory locations. The higher order (most significant) 8 bits are located at the address of M, and the lower order (least significant) 8 bits are located at the next higher sequential address.

8.6.5 Condition code register (CCR) bits

V = Two’s complement overflow indicator, bit 7

H = Half carry, bit 4

I = Interrupt mask, bit 3

N = Negative indicator, bit 2

Z = Zero indicator, bit 1

C = Carry/borrow, bit 0 (carry out of bit 7)

8.6.6 CCR activity notation

– = Bit not affected

0 = Bit forced to 0

1 = Bit forced to 1

Þ = Bit set or cleared according to results of operation

U = Undefined after the operation

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8.6.7 Machine coding notation

dd = Low-order 8 bits of a direct address 0x0000–0x00FF (high byte assumed to be 0x00)

ee = Upper 8 bits of 16-bit offset

ff = Lower 8 bits of 16-bit offset or 8-bit offset

ii = One byte of immediate data

jj = High-order byte of a 16-bit immediate data value

kk = Low-order byte of a 16-bit immediate data value

hh = High-order byte of 16-bit extended address

ll = Low-order byte of 16-bit extended address

rr = Relative offset

8.6.8 Source form

Everything in the source forms columns, except expressions in italic characters, is literal information that must appear in the assembly source file exactly as shown. The initial 3- to 5-letter mnemonic is always a literal expression. All commas, pound signs (#), parentheses, and plus signs (+) are literal characters.

n — Any label or expression that evaluates to a single integer in the range 0–7

opr8i — Any label or expression that evaluates to an 8-bit immediate value

opr16i — Any label or expression that evaluates to a 16-bit immediate value

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opr8a — Any label or expression that evaluates to an 8-bit value. The instruction treats this 8-bit value as the low order 8 bits of an address in the direct page of the 64 kB address space (0x00xx).

opr16a — Any label or expression that evaluates to a 16-bit value. The instruction treats this value as an address in the 64 kB address space.

oprx8 — Any label or expression that evaluates to an unsigned 8-bit value, used for indexed addressing

oprx16 — Any label or expression that evaluates to a 16-bit value. Because the HCS08 has a 16-bit address bus, this can be either a signed or an unsigned value.

rel — Any label or expression that refers to an address that is within –128 to +127 locations from the next address after the last byte of object code for the current instruction. The assembler calculates the 8-bit signed offset and include it in the object code for this instruction.

8.6.9 Address modes

INH = Inherent (no operands)

IMM = 8-bit or 16-bit immediate

DIR = 8-bit direct

EXT = 16-bit extended

IX = 16-bit indexed no offset

IX+ = 16-bit indexed no offset, post increment (CBEQ and MOV only)

IX1 = 16-bit indexed with 8-bit offset from H:X

IX1+ = 16-bit indexed with 8-bit offset, post increment (CBEQ only)

IX2 = 16-bit indexed with 16-bit offset from H:X

rel = 8-bit relative offset

SP1 = Stack pointer with 8-bit offset

SP2 = Stack pointer with 16-bit offset

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Table 7. HCS08 instruction set summary

Effect

Source Form Operation Description

ADC #opr8i ADC opr8a ADC opr16a ADC oprx16,X ADC oprx8,X ADC,X ADC oprx16,SP ADC oprx8,SP

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Add with Carry A ← (A) + (M) + (C) Þ Þ – Þ Þ Þ

on CCR

V H I N Z C

Address

Mode

IMM DIR EXT IX2 IX1 IX SP2 SP1

Opcode Operand

hh ll

ee ff

9ED9

ee ff

9EE9

Bus

Cycles

[1]

2 3 4 4 3 3 5 4

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Table 7. HCS08 instruction set summary...continued

Effect

Source Form Operation Description

on CCR

V H I N Z C

ADD #opr8i ADD opr8a ADD opr16a ADD oprx16,X ADD oprx8,X

Add without Carry A ← (A) + (M) Þ Þ – Þ Þ Þ

ADD ,X ADD oprx16,SP ADD oprx8,SP

SP ← (SP) + (M) M is sign extended to a

16-bit value

H:X ← (H:X) + (M) M is sign extended to a

16-bit value

– – – – – – IMM A7 ii

– – – – – – IMM AF ii

AIS #opr8i

AIX #opr8i

Add Immediate Value (Signed) to Stack Pointer

Add Immediate Value (Signed) to Index Register (H:X)

AND #opr8i AND opr8a AND opr16a AND oprx16,X AND oprx8,X

Logical AND A ← (A) & (M) 0 – – Þ Þ –

AND ,X AND oprx16,SP AND oprx8,SP

ASL opr8a ASLA ASLX ASL oprx8,X ASL ,X ASL oprx8,SP

ASR opr8a ASRA ASRX ASR oprx8,X ASR ,X ASR oprx8,SP

BCC rel

BCLR n,opr8a

BCS rel

Arithmetic Shift Left (Same as LSL)

Arithmetic Shift Right

Branch if Carry Bit Clear

Clear Bit n in Memory

Branch if Carry Bit Set (Same as BLO)

Þ – – Þ Þ Þ

Branch if (C) = 0 – – – – – – rel

Mn ← 0 – – – – – –

Branch if (C) = 1 – – – – – – rel

BEQ rel Branch if Equal Branch if (Z) = 1 – – – – – – rel 27 rr 3

Address

Mode

IMM DIR EXT IX2 IX1 IX SP2 SP1

DIR INH INH IX1 IX SP1

DIR (b0) DIR (b1) DIR (b2) DIR (b3) DIR (b4) DIR (b5) DIR (b6) DIR (b7)

Opcode Operand

hh ll

ee ff

9EDB

ee ff

9EEB

hh ll

ee ff

9ED4

ee ff

9EE4

dd 48 58 68

ff 78

9E68

dd 47 57 67

ff 77

9E67

24 rr 3

dd 13

dd 15

dd 17

dd 19

25 rr 3

Cycles

Bus

[1]

2 3 4 4 3 3 5 4

5 1 1 5 4 6

5 5 5 5 5 5 5 5

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Table 7. HCS08 instruction set summary...continued

Effect

Source Form Operation Description

BGE rel

BGND

BGT rel

BHCC rel

BHCS rel

BHI rel Branch if Higher Branch if (C) | (Z) = 0 – – – – – – rel 22 rr 3

BHS rel

BIH rel

BIL rel

BIT #opr8i BIT opr8a BIT opr16a BIT oprx16,X BIT oprx8,X BIT ,X BIT oprx16,SP BIT oprx8,SP

BLE rel

BLO rel

BLS rel

BLT rel

BMC rel

BMI rel Branch if Minus Branch if (N) = 1 – – – – – – rel 2B rr 3

BMS rel

BNE rel Branch if Not Equal Branch if (Z) = 0 – – – – – – rel 26 rr 3

BPL rel Branch if Plus Branch if (N) = 0 – – – – – – rel 2A rr 3

BRA rel Branch Always No Test – – – – – – rel 20 rr 3

Branch if Greater Than or Equal To (Signed Operands)

Enter ACTIVE BACK-GROUND if ENBDM = 1

Branch if Greater Than (Signed Operands)

Branch if Half Carry Bit Clear

Branch if Half Carry Bit Set

Branch if Higher or Same (Same as BCC)

Branch if IRQ Pin High

Branch if IRQ Pin Low

Bit Test

Branch if Less Than or Equal To (Signed Operands)

Branch if Lower (Same as BCS)

Branch if Lower or Same

Branch if Less Than (Signed Operands)

Branch if Interrupt Mask Clear

Branch if Interrupt Mask Set

Branch if (N ⊕ V) = 0

Waits For and Processes BDM Commands Until GO, TRACE1, or TAGGO

Branch if (Z) | (N ⊕ V) = 0

Branch if (H) = 0 – – – – – – rel

Branch if (H) = 1 – – – – – – rel

Branch if (C) = 0 – – – – – – rel

Branch if IRQ pin = 1 – – – – – – rel

Branch if IRQ pin = 0 – – – – – – rel

(A) & (M) (CCR Updated but

Operands Not Changed)

Branch if (Z) | (N ⊕ V) = 1

Branch if (C) = 1 – – – – – – rel

Branch if (C) | (Z) = 1 – – – – – – rel

Branch if (N ⊕ V ) = 1

Branch if (I) = 0 – – – – – – rel

Branch if (I) = 1 – – – – – – rel

on CCR

V H I N Z C

– – – – – – rel

– – – – – – INH

– – – – – – rel

0 – – Þ Þ –

– – – – – – rel

Address

Mode

IMM DIR EXT IX2 IX1 IX SP2 SP1

Opcode Operand

90 rr 3

82 5+

92 rr 3

28 rr 3

29 rr 3

24 rr 3

2F rr 3

2E rr 3

hh ll

ee ff

9ED5

ee ff

9EE5

93 rr 3

25 rr 3

23 rr 3

91 rr 3

2C rr 3

2D rr 3

Cycles

Bus

[1]

2 3 4 4 3 3 5 4

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UM11227

NTM88 family of tire pressure monitor sensors

Table 7. HCS08 instruction set summary...continued

Effect

Source Form Operation Description

BRCLR n,opr8a,rel

BRN rel Branch Never Uses 3 Bus Cycles – – – – – – rel 21 rr 3

BRSET n,opr8a,rel

BSET n,opr8a Set Bit n in Memory Mn ← 1 – – – – – –

BSR rel

CBEQ opr8a,rel CBEQA #opr8i,rel CBEQX #opr8i,rel CBEQ oprx8,X+,rel CBEQ ,X+,rel CBEQ oprx8,SP,rel

CLC Clear Carry Bit C ← 0 – – – – – 0 INH 98 1

CLI

CLR opr8a CLRA CLRX CLRH CLR oprx8,X CLR ,X CLR oprx8,SP

Branch if Bit n in Memory Clear

Branch if Bit n in Memory Set

Branch to Subroutine

Compare and Branch if Equal

Clear Interrupt Mask Bit

Clear

Branch if (Mn) = 0 – – – – – Þ

Branch if (Mn) = 1 – – – – – Þ

PC ← (PC) + 0x0002 push (PCL); SP ←

(SP) – 0x0001 push (PCH); SP ←

(SP) – 0x0001 PC ← (PC) + rel

Branch if (A) = (M) Branch if (A) = (M) Branch if (X) = (M) Branch if (A) = (M) Branch if (A) = (M) Branch if (A) = (M)

I ← 0 – – 0 – – – INH

M ← 0x00 A ← 0x00 X ← 0x00 H ← 0x00 M ← 0x00 M ← 0x00 M ← 0x00

on CCR

V H I N Z C

– – – – – – rel

– – – – – –

0 – – 0 1 –

Address

Mode

DIR (b0) DIR (b1) DIR (b2) DIR (b3) DIR (b4) DIR (b5) DIR (b6) DIR (b7)

DIR IMM IMM IX1+ IX+ SP1

DIR INH INH INH IX1 IX SP1

Opcode Operand

dd rr 03

dd rr 05

dd rr 07

dd rr 09

dd rr

dd rr 02

dd rr 04

dd rr 06

dd rr 08

dd rr

dd 12

dd 14

dd 16

dd 18

AD rr 5

dd rr 41

ii rr 51

ii rr 61

ff rr 71

rr ff

9E61

9A 1

4F 5F

9E6F

Cycles

Bus

[1]

5 5 5 5 5 5 5 5

5 4 4 5 5 6

5 1 1 1 5 4 6

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NXP Semiconductors

Table 7. HCS08 instruction set summary...continued

Source Form Operation Description

CMP #opr8i CMP opr8a CMP opr16a CMP oprx16,X CMP oprx8,X CMP ,X CMP oprx16,SP CMP oprx8,SP

COM opr8a COMA COMX COM oprx8,X COM ,X COM oprx8,SP

CPHX opr16a CPHX #opr16i CPHX opr8a CPHX oprx8,SP

CPX #opr8i CPX opr8a CPX opr16a CPX oprx16,X CPX oprx8,X CPX ,X CPX oprx16,SP CPX oprx8,SP

DAA

DBNZ opr8a,rel DBNZA rel DBNZX rel DBNZ oprx8,X,rel DBNZ ,X,rel DBNZ oprx8,SP,rel

DEC opr8a DECA DECX DEC oprx8,X DEC ,X DEC oprx8,SP

DIV Divide

Compare Accumulator with Memory

Complement (One’s Complement)

Compare Index Register (H:X) with Memory

Compare X (Index Register Low) with Memory

Decimal Adjust Accumulator After ADD or ADC of BCD Values

Decrement and Branch if

Not Zero

Decrement

(A) – (M) (CCR Updated

But Operands Not Changed)

M ← (M)= 0xFF – (M) A ← (A) = 0xFF – (A) X ← (X) = 0xFF – (X) M ← (M) = 0xFF – (M) M ← (M) = 0xFF – (M) M ← (M) = 0xFF – (M)

(H:X) – (M:M + 0x0001)

(CCR Updated But Operands Not Changed)

(X) – (M) (CCR Updated

But Operands Not Changed)

(A)

Decrement A, X, or M Branch if (result) ≠ 0 DBNZX Affects X Not

M ← (M) – 0x01 A ← (A) – 0x01 X ← (X) – 0x01 M ← (M) – 0x01 M ← (M) – 0x01 M ← (M) – 0x01

A ← (H:A) ÷ (X) H ← Remainder

UM11227

NTM88 family of tire pressure monitor sensors

Effect

on CCR

V H I N Z C

Þ – – Þ Þ Þ

0 – – Þ Þ 1

Þ – – Þ Þ Þ

U – – Þ Þ Þ INH

– – – – – –

Þ – – Þ Þ –

– – – – Þ Þ INH

Address

Mode

IMM DIR EXT IX2 IX1 IX SP2 SP1

DIR INH INH IX1 IX SP1

EXT IMM DIR SP1

IMM DIR EXT IX2 IX1 IX SP2 SP1

DIR INH INH IX1 IX SP1

Opcode Operand

hh ll

ee ff

9ED1

ee ff

9EE1

dd 43 53 63

ff 73

9E63

hh ll 65

jj kk 75

9EF3

hh ll

ee ff

9ED3

ee ff

9EE3

72 1

dd rr

ff rr

9E6B

ff rr

4A 5A 6A

9E6A

52 6

Bus

Cycles

[1]

2 3 4 4 3 3 5 4

5 1 1 5 4 6

6 3 5 6

2 3 4 4 3 3 5 4

7 4 4 7 6 8

5 1 1 5 4 6

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NXP Semiconductors

Table 7. HCS08 instruction set summary...continued

Source Form Operation Description

EOR #opr8i EOR opr8a EOR opr16a EOR oprx16,X EOR oprx8,X EOR ,X EOR oprx16,SP EOR oprx8,SP

INC opr8a INCA INCX INC oprx8,X INC ,X INC oprx8,SP

JMP opr8a JMP opr16a JMP oprx16,X JMP oprx8,X JMP ,X

JSR opr8a JSR opr16a JSR oprx16,X JSR oprx8,X JSR ,X

LDA #opr8i LDA opr8a LDA opr16a LDA oprx16,X LDA oprx8,X LDA ,X LDA oprx16,SP LDA oprx8,SP

LDHX #opr16i LDHX opr8a LDHX opr16a LDHX ,X LDHX oprx16,X LDHX oprx8,X LDHX oprx8,SP

LDX #opr8i LDX opr8a LDX opr16a LDX oprx16,X LDX oprx8,X LDX ,X LDX oprx16,SP LDX oprx8,SP

Exclusive OR Memory with Accumulator

Increment

Jump PC ← Jump Address – – – – – –

Jump to Subroutine

Load Accumulator from Memory

Load Index Register (H:X) from Memory

Load X (Index Register Low) from Memory

A ← (A ⊕ M)

M ← (M) + 0x01 A ← (A) + 0x01 X ← (X) + 0x01 M ← (M) + 0x01 M ← (M) + 0x01 M ← (M) + 0x01

PC ← (PC) + n (n = 1, 2, or 3)

Push (PCL); SP ← (SP) – 0x0001

Push (PCH); SP ← (SP) – 0x0001

PC ← Unconditional Address

A ← (M) 0 – – Þ Þ –

H:X ← (M:M + 0x0001) 0 – – Þ Þ –

X ← (M) 0 – – Þ Þ –

UM11227

NTM88 family of tire pressure monitor sensors

Effect

on CCR

V H I N Z C

0 – – Þ Þ –

Þ – – Þ Þ –

– – – – – –

Address

Mode

IMM DIR EXT IX2 IX1 IX SP2 SP1

DIR INH INH IX1 IX SP1

DIR EXT IX2 IX1 IX

IMM DIR EXT IX2 IX1 IX SP2 SP1

IMM DIR EXT IX IX2 IX1 SP1

IMM DIR EXT IX2 IX1 IX SP2 SP1

Opcode Operand

hh ll

ee ff

9ED8

ee ff

9EE8

4C 5C 6C

9E6C

hh ll

ee ff

hh ll

ee ff

hh ll

ee ff

9ED6

ee ff

9EE6

jj kk 55

dd 32

hh ll

9EAE 9EBE

ee ff

9ECE

9EFE

hh ll

ee ff

9EDE

ee ff

9EEE

Bus

Cycles

[1]

2 3 4 4 3 3 5 4

5 1 1 5 4 6

3 4 4 3 3

5 6 6 5 5

2 3 4 4 3 3 5 4

3 4 5 5 6 5 5

2 3 4 4 3 3 5 4

User manual Rev. 7 — 29 March 2021

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NXP Semiconductors

aaa-028008

aaa-028009

UM11227

NTM88 family of tire pressure monitor sensors

Table 7. HCS08 instruction set summary...continued

Effect

Source Form Operation Description

on CCR

V H I N Z C

LSL opr8a LSLA LSLX LSL oprx8,X LSL ,X LSL oprx8,SP

LSR opr8a LSRA LSRX LSR oprx8,X LSR ,X LSR oprx8,SP

MOV opr8a,opr8a MOV opr8a,X+ MOV #opr8i,opr8a MOV ,X+,opr8a

Logical Shift Left (Same as ASL)

Logical Shift Right

Move

(M) (M)

destination

source

←

H:X ← (H:X) + 0x0001 in

IX+/DIR and DIR/IX+

Þ – – Þ Þ Þ

Þ – – 0 Þ Þ

0 – – Þ Þ –

Modes

MUL Unsigned multiply X:A ← (X) × (A) – 0 – – – 0 INH 42 5

M ← – (M) = 0x00 – (M)

NEG opr8a NEGA NEGX NEG oprx8,X NEG ,X NEG oprx8,SP

Negate (Two’s

Complement)

A ← – (A) = 0x00 – (A) X ← – (X) = 0x00 – (X) M ← – (M) = 0x00 –

(M) M ← – (M) = 0x00 –

(M)

Þ – – Þ Þ Þ

M ← – (M) = 0x00 – (M)

NOP No Operation Uses 1 Bus Cycle – – – – – – INH 9D 1

NSA

Nibble Swap Accumulator

A ← (A[3:0]:A[7:4]) – – – – – – INH

ORA #opr8i ORA opr8a ORA opr16a ORA oprx16,X ORA oprx8,X ORA ,X

Inclusive OR Accumulator and Memory

A ← (A) | (M) 0 – – Þ Þ –

ORA oprx16,SP ORA oprx8,SP

PSHA

PSHH

PSHX

PULA

Push Accumulator onto Stack

Push H (Index Register High) onto Stack

Push X (Index Register Low) onto Stack

Pull Accumulator from Stack

Push (A); SP ← (SP) – 0x0001

Push (H); SP ← (SP) – 0x0001

Push (X); SP ← (SP) – 0x0001

SP ← (SP + 0x0001); Pull (A)

– – – – – – INH

Address

Mode

DIR INH INH IX1 IX SP1

DIR/DIR DIR/IX+ IMM/DIR IX+/DIR

DIR INH INH IX1 IX SP1

IMM DIR EXT IX2 IX1 IX SP2 SP1

Opcode Operand

dd 48 58 68

ff 78

9E68

dd 44 54 64

ff 74

9E64

dd dd

ii dd

dd 40 50 60

ff 70

9E60

62 1

hh ll

ee ff

9EDA

ee ff

9EEA

87 2

8B 2

89 2

86 3

Cycles

Bus

[1]

5 1 1 5 4 6

5 5 4 5

5 1 1 5 4 6

2 3 4 4 3 3 5 4

User manual Rev. 7 — 29 March 2021

30 / 207

+ 177 hidden pages

NXP UM11227, NTM88 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

1 Introduction

1.1 Purpose

1.2 Audience

2 General description

3 Features and benefits

4 Configuration options

4.1 Electronic encoding - "CodeF"

4.2 Electronic encoding - "CodeH"

4.3 Device identification

4.4 Definition of signal ranges

4.5 Memory resource usage

5 Marking

5.1 Exterior markings

6 Block diagram

7 Pinning information

7.1 Pinout

7.2 Pin description

7.3 Orientation

8 Central processing unit

8.1 Introduction

8.2 Features

8.3 Programmer’s model and CPU registers

8.3.1 Accumulator (A)

8.3.2 Index register (H:X)

8.3.3 Stack pointer (SP)

8.3.4 Program counter (PC)

8.3.5 Condition code register (CCR)

8.4 Addressing modes

8.4.1 Inherent addressing mode (INH)

8.4.2 Relative addressing mode (REL)

8.4.3 Immediate addressing mode (IMM)

8.4.4 Direct addressing mode (DIR)

8.4.5 Extended addressing mode (EXT)

8.4.6 Indexed addressing mode

8.4.6.1 Indexed, no offset (IX)

8.4.6.2 Indexed, no offset with post increment (IX+)

8.4.6.3 Indexed, 8-bit offset (IX1)

8.4.6.4 Indexed, 8-bit offset with post increment (IX1+)

8.4.6.5 Indexed, 16-bit offset (IX2)

8.4.6.6 SP-Relative, 8-bit offset (SP1)

8.4.6.7 SP-Relative, 16-bit offset (SP2)

8.5 Special operations

8.5.1 Reset sequence

8.5.2 Interrupt sequence

8.5.3 WAIT mode operation

8.5.4 STOP mode operation

8.5.5 BGND instruction

8.6 HCS08 instruction set summary

8.6.1 Instruction set summary nomenclature

8.6.2 Operators

8.6.3 CPU registers

8.6.4 Memory and addressing

8.6.5 Condition code register (CCR) bits

8.6.6 CCR activity notation

8.6.7 Machine coding notation

8.6.8 Source form

8.6.9 Address modes