VGA/video interface with integrated buffers, ESD protection
and integrated termination resistors
Rev. 2 — 19 May 2011Product data sheet
The IP4770CZ16, IP4771CZ16, IP4772CZ16 is connected between the VGA/DVI
interface and the video graphics controller and includes level shifting for the DDC signals,
buffering for the SYNC lines as well as high-level ESD protection diodes for the RGB
signal lines.
The level shifting functions are required when the DDC controller operates at a lower
supply voltage than the monitor. To use this level shifting function the gates of the two
N-channel MOSFETs have to be connected to the supply rail of the DDC transceivers.
Buffering for the SYNC signals is provided by two non-inverting buf fers, which accept TTL
input levels and convert these to CMOS compliant output levels between pins V
and GND.
CC(SYNC)
The IP4770CZ16 and IP4771CZ16 contain the formerly external termination resistors,
which are typically required for the HSYNC and VSYNC lines of the video interface:
• IP4770CZ16: R
• IP4771CZ16: R
• IP4772CZ16: R
All RGB I/Os are protected by a special diode configuration offering a low line capacitance
of 4 pF (maximum) only to provide protection to downstream components for ESD
voltages as high as ±8 kV contact discharge according to IEC 61000-4-2, level 4
standard.
2. Features and benefits
Integrated high-level ESD protection, buffering, SYNC signal impedance matchin g and
level shifting
T er minal connections with integrated rail-to-rail clam ping diodes with downstream ESD
protection of ±8 kV according to IEC 61000-4-2, level 4 standard
Backflow protection on DDC lines
Drivers for HSYNC and VSYNC lines
Bidirectional level shifting N-channel FETs available for DDC clock and DDC data
channels
Integrated impedance matching resistors on SYNC lines
Line capacitance < 4 pF per channel
Lead-free package and RoHS compliant
=55Ω
sync
=65Ω
sync
=10Ω to allow termination of the SYNC lines
sync
NXP Semiconductors
3. Applications
To terminate and to buffer channels, to reduce EMI/RFI and to provide downstream
ESD protection for:
VGA interfaces including DDC channels
Desktop and notebooks PCs
Graphics cards
Set-top boxes
4. Ordering information
Table 1.Ordering information
Type numberPackage
IP4770CZ16SSOP16plastic shrink small outline package; 16 leads; body
IP4771CZ16
IP4772CZ16
level 4; contact−8+8kV
level 4; air discharge−15+15kV
IEC 61000-4-2; all other
pins
level 1; contact−2+2kV
level 1; air discharge−2+2kV
V
CC(VIDEO)
V
CC(DDC)
V
CC(SYNC)
V
I(VIDEO_1)
V
I(VIDEO_2)
V
I(VIDEO_3)
V
I(DDC_IN1)
V
I(DDC_IN2)
V
I(SYNC_IN1)
V
I(SYNC_IN2)
V
O(DDC_OUT1)
V
O(DDC_OUT2)
P
tot
T
stg
video supply voltage−0.55.5V
data display channel supply voltage−0.55.5V
synchronization supply voltage−0.55.5V
input voltage on pin VIDEO_1−0.5V
input voltage on pin VIDEO_2−0.5V
input voltage on pin VIDEO_3−0.5V
input voltage on pin DDC_IN1−0.5V
input voltage on pin DDC_IN2−0.5V
input voltage on pin SYNC_IN1−0.5V
input voltage on pin SYNC_IN2−0.5V
output voltage on pin DDC_OUT1−0.5V
output voltage on pin DDC_OUT2−0.5V
total power dissipationT
inductance, chip ceramic capacitor at each supply pin.
ESD pulse is applied between the pins VIDEO_1, VIDEO_2, VIDEO_3, SYNC_OUT1, SYNC_OUT2, DDC_OUT1, DDC_OUT2 and
GND.
The bypass capacitor at pin BYP can be omitted. In this case the maximum ESD level for DDC_OUT1 and DDC_OUT2 pins is reduced
must be bypassed to ground (pin GND) via a low-impedance ground plane with 0.22 μF, low
CC(SYNC)
NXP Semiconductors
9. Recommended operating conditions
IP4770/71/72CZ16
VGA/video interface
Table 5.Recommended operating conditions
SymbolParameterConditionsMinTypMaxUnit
T
oper
operating temperature−40-+85°C
10. Characteristics
Table 6.Sync circuit characteristics
V
CC(SYNC)
=5V; T
SymbolParameterConditionsMinTypMaxUnit
Supply: pin V
I
CC(SYNC)
CC(SYNC)
supply current on pin V
Input: pins SYNC_IN1 and SYNC_IN2
V
IH
V
IL
HIGH-level input voltage 2.0--V
LOW-level input voltage --0.6V
Output: pins SYNC_OUT1 and SYNC_OUT2
V
OH
V
OL
R
sync
HIGH-level output voltage IOH= 1 mA4.85--V
LOW-level output voltage IOL= 1 mA--0.15V
synchronization resistanceIP4770CZ16
Sync channel
t
PLH
t
PHL
t
r(o)
t
f(o)
LOW to HIGH propagation delay CL=50pF; tr and tf≤ 5ns
HIGH to LOW propagation delay CL=50pF; tr and tf≤ 5ns
output rise time CL=50pF; tr and tf≤ 5ns-4-ns
output fall time CL= 50 pF; tr and tf≤ 5ns-4-ns
Protection diode
I
L(r)
V
V
BRzd
Fd
reverse leakage currentper channel; V = 3.0 V--1μA
Zener diode breakdown voltage I = 1 mA6-9V
diode forward voltageIF=1mA-0.7-V
=25°C; unless otherwise specified.
amb
CC(SYNC)
[1]
--50μA
[1]
SYNC input at 3 V
IP4772CZ16; I
IP4772CZ16; I
=24mA2.0--V
OH
=24mA--0.8V
OL
IP4771CZ16
IP4772CZ16
=7pF; tr and tf≤ 5 ns-1.5-ns
C
L
=7pF; tr and tf≤ 5 ns-1.5-ns
C
L
--2mA
[2]
-55-Ω
[2]
-65-Ω
[3]
-10-Ω
[4]
--12ns
[4]
--12ns
[1] SYNC outputs unloaded.
[2] R
sync=Rterm+Rbuffer
[3] R
sync=Rbuffer
[4] This parameter is guaranteed by design and characterization.
The IP4770CZ16, IP4771CZ16, IP4772CZ16 should be placed as close as possible to the
VGA/DVI interface connector.
The ESD protection channels VIDEO_1, VIDEO_2 and VIDEO_3 can be connected in any
order with RBG signals.
The 100 kΩ resistors between the DDC_OUTx channels and VCC_5V are optional. They
may be used, if required, to pull-up the DDC_OUTx lines to VCC_5V when no monitor is
connected to the VGA connector. Backflow current can flow between pins DDC_OUTx
and VCC_5V via these resistors when VCC_5V is powered down.
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