NXP IP4770CZ16, IP4771CZ16, IP4772CZ16 Schematic [ru]

IP4770/71/72CZ16

SSOP16

1. General description

VGA/video interface with integrated buffers, ESD protection
and integrated termination resistors

Rev. 2 — 19 May 2011 Product data sheet

The IP4770CZ16, IP4771CZ16, IP4772CZ16 is connected between the VGA/DVI
interface and the video graphics controller and includes level shifting for the DDC signals,
buffering for the SYNC lines as well as high-level ESD protection diodes for the RGB
signal lines.

The level shifting functions are required when the DDC controller operates at a lower
supply voltage than the monitor. To use this level shifting function the gates of the two
N-channel MOSFETs have to be connected to the supply rail of the DDC transceivers.

Buffering for the SYNC signals is provided by two non-inverting buf fers, which accept TTL
input levels and convert these to CMOS compliant output levels between pins V
and GND.

CC(SYNC)

The IP4770CZ16 and IP4771CZ16 contain the formerly external termination resistors,
which are typically required for the HSYNC and VSYNC lines of the video interface:

• IP4770CZ16: R

• IP4771CZ16: R

• IP4772CZ16: R

All RGB I/Os are protected by a special diode configuration offering a low line capacitance
of 4 pF (maximum) only to provide protection to downstream components for ESD
voltages as high as ±8 kV contact discharge according to IEC 61000-4-2, level 4
standard.

2. Features and benefits

 Integrated high-level ESD protection, buffering, SYNC signal impedance matchin g and

level shifting

 T er minal connections with integrated rail-to-rail clam ping diodes with downstream ESD

protection of ±8 kV according to IEC 61000-4-2, level 4 standard

 Backflow protection on DDC lines
 Drivers for HSYNC and VSYNC lines
 Bidirectional level shifting N-channel FETs available for DDC clock and DDC data

channels

 Integrated impedance matching resistors on SYNC lines
 Line capacitance < 4 pF per channel
 Lead-free package and RoHS compliant

=55Ω

sync

=65Ω

sync

=10Ω to allow termination of the SYNC lines

sync

NXP Semiconductors

3. Applications

 To terminate and to buffer channels, to reduce EMI/RFI and to provide downstream

ESD protection for:

 VGA interfaces including DDC channels
 Desktop and notebooks PCs
 Graphics cards
 Set-top boxes

4. Ordering information

Table 1. Ordering information

Type number Package

IP4770CZ16 SSOP16 plastic shrink small outline package; 16 leads; body
IP4771CZ16
IP4772CZ16

IP4770/71/72CZ16

VGA/video interface

Name Description Version

SOT519-1

width 3.9 mm; lead pitch 0.635 mm

5. Marking

Table 2. Marking codes

Type number Marking code

IP4770CZ16 4770
IP4771CZ16 4771
IP4772CZ16 4772

IP4770_71_72CZ16 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.

Product data sheet Rev. 2 — 19 May 2011 2 of 14

NXP Semiconductors

6. Functional diagram

V

CC(SYNC)

SYNC_IN1

SYNC_IN2

R

term

R

term

V

CC(SYNC)

V

CC(DDC)

IP4770/71/72CZ16

VGA/video interface

V

CC(VIDEO)

SYNC_OUT1

SYNC_OUT2

VIDEO_1
VIDEO_2
VIDEO_3

DDC_OUT1
DDC_OUT2

BYP

DDC_IN1
DDC_IN2

IP4772CZ16: R

sync=Rbuffer

Fig 1. Functional diagram

and R

term

001aae818

=0Ω.

IP4770_71_72CZ16 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.

Product data sheet Rev. 2 — 19 May 2011 3 of 14

NXP Semiconductors

7. Pinning information

7.1 Pinning

IP4770/71/72CZ16

VGA/video interface

V

CC(SYNC)

V

CC(VIDEO)

VIDEO_1 SYNC_OUT1

VIDEO_2 SYNC_IN1

VIDEO_3 DDC_OUT2

V

CC(DCC)

1

2

3

IP4770CZ16

4

IP4771CZ16

5

IP4772CZ16

6

GND DDC_IN2

7

8

BYP DDC_OUT1

001aae809

16

SYNC_OUT2

15

SYNC_IN2

14

13

12

11

10

DDC_IN1

9

Fig 2. Pin configuration

7.2 Pin description

Table 3. Pin description

Symbol Pin Description

V

CC(SYNC)

V

CC(VIDEO)

VIDEO_1 3 video si gnal ESD protection channel 1
VIDEO_2 4 video si gnal ESD protection channel 2
VIDEO_3 5 video si gnal ESD protection channel 3
GND 6 ground
V

CC(DDC)

BYP 8 this input is used to connect an external 0.2 μF bypass capacitor to increase

DDC_OUT1 9 DDC signal outpu t 1; connected to the video connector side of one of the

DDC_IN1 10 DDC signal input 1; connected to the VGA controller side of one of the SYNC

DDC_IN2 11 DDC signal input 2; connected to the VGA controller side of one of the SYNC

DDC_OUT2 12 DDC signal output 2; connected to the video connector side of one of the

SYNC_IN1 13 SYNC signal input 1; connected to the VGA controller side of one of the

SYNC_OUT1 14 SYNC signal output 1; connected to the video connector side of one of the

SYNC_IN2 15 SYNC signal input 2; connected to the VGA controller side of one of the

SYNC_OUT2 16 SYNC signal output 2; connected to the video connector side of one of the

1 supply voltage for SYNC_1 and SYNC_2 level shifter and their connected

ESD protections

2 supply voltage for VIDEO_1, VIDEO_2 and VIDEO_3 protection circuits

7 supply voltage for DDC_1 and DDC_2 level shifter N-FET gates

ESD withstand voltage rating for the DDC outputs (±8 kV with capacitor or
±4 kV without capacitor)

SYNC lines

lines

lines

SYNC lines

SYNC lines

SYNC lines

SYNC lines

SYNC lines

IP4770_71_72CZ16 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.

Product data sheet Rev. 2 — 19 May 2011 4 of 14

NXP Semiconductors

8. Limiting values

IP4770/71/72CZ16

VGA/video interface

Table 4. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to ground (GND).

Symbol Parameter Conditions Min Max Unit

V

ESD

electrostatic discharge voltage IEC 61000-4-2; pins

[1]

VIDEO_1, VIDEO_2,
VIDEO_3, SYNC_OUT1,
SYNC_OUT2,
DDC_OUT1, DDC_OUT2

level 4; contact −8+8 kV
level 4; air discharge −15 +15 kV

IEC 61000-4-2; all other
pins

level 1; contact −2+2 kV
level 1; air discharge −2+2 kV

V

CC(VIDEO)

V

CC(DDC)

V

CC(SYNC)

V

I(VIDEO_1)

V

I(VIDEO_2)

V

I(VIDEO_3)

V

I(DDC_IN1)

V

I(DDC_IN2)

V

I(SYNC_IN1)

V

I(SYNC_IN2)

V

O(DDC_OUT1)

V

O(DDC_OUT2)

P

tot

T

stg

video supply voltage −0.5 5.5 V
data display channel supply voltage −0.5 5.5 V
synchronization supply voltage −0.5 5.5 V
input voltage on pin VIDEO_1 −0.5 V
input voltage on pin VIDEO_2 −0.5 V
input voltage on pin VIDEO_3 −0.5 V
input voltage on pin DDC_IN1 −0.5 V
input voltage on pin DDC_IN2 −0.5 V
input voltage on pin SYNC_IN1 −0.5 V
input voltage on pin SYNC_IN2 −0.5 V
output voltage on pin DDC_OUT1 −0.5 V
output voltage on pin DDC_OUT2 −0.5 V
total power dissipation T

=25°C - 500 mW

amb

CC(VIDEO)
CC(VIDEO)
CC(VIDEO)
CC(DDC)
CC(DDC)
CC(SYNC)
CC(SYNC)
CC(DDC)
CC(DDC)

V
V
V
V
V
V
V
V
V

storage temperature −55 +125 °C

[1] Pins BYP, V

inductance, chip ceramic capacitor at each supply pin.
ESD pulse is applied between the pins VIDEO_1, VIDEO_2, VIDEO_3, SYNC_OUT1, SYNC_OUT2, DDC_OUT1, DDC_OUT2 and

GND.
The bypass capacitor at pin BYP can be omitted. In this case the maximum ESD level for DDC_OUT1 and DDC_OUT2 pins is reduced

to ±4kV.

IP4770_71_72CZ16 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.

Product data sheet Rev. 2 — 19 May 2011 5 of 14

CC(VIDEO)

and V

must be bypassed to ground (pin GND) via a low-impedance ground plane with 0.22 μF, low

CC(SYNC)