NXP i.MX 8QuadMax User Manual
NXP Semiconductors
Package Information
29 x 29 mm package case outline
Data Sheet: Technical Data
i.MX 8QuadMax Automotive and Infotainment Applications Processors
Document Number: IMX8QMAEC
Rev. 1, 12/2020
MIMX8QMnAVU xxAx
Ordering Information
1 Introduction
The i.MX 8 Family consists of two processors:
i.MX 8QuadMax and 8QuadPlus. This data sheet covers
the i.MX 8QuadMax processor, which is composed of
eight cores (two Arm® Cortex®-A72, four Arm
Cortex®-A53, and two Arm Cortex®-M4F), dual 32-bit
GPU subsystems, 4K H.265 capable VPU, and dual
failover-ready display controllers. This processor
supports a single 4K display (with multiple display
output options, including MIPI-DSI, HDMI, eDP/DP,
and LVDS), or multiple smaller displays. Memory
interfaces supporting LPDDR4, Quad SPI/Octal SPI
(FlexSPI), eMMC 5.1, RAW NAND, SD 3.0, and a wide
range of peripheral I/Os such as PCIe 3.0, provide wide
flexibility. Advanced multicore audio processing is
supported by the Arm cores and a high performance
Tensilica® HiFi 4 DSP for pre- and post-audio
processing as well as voice recognition.
See Table 2 on page 5
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . 5
1.2 System Controller Firmware (SCFW) Requirements5
1.3 Related resources . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2 Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3 Modules List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.1 Special Signal Considerations. . . . . . . . . . . . . . . . 14
3.2 Recommended Connections for Unused Interfaces14
4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.1 Chip-level conditions . . . . . . . . . . . . . . . . . . . . . . . 15
4.2 Power supplies requirements and restrictions. . . . 28
4.3 PLL electrical characteristics . . . . . . . . . . . . . . . . . 31
4.4 On-chip oscillators . . . . . . . . . . . . . . . . . . . . . . . . . 35
4.5 I/O DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . 38
4.6 I/O AC Parameters . . . . . . . . . . . . . . . . . . . . . . . . 44
4.7 Output Buffer Impedance Parameters. . . . . . . . . . 47
4.8 System Modules Timing . . . . . . . . . . . . . . . . . . . . 51
4.9 General-Purpose Media Interface (GPMI) Timing . 55
4.10 External Peripheral Interface Parameters . . . . . . . 64
4.11 Analog-to-digital converter (ADC) . . . . . . . . . . . . 113
5 Boot mode configuration . . . . . . . . . . . . . . . . . . . . . . . . 117
5.1 Boot mode configuration pins . . . . . . . . . . . . . . . 117
5.2 Boot devices interfaces allocation . . . . . . . . . . . . 118
6 Package information and contact assignments . . . . . . 119
6.1 FCPBGA, 29 x 29 mm, 0.75 mm pitch . . . . . . . . 119
7 Release Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
NXP reserves the right to change the detail specifications as may be required to permit improvements in the design of
its products.
© 2018-2020 NXP B.V.
Introduction
The i.MX 8QuadMax processor offers numerous advanced features as shown in this table.
Table 1. i.MX 8QuadMax advanced features
Function Feature
Multicore architecture provides
4× Cortex-A53, 2× Cortex-A72 cores,
and 2× Cortex-M4F cores
Graphics Processing Unit (GPU) 16× Vec4 shaders with 64 execution units. Split GPU architecture allows for dual
Video Processing Unit (VPU) H.264 decode (4Kp30)
AArch64 for 64-bit support and new architectural features
AArch32 for full backward compatibility with ARMv7
Cortex-A72 and Cortex-A53 cores support ARM virtualization extensions. sMMU
provides address virtualization to all subsystems.
Cortex-M4F cores for real-time applications
independent 8-Vec4 shader GPUs or a combined 16-Vec4 shader GPU.
Supports OpenGL 3.0, 2.1,; OpenGL ES 3.2, 3.1 (with AEP), 3.0, 2.0, and 1.1;
OpenCL 1.2 Full Profile and 1.1; OpenVG 1.1; and Vulkan
High-performance 2D Blit Engine
H.265 decode (4Kp60)
WMV9/VC-1 imple decode
MPEG 1 and 2 decode
AVS decode
MPEG4.2 ASP, H.263, Sorenson Spark decode
Divx 3.11 including GMC decode
ON2/Google VP6/VP8 decode
RealVideo 8/9/10 decode
JPEG and MJPEG decode
2× H.264 encode (1080p30)
Tensilica HiFi 4 DSP for pre- and
post-processing
Memory 64-bit LPDDR4 @1600 MHz
i.MX 8QuadMax Automotive and Infotainment Applications Processors, Rev. 1, 12/2020
666 MHz
Fixed-point and vector-floating-point support
32 KB instruction cache, 48 KB data cache, 512 KB SRAM (448 KB of OCRAM and
64 KB of TCM)
1× Quad SPI which can be used to connect to an FPGA
2× Quad SPI or 1× Octal SPI (FlexSPI) for fast boot from SPI NOR flash
2× SD 3.0 card interfaces
1× eMMC5.1/SD3.0
RAW NAND (62-bit ECC support via BCH-62 module)
NXP Semiconductors2
Introduction
Table 1. i.MX 8QuadMax advanced features (continued)
Function Feature
Display Controller Supports single UltraHD 4Kp60 display or up to 4 independent FullHD 1080p60
displays
Up to 18-layer composition
Complementary 2D blitting engines and online warping functionality
Integrated Failover Path (SafeAssure) to ensure display content stays valid even in
event of a software failure
Display I/O 2× MIPI-DSI with 4 lanes each
1× HDMI-TX/DisplayPort compliant with:
• HDMI 1.4b and 2.0a
•eDP 1.4
•DP 1.3
2× LVDS Tx with 2 channels of 4 lanes each
Camera I/O and video 2× MIPI-CSI with 4-lanes each, MIPI DPHYSM v1.1
Security Advanced High Assurance Boot (AHAB) secure & encrypted boot
Random Number Generator with a high-quality entropy source generator and
Hash_DRBG (based on hash functions)
RSA up to 4096, Elliptic Curve up to 1023
AES-128/192/256, DES, 3DES, MD5, SHA-1, SHA-224/256/384/512
Dedicated Security Controller for Flashless SHE and HSM support, Trustzone, RTIC
Built-in ECDSA/DSA protocol support
See the security reference manual for this chip for a full list of security features.
System Control • 2× I
• The tightly coupled M4 I2C ports cannot be used for general-purpose use
• System Control Unit (SCU):
• Power control, clocks, reset
• Boot ROMs
• PMIC interface
• Resource Domain Controller
2
C tightly coupled with Cortex-M4 cores (1× per Cortex M4F core)
i.MX 8QuadMax Automotive and Infotainment Applications Processors, Rev. 1, 12/2020
NXP Semiconductors 3
Introduction
Table 1. i.MX 8QuadMax advanced features (continued)
Function Feature
I/O 1× PCIe (2-lanes). Can be used as two PCIe 3.0 controllers with one-lane,
independent operation. PCIe 1.0 and 2.0 compliant. PCIe 3.0 capable, contact your
NXP representative.
1× USB 3.0 with PHY
2× USB 2.0 (1 with PHY, 1 with HSIC)
1× SATA 3.0 can be used as PCIe one-lane. This is in addition to the standard PCIe
controller. PCIe 1.0 and 2.0 compliant. PCIe 3.0 capable, contact your NXP
representative.
2× 1Gb Ethernet with AVB (can be used as 10/100 Mbps ENET with AVB)
3× CAN/CAN-FD
8× UARTs:
•5× UARTs (2× with hardware flow control)
•2× UARTs tightly coupled with Cortex-M4F cores (1× per Cortex-M4F core)
•1× UART tightly coupled with SCU
2
C:
18× I
•5× General-Purpose I2C (full-speed with DMA support)
• Low-speed I
•2× master I2C in MIPI-DSI (1× per instance)
•4× master I2C in LVDS (2× per instance)
•2× master I
•2× master I2C in MIPI-CSI (1× per instance)
Note: Although low-speed I2Cs can be made available for general purpose use
which requires the associated PHY (for example, MIPI) to be powered on, it is not
recommended.
Note: I/O muxing constraints prevent using all I
• 2x I2C tightly coupled with Cortex-M4 cores (1x per Cortex M4F core)
Note: The tightly coupled M4 I2C ports cannot be used for general purpose use.
2
C tightly coupled with SCU for communication with the PMIC. Not general
•1× I
purpose and not available for non-PMIC uses.
2
C without DMA support:
2
C in HDMI-TX
2
Cs simultaneously.
4× SAI (SAI0 and SAI1 are transmit/receive; SAI2 and SAI3 are receive only)
2× Enhanced Serial Audio Interface (ESAI)
× ASRC (Asynchronous Sample Rate Converter) (note: no I/O signals are directly
connected to this module)
1× SPDIF (Tx and Rx)
2× 4-channel ADC converters
3.3 V/1.8 V GPIO
4× PWM channels
1× 6×8 KPP (Key Pad Port)
1× MQS (Medium Quality Sound)
4× SPI
Packaging Case FCPBGA 29 x 29 mm, 0.75 mm pitch
i.MX 8QuadMax Automotive and Infotainment Applications Processors, Rev. 1, 12/2020
NXP Semiconductors4
1.1 Ordering Information
For ordering information, contact an NXP representative at nxp.com.
Table 2. i.MX 8QuadMax Orderable part numbers
Introduction
Part Number Options
MIMX8QM5AVUFFAB With VPU,
GPU
MIMX8QM6AVUFFAB With VPU,
GPU, DSP
Cortex-A72
Speed
Grade
1.6 GHz 1.20 GHz 264 MHz Automotive 29 mm
1.6 GHz 1.20 GHz 264 MHz Automotive 29 mm × 29 mm, 0.75 mm
Cortex-A53
Speed
Grade
Cortex-M4F
Speed
Grade
Tem per atur e
Grade
Package
× 29 mm, 0.75 mm
pitch, FCPBGA (lidded)
pitch, FCPBGA (lidded)
1.2 System Controller Firmware (SCFW) Requirements
The i.MX 8 and 8X families require a minimum SCFW release version for correct operation and to prevent
potential reliability issues.
The SCFW is released as part of a Board Support Package (e.g. Linux, Android) which may vary in version
number for a specific BSP.
For example, NXP Yocto Linux release 5.4.47_2.2.0 GA contains SCFW version 1.6.0, whereas NXP
Yocto Linux release 5.4.47_2.2.0 GA contains SCFW version 1.6.0.
The released SCFW version associated within each BSP is the minimum version required to correctly
support the wider BSP functionality.
Customers should always check that they are using the specific SCFW binary delivered within their chosen
BSP release. Customers should not mix newer BSP versions with older revisions of the SCFW.
1.3 Related resources
Table 3. Related resources
Type Description
Reference manual The i.MX 8QuadMax Applications Processor Reference Manual (IMX8DQXPRM)
contains a comprehensive description of the structure and function (operation) of the
SoC.
Data sheet This data sheet includes electrical characteristics and signal connections.
Chip Errata The chip mask set errata provides additional and/or corrective information for a particular
device mask set.
Package drawing Package dimensions are provided in Section 6, “Package information and contact
assignments".”
Hardware guide The i.MX 8QuadMax/8QuadPlus Hardware Developer’s Guide provides system design
guidelines.
i.MX 8QuadMax Automotive and Infotainment Applications Processors, Rev. 1, 12/2020
NXP Semiconductors 5
Architectural Overview
2 Architectural Overview
The following subsections provide an architectural overview of the i.MX 8QuadMax processor system.
i.MX 8QuadMax Automotive and Infotainment Applications Processors, Rev. 1, 12/2020
NXP Semiconductors6
2.1 Block Diagram
VFP
1MB L2 w/ ECC
32KB D$
NEON
32KB I$
4x ARM Cortex-A53
CPU1 Platform
VFP
1MB L2 w/ optional ECC
32KB D$
NEON
48KB I$
2x ARM Cortex-A72
CPU2 Platform
RNG
Ciphers
(ECC, RSA)
Secure RTC
Tamper
Detection
Secure
JTAG
64k Secure
RAM
ADC
(4 channels each)
CAN / CAN-FD
I2C w/ DMA
UART (5 Mb/s)
32-bit GPIO
24M and 32k
XTALOSC
Sources
System Control Unit
Clock, Reset
IOMUX
OTP
ADM
SNVS
CAAM
Security
256KB TCM w/ ECC
16KB system$
MMCAU
16KB code$
MCM
nvic
fpu mpu
M4 CPU
M4 Platform
SCU CM4 Complex
Debug
DAP, CTI, etc
SJC
Boot ROM
RDC
Power Mgmt
PWM
PMIC I/F
2x MU
INTs
WDOG
RGPIO
LPUART
LPI2C
LPIT
HAB
Tempmon
2x ADC
5x LPUART
5x LPI2C
4x LPSPI
2x eDMA
3x FlexCAN
DMA Subsystem
Audio Subsystem
2x LVDS
TX
2x MIPI
CSI2
Display Controllers
Imaging
ISI
MJPEG
ENC
MJPEG
DEC
Video Processing Unit
VPU
DSP Core
HIFI4 DSP
32KB I$ 48KB D$
64KB TCM
448KB OCRAM
HDMI
LPI2C
LPI2C
LPI2C
External Memory Interface
DDR
Controller
BN
PG
PG
PG
Graphics Processing Unit
1x I2C
1x UART
1x GPIO
Dedicated
1x eMMC
5.1 / SD 3.0
1x USB 3.0 PHY
6x8 Keypad
2x SD 3.0 (UHS-I)
1x USB 2.0
Host / HSIC
10/100/1000M
Ethernet + AVB
64-bit LPDDR4
@1600 MHz
RAW /
ONFI 3.2
NAND Flash
2x Quad SPI /
1x Octal SPI
NOR Flash
Mult-format Decode
H.265 Dec (4k60)
H.264 Dec (1080p60)
H.264 Enc (1080p30)
Dual Core, 16 shaders
Vulkan, OGLES 3.2 w/ AEP,
OCL 2.0, VG 1.1
2D Blit Engine
2x MIPI CSI2
(4-lanes)
1/2 LVDS TX
(4 lanes each)
1x I2C
1x I2C
HDMI Tx 2.0a
(eDP 1.4
DisplayPort 1.3)
1x I2C
SPDIF TX / RX
2x SAI TX / RX
2x SAI RX
ESAI TX / RX
SSI Bus
PG
2x User CM4 Complexes
256KB TCM w/ ECC
16KB system$
MMCAU
16KB code$
MCM
nvic
fpu mpu
M4 CPU
M4 Platform
PWM
2x MU
INTs
WDOG
RGPIO
LPUART
LPI2C
LPIT
1x I2C
(each)
1x UART
(each)
1x GPIO
(each)
Cache Coherent Interconnect (CCI-400)
2x DPU (4x LCD)
2x GPU
2x MIPI
DSI
LPI2C
MIPI Display
(4-lanes)
1x I2C
SATA
High Speed I/O
PHYPHY
2x PCIe
1x SATA 3.0 /
1x PCIe
(1 lane)
x1 PCIe
2 lanes /
x2 PCIe
1 lane each
1x USB 2.0
OTG, PHY
Connectivity Subsystem
USB3
2x USB2
3x uSDHC
2x ENET
NAND
2x EVM SIM
2x FTM
LPI2C
1x I2C
Security
Controller
(M0+)
SECO
2x ESAI
2x ASRC
8x SAI
MQS
SPDIF
6x GPT
HDMI TX SAI
2x eDMA
ACM
Audio Mixer
OCRAM (256KB)
Internal Memory
Low Speed I/O
(LSIO) Subsystem
14x MU
IEE
5x GPT
4x PWM
KPP
2x FlexSPI
8x GPIO
VPU Subsystem
The following figure shows the functional modules in the processor system.
Architectural Overview
Figure 1. i.MX 8QuadMax System Block Diagram
i.MX 8QuadMax Automotive and Infotainment Applications Processors, Rev. 1, 12/2020
NXP Semiconductors 7
Modules List
3 Modules List
The i.MX 8QuadMax processors contain a variety of digital and analog modules. This table describes the
processor modules in alphabetical order.
Table 4. i.MX 8QuadMax modules list
Block
Mnemonic
ADC Analog-to-Digital
APBH-DMA NAND Flash and BCH
A53 Arm (CPU1) CPU cluster embedding 4x Cortex-A53 CPUs with a 32KB L1 instruction cache and
A72 Arm (CPU2) CPU cluster embedding 2x Cortex-A72 CPUs with a 48 KB L1 instruction cache
ASRC Asynchronous Sample
BCH-62 Binary-BCH ECC
CAAM Cryptographic
Block Name Brief Description
The analog-to-digital converter (ADC) is a successive approximation ADC
Converter
ECC DMA Controller
Rate Converter
Processor
Accelerator and
Assurance Module
designed for operation within a SoC.
The AHB-to-APBH bridge provides the chip with a peripheral attachment bus
running on the AHB's HCLK, which includes the AHB-to-APB PIO bridge for a
memory-mapped I/O to the APB devices, as well as a central DMA facility for
devices on this bus and a vectored interrupt controller for the Arm core.
a 32KB data cache. The CPUs share a 1 MB L2 cache.
and 32 KB data cache. The CPUs have a 1MB L2 cache.
The Asynchronous Sample Rate Converter (ASRC) converts the sampling rate of
a signal associated to an input clock into a signal associated to a different output
clock. The ASRC supports concurrent sample rate conversion of up to 10 channels
of about -120dB THD+N. The sample rate conversion of each channel is
associated to a pair of incoming and outgoing sampling rates. The ASRC supports
up to three sampling rate pairs.
The BCH62 module provides up to 62-bit ECC for NAND Flash controller (GPMI2)
CAAM is a cryptographic accelerator and assurance module. CAAM implements
several encryption and hashing functions, a run-time integrity checker, and a
Pseudo Random Number Generator (PRNG).
CAAM also implements a Secure Memory mechanism. In this device the security
memory provided is 64 KB.
CTI Cross Trigger Interface CTI sends signals across the chip indicating that debug events have occurred. It is
used by features of the Coresight infrastructure.
CTM Cross Trigger Matrix Cross Trigger Matrix IP is used to route triggering events between CTIs.
DAP Debug Access Port The DAP provides real-time access for the debugger without halting the core to:
• System memory and peripheral registers
• All debug configuration registers
The DAP also provides debugger access to JTAG scan chains.
DC Display Controller Dual display controller
DDR Controller DRAM Controller • Memory types: LPDDR4
• Two channels of 32-bit memory:
• LPDDR4 up to 1.6 GHz
i.MX 8QuadMax Automotive and Infotainment Applications Processors, Rev. 1, 12/2020
NXP Semiconductors8
Table 4. i.MX 8QuadMax modules list (continued)
Modules List
Block
Mnemonic
DPR Display/Prefetch/
eDMA Enhanced Direct
Block Name Brief Description
Resolve
Memory Access
The DPR prefetches data from memory and converts the data to raster format for
display output. Raster source buffers can also be prefetched unconverted. The
resolve process supports graphics and video formatted tile frame buffers and
converts them to raster format. Embedded display memory is used as temporary
storage for data which is sourced by the display controller to drive the display.
•4× eDMA with a total of 128 channels (note: all channels are not assigned; see
the product reference manual for more information):
•4× instances with 32 channels each
• Programmable source, destination addresses, transfer size, plus support for
enhanced addressing modes
• Internal data buffer, used as temporary storage to support 64-byte burst
transfers, one outstanding transaction per DMA controller.
• Transfer control descriptor organized to support two-deep, nested transfer
operations
• Channel service request via one of three methods:
• Explicit software initiation
• Initiation via a channel-to-channel linking mechanism for continuous
transfers
• Peripheral-paced hardware requests (one per channel)
• Support for fixed-priority and round-robin channel arbitration
• Channel completion reported via interrupt requests
• Support for scatter/gather DMA processing
• Support for complex data structures via transfer descriptors
• Support to cancel transfers via software or hardware
• Each eDMA instance can be uniquely assigned to a different resource domain,
security (TZ) state, and virtual machine
• In scatter-gather mode, each transfer descriptor’s buffers can be assigned to
different SMMU translation
ENET Ethernet Controller 2× 1 Gbps Ethernet controllers supporting RGMII + AVB (Audio Video Bridging,
IEEE 802.1Qav)
ESAI Enhanced Serial Audio
Interface
FTM FlexTimer Provides input signal capture and PWM support
FlexCAN Flexible Controller Area
Network
i.MX 8QuadMax Automotive and Infotainment Applications Processors, Rev. 1, 12/2020
The Enhanced Serial Audio Interface (ESAI) provides a full-duplex serial port for
serial communication with a variety of serial devices, including industry-standard
codecs, SPDIF transceivers, and other processors. The ESAI consists of
independent transmitter and receiver sections, each section with its own clock
generator. All serial transfers are synchronized to a clock. Additional
synchronization signals are used to delineate the word frames. The normal mode
of operation is used to transfer data at a periodic rate, one word per period. The
network mode is also intended for periodic transfers; however, it supports up to 32
words (time slots) per period. This mode can be used to build time division
multiplexed (TDM) networks. In contrast, the on-demand mode is intended for
non-periodic transfers of data and to transfer data serially at high speed when the
data becomes available.
The ESAI has 12 pins for data and clocking connection to external devices.
Communication controller implementing the CAN with Flexible Data rate (CAN FD)
protocol and the CAN protocol according to the CAN 2.0B protocol specification.
NXP Semiconductors 9
Modules List
Table 4. i.MX 8QuadMax modules list (continued)
Block
Mnemonic
FlexSpi (Quad
SPI/Octal SPI)
GIC Generic Interrupt
GPIO General Purpose I/O
GPMI General Purpose Media
GPT General Purpose Timer Each GPT is a 32-bit “free-running” or “set and forget” mode timer with
Block Name Brief Description
Flexible Serial
Peripheral Interface
Controller
Modules
Interface
• Flexible sequence engine to support various flash vendor devices, including
HyperBus™ devices:
• Support for FPGA interface
• Single, dual, quad, and octal mode of operation.
• DDR/DTR mode wherein the data is generated on every edge of the serial flash
clock.
• Support for flash data strobe signal for data sampling in DDR and SDR mode.
• Two identical serial flash devices can be connected and accessed in parallel for
data read operations, forming one (virtual) flash memory with doubled readout
bandwidth.
The GIC-500 handles all interrupts from the various subsystems and is ready for
virtualization.
Used for general purpose input/output to external devices. Each GPIO module
supports 32 bits of I/O.
The GPMI module supports up to 8
encryption/decryption for NAND Flash controller (GPMI). The GPMI supports
separate DMA channels per NAND device.
programmable prescaler and compare and capture register. A timer counter value
can be captured using an external event and can be configured to trigger a capture
event on either the leading or trailing edges of an input pulse. When the timer is
configured to operate in “set and forget” mode, it is capable of providing precise
interrupts at regular intervals with minimal processor intervention. The counter has
output compare logic to provide the status and interrupt at comparison. This timer
can be configured to run either on an external clock or on an internal clock.
× NAND devices. 62-bit ECC (BCH)
GPU Graphics Processing 2× GC7000XSVX GPUs with 8 shaders each that can run either independently or
in “dual-mode” with 16 shaders.
HDMI Tx/
DP/eDP
HiFi 4 DSP Audio Processor A highly optimized audio processor geared for efficient execution of audio and
2
CI
I
IEE • Supports direct encryption and decryption of FlexSPI memory type
IOMUXC IOMUX Control This module enables flexible I/O multiplexing. Each I/O pad has default and several
JPEG/dec MJPEG engine for
HDMI Tx interface HDMI transmitter, Display Port 1.3 and embedded Display Port 1.4
voice codecs and pre- and post-processing modules to offload the Arm core.
2
C Interface I2C provides serial interface for external devices.
• Provides decryption services (lower performance) for DRAM traffic
• Supports I/O direct encrypted storage and retrieval
• Support for a number of cryptographic standards:
• 128/256-bit AES Encryption (AES-CTR, AES-XTS mode options)
• Multiple keys supported:
• Loaded via secure key channel from security block
• Key selection is per access and based on source of transaction
alternate functions. The alternate functions are software configurable.
Provides up to 4-stream decoding in parallel.
decode
i.MX 8QuadMax Automotive and Infotainment Applications Processors, Rev. 1, 12/2020
NXP Semiconductors10
Table 4. i.MX 8QuadMax modules list (continued)
Modules List
Block
Mnemonic
JPEG/enc MJPEG engine for
KPP Key Pad Port The Keypad Port (KPP) is a 16-bit peripheral that can be used as a 6 x 8 keypad
LPIT-1
LPIT-2
LPSPI 0–3 Configurable SPI Full-duplex enhanced Synchronous Serial Interface. It is configurable to support
LVDS LVDS Display Bridge
M4F Arm (CPU3) • Cortex-M4F core
Block Name Brief Description
Provides up to 4-stream encoding in parallel.
encode
matrix interface or as general purpose input/output (I/O).
Low-Power Periodic
Interrupt Timer
Each LPIT is a 32-bit “set and forget” timer that starts counting after the LPIT is
enabled by software. It is capable of providing precise interrupts at regular intervals
with minimal processor intervention. It has a 12-bit prescaler for division of input
clock frequency to get the required time setting for the interrupts to occur, and
counter value can be programmed on the fly.
Master/Slave modes, four chip selects to support multiple peripherals.
The LVDS is a high performance serializer that interfaces with LVDS
displays
• AHB LMEM (Local Memory Controller) including controllers for TCM and cache
• 256 KB embedded tightly coupled memory(TCM) (128 KB TCMU, 128 KB
• 16 KB Code Bus Cache
• 16 KB System Bus Cache
• ECC for TCM memories and parity for code and system caches
• Integrated Nested Vector Interrupt Controller (NVIC)
• Wakeup Interrupt Controller (WIC)
• FPU (Floating Point Unit)
• Core MPU (Memory Protection Unit)
• Support for exclusive access on the system bus
• MMCAU (Crypto Acceleration Unit)
• MCM (Miscellaneous Control Module)
.
memories
TCML)
MIPI CSI-2 MIPI CSI-2 Interface The MIPI CSI-2 IP provides MIPI CSI-2 standard camera interface ports. The MIPI
CSI-2 interface supports up to 1.5 Gbps for up to 4 data lanes
MIPI-DSI MIPI DSI interface The MIPI DSI IP provides DSI standard display serial interface. The DSI interface
supports 80 Mbps to 1.5 Gbps speed per data lane.
MQS Medium Quality Sound Medium Quality Sound (MQS) is used to generate 2-channel medium quality
PWM-like audio via two standard digital GPIO pins.
OCOTP_CTRL OTP Controller The On-Chip OTP controller (OCOTP_CTRL) provides an interface for reading,
programming, and/or overriding identification and control information stored in
on-chip fuse elements. The module supports electrically-programmable poly fuses
(eFUSEs). The OCOTP_CTRL also provides a set of volatile software-accessible
signals that can be used for software control of hardware elements, not requiring
non-volatility. The OCOTP_CTRL provides the primary user-visible mechanism for
interfacing with on-chip fuse elements. Among the uses for the fuses are unique
chip identifiers, mask revision numbers, cryptographic keys, JTAG secure mode,
boot characteristics, and various control signals requiring permanent nonvolatility.
i.MX 8QuadMax Automotive and Infotainment Applications Processors, Rev. 1, 12/2020
NXP Semiconductors 11
Modules List
Table 4. i.MX 8QuadMax modules list (continued)
Block
Mnemonic
OCRAM On-Chip Memory
PCIe PCI Express PCIe 1.0 and 2.0 compliant. PCIe 3.0 capable; contact your NXP representative. .
PRG Prefetch/Resolve
PWM Pulse Width Modulation The pulse-width modulator (PWM) has a 16-bit counter and is optimized to
RAM
64 KB Secure
RAM
RAM
256 KB
RNG Random Number
Block Name Brief Description
The On-Chip Memory controller (OCRAM) module is designed as an interface
Controller
Gasket
Secure/non-secure
RAM
Internal RAM Internal RAM, which is accessed through OCRAM memory controllers.
Generator
between the system’s AXI bus and the internal (on-chip) SRAM memory module.
The OCRAM is used for controlling the 256 KB multimedia RAM through a 64-bit
AXI bus.
The PRG is a gasket which translates system memory accesses to local display
RTRAM accesses for display refresh. It works with the DPR to complete the
prefetch and resolving operations needed to drive the display.
generate sound from stored sample audio images and it can also generate tones.
It uses 16-bit resolution and a 4×16 data FIFO to generate square waveforms.
Secure/non-secure Internal RAM, interfaced through the CAAM.
The purpose of the RNG is to generate cryptographically strong random data. It
uses a true random number generator (TRNG) and a pseudo-random number
generator (PRNG) to achieve true randomness and cryptographic strength. The
RNG generates random numbers for secret keys, per message secrets, random
challenges, and other similar quantities used in cryptographic algorithms.
SAI I2S/SSI/AC97 Interface The SAI module provides a synchronous audio interface that supports full duplex
serial interfaces with frame synchronization, such as I2S, AC97, TDM, and
codec/DSP interfaces.
SECO Security Controller Core and associated memory and hardware responsible for key management.
SJC Secure JTAG Controller The SJC provides the JTAG interface, which is compatible with JTAG TAP
standards, to internal logic. This device uses JTAG port for production, testing, and
system debugging. Additionally, the SJC provides BSR (Boundary Scan Register)
standard support, which is compatible with IEEE1149.1 and IEEE1149.6 standards.
The JTAG port must be accessible during platform initial laboratory bring-up, for
manufacturing tests and troubleshooting, as well as for software debugging by
authorized entities. The SJC incorporates three security modes for protecting
against unauthorized accesses. Modes are selected through eFUSE configuration.
sMMU System MMU The System MMU is an MMU-500 from Arm. It supports two-stage address
translation and multiple translation contexts.
SNVS Secure Non-Volatile
Storage
SPDIF Sony Philips Digital
Interconnect Format
Secure Non-Volatile Storage, including Secure Real Time Clock, Security State
Machine, Master Key Control.
The Sony/Philips Digital Interface (SPDIF) audio block is a stereo transceiver that
allows the processor to receive and transmit digital audio. The SPDIF transceiver
allows the handling of both SPDIF channel status (CS) and User (U) data and
includes a frequency measurement block that allows the precise measurement of
an incoming sampling frequency.
i.MX 8QuadMax Automotive and Infotainment Applications Processors, Rev. 1, 12/2020
NXP Semiconductors12
Table 4. i.MX 8QuadMax modules list (continued)
Modules List
Block
Mnemonic
TEMPMON Temperature Monitor The temperature monitor/sensor IP module for detecting high temperature
UART UART Interface • High-speed TIA/EIA-232-F compatible, up to 5.0 Mbps
USB3/USB2 The USB3/USB2 OTG module has been specified to perform USB 3.0 dual role and
Block Name Brief Description
conditions. The temperature read out does not reflect case or ambient temperature.
It reflects the temperature in proximity of the sensor location on the die.
Temperature distribution may not be uniformly distributed; therefore, the read-out
value may not be the reflection of the temperature value for the entire die.
• Serial IR interface low-speed, IrDA-compatible (up to 115.2 Kbit/s)
• 9-bit or Multidrop mode (RS-485) support (automatic slave address detection)
• 7, 8, 9, or 10-bit data characters (7-bits only with parity)
• 1 or 2 stop bits
• Programmable parity (even, odd, and no parity)
• Hardware flow control support for request to send (RTS_B) and clear to send
(CTS_B) signals
USB 2.0 On-The-Go (OTG) compatible with the USB 3.0, and USB 2.0
specification with OTG supplementary specifications. This controller supports
twoindependent USB cores (1
the PHY and I/O interfaces to support this operation. The full pinout of the USB 3.0
controller includes the signaling for both USB 3.0 and USB 2.0. This does not
mean there is a separate USB 2.0 controller that can be used independently and
simultaneously with USB 3.0. This device has an additional separate,
independent USB 2.0 OTG controller which can be used simultaneously with this
USB 3.0. Specific features requested for this updated module:
• Super Speed (5 Gbps), High Speed (480 Mbps), full speed (12 Mbps) and low
speed (1.5 Mbps)
• Fully compatible with the USB 3.0 specification (backward compatible with USB
2.0)
• Fully compatible with the USB On-The-Go supplement to the USB 2.0
specification
• Hardware support for OTG signaling
• Host Negotiation Protocol (HNP) and Session Request Protocol (SRP)
implemented in hardware, which can also be controlled by software
× USB3.0 dual-role, 1× USB2.0 OTG) and includes
USBOH The USBOH module has been specified which performs USB 2.0 On-The-Go
(OTG) and USB 2.0 Host functionality compatible with the USB 2.0 with OTG
supplement and HS IC-USB specification. This controller supports two
independent USB cores (1
and I/O interfaces to support this operation.
Key features:
• One USB2.0 OTG controller
• High Speed (480 Mbps), full speed (12 Mbps) and low speed (1.5 Mbps)
• Fully compatible with the USB 2.0 specification
• Fully compatible with the USB On-The-Go supplement to the USB 2.0
specification
• Hardware support for OTG signaling
• Host Negotiation Protocol (HNP) and Session Request Protocol (SRP)
implemented in hardware, which can also be controlled by software
• USB2.0 Host with HS IC-USB specification
• HS IC-USB transceiver-less downstream support (Host only).
i.MX 8QuadMax Automotive and Infotainment Applications Processors, Rev. 1, 12/2020
NXP Semiconductors 13
× USB2.0 OTG, 1× USB2.0 Host) and includes the PHY
Modules List
Table 4. i.MX 8QuadMax modules list (continued)
Block
Mnemonic
uSDHC SD/eMMC and SDXC
VPU Video Processing Unit See the device reference manual for the complete list of the VPU’s
WDOG Watchdog The Watchdog Timer supports two comparison points during each counting period.
XTAL OSC24M The 24 MHz clock source is an external crystal that acts as the main system clock.
XTAL OSC32K The 32 KHz clock source is an external crystal. The OSC32K is intended to be
Block Name Brief Description
i.MX 8 Family SoC-specific characteristics:
Enhanced Multi-Media
Card / Secure Digital
Host Controller
All three MMC/SD/SDIO controller IPs are identical and are based on the uSDHC
IP.
The uSDHC is a host controller used to communicate with external low cost data
storage and communication media. It supports the previous versions of the
MultiMediaCard (MMC) and Secure Digital Card (SD) standards. Specifically, the
uSDHC supports:
• SD Host Controller Standard Specification v3.0 with the exception that all the
registers do not match the standards address mapping.
• SD Physical Layer Specification v3.0 UHS-I (SDR104/DDR50)
• SDIO specification v3.0
• eMMC System Specification v5.1
decoding/encoding capabilities.
Each of the comparison points is configurable to evoke an interrupt to the Arm core,
and a second point evokes an external event on the WDOG line.
The OSC24M is used as the source clock for subsystem PLLs. OSC24M can be
turned off by the System Control Unit (SCU) during sleep mode.
always on and is distributed by the SCU to modules in the chip.
3.1 Special Signal Considerations
The package contact assignments can be found in Section 6, “Package information and contact
assignments".” Signal descriptions are defined in the device reference manual.
3.2 Recommended Connections for Unused Interfaces
The recommended connections for unused analog interfaces can be found in the section, “Unused
Input/Output Terminations,” in the hardware development guide for this device.
i.MX 8QuadMax Automotive and Infotainment Applications Processors, Rev. 1, 12/2020
NXP Semiconductors14
Electrical characteristics
4 Electrical characteristics
This section provides the device and module-level electrical characteristics for these processors.
4.1 Chip-level conditions
This section provides the device-level electrical characteristics for the SoC. See the following table for a
quick reference to the individual tables and sections.
Table 5. Chip-level conditions
For these characteristics, … Topic appears …
Absolute maximum ratings on page 16
FCPBGA package thermal resistance data on page 18
Operating ranges on page 18
External Input Clock Frequency on page 22
Maximum supply currents on page 22
Standby use cases on page 48
USB 2.0 PHY typical current consumption in Power-Down
Mode
USB 3.0 PHY typical current consumption in Power-Down
Mode
Typical current consumption in Power-Down mode for USB
2.0 PHY embedded in USB 3.0 PHY
4.1.1 Absolute Maximum Ratings
CAUTION
Stresses beyond those listed under Table 6 may affect reliability or cause
permanent damage to the device. These are stress ratings only. Functional
operation of the device at these or any other conditions beyond those
indicated in the “Operating ranges” or other parameter tables is not implied.
Exposure to absolute-maximum-rated conditions for extended periods will
affect device reliability.
on page 26
on page 26
on page 26
i.MX 8QuadMax Automotive and Infotainment Applications Processors, Rev. 1, 12/2020
NXP Semiconductors 15
Electrical characteristics
Table 6. Absolute maximum ratings
Parameter Description Symbol Min Max Units
Core Supplies Input Voltage VDD_A72 -0.3 1.2 V
VDD_A53
VDD_GPU0
VDD_GPU1
VDD_MAIN
VDD_MEMC
DDR PHY supplies VDD_DDR_VDDQ -0.3 1.75 V
1.0V IO supplies VDD_MIPI_1P0 -0.3 1.2 V
VDD_USB_OTG_1P0
IO Supply for GPIO Type
1.8V IO Single supply
IO Supply for GPIO Type
1.8 / 2.5 / 3.3V IO Tri-voltage Supply
VDD_ADC_1P8 -0.5 2.1 V
VDD_ADC_DIG_1P8
VDD_ANA0_1P8 (IO, analog,OSC SCU)
VDD_ANA1_1P8 (IO, analog,OSC SCU)
VDD_DDR_PLL_1P8 (memory PLLs)
VDD_MIPI_1P8 (PHY, GPIO)
VDD_MIPI_CSI_DIG_1P8 (PHY, GPIO)
VDD_PCIE_1P8 (PHY)
VDD_USB_1P8 (PHY, GPIO)
VDD_ENET1_1P8_2P5_3P3 -0.3 3.8 V
VDD_ENET0_1P8_3P3
i.MX 8QuadMax Automotive and Infotainment Applications Processors, Rev. 1, 12/2020
NXP Semiconductors16
Electrical characteristics
Table 6. Absolute maximum ratings (continued)
Parameter Description Symbol Min Max Units
IO Supply for GPIO Type
1.8 / 3.3V IO Dual Voltage Supply
SNVS Coin Cell VDD_SNVS_4P2 -0.3 4.3 V
USB VBUS (OTG2) USB_OTG2_VBUS -0.3 3.63 V
VDD_CAN_UART_1P8_3P3 -0.3 3.8 V
VDD_CSI_1P8_3P3
VDD_EMMC0_1P8_3P3
VDD_EMMC0_VSELECT_1P8_3P3
VDD_ENET_MDIO_1P8_3P3
VDD_MIPI_DSI_DIG_1P8_3P3
VDD_PCIE_DIG_1P8_3P3
VDD_QSPI0A_1P8_3P3
VDD_QSPI0B_1P8_3P3
VDD_SPI_MCLK_UART_1P8_3P3
VDD_SPI_SAI_1P8_3P3
VDD_TMPR_CSI_1P8_3P3
VDD_USB_3P3 (PHY & GPIO)
VDD_USDHC1_1P8_3P3
VDD_USDHC1_VSELECT_1P8_3P3
USB VBUS (OTG1) USB_OTG1_VBUS -0.3 5.5 V
I/O Voltage for USB Drivers USB_OTG1_DP/USB_OTG1_DN -0.3 3.63 V
USB_OTG2_DP/USB_OTG2_DN
I/O Voltage for ADC ADC_INx -0.1 2.1 V
Vin/Vout input/output voltage range (GPIO
Type Pins)
Vin/Vout input/output voltage range (DDR
pins)
ESD immunity (HBM). Vesd_HBMX —
ESD immunity (CDM). Vesd_CDM — 250 V
Storage temperature range Tstorage -40 150 °C
Vin/Vout See Section 4.6.1 V
Vin/Vout See Section 4.6.1 V
1000 V
NOTE
HDMI CEC is 3.3V tolerant. HDMI DDC signals and HPD are 5V tolerant.
Refer to the Hardware Developer’s Guide for proper terminations.
i.MX 8QuadMax Automotive and Infotainment Applications Processors, Rev. 1, 12/2020
NXP Semiconductors 17
Electrical characteristics
4.1.2 Thermal resistance
4.1.2.1 FCPBGA package thermal resistance
This table provides the FCPBGA package thermal resistance data.
Table 7. FCPBGA package thermal resistance data
Rating Board Type
Junction to Ambient Thermal Resistance
Junction to Package Top Thermal Resistance
Junction to Case Thermal Resistance
1
Thermal test board meets JEDEC specification for this package (JESD51-9).
2
Determined in accordance to JEDEC JESD51-2A natural convection environment. Thermal resistance data in this report is
2
2
3
JESD51-9, 2s2p R
JESD51-9, 2s2p Ψ
JESD51-9, 1s R
1
Symbol
θJA
JT
θJC
29x29 mm
package
12.9 °C/W
0.1 °C/W
0.3 °C/W
Unit
solely for a thermal performance comparison of one package to another in a standardized specified environment. It is not meant
to predict the performance of a package in an application-specific environment.
3
Junction-to-Case thermal resistance determined using an isothermal cold plate. Case temperature refers to the mold surface
temperature at the package top side dead center.
4.1.3 Operating Ranges
The following table provides the operating ranges of these processors.
1
VDD_A72
VDD_A53
Table 8. Operating ranges
Symbol Description Mode Min Typ Max Unit Comments
2
2
Power supply
of Cortex-A72
cluster
Power supply
of Cortex-A53
cluster
Overdrive 1.05 1.10 1.15 V Max frequency is 1.6 GHz
Nominal 0.95 1.00 1.10 V Max frequency is 1.06 GHz
Overdrive 1.05 1.10 1.15 V Max frequency is 1.2 GHz
Nominal 0.95 1.00 1.10 V Max frequency is 900 MHz
VDD_GPU0 Power supply
of first GPU
instance
VDD_GPU1 Power supply
of second
GPU instance
i.MX 8QuadMax Automotive and Infotainment Applications Processors, Rev. 1, 12/2020
Overdrive 1.05 1.10 1.15 V Max frequencies: shaders:
1GHz;
core: 800 MHz
Nominal 0.95 1.00 1.10 V Max frequencies: shaders:
700 MHz;
core: 650 MHz
Overdrive 1.05 1.10 1.15 V Max freq.: shaders: 1 GHz;
core: 800 MHz
Nominal 0.95 1.00 1.10 V Max freq.: shaders: 700 MHz;
core: 650 MHz
NXP Semiconductors18
Electrical characteristics
Table 8. Operating ranges1 (continued)
Symbol Description Mode Min Typ Max Unit Comments
VDD_MEMC Power supply
of memory
controller
VDD_MAIN
3
Power supply
of remaining
core logic
VDD_DDR_CH0_VDDQ,
VDD_DDR_CH0_VDDQ_CKE,
VDD_DDR_CH1_VDDQ,
Power
supplies of
memory I/Os
VDD_DDR_CH1_VDDQ_CKE,
VDD_DDR_CH0_VDDA_PLL_1P8,
VDD_DDR_CH1_VDDA_PLL_1P8
Power
supplies of
memory PLLs
VDD_MIPI_CSI0_1P0,
VDD_MIPI_CSI1_1P0,
VDD_MIPI_DSI0_1P0,
VDD_MIPI_DSI0_PLL_1P0,
Power
supplies of
PHYs (1.0 V
part)
VDD_MIPI_DSI1_1P0,
VDD_MIPI_DSI1_PLL_1P0,
VDD_LVDS0_1P0,
VDD_LVDS1_1P0
VDD_ANA1_1P8, VDD_ANA2_1P8,
VDD_ANA3_1P8, VDD_CP_1P8,
VDD_SCU_1P8,
VDD_SCU_ANA_1P8,
VDD_SCU_XTAL_1P8
Power
supplies of
I/Os, analog
and oscillator
of the SCU
N/A 1.05 1.10 1.15 V —
N/A 0.95 1.00 1.10 V Max freq.: HiFi4 DSP 666 MHz
Max freq.: M4 264 MHz
Max freq.: VPU 600 MHz
LPDDR4 1.06 1.10 1.17 V Max frequency: 1.6 GHz to
support LPDDR4-3200
N/A 1.65 1.80 1.95 V PLL supply can be merged with
other 1.8V supplies with proper
on board decoupling.
N/A 0.95 1.00 1.10 V These balls shall be connected to
the same power supply as
VDD_MAIN. It shall be a star
connection from the power
supply. Each VDD power supply
ball shall have its own dedicated
decoupling caps.
N/A 1.65 1.70 1.75 V These balls shall be powered by a
dedicated supply.
Note: The disconnect between
the ball naming, implying a 1.8 V
supply, and the actual required
operating voltage of 1.7 V is
known and correct as shown.
VDD_PCIE_IOB_1P8,
VDD_ADC_1P8,
VDD_ADC_DIG_1P8,
VDD_HDMI_RX0_1P8
VDD_HDMI_TX0_1P8,
VDD_LVDS0_1P8,
VDD_LVDS1_1P8,
Power
supplies of
4
,
PHYs (1.8 V
part) and
GPIO
operating at
1.8 V only.
N/A 1.65 1.80 1.95 V —
VDD_MIPI_CSI0_1P8,
VDD_MIPI_CSI1_1P8,
VDD_MIPI_DSI0_1P8,
VDD_MIPI_DSI1_1P8,
VDD_MLB_1P8
5
,
VDD_PCIE_LDO_1P8,
VDD_PCIE_SATA0_PLL_1P84,
VDD_PCIE0_PLL_1P8,
VDD_PCIE1_PLL_1P8,
VDD_USB_HSIC0_1P8,
VDD_ANA0_1P8,
VDD_MIPI_CSI_DIG_1P8
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NXP Semiconductors 19
Electrical characteristics
Symbol Description Mode Min Typ Max Unit Comments
VDD_HDMI_RX0_VH_RX_3P3
VDD_HDMI_TX0_DIG_3P3,
VDD_USB_OTG1_3P3,
VDD_USB_OTG2_3P3,
VDD_USB_SS3_TC_3P3
4
,
Table 8. Operating ranges1 (continued)
Power
supplies of
PHYs (3.3 V
part) and
GPIO
operating at
3.3 V only
N/A 3.00 3.30 3.60 V —
VDD_PCIE_DIG_1P8_3P3,
VDD_ENET0_1P8_3P3,
VDD_ENET_MDIO_1P8_3P3,
VDD_EMMC0_1P8_3P3,
VDD_USDHC1_1P8_3P3,
VDD_USDHC2_1P8_3P3,
Power
supplies of
GPIO
supporting
both 1.8 V or
3.3 V
VDD_USDHC_VSELECT_1P8_3P3,
VDD_SIM0_1P8_3P3,
VDD_ESAI0_MCLK_1P8_3P3,
VDD_ESAI1_SPDIF_SPI_1P8_3P3,
VDD_FLEXCAN_1P8_3P3,
VDD_LVDS_DIG_1P8_3P3,
VDD_M4_GPT_UART_1P8_3P3,
VDD_MIPI_DSI_DIG_1P8_3P3,
VDD_MLB_DIG_1P8_3P3
6
,
VDD_QSPI0_1P8_3P3,
VDD_QSPI1A_1P8_3P3,
VDD_SPI_SAI_1P8_3P3
VDD_ENET1_1P8_2P5_3P3 Power
supplies of
ethernet I/Os
VDD_USB_HSIC0_1P2 Power supply
of USB-HSIC
I/Os
1.8 V 1.65 1.80 1.95 V When VDD_USDHC1_1P8_3P3
3.3 V 3.00 3.30 3.60 V
or VDD_USDHC2_1P8_3P3 is
used to support an SD card then
it shall be on a dedicated
1.8V/3.3V regulator.
When VDD_SIM0_1P8_3P3 is
used to support a SIM card, it
shall be on a dedicated 1.8V/3.3V
regulator.
VDDs of this list targeting 1.8V
can share 1.8V regulator of 1.8V
only VDDs
VDDs of this list targeting 3.3V
can share 3.3V regulator of 3.3V
only VDDs
1.8 V 1.65 1.80 1.95 V —
2.5 V 2.38 2.50 2.63 V —
3.3 V 3.00 3.30 3.60 V —
N/A 1.1 1.2 1.3 V —
VDD_SNVS_4P2 Power supply
of SNVS
Output of embedded LDOs and negative charge pump
VDD_USB_SS3_LDO_1P0_CAP,
VDD_HDMI_RX0_LDO0_1P0_CAP
,
VDD_HDMI_RX0_LDO1_1P0_CAP
1.0 V output of
4
embedded
LDOs
4
, VDD_HDMI_TX0_LDO_1P0_CAP,
VDD_PCIE_LDO_1P0_CAP
VDD_SNVS_LDO_1P8_CAP 1.8 V output of
SNVS
embedded
LDO
i.MX 8QuadMax Automotive and Infotainment Applications Processors, Rev. 1, 12/2020
N/A 2.80 3.30 4.20 V It can be supplied by a backup
battery: a coin cell or a super cap.
N/A — 1.00 — V —
N/A — 1.80 — V —
NXP Semiconductors20
Electrical characteristics
Table 8. Operating ranges1 (continued)
Symbol Description Mode Min Typ Max Unit Comments
VDD_M1P8 _CAP -1.8 V output
of embedded
charge pump
Power supplies that shall be connected to output of an embedded LDO
VDD_HDMI_TX0_1P0 — N/A — 1.00 — V Shall be externally connected to
4
VDD_PCIE_SATA0_1P0
VDD_PCIE0_1P0, VDD_PCIE1_1P0
VDD_USB_OTG1_1P0,
VDD_USB_OTG2_1P0
Junction temperature — — -40 125
1
Voltage ranges are defined to group as many supplies as possible. Some supplies may have a wider range than listed here.
2
These are the supported frequencies included in the Linux, Android, and all other operating systems using the SCU defined
DVFS (Dynamic Voltage and Frequency Scaling) set points. An additional Overdrive set point is included to provide a more
balanced power-versus-performance trade-off, where the A72 runs at 1.3 GHz and the A53 runs at 1.1 GHz. Likewise, an
additional Nominal set point is included where both the A72 and A53 run at 600 MHz.
3
During low power state, this voltage can be dropped to 0.8 V +/- 3% for retention.
4
HDMI-RX is not currently supported, the related power and signal connections are provided for future use when it is expected
HDMI-RX support will be enabled.
5
MLB is not supported on this product. This MLB power rail may be tied to the power supply voltage indicated or may be
terminated, per the Hardware Developer’s Guide power supplies of unused functions.
6
MLB is not supported on this product. The MLB power rail must be tied to the power supply voltage indicated if other I/O
functions are used, as determined by IOMUX selection. Alternately, terminate the MLB supply per the Hardware Developer’s
Guide power supplies of unused functions.
,
— N/A — 1.00 — V Shall be externally connected to
— N/A — 1.00 — V Shall be externally connected to
N/A — -1.80 — V —
VDD_HDMI_TX0_LDO_1P0_CA
P
VDD_PCIE_LDO_1P0_CAP
VDD_USB_SS3_LDO_1P0_CA
P
Junction temperature
°C—
4.1.4 External clock sources
Each processor has two external input system clocks: a low frequency (RTC_XTALI) and a high frequency
(XTALI).
The RTC_XTALI is used for real time functions. It supplies the clock for real time clock operation and for
slow-system and watchdog counters. The clock input can be connected to either an external oscillator or a
crystal using the internal oscillator amplifier.
The system clock input XTALI is used to generate the main system clock. It supplies the PLLs and other
peripherals. The system clock input requires a crystal using the internal oscillator amplifier.
The PCIe oscillator can be sourced internally or input to the chip. In both cases, it is a 100 MHz nominal
clock using HCSL signaling to provide the PCIe reference clock.
i.MX 8QuadMax Automotive and Infotainment Applications Processors, Rev. 1, 12/2020
NXP Semiconductors 21
Electrical characteristics
The following table shows the interface frequency requirements.
Table 9. External Input Clock Frequency
Parameter Description Symbol Min Typ Max Unit
RTC_XTALI Oscillator
XTALI Oscillator
PCIe oscillator
Frequency accuracy — — — ±300 ppm
1
External oscillator or a crystal with internal oscillator amplifier.
2
The required frequency stability of this clock source is application dependent. For recommendations, see the hardware
development guide for this device.
3
Recommended nominal frequency 32.768 kHz.
4
Fundamental frequency crystal with internal oscillator amplifier.
5
If using an external clock instead of the internal clock source, an HCSL-compatible clock is required. Concerning EMI/EMC,
note that internal source is not spread-spectrum capable.
1,2
4,2
5
f
f
f
100M
ckil
xtal
— 32.7683/32.0
—24—MHz
—100—MHz
—kHz
The typical values shown in Table 9 are required for use with NXP board support packages (BSPs) to
ensure precise time keeping and USB and HDMI operations.
4.1.5 Maximum Supply Currents
NOTE
Some of the numbers shown in this table are based on the companion
regulator limits and not actual use cases. Work is in progress to provide use
case–based numbers in future data sheet releases.
Table 10. Maximum supply currents
Symbol Value Unit Comments
VDD_A72 5000 mA Value based on max current delivered by PMIC
VDD_A53 2500 mA Value based on max current delivered by PMIC
VDD_GPU0 5000 mA Value based on max current delivered by PMIC
VDD_GPU1 5000 mA Value based on max current delivered by PMIC
VDD_MAIN 5000 mA Value based on max current delivered by PMIC
VDD_MEMC 3200 mA Value based on max current delivered by PMIC
VDD_DDR_CH0_VDDQ 800 mA Does not include current used by external memory.
VDD_DDR_CH0_VDDQ_CKE 200 mA Does not include current used by external memory.
VDD_DDR_CH0_VDDA_PLL_1P8 20 mA
VDD_DDR_CH1_VDDQ 800 mA Does not include current used by external memory.
i.MX 8QuadMax Automotive and Infotainment Applications Processors, Rev. 1, 12/2020
NXP Semiconductors22
Electrical characteristics
Table 10. Maximum supply currents (continued)
Symbol Value Unit Comments
VDD_DDR_CH1_VDDQ_CKE 200 mA Does not include current used by external memory.
VDD_DDR_CH1_VDDA_PLL_1P8 20 mA
VDD_SCU_ANA_1P8 5 mA
VDD_SCU_1P8 20 mA Digital I/Os of SCU
VDD_CP_1P8 60 ma There is a peak current of 60mA over 140 μs.
VDD_SCU_XTAL_1P8 10 mA Supply of crystal oscillator and integrated 200 MHz oscillator
VDD_ANA0_1P8 175 mA
VDD_ANA1_1P8 45 mA
VDD_ANA2_1P8 140 mA
VDD_ANA3_1P8 110 mA
VDD_SIM0_1P8_3P3 15 mA
VDD_M4_GPT_UART_1P8_3P3 45 mA
VDD_ESAI1_SPDIF_SPI_1P8_3P3 40 mA
VDD_ESAI0_MCLK_1P8_3P3 25 mA
VDD_SPI_SAI_1P8_3P3 35 mA
VDD_FLEXCAN_1P8_3P3 15 mA
VDD_QSPI1A_1P8_3P3 20 mA
VDD_QSPI0_1P8_3P3 35 mA
VDD_EMMC0_1P8_3P3 55 mA
VDD_USDHC_VSELECT_1P8_3P3 5 mA
VDD_USDHC1_1P8_3P3 55 mA
VDD_USDHC2_1P8_3P3 35 mA
VDD_ENET_MDIO_1P8_3P3 15 mA
VDD_ENET0_1P8_3P3 25 mA
VDD_ENET1_1P8_2P5_3P3 25 mA
VDD_LVDS_DIG_1P8_3P3 25 mA
VDD_LVDSx_1P8 100 mA x is 0 or 1
VDD_LVDSx_1P0 5 mA x is 0 or 1
VDD_MIPI_DSI_DIG_1P8_3P3 20 mA
VDD_MIPI_DSIx_1P8 5 mA x is 0 or 1
VDD_MIPI_DSIx_1P0 35 mA x is 0 or 1
VDD_MIPI_DSIx_PLL_1P0 5 mA x is 0 or 1
VDD_MIPI_CSI_DIG_1P8 20 mA
i.MX 8QuadMax Automotive and Infotainment Applications Processors, Rev. 1, 12/2020
NXP Semiconductors 23
Electrical characteristics
Table 10. Maximum supply currents (continued)
Symbol Value Unit Comments
VDD_MIPI_CSIx_1P8 5 mA x is 0 or 1
VDD_MIPI_CSIx_1P0 20 mA x is 0 or 1
VDD_HDMI_TX0_DIG_3P3 5 mA
VDD_HDMI_TX0_1P8 80 mA
VDD_HDMI_TX0_1P0 80 mA Shall be externally connected to VDD_HDMI_TX0_LDO_1P0_CAP
VDD_ADC_1P8 5 mA
VDD_ADC_DIG_1P8 1 mA
VDD_MLB_DIG_1P8_3P3
VDD_MLB_1P8
2
1
VDD_USB_OTG1_1P0 1 mA Shall be externally connected to VDD_USB_SS3_LDO_1P0_CAP
VDD_USB_OTG1_3P3 30 mA
VDD_USB_OTG2_1P0 35 mA Shall be externally connected to VDD_USB_SS3_LDO_1P0_CAP
VDD_USB_OTG2_3P3 10 mA
10 mA
50 mA
VDD_USB_SS3_TC_3P3 10 mA
VDD_USB_HSIC0_1P2 10 mA
VDD_USB_HSIC0_1P8 5 mA
VDD_PCIE_DIG_1P8_3P3 5 mA
VDD_PCIE_IOB_1P8 45 mA
VDD_PCIE_LDO_1P8 190 mA
VDD_PCIE_SATA0_PLL_1P8 20 mA
VDD_PCIE0_PLL_1P8 20 mA
VDD_PCIE1_PLL_1P8 20 mA
VDD_PCIE_SATA0_1P0 65 mA Shall be externally connected to VDD_PCIE_LDO_1P0_CAP
VDD_PCIE0_1P0 65 mA Shall be externally connected to VDD_PCIE_LDO_1P0_CAP
VDD_PCIE1_1P0 60 mA Shall be externally connected to VDD_PCIE_LDO_1P0_CAP
VDD_SNVS_4P2
1
MLB is not supported on this product. This MLB power rail must be tied to the voltage specified in Ta b le 8 if other I/O functions
3
5 mA Start-up current
are used, as determined by IOMUX selection. Alternately, terminate the MLB supply per the Hardware Developer’s Guide
power supplies of unused functions.
2
MLB is not supported on this product. The MLB power rail must be tied to the voltage specified in Ta b le 8 or may be terminated,
per the Hardware Developer’s Guide power supplies of unused tables.
3
Under normal operating conditions, the maximum current on VDD_SNVS_4P2 is shown Table 11. During initial power on,
VDD_SNVS_4P2 can draw up to 5 mA if the supply is capable of sourcing that current. If less than 5 mA is available, the
VDD_SNVS_LDO_1P8_CAP charge time will increase.
i.MX 8QuadMax Automotive and Infotainment Applications Processors, Rev. 1, 12/2020
NXP Semiconductors24
Electrical characteristics
4.1.6 Low power mode supply currents
The following table shows the current core consumption (not including I/O) in selected low power modes.
Table 11. i.MX 8QuadMax Key State (KSx) power consumption
Mode Test conditions Supply Max Unit
KS0 SNVS only, all other supplies OFF. RTC running,
tamper not active, external 32K crystal.
1
KS1
RAM and IO state retained.
DRAM in self-refresh, associated I/O’s OFF.
32K running, 24M, PLLs and ring oscillators OFF
PHYs are in idle state.
MEMC, A53, A72, and GPU supplies OFF.
2
dropped to 0.8 V.
MAIN
3
KS4
Leakage test, not intended as a customer use case.
Overdrive conditions set, memories active, all
sub-systems powered ON.
Active power minimized.
VDD_SNVS_4P2 (4.2 V) 50 μA
VDD_ANAx_1P8, VDD_SCUx_1P8,
6mA
VDD_CP_1P8 (1.7V)
VDD_A35 (OFF) — mA
VDD_A72 (OFF) — mA
VDD_GPU0 (OFF) — mA
VDD_GPU1 (OFF) — mA
VDD_MEMC (OFF) — mA
VDD_DDR_CHx_VDDQ (1.1V) 1.4 mA
VDD_MAIN (0.8V) 12 mA
Total 21.94 mW
VDD_A53 (1.1V) 1066 mA
VDD_A72 (1.1V) 2000 mA
VDD_GPU0 (1.1V) 2000 mA
VDD_GPU1 (1.1V) 2000 mA
VDD_MEMC (1.1V) 1800 mA
VDD_MAIN (1.0V) 1500 mA
Total 11252.6 mW
1
Maximum values are for 25 °C T
2
0.8 V nominal—voltage specification under this case is ± 3%.
3
Maximum values are for 125 °C T
.
ambient
. Stated supply voltages do not exceed +2% during test.
junction
i.MX 8QuadMax Automotive and Infotainment Applications Processors, Rev. 1, 12/2020
NXP Semiconductors 25
Electrical characteristics
4.1.7 USB 2.0 PHY typical current consumption in Power-Down mode
In power down mode, everything is powered down, including the VBUS valid detectors, typical condition.
The following table shows the USB interface typical current consumption in Power-Down mode.
Table 12. USB 2.0 PHY typical current consumption in Power-Down Mode
VDD_USB_OTG1_3P3 (3.3 V) VDD_ANA0_1P8 (1.8 V) VDD_USB_OTG1_1P0 (1.0 V)
Current 1 μA0.06 μA0.5 μA
4.1.8 USB 3.0 PHY typical current consumption in Power-Down mode
In power down mode, everything is powered down, including the VBUS valid detectors, typical condition.
The following table shows the USB interface typical current consumption in Power-Down mode.
Table 13. USB 3.0 PHY typical current consumption in Power-Down Mode
— VDD_ANA0_1P8 (1.8 V) VDD_USB_OTG2_1P0 (1.0 V)
Current — 10 μA 70 μA
The following table shows the current consumption for the USB 2.0 PHY embedded in the USB 3.0
PHY.
Table 14. Typical current consumption in Power-Down mode for USB 2.0 PHY embedded in USB 3.0 PHY
VDD_USB_OTG2_3P3 (3.3 V) VDD_ANA0_1P8 (1.8 V) VDD_USB_OTG2_1P0 (1.0 V)
Current—Host mode 22.6 μA 12.7 μΑ 81.5 μΑ
Current—Device mode 12.6 μΑ 85.7 μΑ 78.5 μΑ
4.1.8.1 USB 3.0 Type-C connector considerations
The device supports USB 3.0 Type-C connection when used in conjunction with the following devices:
• PTN36043
• PTN5150A
• NX5P3090UK
NXP supports many other configurations and implementations for USB 3.0 Type-C connections. See NXP
USB Type-C: True Plug’n Play .
i.MX 8QuadMax Automotive and Infotainment Applications Processors, Rev. 1, 12/2020
NXP Semiconductors26
Electrical characteristics
4.2 Power supplies requirements and restrictions
The system design must comply with power-up sequence, power-down sequence, and steady state
guidelines as described in this section to ensure the reliable operation of the device. Any deviation from
these sequences may result in the following situations:
• Excessive current during power-up phase
• Prevention of the device from booting
• Irreversible damage to the processor
4.2.1 Power-up sequence
The device has the following power-up sequence requirements:
• Supply group 0 (SNVS) must be powered first. It is expected that group 0 will typically remain
always on after the first power-on.
• Supply group 1 (MAIN and SCU) and group 0 must both be powered to their nominal values prior
to boot. They must power up after or simultaneously with group 0.
• Supply group 2 (I/O’s and DDR interface) consists of those modules required to start the boot
process by accessing external storage devices. These must be fully powered prior to POR release
if booting from one of these supplies interfaces. They must power up after or simultaneously with
group 1.
• Supply group 3 consists of the remaining portions of the SoC. This includes nonboot I/O voltages
and supplies for the major computational units. These can be sequenced in any order and as
required to perform the desired functions for the intended application. They must power up after
or simultaneously with group 2.
NOTE
The definition of “power-up” refers to a stable voltage operating within the
range defined in Table 8. This should be taken into consideration, along
with the different capacitive loading on each rail, if considering
simultaneous switch-on of the different supply groups.
4.2.2 Power-down sequence
The device processor has the following power-down sequence requirements:
• Supply group 0 must be turned off last, after all other supplies.
• Supply group 1 can be turned off just prior to group 0.
All remaining supplies can be turned off prior to group 1.
NOTE
When switching off supply group 0 (SNVS), VDD_SNVS_LDO_1P8_CAP
must be fully discharged to 0 V before starting the next power-up sequence
to ensure correct operation.
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NXP Semiconductors 27
Electrical characteristics
4.2.3 Power Supplies Usage
The following table shows the power supplies usage by group.
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NXP Semiconductors28
NXP Semiconductors 29
Table 15. Power supplies usage
Supply
Groups
Group 0 2.4 - 4.2v
i.MX 8QuadMax Automotive and Infotainment Applications Processors, Rev. 1, 12/2020
Group 1 1.0v 1.8v
Group 2 1.1V 1.8v 1.8v or 3.3v 1.8v or 3.3v switchable 3.3v
Group 3 1.1 - 1.1v 1.0v internal LDO's 1.2v 1.8v or 2.5v or 3.3v
1
MLB is not supported on this product. This MLB power rail must be tied to the voltage specified in Ta bl e 8 if other I/O functions are used as determined by
VDD_SNVS_4P2
VDD_MAIN VDD_ANA1_1P8
VDD_LVDSx_1P0 VDD_ANA2_1P8
VDD_MIPI_CSIx_1P0 VDD_ANA3_1P8
VDD_MIPI_DSIx_1P0 VDD_CP_1P8
VDD_MIPI_DSIx_PLL_1P0 VDD_SCU_1P8
VDD_SCU_x_1P8
VDD_MEMC VDD_ADC_DIG_1P8 VDD_EMMC0_1P8_3P3 VDD_USDHCx_1P8_3P3 VDD_HDMI_RX0_VH_RX_3P3
VDD_DDR_CHx_VDDQ VDD_ADC_1P8 VDD_ESAI0_MCLK_1P8_3P3 VDD_SIM0_1P8_3P3 VDD_HDMI_TX0_DIG_3P3
VDD_DDR_CHx_VDDQ_CKE VDD_ANA0_1P8 VDD_ESAI1_SPDIF_SPI_1P8_3P3 VDD_USB_OTGx_3P3
VDD_DDR_CHx_VDDA_PLL_1P8 VDD_FLEXCAN_1P8_3P3 VDD_USB_SS3_TC_3P3
VDD_HDMI_x_1P8 VDD_LVDS_DIG_1P8_3P3
VDD_LVDSx_1P8 VDD_M4_GPT_UART_1P8_3P3
VDD_MIPI_CSI_DIG_1P8 VDD_MIPI_DSI_DIG_1P8_3P3
VDD_MIPI_x_1P8 VDD_MLB_DIG_1P8_3P3
VDD_MLB_1P8
VDD_PCIE_SATA0_PLL_1P8 VDD_QSPIx_1P8_3P3
VDD_PCIE_x_1P8 VDD_SPI_SAI_1P8_3P3
VDD_PCIEx_PLL_1P8 VDD_USDHC_VSELECT_1P8_3P3
VDD_USB_HSIC0_1P8
VDD_A53 VDD_HDMI_TX0_1P0 VDD_USB_HSIC0_1P2 VDD_ENET_MDIO_1P8_3P3
VDD_A72 VDD_PCIE_SATA0_1P0 VDD_ENET0_1P8_3P3
VDD_GPUx VDD_PCIEx_1P0
VDD_USB_OTGx_1P0
Vol tag e
1
2
VDD_PCIE_DIG_1P8_3P3
VDD_ENET1_1P8_2P5_3P3
IOMUX selection. Alternately, terminate the MLB supply, per the Hardware Developer’s Guide power supplies usage of unused features.
2
MLB is not supported on this product. The MLB power rail must be tied to the voltage specified in Table 8 or may be terminated, per the Hardware Developter’s
Guide power supplies of unused funtions.
Electrical characteristics
Electrical characteristics
4.3 PLL electrical characteristics
4.3.1 PLLs of subsystems
i.MX 8QuadMax embeds a large number of PLLs to address clocking requirements of the various
subsystems. These PLLs are controlled through the SCU and not directly by Cortex-A or Cortex-M4F
processors. A software API shall be used by those processors to access the PLL settings. Additional PLLs
are specific to high-performance interfaces. These are described in the following sections.
This table summarizes the PLLs controlled by the SCU.
Table 16. PLLs controlled by SCU
Locking range
Subsystem PLL usage Source clock
Min freq. Max freq.
Cortex-A53
Cortex-A72
CCI Subsystem 24 650 1300 1000 MHz
GPU PLL #0: subsystem 24 1250 2500 • Overdrive: 1600
DRC (DRAM
Controller)
DB (DRAM Block) Subsystem 24 650 1300 750 MHz
DBLog Subsystem 24 650 1300 800 MHz
Display Controller 0 PLL #0: subsystem 24 650 1300 800 MHz
2
3
Subsystem 24 1250 2500 • Overdrive: 2400
Subsystem 24 1250 2500 • Overdrive: 1600
PLL #1: shaders 24 1250 2500 • Overdrive: 2000
Subsystem 24 1250 2500 • LPDDR4: 1600 MHz
PLL #1: display clock #0 24 650 1300 User-configurable MHz
1
• Nominal: 1800
• Nominal: 2120
• Nominal: 1300
• Underdrive: 1600
• Nominal: 1400
• Underdrive: 1600
Lock freq. Unit
MHz
MHz
MHz
4
MHz
5
PLL #2: display clock #1 24 650 1300 User-configurable MHz
Display Controller 1 PLL #0: subsystem 24 650 1300 800 MHz
PLL #1: display clock #0 24 650 1300 User-configurable MHz
PLL #2: display clock #1 24 650 1300 User-configurable MHz
Imaging Subsystem 24 650 1300 1200 MHz
Audio PLL #0: subsystem 24 650 1300 700 MHz
PLL #1: audio PLL #0 24 650 1300 User-configurable MHz
PLL #2: audio PLL #1 24 650 1300 User-configurable MHz
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NXP Semiconductors30
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