The i.MX 7ULP product family members are optimized for powersensitive applications benefiting from NXP's Heterogeneous
Multicore Processing (HMP) architecture. Achieving an efficient
balance between processing power and deterministic processing
needs, the i.MX 7ULP is an asymmetric processor consisting of
two separate processing domains: an application domain and a
real-time domain. The application domain is built around an
ARM® Cortex®-A7 processor with an ARM NEON™ SIMD
engine and floating point unit (FPU) and is optimized for rich OS
based applications. The real-time domain is built around an ARM
Cortex-M4 processor (with FPU) optimized for lowest possible
leakage. Both domains are completely independent, with
separate power, clocking, and peripheral domains, but the bus
fabric of each domain is tightly integrated for efficient
communication. The part is streamlined to minimize pin count, enabling small packages and simple system
integration.
Simple tamper detection—
Four I2C Fast mode plusFour I2C Fast mode plus
SD 3.0/MMC 5.0FlexI/O
Four UARTs with flow controlFour UARTs with flow control
Two LPSPI peripheralsTwo LPSPI peripherals
Four 32-bit general-purpose timers with
capture and compare; one 64-bit timer
Watchdog timerWatchdog timer
Encrypt/decrypt engines (LTC)
Four 32-bit general purpose-timers with
capture and compare; one 64-bit timer
The following figure describes the part number nomenclature so users can identify the characteristics of the
specific part number.
Figure 2. i.MX 7 Family Part Number Definition
Related Resources
TypeDescription
Reference ManualThe i.MX 7ULP Applications Processor Reference Manual contains a comprehensive description of
the structure and function (operation) of the SoC.
Data SheetThe Data Sheet includes electrical characteristics and signal connections.
Chip ErrataThe chip mask set errata provides additional or corrective information for a particular device mask
set.
Package drawingPackage dimensions are provided in Package information and contact assignments
The i.MX 7ULP applications processor contains a variety of digital and analog
modules. The following table describes these modules in alphabetical order.
In the Domain column in this table:
• AD = Application Power Domain (primarily controlled by the Cortex-A7)
• RT = Real-Time Power Domain (primarily controlled by the Cortex-M4)
• VBAT = RTC/VBAT power domain Real-Time Domain
• DGO = “always-on” DGO power domain
• SYS = system-level functions that are implemented separately from the domains
listed above.
Table 1. i.MX 7ULP modules list
Block NameBlock MnemonicSubsystemPower
AMBA Network
Interconnect Crossbar
Analog PMC
Analog-to-Digital
Converter
NIC0-1DMA and Bus Fabrics ADThe AMBA Network Interconnect
Analog PMCPower ManagementSYSThe Analog PMC consists of voltage/
ADC0-1AnalogRTAnalog-to-Digital Converter (ADC) is a
Table continues on the next page...
Brief description
Domain
Crossbar (NIC) is a highly configurable
and high performance AMBA-compliant
network infrastructure which arbitrates
between multiple AXI or AHB masters to
grant access to internal or external
memories or other slave devices. It
supports connectivity between several
slave and master ports for parallel
processing. It uses a hybrid round-robin
arbitration scheme and contains
frequency converters, data width
converters, bus protocol converter, and
AXI channel buffers.
current references, core logic supply
regulators, memory supply regulators,
Back and Forward Biasing regulators,
monitors and power switches, etc. There
are two Analog PMC subsystems in i.MX
7ULP, one associated with the M4 power
domain and the other with the A7 power
domain.
12-bit resolution, successive
approximation analog to digital
converter. The ADC module supports up
to 16 single-ended external analog
inputs. It outputs 12-bit, 10-bit, or 8-bit
digital signal in right-justified unsigned
Controller (AWIC) module is capable of
interrupt detection and wake-up of a
processor when it is in low power mode.
BMEMulticore peripherals
and resource domain
control submodules
CAAMSecurityADCryptographic Acceleration and
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RTThe Bit Manipulation Engine (BME)
provides hardware support for atomic
read-modify-write memory operations to
the peripheral address space. This
architectural capability is also known as
"decorated storage" as it defines a
mechanism for providing additional
semantics for load and store operations
to memory-mapped peripherals beyond
just the reading and writing of data
values to the addressed memory
locations.
comparing two analog input voltages.
The comparator circuit is designed to
operate across the full range of the
supply voltage (rail to rail operation).
component of the Embedded Cross
Trigger (ECT), which is key in the
multicore debug strategy. The CTM
receives signals from various sources
(i.e. cores and peripherals) and
propagates or routes them to the
different debug resources of the SoC.
Those debug resources can include time
stamping capability, real-time trace,
triggers and debug interrupts.
Assurance Module (CAAM) is a
multifunction accelerator that supports
the cryptographic functions common in
many security protocols. This includes
AES128, AES256, DES, 3DES, SHA1,
SHA224, SHA256, and a random
number generator with a true entropic
seed. CAAM includes a DMA engine that
is descriptor based to reduce processoraccelerator interaction. Security feature
clear keys and memories when on-chip
security monitor detects tampering. The
Secure RAM is implemented and
provides secure storage of sensitive
information both in on-chip RAM and in
off-chip, nonvolatile memory. For details,
see the i.MX 7ULP Security ReferenceManual.
Cyclic Redundancy
Check
Debug Access PortDAPDebugRTDebug Port Access (DAP) provides
Digital PMCDigital PMCPower ManagementSYSThe Digital PMC module allows user
Digital-to-Analog
Converter
Direct Memory
Access
Direct Memory
Access Multiplexer
CRCConnectivity and
Communications
DAC0-1AnalogRTDigital-to-Analog Converter (DAC) is the
DMA0-1DMA and Bus Fabrics AD, RTDirect Memory Access (DMA) is capable
DMAMUX0-1DMA and Bus Fabrics AD, RTThe Direct Memory Access Multiplexer
Table continues on the next page...
RTThe Cyclic Redundancy Check (CRC)
module is a hardware CRC generator
circuit using 16/32-bit shift register. The
CRC module supports error detection for
all single, double, odd, and most multibits errors, programmable initial seed
value, and optional feature to transpose
input data and CRC result via transpose
register.
debugger access to on-chip system
resources via the SWJ-DP port. The
DAP provides internal system access to
A7 Debug Port, M4 Debug Port, System
Bus, JTAG controller, and SoC Control
and Status. The DAP also enables
system access to CoreSight debug
subsystem through the APBIC port.
software to control power modes of the
chip and to optimize power consumption
for the level of functionality needed.
There are two instances of Digital PMC
on this device, one for each main power
domain.
12-bit resolution digital-to-analog
converters with programmable reference
generator output. The output of the DAC
can be placed on an external pin or set
as one of the inputs to the analog
comparator or ADC. The DAC is capable
of achieving 1 ms conversion rate for
high-speed signals and 2 ms conversion
rate for low-speed signals.
of performing complex data transfers
with minimal intervention from a host
processor. Each DMA module supports
32 DMA channels. The transfer control
descriptors for each of the 32 channels
locate in system memory. DMA0 is in the
real-time domain. DMA1 is in the
application domain.
(DMAMUX) module routes DMA
sources, called slots, to any of the
ETRDebugRTThe ETR is a trace sink that redirects the
XRDCMulticore Peripherals
and Resource Domain
Control submodules
FlexBusMemories and Memory
Controllers
Brief description
Domain
supported DMA channels. DMAMUX0 is
in the real-time domain. DMAMUX1 is in
the application domain.
consists of a formatter, control, and the
trace RAM. It is a configuration of the
Trace Memory Controller (TMC). The
ETF will have a memory size of
16Kbytes. The ETF and associated
memory should be connected in the
system such that it will retain the
information though a warm or cold reset
of the system. This is to allow for debug
information to be retained for debugging
problems that may arise and cause a
reset of the system.
trace stream onto the AXI bus to external
storage. It can utilize a single contiguous
region or a scattered allocation of blocks
for a circular buffer. Reading of the AXI
based trace buffer can either be done
directly over AXI from a normal bus
master. The ETR is a configuration
option of the TMC as is the ETF.
AD, RTThe Extended Resource Domain
Controller (XRDC) provides an
integrated, scalable architectural
framework for access control, system
memory protection and peripheral
isolation. It allows software to assign
chip resources (like processor cores,
non-core bus masters, memory regions
and slave peripherals) to processing
domains, to support enforcement of
robust operational environments. The
XRDC implementation is distributed
across multiple submodules instantiated
throughout the device.
ADThe External Bus Interface (FlexBus)
module provides external memory
expansion and provides connection to
external peripherals with a parallel,
memory-mapped interface. The FlexBus
supports asynchronous and
synchronous interface to external ROM,
NOR flash, SRAM, PSRAM,
programmable logic devices and other
memory-mapped slave devices.
module is designed to monitor external
circuits, as well as the software flow.
This provides a back-up mechanism to
the internal WDOG that can reset the
system. The EWM differs from the
internal WDOG in that it does not reset
the system. The EWM, if allowed to timeout, provides an independent trigger pin
that when asserted resets or places an
external circuit into a safe mode.
SYSThe Fast Internal Reference Clock
(FIRC) module is an internal oscillator
that can generate a reference clock in
the range from 48 MHz to 60 MHz. The
FIRC output clock is used as a reference
to the SCG module, and it is also used
as a clock option to most on-chip
modules.
SYSThe Fixed-frequency PLL is the same as
the USB PLL. In addition to the main
clock output, this PLL also includes 4
Phase Fractional Dividers (PFDs) that
can generate other clock frequencies.
There is one instance of the Fixed-freq
PLL (PLL0) provides clocks for M4 core
and buses and peripherals in the Realtime domains.
AD, RTThe Flexible Input/Output (FlexIO)
module is capable of supporting a wide
range of protocols including, but not
limited to: UART, I2C, SPI, I2S, camera
interface, display interface, PWM
waveform generation, etc. FlexIO0 is in
the real-time domain. FlexIO1 is in the
application domain.
SYSThe Fractional-N (Frac-N) PLL can
generate an output clock of 528 MHz
from a supported reference clock. In
addition to the main clock output, this
PLL also includes up to 4 Phase
Fractional Dividers (PFDs) that can
generate other clock frequencies. This
PLL also supports tunable clock for
audio applications.
Processing Core (CPC) GPU. It supports
user interface rendering and performs
functions like blending, filtering, rotation,
GPU-3DMultimediaADi.MX 7ULP integrates the Vivante
Multicore Peripherals
SEMA42_1
IOMUXC0-1 &
IOMUXC_DDR
IRC1KClock Sources and
JTAGCDebugRTJoint Test Action Group Controller
LCDIFMultimediaADThe LCDIF is a general purpose display
and Resource Domain
Control submodules
System ControlAD, RTThe Input/Output Multiplexing Controller
Control
Table continues on the next page...
Brief description
Domain
overlay, resizing, transparency, and
other dynamic effects.
GC7000 Nano Ultra Graphic Processing
Unit (GPU-3D). supporting OpenGL
ES2.0/1.1, Desktop OpenGL 2.1,
OpenVG1.1, and GLSL shading
language support.
AD, RTThe Hardware Semaphore (SEMA42)
module provides the hardware support
needed in multicore systems for
implementing semaphores and provide a
simple mechanism to achieve "lock/
unlock" operations via a single write
access. SEMA42_0 is in the real-time
domain. SEMA42_1 is in the application
domain.
(IOMUXC) enables the chip to share one
pad for multiple signals from different
peripheral interfaces. This pad sharing
mechanism is done by multiplexing the
pad's input and output signals. The
IOMUXC also controls the pads setting
parameters and digital filter functions of
the pad. In addition, the IOMUXC
controls input multiplexing logic for input
signals multiplexed at multiple locations.
IOMUXC0 is in the real-time domain.
IOMUXC1 and IOMUXC_DDR are in the
application domain.
SYSThe Internal Reference Clock 1kHz
(IRC1K) module is an internal oscillator
that can generate a reference clock of
1kHz. The IRC1K clock is enabled in all
modes of operation, including all low
power modes.
(JTAGC) provides the means to test chip
functionality and connectivity while
remaining transparent to system logic
when not in test mode. Testing is
performed via a boundary scan
technique, as defined in the IEEE
1149.1-2001 standard.
controller used to drive a wide range of
display devices varying in size and
capabilities. The LCDIF is used as a
LLWUSystem ControlDGOThe Low-Leakage Wake-Up Unit (LLWU)
LPI2C0-7Connectivity and
Communications
LPIT0-1TimersAD, RTLow Power Periodic Interrupt Timer
LPSPI0-3Connectivity and
Communications
LTCSecurityRTLow-power Trusted Cryptography is an
Brief description
Domain
bridge between the DSI controller and
the NIC0 crossbar.
module allows user to select up to 32
external pin sources and up to 8 internal
modules as a wakeup source from low
leakage power modes.
AD, RTThe Low Power Inter-Integrated Circuit
(LPI2C) module implements an efficient
interface to an I2C bus as a master. The
LPI2C can continue operating while the
processor is in stop mode provided an
appropriate peripheral clock is available.
This module is designed for low CPU
overhead with DMA offloading of FIFO
register accesses. LPI2C0 - LPI2C3 are
in the real-time domain. LPI2C4 LPI2C7 are in the application domain.
(LPIT) is a multichannel timer module
that can generate independent pretrigger and trigger outputs. These timer
channels can operate individually or can
be chained together. The pre-trigger and
trigger outputs can be used to trigger
other modules on the device. The LPIT
can also operate in low power modes.
LPIT0 is in the real-time domain. LPIT1
is in the application domain.
AD, RTThe Low Power Serial Peripheral
Interface (LPSPI) module implements an
efficient interface to an SPI bus as a
master and/or a slave. The LPSPI can
continue operating while the processor is
in stop mode if an appropriate peripheral
clock is available. This module is
designed for low CPU overhead with
DMA offloading of FIFO register
accesses. LPSPI0 and LPSPI1 are in the
real-time domain. LPSPI2 and LPSPI3
are in the application domain.
architecture that allows multiple
cryptographic hardware accelerator
engines to be instantiated and share
common registers. This version of LTC
supports 128-bit AES. For details, see
the i.MX 7ULP Security Reference
Low Power Universal
Asynchronous
Receiver/Transmitter
Low Power Timer
Memory-Mapped
Cryptographic
Acceleration Unit
Messaging UnitMUMulticore Peripherals
MIPI Display Serial
Interface Controller
MIPI Display Serial
Interface Physical
Layer
LPUART0-7Connectivity and
Communications
LPTMR0-1TimersDGOThe Low Power Timer (LPTMR) module
MMCAUSecurityRTMemory-Mapped Cryptographic
and Resource Domain
Control submodules
DSI ControllerMultimediaADThe MIPI Display Serial Interface
DSI PHYMultimediaADThe MIPI Display Serial Interface
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Brief description
Domain
AD, RTThe Low Power Universal Asynchronous
Receiver/Transmitter (LPUART) module
provides asynchronous, serial
communication capability with external
devices. LPUART supports non-returnto-zero (NRZ) encoding format and IrDAcompatible infrared (low-speed) SIR
format. The LPUART can continue
operating while the processor is in stop
mode if an appropriate peripheral clock
is available. This module is designed for
low CPU overhead with DMA offloading
of FIFO register accesses. LPUART0 –
LPUART3 are in the real-time domain.
LPUART4 – LPUART7 are in the
application domain.
is a 16-bit timer which operates as realtime interrupt or pulse accumulator. This
LPTMR module can remain functional
when the chip is in low power modes,
provided the reference clock to this timer
is active.
Acceleration Unit (MMCAU) is an
optimized security accelerator that
supports the cryptographic functions
common in many security protocols. This
includes DES, 3DES, AES, MD5, SHA-1,
SHA-256 algorithms via simple C calls to
optimized security functions.
RTMessaging Unit (MU) is a shared
peripheral with a 32-bit IP bus interface
and interrupt request signals to each
host processor. The MU exposes a set
of registers to each processor which
facilitate inter-processor communication
via 32-bit words, interrupts and flags.
Interrupts may be independently masked
by each processor to allow polled-mode
operation.
Controller (DSI Controller) is responsible
for serializing display data from the GPU.
Data can come from either the GPU or
the processor/DMA controller.
Physical Layer (DSI PHY) is a two-lane
interface that supports up to 1 Gbps of
data on each lane. DSI PHY includes a
(MSMC) is responsible for sequencing
the system into and out of all low power
Stop and Run modes. MSMC monitors
events to trigger transitions between
power modes, while controlling the
power, clocks, and memories of the
system to achieve the power
consumption and functionality of that
mode.
ADThe Multi Mode DDR Controller (MMDC)
is a configurable DDR controller that
provides interface to LPDDR2 or
LPDDR3 memory. The MMDC consists
of a core and PHY. The core is
responsible for communication with the
system through AXI interface, DDR
commands generation, DDR command
optimizations, and read/ write data path.
The PHY performs timing adjustment
using special calibration mechanisms to
ensure data capture margin at the
supported clock rate.
(OTFAD) module provides an advanced
hardware implementation that minimizes
any incremental cycles of latency
introduced by the decryption in the
overall external memory access time.
The OTFAD engine also includes
complete hardware support for a
standard AES key unwrap mechanism to
decrypt a key BLOB data instruction
containing the parameters needed for up
to 4 unique AES contexts.
AD, RTThe Peripheral Clock Control (PCC)
module is responsible for clock selection,
optional division and clock gating mode
for peripherals in their respected power
domain. PCC0 and PCC1 are in the realtime domain. PCC2 and PCC3 are in the
application domain.
implements reset modes and reset
functions of the chip.
Controller (OCOTP_CTRL) module
provides an interface for reading,
programming and/or overriding
identification and control information
stored in on-chip fuse elements. The
module supports electricallyprogrammable poly fuses. The
OCOTP_CTRL also provides a set of
volatile software-accessible signals
which can be used for software control of
hardware elements, not requiring nonvolatility.
Peripheral Trigger
Multiplexing
Port ControlPCTL_A-FSystem ControlAD, RTThe Port Control (PCTL) module
Quad Serial
Peripheral Interface
Rapid GeneralPurpose Input and
Output
Read-only memory
Controller
Real Time Clock
Oscillator
Single Wire OutputSWODebugRTSingle Wire Output (SWO) is a trace
(TRGMUX) TRGMUX0 is in the real-time
domain. TRGMUX1 is in the application
domain.
provides control for GPIO interrupt
function. GPIO interrupt can be
configured independently for each pin in
the 32-bit port. There is one instance of
the PCTL module for each port. PCTL_A
and PCTL_B are in the real-time domain.
PCTL_C - PCTL_F are in the application
domain.
QSPIMemories and Memory
Controllers
RGPIO2P0-1System ControlAD, RTThe Rapid General-Purpose Input and
ROMCP0/1Memories and Memory
Controllers
RTC OSCClock Sources and
Control
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RTThe Quad Serial Peripheral Interface
(QSPI) module provides an interface to
various types of serial flash memory.
The QSPI interface allows one serial
flash connection. It supports 1-bit, 4-bit
and 8-bit SPI bus width.
Output with 2 Ports (RGPIO2P) is similar
to the RGPIO module, except it has an
AHB-lite port, in addition to the IPS port,
for faster access. RGPIO2P0 is in the
real-time domain. RGPIO2P1 is in the
application domain.
AD, RTA ROM controller and boot ROM are
present in for both the A7 and M4 CPU
cores. ROMCP0 and a 64 kB ROM are
in the real-time domain. ROMCP1 and a
96 kB ROM are in the application
domain.
VBATThe Real Time Clock Oscillator (RTC
OSC) module provides the clock source
for the Real-Time Clock module. The
RTC OSC module, in conjunction with an
external crystal, generates a 32.678 kHz
reference clock for the RTC.
the on-chip trace data to a data stream
that is captured by the Trace Port
Analyzer. It is a TPIU-like device that
supports a limited subset of the full TPIU
functionality for a simple debug solution.
authenticated debug module that
implements a challenge/response
mechanism using a standard
cryptographic algorithm. This allows post
production silicon debug without
compromising security requirements.
The SJC is connected in parallel with the
JTAGC module, but it is only used for
authenticated debug.
(SNVS) module is designed to safely
hold security-related data such as
cryptographic key, time counter,
monotonic counter, and general purpose
security information. A part of the SNVS
module belongs to the VBAT domain
that has its own dedicated power supply
which is always on. This enables SNVS
to keep this data valid and continue to
increment the time counter when the
power goes down in the rest of the SoC.
SNVS includes the Real-Time Clock
(RTC) module, which provides 64-bit
monotonic counter with roll-over
protection, 32-bit seconds counter with
roll-over protection and 32-bit alarm.
SYSThe Slow Internal Reference Clock
(SIRC) module is an internal oscillator
that can generate a reference clock of 16
MHz. The SIRC output clock is used as
a reference to the SCG module, and it is
also used as a clock option to most onchip modules.
module implements full-duplex serial
interfaces with frame synchronization
such as I2S, AC97, and CODEC/DSP
interfaces.
AD, RTThe System Clock Generation (SCG)
module is responsible for clock
generation and distribution across this
device. Functions performed by the SCG
include: clock reference selection,
generation of clock used to derive
processor, system, peripheral bus and
external memory interface clocks; source
selection for peripheral clocks; and,
control of power saving clock gating
mode. SCG0 is in the real-time domain.
SCG1 is in the application domain.
System Integration
Module
System OscillatorSYS OSCClock Sources and
Tightly-Coupled
Memory
Timer/Pulse Width
Modulation
TimeStamp
Components
Timestamp timerTSTMRTimersAD, RTThe TSTMR module is a free running
SIMSystem ControlAD, RTThe System Integration Module (SIM)
provides system control and chip
configuration registers. The SIM includes
the TSTMR module.
module is a crystal oscillator. The SYS
OSC, in conjunction with an external
crystal or resonator, generates a
reference clock for this device. It also
optionally supports an external input
clock provided to EXTAL signal directly.
This RAM is tightly integrated to the M4
processor. M4 accesses this memory
with zero wait-state. There is a backdoor
port that allows M4 DMA and other bus
masters in the SoC to access this
memory.
Module (TPM) is a multichannel timer
module that supports input capture,
output compare, and the generation of
PWM signals. The counter, compare and
capture registers are clocked by an
asynchronous clock that can remain
enabled in low power modes. LPTPM0 –
LPTPM3 are in the real-time domain.
LPTPM4 – LPTPM7 are in the
application domain.
and distribute a consistent timestamp
value for multiple processors and other
blocks in a SoC.
incrementing counter that starts running
after system reset de-assertion and can
be read at any time by the software for
determining the software ticks. The
TSTMR is a 64-bit clock cycle counter. It
runs off the 1 MHz clock and resets on
every system reset. The counter only
stops when the clock to the TSTMR is
disabled.
Trace FunnelFUNLDebugRTThe Trace Funnel (FUNL) is used when
there is more than one trace source. The
Trace Funnel combines multiple trace
streams onto a single ATB bus. The
Trace Funnel includes an arbiter that
determines the priority of the ATB inputs.
Universal Serial Bus
High-Speed Inter
Chip Physical Layer
Universal Serial Bus
On-The-Go
TPIUDebugRTTrace Port Interface Unit (TPIU) acts as
a bridge between on-chip trace data, ID
distinguishable, and a TPA. It receives
ATB trace data and sends it off chip via
ARM’s standard trace interface. The
TPIU includes ATB interface, APB
interface, Formatter, Asynchronous
FIFO, Register bank, Trace out
serializer, and a pattern generator.
enables two trace sinks (TPIU and TMC)
to be wired together and receive ATB
trace data from the same trace source. It
takes incoming data from a single source
and replicates it to two master ports.
TRNGSecurityRTThe True Random Number Generator
(TRNG) module is to generate high
quality, cryptographically secure, random
data. The TRNG module is capable of
generating its own entropy using an
integrated ring oscillator. In addition, the
module’s NIST certifiable PseudoRandom Number Generator (PRNG)
provides accelerated processing of
pseudo-random data.
uSDHC0/1Memories and Memory
Controllers
HSIC-PHYConnectivity and
Communications
USB-OTGConnectivity and
Communications
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ADThe ultra Secured Digital Host Controller
(uSDHC) provides the interface between
the host system and SD, SDIO or eMMC
cards. The uSDHC acts as a bridge,
passing host bus transactions to the
cards by sending commands and
performing data accesses to/from the
cards or devices. It handles SD, SDIO
and eMMC protocol at transmission
level.
ADUSB High-Speed Inter Chip Physical
Layer (HSIC-PHY) is a complete digital
IP designed to implement USB 2.0 HSIC
connectivity interface.
ADThe Universal System Bus On-The-Go
(USB-OTG) module is a USB 2.0compliant implementation. The registers
and data structures of this USB
controller are based on the Enhanced
Host Controller Interface Specification
for Universal Serial Bus (EHCI). This
module can act as a host, a device or an
On-The-Go negotiable host/device on
the USB bus.
Universal Serial Bus
Phase Locked Loop
Universal Serial Bus
Physical Layer
Video Input UnitVIUMultimediaADThe Video Input Unit (VIU) provides a
Wakeup UnitWKPUSystem ControlADWakeup Unit (WKPU) module is capable
embedded in the USB transceiver block.
This PLL allows an exact 480 MHz to be
generated from a supported reference
clock of 24 MHz. The output of this PLL
is primarily used for PLL operation. The
USB PLL clock is also made available as
a clock source for other peripherals in
the SoC.
ADThe Universal System Bus Physical
Layer (USB-PHY) implements USB
physical layer connecting to USB host/
device systems at low-speed, full-speed,
and high-speed. USB-PHY provides a
standard UTMI interface for connection
to the USB-OTG controller.
parallel interface for digital video. The
VIU accepts various types of digital
video input on its parallel interface,
decodes it and optionally performs
processes such as down-scaling,
horizontal up-scaling, brightness and
contrast adjustment, pixel format
conversion, deinterlacing and horizontal
mirroring. The resultant video stream is
then stored to system memory for
subsequent post-processing and display.
of interrupt detection and wake-up of the
Cortex-A processor when it is in low
power mode.
keeps a watch on the system functioning
and resets it in case of its failure.
Reasons for failure include run-away
software code and the stoppage of the
system clock that in a safety critical
system can lead to serious
consequences. In such cases, the
WDOG brings the system into a safe
state of operation. The WDOG monitors
the operation of the system by expecting
periodic communication from the
software, generally known as servicing
or refreshing the WDOG. If this periodic
refreshing does not occur, the WDOG
resets the system. WDOG0 is in the realtime domain. WDOG1 and WDOG2 are
in the application domain.
RTThe XRDC Manager (MGR) submodule
coordinates all programming model
reads and writes.
AD, RTThe XRDC Master Domain Assignment
Controller (MDAC) submodule handles
resource assignments and generation of
the domain identifiers.
AD, RTThe XRDC Memory Region Controller
(MRC) submodule implements the
access controls for slave memories
based on the pre-programmed region
descriptor registers.
AD, RTThe XRDC Peripheral Access Controller
(PAC) implements the access controls
for slave peripherals based on the preprogrammed domain access control
registers.
2Clocking
2.1Introduction
This section details the clock sources, distribution and management within the i.MX
7ULP. These functions are under joint control of the System Clock Generation (SCG)
modules, Peripheral Clock Control (PCC) modules, and Core Mode Controller (CMC)
blocks.
NOTE
References in this chapter to “Core 0” or “Processor A”
correspond to the Cortex M4 core. References in this chapter
to “Core 1” or “Processor B” correspond to the Cortex A7
core.
The clocking scheme provides clear separation between M4 domain and A7 domain.
Except for a few clock sources shared between two domains, such as the System
Oscillator clock, the Slow IRC (SIRC), and the Fast IRC clock (FIRC), clock sources
and clock management are separated and contained within each domain.
M4 clock management consists of SCG0, PCC0, PCC1, and CMC0 modules.
A7 clock management consists of SCG1, PCC2, PCC3, and CMC1 modules.
2.2Clock distribution
The SCG modules generate and distribute clocks on the device. SCG functions
include:
• clock reference selection
• generation of clock used to derive processor, system, peripheral bus and external
memory interface clocks
• source selection for peripheral clocks
• control of power-saving clock-gating mode
PCC modules control clock selection, optional division and clock gating mode for
peripherals.
NOTE
• To bypass system oscillator and directly apply clock
from pin, SCG_SOSCCFG[EREFS] should be set to 0.
The direct clock should be applied on the EXTAL pin.
• For using oscillator reference,
SCG_SOSCCSR[SOSCEN] and
SCG_SOSCCFG[EREFS] should both be set to 1.
2.3
External clock sources
In normal functional mode, this device operates off two primary external reference
clocks: System oscillator clock (SOSC) and RTC oscillator clock (ROSC):
• System oscillator clock is a high frequency reference clock with a frequency in
the range of 16 MHz to 32 MHz. This clock is used as a reference clock to the onchip PLLs which generate all the required high frequency clocks.
• RTC oscillator clock is the 32.768 kHz constant frequency, real-time clock.
The system oscillator, in conjunction with an external crystal or resonator, generates a
reference clock for the device. The system oscillator module supports 16-32 MHz
crystals or resonators. It also provides the option for an external input clock to EXTAL
signal directly.
The RTC oscillator is in the VBAT domain. The RTC oscillator module, in conjunction
with an external crystal, generates a 32.768 kHz real-time reference clock for the RTC
and will always be enabled and supplying clock to SRTC. This is the default clock
source.
2.5
Internal clock sources
This device is capable of generating these internal reference clocks:
• The FIRC is the fast IRC clock with nominal frequency in the range from 48 to 60
MHz. In addition, the FIRC provides a clock selection option for peripherals.
• The SIRC is the slow IRC clock with nominal frequency of 16 MHz. The SIRC
provides a clock selection option for peripherals.
• The IRC1K generates 1 kHz clock that is enabled in all modes of operation,
including all low power modes.
• The RTC OSC has the capability to provide nominal 32 kHz (not recommended for
accurate clock and normal operation) IRC in absence of the external OSC reference
clock if the VBAT domain is enabled.
NOTE
The internal oscillator is automatically multiplexed in the
clocking system when the system detects a loss of clock. The
internal oscillator will provide clocks to the same on-chip
modules as the external 32 kHz oscillator. The internal
oscillator is not precise relative to a crystal. While it will
provide a clock to the system, it generally will not be precise
enough for long-term time keeping. The internal oscillator is
anticipated to be useful for quicker start-up times and
tampering prevention, but should not be used as the exclusive
source for the 32 kHz clocks. An external 32 kHz clock
source must be used for production systems.
The application domain is built around an ARM Cortex-A7 processor optimized to
run nominally at 500 MHz, supported by a 32 KB L1 instruction and data cache, a
large L2 cache, and an LPDDR2/LPDDR3 memory interface. The Cortex-A7
processor is a high-performance low-power processor that implements the ARMv7-A
architecture. It uses the generic interrupt controller (GIC), generic 64-bit OS timer,
FPU and the ARM NEON SIMD engine. Additionally, all the optional debug features
are included.
3.1
Memory system—application domain
3.1.1Internal memory (application domain)
3.1.2Multi Mode DDR Controller (MMDC)
The Multi Mode DDR Controller is a dedicated interface to LPDDR2/LPDDR3
SDRAM.
The i.MX 7ULP MMDC is compatible with the following JEDEC-compliant memory
types:
• LPDDR2 SDRAM compliant to JESD209-2F LPDDR2 JEDEC standard released
June, 2013
• LPDDR3 SDRAM compliant to JESD209-3C JEDEC standard released August,
2015
MMDC operation with the standards stated above is contingent upon the board DDR
design adherence to the DDR design and layout requirements stated in the HardwareDevelopment Guide for the i.MX 7ULP Applications Processor (IMX7ULPHDG).
NOTE
For more information on MMDC, please refer to the
following Engineering Bulletin: EB00913 - LPDDR2/
LPDDR3 Parameter Optimizations for i.MX 7ULP.
Clock frequencyup to 380.16 MHz
Bus widthx16/x32
ChannelSingle
Chip selectUp to two
3.1.3eMMC
eMMC is a managed NAND device.
See Ultra-high-speed SD/SDIO/MMC host interface (uSDHC) AC timing—application
domain.
3.2
Peripherals—application domain
3.2.1Graphics processor human machine interfaces
The i.MX 7ULP Application Domain implements the following graphics processor
human machine interfaces:
• 3D graphics processing unit (GPU-3D)
• 2D graphics processing unit (GPU-2D)
• MIPI Display Serial Interface Controller (MIPI DSI)
• Video Interface Unit (VIU)
See the i.MX 7ULP modules list for more details.
3.2.2
3.2.2.1True Random Number Generator (TRNG)
The TRNG module is used to generate high quality, cryptographically secure, random
data. The TRNG module is capable of generating its own entropy using an integrated
ring oscillator. In addition, the module’s Pseudo-Random Number Generator (PRNG)
provides accelerated processing of pseudo-random data.
The RTC module provides 64-bit monotonic counter with roll-over protection, 32-bit
seconds counter with roll-over protection and 32-bit alarm. This timer module is
extremely low power that allows it to operate on a backup power supply when the
main power supply is cut off. The RTC remains functional in all low power modes
and can generate an interrupt to exit any low power mode.
3.2.2.3High Assurance Boot (HAB)
The High Assurance Boot (HAB) component of the ROM protects against the
potential threat of attackers modifying areas of code or data in programmable memory
to make it behave in an incorrect manner. The HAB also prevents attempts to gain
access to features which should not be available.
The integration of the HAB feature with the ROM code ensures that the chip does not
enter an operational state if the existing hardware security blocks have detected a
condition that may be a security threat or areas of memory deemed to be important
have been modified. The HAB uses RSA digital signatures to enforce these policies.
Figure 3. Secure Boot Components
NXP provides a reference Code Signing Tool (CST) for key
generation, certificate generation and code signing for use
The real-time domain contains 256 kB of SRAM organized in sub-blocks of 32 kB
each. Each sub-block can be power-gated under software control to optimize power
consumption.
4.1.2QuadSPI flash
The Quad Serial Peripheral Interface (QSPI) module provides an interface to various
types of serial flash memory. It allows one serial flash connection and supports 1-bit,
4-bit and 8-bit SPI bus width.
4.2
Peripherals—real-time domain
4.2.1Analog—real-time domain
The i.MX 7ULP Real-Time Domain implements the following analog peripherals:
• 12-bit Analog to Digital Converter
• 12-bit Digital to Analog Converter
• Comparators
See i.MX 7ULP modules list for more details.
4.2.2
The i.MX 7ULP Real-Time Domain implements the following connectivity and
communications peripherals:
• Low Power Universal Asynchronous Receiver/Transmitter (LPUART)
• Low Power Inter-Integrated Circuit (LPI2C)
• Low Power Serial Peripheral Interface (LPSPI)
• Rapid General-Purpose Input and Output with 2 Ports (RGPIO2P)
Joint Test Action Group Controller (JTAGC) provides the means to test chip
functionality and connectivity while remaining transparent to system logic when not in
test mode. Testing is performed via a boundary scan technique, as defined in the IEEE
1149.1-2001 standard.
5.2JTAG device identification register
The device identification register (JTAG ID) allows the revision number and part
number to be read through the TAP. See the device identification register section of the
i.MX 7ULP Applications Processor Reference Manual for details. This table shows the
Part Identification Number (PIN) and the Part Revision Number (PRN) for each i.MX
7ULP silicon revision.
Table 3. JTAG device identification register information
Silicon RevisionPart Identification Number (PIN)Part Revision Number (PRN)
The contents of the JTAD ID register are also mirrored in a SIM register called
JTAG_ID_REG (address 0x410A_308C).
5.3
Oscillators and PLLs
5.3.1System oscillator (SYS OSC)
The system oscillator (SYS OSC) is a crystal oscillator. The SYS OSC, in conjunction
with an external crystal or resonator, generates a reference clock for this chip. It also
provides the option for an external input clock to EXTAL signal directly.
The RTC OSC module provides the clock source for the Real-Time Clock module.
The RTC OSC module, in conjunction with an external crystal, generates a 32.678
kHz reference clock for the RTC.
5.3.3USB PLL
The USB PLL is embedded in the USB transceiver block. This PLL allows an exact
480 MHz to be generated from a supported reference clock of 24 MHz. The output of
this PLL is primarily used for USB operations. The USB PLL clock is also made
available as a clock source for other peripherals in the SoC.
5.3.4Fixed Frequency PLL (Fixed-freq PLL)
In addition to the main clock output, this PLL also includes 4 Phase Fractional
Dividers (PFDs) that can generate other clock frequencies. There is one instance of the
Fixed-freq PLL (PLL0), which provides clocks for the M4 core, buses, and
peripherals in the real-time domain.
5.3.5
Fractional-N PLL (FracN PLL)
The Fractional-N (Frac-N) PLL can generate an output clock 528 MHz from a
supported reference clock. In addition to the main clock output, this PLL also includes
up to four Phase Fractional Dividers (PFDs) that can generate other clock frequencies.
This PLL also supports a tunable clock for audio applications.
5.4
Power Management
The i.MX 7ULP implements multiple options minimizing application power
consumption:
• On-chip power management including regulators, drivers and switches for
flexible power supplies, efficient power consumption and short wake up time
• Multiple power domains and ultra-low power modes allow flexible power saving
• Voltage and frequency scaling in dynamic operating modes
• Software-controlled clock gating for cores and peripherals
The digital PMC module allows user software to control power modes and of the chip
and to optimize power consumption for the level of functionality needed. There are two
instances of digital PMC on this chip, one for each main power domain.
5.4.2Analog power management controller (Analog PMC)
The Analog PMC consists of voltage/current references, core logic supply regulators,
memory supply regulators, back and forward biasing regulators, monitors and power
switches, etc. There are two Analog PMC subsystems, one associated with the M4
power domain and the other with the A7 power domain.
6
i.MX 7ULP LDO Bypass versus LDO-enabled modes
i.MX 7ULP has internal low-dropout (LDO) regulators to power certain sections of the
core logic. In LDO Enabled mode, the internal LDO is used to regulate the core logic
voltage under software control. In LDO Bypass mode, the internal LDO is disabled and
the core logic supply voltage is provided externally.
The Real-time domain only supports LDO Enabled mode. The Application Domain
supports either mode. The LDO modes require specific board-level connections. LDO
Bypass vs. Enabled mode must be chosen prior to board design because the physical
connection is different.
6.1
Real-time domain LDO Enabled mode
A 1.8 V nominal voltage supply is provided externally to the VDD_PMC18_DIG0
supply. The internal LDO output is routed to VDD_PMC11_DIG0_CAP.
VDD_PMC11_DIG0_CAP must be routed back to VDD_DIG0 at the board-level with
appropriate bypass capacitors to VSS. This connection has a maximum board routing
impedance requirement. See parameter RDIG0 in Table 5.
See the i.MX 7ULP Hardware Development Guide (IMX7ULPHDG) for details on the
required bypass capacitors.
A 1.2 V nominal voltage supply is provided externally to the VDD_PMC12_DIG1
supply. The internal LDO output is routed to VDD_PMC11_DIG1_CAP.
VDD_PMC11_DIG1_CAP must be routed back to VDD_DIG1 at the board-level
with appropriate bypass capacitors to VSS. This connection has a maximum board
routing impedance requirement. See parameter RDIG1 in Table 5.
See the i.MX 7ULP Hardware Development Guide (IMX7ULPHDG) for details on
the required bypass capacitors.
6.3
Application domain LDO BYPASS mode
The desired core logic supply voltage is provided externally to the
VDD_PMC12_DIG1, VDD_PMC11_DIG1_CAPand VDD_DIG1 which are all tied
together.
See the i.MX 7ULP Hardware Development Guide (IMX7ULPHDG) for details on
the required bypass capacitors.
7
System specifications
7.1Ratings
7.1.1Thermal handling ratings
SymbolDescriptionMin.Max.UnitNotes
T
STG
T
SDR
1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life.
2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for NonhermeticSolid State Surface Mount Devices.
1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for NonhermeticSolid State Surface Mount Devices.
7.1.3ESD handling ratings
SymbolDescriptionMin.Max.UnitNotes
V
V
HBM
CDM
Electrostatic discharge voltage, human body model-1000+1000V1
Electrostatic discharge voltage, charged-device
model
-250+250V2
1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing HumanBody Model (HBM).
2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method forElectrostatic-Discharge-Withstand Thresholds of Microelectronic Components.
7.1.4Absolute maximum ratings
CAUTION
Stresses beyond those listed under this table may cause
permanent damage to the device. These are stress ratings only.
Functional operation of the device at these or any other
conditions beyond those indicated under “recommended
operating conditions” is not implied. Exposure to absolutemaximum-rated conditions for extended periods may affect
device reliability.
A7 domain core and logic supply inputsVDD_PMC12_DIG1-0.31.65V
VDD_PMC11_DIG1_CAP
VDD_DIG1-0.31.155V
GPIO Port A supply inputVDD_PTA-0.33.96V
GPIO Port B supply inputVDD_PTB-0.31.98V
GPIO Port C supply inputVDD_PTC-0.33.96V
GPIO Port D supply inputVDD_PTD-0.33.96V
GPIO Port E supply inputVDD_PTE-0.33.96V
GPIO Port F supply inputVDD_PTF-0.33.96V
HSIC supply inputVDD_HSIC-0.31.98V
HSIC 1.8V pre-driver supply inputVDD18_HSIC-0.31.98V
DDR I/O supply inputVDD_DDR-0.31.98V
DDR 1.8V pre-driver supply inputVDD18_DDR-0.31.98V
MIPI DSI 1.1V supply inputVDD_DSI11-0.31.155V
MIPI DSI 1.8V supply inputVDD_DSI18-0.31.98V
USB PHY 3.3V supply inputVDD_USB33-0.33.6V
USB PHY 1.8V supply inputVDD_USB18-0.31.98V
USB0 VBUS detectionUSB0_VBUS-0.35.6V
PLL analog supply inputVDD_PLL18-0.31.98V
ADC high reference supply inputVREFH_ANA18-0.31.98V
ADC analog and IO 1.8V supply inputVDD_ANA18-0.31.98V
ADC analog and IO 3.3V supply inputVDD_ANA33-0.33.96V
1
-0.31.155V
1. When used as an input in LDO Bypass Mode
7.1.5Recommended operating conditions—system
NOTE
All supply inputs shown represent the voltage at the package
ball.
Table 5. Recommended operating conditions
SymbolDescriptionConditionsMinTypMaxUnits
SNVS (Always On) Domain Supply Voltage Requirements
STOP mode (CA7
halted and
peripherals running
at full rated speed)
PMC1_STOP[LDOVL]PMC1 STOP mode LDO
configuration requirements
STOP mode (CA7
halted and
peripherals running
at VLPR speeds)
PMC1_VLPS[LDOVL]PMC1 VLPS mode LDO
VLPS mode—011110b
configuration requirements
PMC1_LLS[LDOVL]PMC1 LLS mode LDO
LLS Mode—001011b
configuration requirements
RDIG1External board routing
———50mΩ
impedance from
VDD_PMC11_DIG1_CAP to
VDD_DIG1
15
VDD_PTA
VDD_PTB
16, 17
1
GPIO Supplies
GPIO Port A supply input—1.711.8 or 3.33.6V
GPIO Port B supply input—1.711.81.89V
VDD_PTCGPIO Port C supply input—1.711.8 or 3.33.6V
VDD_PTDGPIO Port D supply input—1.711.8 or 3.33.6V
VDD_PTEGPIO Port E supply input—1.711.8 or 3.33.6V
VDD_PTF
VDD_PLL18PLL analog supply input—1.711.81.89V
VREFH_ANA18ADC high reference supply
VREFL_ANAADC low reference supply
VDD_ANA18ADC analog and IO 1.8V
VDD_ANA33ADC analog and IO 3.3V
19
DDR I/O supply input—1.141.21.26V
—1.711.81.89V
input
8
MIPI DSI 1.1V supply input—0.81.11.155 V
20
5.05.5V
or
, 21
3.0
Analog Supplies
—1.711.81.89V
input
—000V
input
—1.711.81.89V
supply input
—1.711.8 or 3.33.6V
supply input
1. VDD_PMC18, VDD18_IOREF and VDD_PTB are connected internally and, as such, must be driven from the same
source.
2. If VDD_PMC18_DIG0 is operated at 1.8 V, it should be tied to VDD_PMC18 at the board level.
3. Note that the M4 LDO is always enabled, and the VDD_PMC11_DIG0_CAP is internally regulated. There is no LDO
bypass option. VDD_PMC0_DIG0_CAP is connected to VDD_DIG0 at the board-level. The voltage observed at
VDD_PMC18_DIG0_CAP differs from the from the programmed voltage on the internal LDO because the sense point
for the LDO is on-chip.
4. The table rows under the heading "Real Time Domain (M4 domain) PMC 0 Register Configuration Requirements" define
the required voltage operating points for each operation mode. The register configurations shown must be used.
5. FBB=+/- 0.3 V is the only supported FBB voltage level on the i.MX 7ULP. CM4 FBB voltage levels are configured in the
PMC 0 Biasing Control register (BCTRL) fields FBBPLEVEL and FBBNLEVEL
6. RBB=+/-1.0 V is the only supported RBB voltage level on the i.MX 7ULP. CM4 RBB voltage levels are configured in the
PMC 0 Biasing Control register (BCTRL) fields RBBPLEVEL and RBBNLEVEL.
7. Note that the A7 LDO can be operated in LDO-enabled mode or LDO-bypass mode. In LDO-bypass mode, the internal
LDO is disabled and the voltage supply for the internal logic in the A7 domain is provided externally to
VDD_PMC12_DIG1, VDD_PMC11_DIG1_CAP, and VDD_DIG1.
8. If the MIPI DSI is used, VDD_DSI11 must be connected to VDD_DIG1 at board level. If MIPI DSI is not used,
VDD_DSI11 can be connected to ground through a 10 KΩ resistor.
9. CA7 domain HSRUN is limited to 2190 power-on hours over the lifetime of the product. The total power-on hours
includes all CA7 power modes except VLLS mode and VBAT mode in which the CA7 domain is internally power-gated.
10. FBB=+/- 0.3 V is the only supported FBB voltage level on the i.MX 7ULP. CA7 FBB voltage levels are configured in the
PMC 1 Biasing Control register (BCTRL) fields FBBPLEVEL and FBBNLEVEL.
11. To minimize power consumption in VLPS mode, configure PMC1 register bit SRAMCTRL[SRAM_STDY] to
RETENTION mode.
12. In VLLS mode, VDD_DIG1 is internally power gated to the application domain logic. VDD_DIG1 must remain powered if
the following supplies are powered: VDD_USB18, VDD_USB33, VDD_DSI18 and VDD_DSI11. If the USB and DSI
supplies are not used/powered, VDD_DIG1 can be turned off at the board level.
13. Note that the A7 LDO can be operated in LDO-enabled mode or LDO-bypass mode. In LDO-enabled mode, the
voltage supply to the internal logic in the A7 domain is regulated by the internal LDO.
14. When using LDO-enabled mode, the voltage at the associated *_CAP ball differs from the programmed voltage
because the sense point for the LDO is on-chip.
15. To achieve minimum power consumption, VDD_PTA, VDD_PTB, VDD_PTC, VDD_PTE, and VDD_PTF must remain
powered in all modes except BAT mode.
16. VDD_PTA must be powered during a power-on reset (POR) for the SMC0 Mode register (MR) BOOTCFG field to
properly latch the boot configuration from the PTA signals (GPIO Boot mode).
17. VDD_ANA33 must be shorted to VDD_PTA at the board level.
18. VDD_PTF must be powered during a power-on reset (POR) for the SMC1 Mode register (MR) BOOTCFG field to
properly latch the boot configuration from the PTF signals (GPIO Boot mode). VDD_PTF must also remain powered
during all A7 power modes except for BAT mode.
19. VDD_DDR must remain powered while VDD18_DDR is powered.
20. The 7ULP USB PHY provides two options for reporting VBUS valid back to the USB controller:
• A programmable internal VBUS_VALID comparator (the default option), or
• An alternate VBUS_VALID_3V detector that will report VBUS valid for voltages above 3 V
USBPHY_USB1_VBUS_DETECTn[VBUSVALID_SEL] selects which option is used. If the VBUS_VALID comparator
is used, USBPHY_USB1_VBUS_DETECTn[VBUSVALID_THRESH] determines the threshold voltage for a valid
VBUS. The programmable range is 4.0V to 4.4V (default).
21. The 7ULP USB PHY provides two options for reporting VBUS valid back to the USB controller:
• A programmable internal VBUS_VALID comparator (the default option), or
• An alternate VBUS_VALID_3V detector that will report VBUS valid for voltages above 3 V.
USBPHY_USB1_VBUS_DETECTn[VBUSVALID_SEL] selects which option is used. If the VBUS_VALID_3V detector
is used, the detector voltage is not programmable.
7.1.6Estimated maximum supply currents
This table represents the estimated maximum current on the power supply rails and
should be used for power supply selection. The data below is based on design
simulation as well as measured data. Note that some of the data in the table is based
on internal companion regulator limits and not actual use cases. Maximum currents
are higher by far than the average power consumption of typical use cases.
Table 6. Estimated maximum supply currents (continued)
Power railConditionsMaximum currentsUnit
VDD_PMC12_DIG1 + VDD_DIG1 +
VDD_DSI11
VDD_PMC12_DIG11.2 V
VDD_PTA1.8 V or 3.3 VUse Maximum IO equation
VDD_PTC1.8 V or 3.3 VUse Maximum IO equation
VDD_PTD1.8 V or 3.3 VUse Maximum IO equation
VDD_PTE1.8 V or 3.3 VUse Maximum IO equation
VDD_PTF1.8 V or 3.3 VUse Maximum IO equation
VDD_DDR1.2 VUse Maximum IO equation
VDD_HSIC1.2 VUse Maximum IO equation
VDD_ANA333.3 V3µA
VDD_USB333.3 V
1.15 V
CA7 LDO Bypass Mode
CA7 500 MHz
1.15 V
CA7 LDO Bypass Mode
CA7 720 MHz
CA7 LDO Enabled Mode
CA7 500 MHz
1.2 V
CA7 LDO Enabled Mode
CA7 720 MHz
Full speed mode
350mA
504mA
350mA
504mA
2
2
2
2
2
2
2
28mA
mA
mA
mA
mA
mA
mA
mA
1. VDD_PMC18, VDD18_IOREF and VDD_PTB are connected internally and, as such, must be driven from the same
source.
2. General equation for estimated, maximum power consumption of an I/O power supply: I
Where:
N = Number of I/O pins supplied by the power line
C = Equivalent external capacitive load
V = I/O voltage
(0.5 x F) = Data change rate
In this equation, I
is in amps, C in farads, V in volts, and F in hertz.
max
= N × C × V × (0.5 × F)
max
NOTE
For additional power information, see the application
note, AN12573: i.MX 7ULP Power Consumption
Measurement.
1. When a crystal is being used with the 32 kHz oscillator, the EXTAL32 and XTAL32 pins should only be connected to
required oscillator components and must not be connected to any other devices.
7.2.1.4.232 kHz oscillator frequency specifications
Table 13. 32 kHz oscillator frequency specifications
SymbolDescriptionMin.Typ.Max.UnitNotes
f
osc_lo
t
start
v
ec_extal32
1. Proper PC board layout procedures must be followed to achieve specifications.
2. This specification is for an externally supplied clock driven to EXTAL32 and does not apply to any other clock input.
The oscillator remains enabled and XTAL32 must be left unconnected.
3. The parameter specified is a peak-to-peak value and VIH and VIL specifications do not apply. The voltage of the
applied clock must be within the range of VSS to VDD_VBAT18_CAP.
7.2.2Core, platform, and system bus clock frequency limitations
The clock ratio restrictions among the core, platform and IP bus clocks are listed as
follows:
• A7 core clock frequency is higher than A7 platform clock frequency.
• Clock ratio must be integers between A7 fast platform (NIC0) and A7 slow
platform (NIC1).
NOTE
Use A7 SPLL for core clock and A7 APLL for
DDR/NIC clocks.
• Clock ratio must be integers between A7 slow platform and A7 system IP bus.
• Clock ratio must be integers between M4 core/platform and M4 system IP bus.
• M4 slow clock must be slower and an integer division of M4 system IP bus.
• A7 Slow platform (NIC1) clock frequency should be higher than A7 System IP
bus clock (NIC1_BUS clock).
The following tables show examples of various allowable clock frequencies for the
cores, platforms, system bus, and DDR in different operating modes.
NOTE
The frequencies stated in these tables are typical
configuration and maximum frequencies in a particular
mode. However, since there are multiple clock dividers,
different clock ratios can be achieved.
The following table lists peripheral clock frequencies and the indication of platform
and IP bus clocks. Some peripherals have a local clock generator that can further
divide the clock, as required, for the desired serial rate.
1. Flexbus clock frequency is generated using SCG1_NICCCR[NIC1_DIVEXT] and SCG1_NICCSR[NIC1_DIVEXT]
fields through the CLKOUT pin
2. This is the value of pix_clk and not the ipg_clk
3. See i.MX 7ULP Security Reference Manual for complete chapter
A7 Slow
Platform
Clk
A7 System
IP Bus ClkM4Platform
Clk
M4 System
IP Bus Clk
Peripheral
Clock (MHz)
7.2.4PLL PFD output
All PLLs on i.MX 7ULP either have VCO base frequency of 480 MHz or 528 MHz.
The following tables show all the possible combination of PFD output supported for
24 MHz input clock.
1. This table indicates the maximum frequency achievable by different PFD configurations; typical frequencies will limit the
PFD Frac values to be programmed
For audio applications where the data stream is coming from a remote source, the
device has to locally tune a clock signal to match the remote system clock. The
Auxiliary PLL, which provides the clock for master audio, has synchronization logic
to support on-the-fly configuration changes. This allows the device to generate a
tunable clock for audio stream. The clock from one of the Auxiliary PLLs (PLL1) can
be divided by the post-dividers in analog and also the dividers in SCG module. The
divided tunable clock generated should meet the following requirement:
• Output center frequency of 12.288 MHz or 11.2896 MHz
• Tunable range of ± 1000 ppm
• Tunable resolution of 1 ppm
• Settling time of < 100 μsec
• RMS TIE jitter (long-term jitter) < 100 psec
• Frequency update must be smooth with no glitches
7.3
Power sequencing—system
7.3.1Power-on sequencing
The power-on sequencing requirements for the device are described in this section.
VDD_VBAT42 must be powered and stable before all other supplies begin to ramp
up.
The real-time domain supplies must be powered and stable before RESET0_B is
deasserted. The real-time domain supplies listed below may be powered on in any
order except for those indicating specific sequencing requirements.
• VDD_PMC18_DIG0 and VDD_PMC18 must be powered on together, or
VDD_PMC18 must be powered on first followed by VDD_PMC18_DIG0
The application domain supplies must be powered on and stable before the A7 core
exits reset. The M4 core controls the release of the A7 from reset. The application
domain supplies listed below may be powered on in any order except for those
indicating specific sequencing requirements.
• VDD_PMC12_DIG1
• VDD_PMC11_DIG1_CAP (if using A7 LDO bypass mode)
• VDD_DIG1 (if using A7 LDO bypass mode)
• VDD_PTC
• VDD_PTD and VDD18_IOREF must be powered together, or VDD18_IOREF
powered on first followed by VDD_PTD
• VDD_PTE
• VDD_PTF
• VDD18_DDR
• DDR_VREF0, DDR_VREF1
• VDD_HSIC
• VDD18_HSIC
• VDD_DSI11
• VDD_DSI18
• VDD_USB33
• VDD_USB18
• VDD_DDR must be powered and stable before the A7 core exits reset.
The application domain supplies must not be powered when the real-time supplies are
off.
In A7 LDO bypass mode, VDD_USB18 and VDD_DSI18 should not be powered when
VDD_DIG1 is not powered, or additional leakage current will occur.
See Table 18 for interfaces and power supplies that are not used.
7.3.2
Power-off sequencing
The i.MX 7ULP has no power-off sequencing requirements.
7.4
Requirements for unused interfaces
This table shows the required connections for unused interfaces.
DSI_DATA1_PMIPI Positive Data1 SignalLeave unconnected
Port D SignalsVDD_PTDPort D supply10 kΩ resistor to ground
USB0VDD_USB33USB0 PHY 3.3 V supply10 kΩ resistor to ground
VDD_USB18USB0 PHY 1.8 V supply10 kΩ resistor to ground
USB0_DMUSB D- Analog Data Signal on
the USB Bus
USB0_DPUSB D+ Analog Data Signal on
the USB Bus
USB0_VBUS_DETECT USB0 VBUS Detect10 kΩ resistor to ground
10 kΩ resistor to ground
10 kΩ resistor to ground
Leave unconnected
Leave unconnected
7.5Electrical Characteristics and Thermal Specifications
7.5.1AC electrical characteristics
Unless otherwise specified, propagation delays are measured from the 50% to the 50%
point, and rise and fall times are measured at the 20% and 80% points, as shown in the
following figure.
• JTAG20—20—ns
J4TCLK rise and fall times—3—3ns
J5Boundary scan input data setup time to TCLK
rise
J6Boundary scan input data hold time after TCLK
rise
J7TCLK low to boundary scan output data valid—28—28ns
J8TCLK low to boundary scan output high-Z—25—25ns
J9TMS, TDI input data setup time to TCLK rise10.5—19—ns
J10TMS, TDI input data hold time after TCLK rise2.5—2—ns
J11TCLK low to TDO data valid—19—19ns
J12TCLK low to TDO high-Z2—2—ns
J13TRST assert time100—100—ns
J14TRST setup time (negation) to TCLK high8—8—ns
Per JEDEC JESD51-2, the intent of thermal resistance
measurements is solely for a thermal performance comparison
of one package to another in a standardized environment. This
methodology is not meant to and does not predict the
performance of a package in an application-specific
environment.
Table 29. Thermal resistance data
RatingTest ConditionsSymbol14x14 mm
(VK) Package
Value
Junction to Ambient
Natural Convection
Junction to Ambient
Natural Convection
Junction to Ambient (@
200 ft/min)
Junction to Ambient (@
200 ft/min)
Junction to Board─RθJB15.624.2°C/W4
Junction to Case─RθJC11.711.4°C/W5
Junction to Package
Top
Junction to Package
Bottom
1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site
(board) temperature, ambient temperature, air flow, power dissipation of the other components on the board, and board
thermal resistance.
2. Per SEMI G38-87 and JEDEC JESD51-2 with the single layer board horizontal.
3. Per JEDEC JESD51-6 with the board horizontal.
4. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured
on the top surface of the board near the package.
5. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883).
6. Thermal characterization parameter indicating the temperature difference between package top and the junction
temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is
written as ΨJT.
Mode)
SD2Clock Low Timet
SD3Clock High Timet
SD4Clock Rise Timet
SD5Clock Fall Timet
uSDHC Output/Card Inputs SD_CMD, SDx_DATAx (Reference to CLK)
SD6uSDHC Output Delayt
uSDHC Input/Card Outputs SD_CMD, SDx_DATAx (Reference to CLK)
SD7uSDHC Input Setup Timet
SD8uSDHC Input Hold Time
4
PP
f
PP
f
PP
f
TLH
THL
OD
WL
WH
OD
ISU
t
IH
1
2
3
0400kHz
025/50MHz
020/52MHz
100400kHz
7—ns
7—ns
—3ns
—3ns
-3.33.6ns
7.5—ns
1.0—ns
1. In Low-Speed mode, card clock must be lower than 400 kHz, voltage ranges from 2.7 to 3.6 V.
2. In Normal (Full) -Speed mode for SD/SDIO card, clock frequency can be any value between 0–25 MHz. In High-speed
mode, clock frequency can be any value between 0–50 MHz.
3. In Normal (Full) -Speed mode for MMC card, clock frequency can be any value between 0–20 MHz. In High-speed
mode, clock frequency can be any value between 0–52 MHz.
4. To satisfy hold timing, the delay difference between clock input and cmd/data input must not exceed 2 ns.
8.1.2.2eMMC4.4/4.41 (dual data rate) AC timing
The following figure shows the timing of eMMC4.4/4.41, and the table lists the
eMMC4.4/4.41 timing characteristics. Note that only DATA is sampled on both edges
of the clock (not applicable to CMD).
SD1Clock Frequency Periodt
SD2Clock Low Timet
SD3Clock High Timet
uSDHC Output/Card Inputs SD_CMD, SDx_DATAx in HS200 (Reference to CLK)
SD5uSDHC Output Delayt
uSDHC Input/Card Outputs SD_CMD, SDx_DATAx in HS200 (Reference to CLK)
SD8Card Output Data Windowt
CLK
CL
CH
OD
ODW
5.0—ns
0.46 × t
0.46 × t
CLK
CLK
0.54 × t
0.54 × t
CLK
CLK
1
-1.60.74ns
0.5 x t
CLK
—ns
ns
ns
1. HS200 is for 8 bits while SDR104 is for 4 bits
8.1.2.4HS400 AC timing—eMMC5.0 only
The following figure depicts the timing of HS400, and the subsequent table lists the
HS400 timing characteristics. Be aware that only data is sampled on both edges of the
clock (not applicable to CMD). The CMD input/output timing for HS400 mode is the
same as CMD input/output timing for SDR104 mode. Check parameters SD5, SD6, and
SD7 in Table 34 for CMD input/output timing for HS400 mode.
All processor bus timings are synchronous; input setup/hold and output delay are
given in respect to the rising edge of a reference clock, FB_CLK. The FB_CLK
frequency may be the same as the internal system bus frequency or an integer divider
of that frequency.
The following timing parameters indicate when data is latched or driven onto the
external bus, relative to the Flexbus output clock (FB_CLK). All other timing
relationships can be derived from these values.
Table 35. Flexbus switching specifications
NumParameterMin.Max.UnitNotes
Frequency of operation
• HSRUN mode
• Normal RUN mode
FB1Clock period
• HSRUN mode
• Normal RUN mode
FB2Address, data, and control output valid—13.0ns1
FB3Address, data, and control output hold1.0—ns1
FB4Data input setup8.5—ns2
FB5Data input hold0.0—ns2
—
15.0
15.0
66
66
—ns
MHz
1. Specification is valid for all FB_AD[31:0], FB_BE, FB_CSn_B, FB_OE_B, FB_RW_B, FB_TBST_B, FB_TSIZ[1:0],
FB_ALE, and FB_TS_B.
The i.MX 7ULP conforms to the MIPI D-PHY electrical specifications MIPI DSI
Version 1.01 and D-PHY specification Rev. 1.0 (and also DPI version 2.0, DBI version
2.0, DSC version 1.0a at protocol layer) for MIPI display port x2 lanes.
8.1.4.2Video Input Unit timing
This section provides the timing parameters of the Video Input Unit (VIU) interface.
Figure 18. VIU Timing Parameters
Table 36. VIU Timing Parameters
SymbolCharacteristicMinMaxUnit
f
PIX_CK
t
DSU
t
DHD
VIU pixel clock frequency_66.7MHz
VIU data setup time9.0_ns
VIU data hold time1_ns
8.1.5Timer specifications—application domain
See General switching timing specifications for EWM, LPTMR, and TPM.
8.1.6
Connectivity and communications specifications—application
domain
tHD; STA4—0.6—0.26—µs
condition. After this period, the
first clock pulse is generated.
LOW period of the SCL clockt
HIGH period of the SCL clockt
Set-up time for a repeated
LOW
HIGH
tSU; STA4.7—0.6—0.26—µs
START condition
Data hold time for I2C bus
tHD; DAT0
devices
Data set-up timetSU; DAT250
Rise time of SDA and SCL
t
r
signals
Fall time of SDA and SCL
t
f
signals
Set-up time for STOP conditiontSU; STO4—0.6—0.26—µs
Bus free time between STOP
t
BUF
and START condition
Pulse width of spikes that must
t
SP
be suppressed by the input filter
0100040001000kHz
4.7—1.3—0.5—µs
4—0.6—0.26—µs
1
4
—100020
—30020
2
3.45
—100
3
0
+0.1C
+0.1C
2, 5
6
b
5
b
1
0.9
0—µs
—50—ns
30020
+0.1C
30020
+0.1C
7
b
5
b
120ns
120ns
4.7—1.3—0.5—µs
N/AN/A050050ns
1. The master mode I2C deasserts ACK of an address byte simultaneously with the falling edge of SCL. If no slaves
acknowledge this address byte, then a negative hold time can result, depending on the edge rates of the SDA and
SCL lines.
2. The maximum tHD; DAT must be met only if the device does not stretch the LOW period (tLOW) of the SCL signal.
3. Input signal Slew = 10 ns and Output Load = 50 pF
4. Set-up time in slave-transmitter mode is 1 IPBus clock period, if the TX FIFO is empty.
5. A Fast mode I2C bus device can be used in a Standard mode I2C bus system, but the requirement t
SU; DAT
≥ 250 ns
must then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If
such a device does stretch the LOW period of the SCL signal, then it must output the next data bit to the SDA line t
+ t
= 1000 + 250 = 1250 ns (according to the Standard mode I2C bus specification) before the SCL line is
SU; DAT
released.
6. Cb = total capacitance of the one bus line in pF.
7. Cb = total capacitance of the one bus line in pF.
Figure 19. Timing definition for standard, fast, and fast plus devices on the I2C bus
2
Table 38. I
ParameterSymbolMinimumMaximumUnit
SCLH Clock Frequencyf
Hold time (repeated) START condition. After this
period, the first clock pulse is generated.
LOW period of the SCLH clockt
HIGH period of the SCLH clockt
Set-up time for a repeated START conditiontSU; STA160—ns
Data hold time for I2C bus devicestHD; DAT070ns
Data set-up timetSU; DAT10—ns
Rise time of SCLH signalt
Rise time of SCLH signal after a repeated START
condition and after an acknowledge bit
Fall time of SCLH signalt
Rise time of SDAH signalt
Fall time of SDAH signalt
Set-up time for STOP conditiontSU; STO160—ns
Pulse width of spikes that must be suppressed by
the input filter
C timing (High speed mode)
SCLH
tHD; STA160—ns
LOW
HIGH
rCL
t
rCL1
fCL
rDA
fDA
t
SP
03.4MHz
160—ns
60—ns
1040ns
1080ns
1040ns
1080ns
1080ns
010ns
8.1.6.3Low Power Serial Peripheral Interface (LPSPI) switching
specifications—application domain
The Low Power Serial Peripheral Interface (LPSPI) provides a synchronous serial bus
with master and slave operations. Many of the transfer attributes are programmable.
The following tables provide timing characteristics for classic LPSPI timing modes. See
the LPSPI chapter of the chip reference manual for information about the modified
transfer formats used for communicating with slower peripheral devices.
All timing is shown with respect to 20% VDD and 80% VDD thresholds, unless noted,
as well as input signal transitions of 3 ns and a 30 pF maximum load on all LPSPI
pins.
SPSCK period:ns—
LPSPI0-166.6—
LPSPI2-340—
SPI_SS valid to SPI_SPSCK delay1—t
SPI_SPSCK to SPI_SS invalid delay1—t
Clock (SPSCK) high or low time(t
Data setup time (inputs):ns—
SU
SPSCK
/2) - 2 (t
/2) + 2ns—
SPSCK
LPSPI0-19—
LPSPI2-34.2—
Data hold time (inputs):ns—
HI
LPSPI0-16—
LPSPI2-33.9—
SPI_SPSCK to SPI_MISO data valid (output
data valid):
LPSPI0-1—20.0
LPSPI2-3—15.5
SPI_SPSCK to SPI_MISO data invalid (output
data hold):
LPSPI0-12.0—
LPSPI2-32.0—
SPI_SS active to SPI_MISO driven18.1—ns—
SPI_SS inactive to SPI_MISO not driven18—ns—
• Title: 5V Short Circuit Withstand Requirement Change
• Applies to: Universal Serial Bus Specification, Revision 2.0
• Errata for USB Revision 2.0 April 27, 2000 as of 12/7/2000
• USB ENGINEERING CHANGE NOTICE
• Title: Pull-up/Pull-down resistors
• Applies to: Universal Serial Bus Specification, Revision 2.0
• USB ENGINEERING CHANGE NOTICE
• Title: Suspend Current Limit Changes
• Applies to: Universal Serial Bus Specification, Revision 2.0
• On-The-Go and Embedded Host Supplement to the USB Revision 2.0
Specification
• Revision 2.0 plus errata and ecn June 4, 2010
• Battery Charging Specification (available from USB-IF)
• Revision 1.2, December 7, 2010
USB0_VBUS pin is a detector function which is 5v tolerant and complies with the
above specifications without needing any external voltage division components.
8.1.6.5
USB HSIC timings
This section describes the electrical information of the USB HSIC port.
NOTE
HSIC is a DDR signal. The following timing specifications
are for both rising and falling edges.
strobe period4.1664.167ns—
data output delay time04.1nsMeasured at 50% point
strobe/data rising/falling time1.2—V/nsAverage of 30% and
8.1.6.5.2USB HSIC receive timing
70% voltage levels
Figure 25. USB HSIC receive waveform
Table 42. USB HSIC receive parameters
NameParameterMinMaxUnitComment
T
T
T
T
strobe
hold
setup
slew
strobe period4.1664.167ns—
data hold time0.3—nsMeasured at 50% point
data setup time0.367—nsMeasured at 50% point
strobe/data rising/falling time1.2—V/nsAverage of 30% and 70%
voltage levels
8.1.6.6Parallel interface (ULPI interface)
Electrical characteristics and timing parameters for the parallel interface are presented
in the subsequent sections. The following table lists the parallel interface signal
definitions.
Table 43. USB signal definitions—Parallel (ULPI) interface
NameDirectionSignal description
USB_CLKInInterface clock. All interface signals are synchronous to
clock.
USB_DAT[7:0]I/OBidirectional data bus, driven low by the link during Idle. Bus
Ccompare
TUETotal unadjusted Error-14 to -2LSB3
DNLDifferential nonlinearity±1.2LSB3,4
INLIntegral nonlinearity±1.2LSB3,4
ENOBEffective number of bits5
Avg = 16—
SINADSignal to noise plus distortionSINAD=6.02 x ENOB + 1.76dB
EFSFull-scale error-4LSB3
EZSZero-scale error0.05LSB3
EILInput leakage errorRAS * IinmV
cycles
≤VREFH)
1. This resistance is external to the SoC. To achieve the best results, the analog source resistance must be kept as low
as possible. The results in this data sheet were derived from a system that had < 15 Ω analog source resistance. The
RAS/CAS time constant should be kept to < 1 ns.
2. See Sample time vs. RAS.
3. 1 LSB = (VREFH - VREFL)/2N, N=12
4. ADC conversion clock at max frequency and using linear histogram.
5. Input data used for test was 1 kHz sine wave.
Table 52. ADC electrical specifications (VREFH=1.68 V and
Table 52. ADC electrical specifications (VREFH=1.68 V and VADIN
max
(continued)
SymbolDescriptionMinTyp2MaxUnitNotes
RADINInput resistance1KΩ
RASAnalog source
resistance
fADCKADC
conversion
clock frequency
CsampleSample cycles3.5131.54
CcompareFixed compare
cycles
CconversionConversion
cycles
TUETotal
unadjusted
error
DNLDifferential
nonlinearity
INLIntegral
nonlinearity
ENOBEffective Number of Bits7
Single-ended mode
Avg = 110.3
Avg = 210.6
Avg = 1611.3
Differential mode
Avg = 111.2
Avg = 2—
Avg = 16—
SINADSignal to noise
plus distortion
EFSFull-scale error-4LSB5
EZSZero-scale error0.05LSB5
EILInput leakage
error
866MHz
17.5Cycles
Cconversion= Csample + CcompareCycles
-14 to -2LSB5
±1.2LSB5,6
±1.2LSB5,6
SINAD=6.02 x ENOB + 1.76dB
RAS * IinmV
5KΩ3
≤VDD_PTA
max
)1
1. Values in this table are based on design simulations.
2. Typical values assume VDD_ANA_18 = 1.8 V, Temp = 25 °C, fACLK = Max, unless otherwise stated. Typical values are
for reference only, and are not tested in production.
3. This resistance is external to the SoC. To achieve the best results, the analog source resistance must be kept as low as
possible. The results in this data sheet were derived from a system that had < 15 Ω analog source resistance. The
RAS/CAS time constant should be kept to < 1 ns.
4. See Sample time vs. RAS.
5. 1 LSB = (VREFH - VREFL)/2N, N=12
6. ADC conversion clock at max frequency and using linear histogram.
1. Values in this table are based on design simulations.
2. Typical values assume VDD_ANA_18 = 1.8 V, Temp = 25 °C, fACLK = Max, unless otherwise stated. Typical values are
for reference only, and are not tested in production.
3. This resistance is external to the SoC. To achieve the best results, the analog source resistance must be kept as low as
possible. The results in this data sheet were derived from a system that had < 15 Ω analog source resistance. The
RAS/CAS time constant should be kept to < 1 ns.
4. See Sample time vs. RAS.
5. 1 LSB = (VREFH - VREFL)/2N, N=12
6. ADC conversion clock at max frequency and using linear histogram.
7. Input data used for test was 1 kHz sine wave.
The following figure shows a plot of the ADC sample time versus RAS.
1. The DAC output can drive R and C loading. The user should consider both DC and dynamic application requirements.
50pF CL provides the best dynamic performance, while 100pF provides the best DC performance.
1. It is recommended to operate the DAC in the output voltage range between 0.15 V and (VDD_ANA18 - 0.15 V) for
best accuracy. Linearity of the output voltage outside this range will be affected as current load increases.
2. When VREFH_ANA18 is selected as the reference (DAC_CR[DACRFS]=1b).
3. When the internal 1.2 V source is selected as the reference (DAC_CR[DACRFS]=1b).
4. The DAC output remains within ±0.5 LSB of the final measured value for digital input code change. Noise on the
power supply can cause this performance to degrade to ±1 LSB. This parameter represents both rising edge and
falling edge settling time.
5. Time for the DAC output to transition from 10% to 90% signal amplitude (rising edge or falling edge).
6. PSRR=20*log{∆VDD_ANA18 /∆VDAC_OUT}
7. If two DACs are used and sharing the same VREFH.
1. The maximum input voltage for CMP analog inputs associated with Port A (PTA) is VDD_PTA. The maximum input
voltage for CMP analog inputs associated with Port B (PTB) is VDD_PTB.
Nominal supply50ns
5µs
20µs
-11LSB
-11LSB
9.2.3Timer specifications—real-time domain
See General switching timing specifications.
9.2.4
Connectivity and communications specifications—real-time
domain
9.2.4.1LPUART
See General switching timing specifications.
9.2.4.2
See Inter-Integrated Circuit Interface (I2C) timing.
9.2.4.3
See Low Power Serial Peripheral Interface (LPSPI) switching specifications—
This section provides the AC timing for the I2S/SAI module in master mode (clocks are
driven) and slave mode (clocks are input). All timing is given for noninverted serial
clock polarity (TCR2[BCP] is 0, RCR2[BCP] is 0) and a noninverted frame sync
(TCR4[FSP] is 0, RCR4[FSP] is 0). If the polarity of the clock and/or the frame sync
have been inverted, all the timing remains valid by inverting the bit clock signal
(BCLK) and/or the frame sync (FS) signal shown in the following figures.
Table 58. I2S/SAI master mode timing
Num.ParameterMinMaxUnit
S1I2S_MCLK cycle time20—ns
S2I2S_MCLK (as an input) pulse width high/low45%55%MCLK period
S3I2S_TX_BCLK/I2S_RX_BCLK cycle time (output)40—ns
S4I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low45%55%BCLK period
S5I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/I2S_RX_FS
output valid
S6I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/I2S_RX_FS
output invalid
S7I2S_TX_BCLK to I2S_TXD valid—15.9ns
S8I2S_TX_BCLK to I2S_TXD invalid1—ns
S9I2S_RXD/I2S_RX_FS input setup before I2S_RX_BCLK21.3—ns
S10I2S_RXD/I2S_RX_FS input hold after I2S_RX_BCLK0—ns
—7.5ns
0—ns
Figure 35. I2S/SAI timing — master modes
Table 59. I2S/SAI slave mode timing
Num.ParameterMinMaxUnit
S11I2S_TX_BCLK/I2S_RX_BCLK cycle time (input)40—ns
S12I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low (input)45%55%MCLK period
S13I2S_TX_FS/I2S_RX_FS input setup before I2S_TX_BCLK/
I2S_RX_BCLK
S14I2S_TX_FS/I2S_RX_FS input hold after I2S_TX_BCLK/
I2S_RX_BCLK
S15I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output valid—22.8ns
S16I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output invalid1—ns
S17I2S_RXD setup before I2S_RX_BCLK12—ns
S18I2S_RXD hold after I2S_RX_BCLK1—ns
S19I2S_TX_FS input assertion to I2S_TXD output valid
1
1. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear
13—ns
1—ns
—17.0ns
9.2.4.5
This section provides the operating performance for the device in VLPR, VLPW, and
VLPS modes.
Num.ParameterMinMaxUnit
S1I2S_MCLK cycle time60—ns
S2I2S_MCLK pulse width high/low45%55%MCLK period
S3I2S_TX_BCLK/I2S_RX_BCLK cycle time (output)100—ns
S4I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low45%55%BCLK period
S5I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/I2S_RX_FS
94
NXP Semiconductors
Figure 36. I2S/SAI timing — slave modes
VLPR, VLPW, and VLPS mode performance
Table 60. I2S/SAI master mode timing in VLPR, VLPW, and VLPS modes
Table 60. I2S/SAI master mode timing in VLPR, VLPW, and VLPS modes (continued)
Num.ParameterMinMaxUnit
S6I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/I2S_RX_FS
output invalid
S7I2S_TX_BCLK to I2S_TXD valid—25ns
S8I2S_TX_BCLK to I2S_TXD invalid0—ns
S9I2S_RXD/I2S_RX_FS input setup before I2S_RX_BCLK25—ns
S10I2S_RXD/I2S_RX_FS input hold after I2S_RX_BCLK0—ns
0—ns
Figure 37. I2S/SAI timing — master modes
Table 61. I2S/SAI slave mode timing in VLPR, VLPW, and VLPS modes
Num.ParameterMinMaxUnit
S11I2S_TX_BCLK/I2S_RX_BCLK cycle time (input)100—ns
S12I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low (input)45%55%MCLK period
S13I2S_TX_FS/I2S_RX_FS input setup before I2S_TX_BCLK/
I2S_RX_BCLK
S14I2S_TX_FS/I2S_RX_FS input hold after I2S_TX_BCLK/
I2S_RX_BCLK
S15I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output valid—40ns
S16I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output invalid1—ns
S17I2S_RXD setup before I2S_RX_BCLK30—ns
S18I2S_RXD hold after I2S_RX_BCLK5—ns
S19I2S_TX_FS input assertion to I2S_TXD output valid
1. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear