NXP HEF 4017BT NXP Datasheet

HEF4017B

5-stage Johnson decade counter

Rev. 8 — 18 November 2011 Product data sheet

1. General description

The HEF4017B is a 5-stage Johnson decade c ounter with ten spike-free decoded active HIGH outputs (Q0 to Q9), an active LOW carry output from the most significant flip-flop (Q

5-9), active HIGH and active LOW clock inputs (CP0, CP1) and an overriding

asynchronous master reset input (MR). The counter is advanced by either a LOW-to-H IGH trans ition a t CP0 whil e CP

a HIGH-to-LOW transition at CP When cascading counters, the Q

6, 7, 8, and 9, can be used to drive the CP0 input of the next counter. A HIGH on MR resets the counter to zero (Q0 = Q inputs (CP0, CP

Automatic counter code correction is provided by an internal circuit: following any illegal code the counter returns to a proper counting mode within 11 clock pulses.

Schmitt trigger action makes the clock inputs highly tolerant of slower rise and fall times. It operates over a recommended V

(usually ground). Unused inputs must be connected to V

2. Features and benefits

 Automatic counter correction  Tolerant of slow clock rise and fall times  Fully static operation  5 V, 10 V, and 15 V pa rametric ratings  Standardized symmetrical output characteristics  Specifie d from 40 C to +125 C  Complies with JEDEC standard JESD 13-B

1).

1 is LOW or

1 while CP0 is HIGH (see Table 3).

5-9 output, which is LOW while the counter is in states 5,

5-9 = HIGH; Q1 to Q9 = LOW) independent of the clock

power supply range of 3 V to 15 V referenced to VSS

, VSS, or another input.

3. Ordering information

Table 1. Ordering information

All types operate from

Type number Package

Name Description Version

HEF4017BP DIP16 plastic dual in-line package; 16 leads (300 mil) SOT38-4 HEF4017BT SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1

40

C to +125C

NXP Semiconductors

001aah242

DECODING AND OUTPUT CIRCUITRY

5-STAGE JOHNSON COUNTER

CP0 MR

CP1

Q12Q24Q37Q410Q51Q65Q76Q89Q9

Q5-9

001aah243

CP1

CP0

Q1 Q2 Q3

Q4 Q5 Q6 Q7 Q8 Q9 Q5-9

4. Functional diagram

Fig 1. Functional diagram

HEF4017B

5-stage Johnson decade counter

Fig 2. Logic diagram

Product data sheet Rev. 8 — 18 November 2011 2 of 18

NXP Semiconductors

Q5-9

11 12

Q8 9

MR15

CP0

CP1

Q7 6

Q5 1

Q3 7

Q2 4

Q1 2

Q0 3

001aah239

CT≥5

11 12

CT = 0

CTRDIV10/DEC

1 5

7 10

001aah240

HEF4017B

Q5 V

Q1 MR

Q0 CP0

Q2 CP1

Q6 Q5-9

Q7 Q9

Q3 Q4

001aae574

5-stage Johnson decade counter

Fig 3. Logic symbol Fig 4. IEE logic symbol

5. Pinning information

HEF4017B

Fig 5. Pin configuration

Table 2. Pin description

Symbol Pin Description

Q0 to Q9 3, 2, 4, 7, 10, 1, 5, 6, 9, 11 decoded output

Product data sheet Rev. 8 — 18 November 2011 3 of 18

5-9 12 carry output (active LOW)

1 13 clock input (HIGH-to-LOW edge-triggered)

5.1 Pinning

5.2 Pin description

8 ground supply voltage

NXP Semiconductors

HEF4017B

5-stage Johnson decade counter

Table 2. Pin description

Symbol Pin Description

CP0 14 clock input (LOW-to-HIGH edge-triggered) MR 15 master reset input V

16 supply voltage

…continued

6. Functional description

Table 3. Function table

MR CP0 CP1 Operation

HXXQ0 = Q LH counter advances L  L counter advances L L X no change L X H no change LH no change L  L no change

[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care;

 = positive-going transition;  = negative-going transition.

[1]

5-9 = H; Q1 to Q9 = L

Product data sheet Rev. 8 — 18 November 2011 4 of 18

NXP Semiconductors

001aah244

CP0 INPUT

CP1 INPUT

MR INPUT

Q0 OUTPUT

Q1 OUTPUT

Q2 OUTPUT

Q3 OUTPUT

Q4 OUTPUT

Q5 OUTPUT

Q6 OUTPUT

Q7 OUTPUT

Q8 OUTPUT

Q9 OUTPUT

Q5-9 OUTPUT

HEF4017B

5-stage Johnson decade counter

Fig 6. Timing diagram

7. Limiting values

Table 4. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol Parameter Conditions Min Max Unit

I/O

supply voltage 0.5 +18 V input clamping current VI< 0.5 V or VI>VDD + 0.5 V - 10 mA input voltage 0.5 VDD + 0.5 V output clamping current VO< 0.5 V or VO>VDD + 0.5 V - 10 mA input/output current - 10 mA

Product data sheet Rev. 8 — 18 November 2011 5 of 18

NXP Semiconductors

HEF4017B

5-stage Johnson decade counter

Table 4. Limiting values

…continued

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol Parameter Conditions Min Max Unit

stg

amb

tot

supply current - 50 mA storage temperature 65 +150 C ambient temperature 40 +125 C total power dissipation T

= 40 C to +125 C

amb

DIP16 package SO16 package

[1]

-750mW

[2]

-500mW

P power dissipation per output - 100 mW

[1] For DIP16 package: P [2] For SO16 package: P

derates linearly with 12 mW/K above 70 C.

tot

derates linearly with 8 mW/K above 70 C.

tot

8. Recommended operating conditions

Table 5. Recommended operating conditions

Symbol Parameter Conditions Min Typ Max Unit

amb

supply voltage 3 - 15 V input voltage 0 - V ambient temperature in free air 40 - +125 C

t/V input transition rise and fall rate V

= 5 V --3.75s/V

= 10 V --0.5s/V

= 15 V --0.08s/V

9. Static characteristics

Table 6. Static characteristics

= 0 V; VI = VSS or VDD unless otherwise specified.

Symbol Parameter Conditions V

HIGH-level input voltage

LOW-level input voltage

HIGH-level output voltage

LOW-level output voltage

IO < 1 A 5 V 3.5 - 3.5 - 3.5 - 3.5 - V

10 V 7.0 - 7.0 - 7.0 - 7.0 - V 15 V 11.0 - 11.0 - 11.0 - 11.0 - V

IO < 1 A 5V -1.5-1.5-1.5-1.5V

10V -3.0-3.0-3.0-3.0V 15V -4.0-4.0-4.0-4.0V

IO < 1 A; VI=VSS or V

10 V 9.95 - 9.95 - 9.95 - 9.95 - V 15 V 14.95 - 14.95 - 14.95 - 14.95 - V

IO < 1 A;

I=VSS

or V

10 V - 0.05 - 0.05 - 0.05 - 0.05 V

15 V - 0.05 - 0.05 - 0.05 - 0.05 V

= 40 C T

amb

= 25 C T

amb

= 85 C T

amb

= 125 C Unit

amb

Min Max Min Max Min Max Min Max

5 V 4.95 - 4.95 - 4.95 - 4.95 - V

5 V - 0.05 - 0.05 - 0.05 - 0.05 V

Product data sheet Rev. 8 — 18 November 2011 6 of 18

NXP Semiconductors

Table 6. Static characteristics …continued

VSS = 0 V; VI = VSS or VDD unless otherwise specified.

Symbol Parameter Conditions V

HIGH-level output current

LOW-level output current

input leakage

VO = 2.5 V 5 V - 1.7 - 1.4 - 1.1 - 1.1 mA

= 4.6 V 5 V - 0.64 - 0.5 - 0.36 - 0.36 mA

= 9.5 V 10 V - 1.6 - 1.3 - 0.9 - 0.9 mA

= 13.5 V 15 V - 4.2 - 3.4 - 2.4 - 2.4 mA

VO = 0.4 V 5 V 0.64 - 0.5 - 0.36 - 0.36 - mA

= 0.5 V 10 V 1.6 - 1.3 - 0.9 - 0.9 - mA

= 1.5 V 15 V 4.2 - 3.4 - 2.4 - 2.4 - mA

current

supply current IO = 0 A;

= VSS or V

input capacitance

15 V - 0.1 - 0.1 - 1.0 - 1.0 A

5 V - 5 - 5 - 150 - 150 A

10 V - 10 - 10 - 300 - 300 A

15 V - 20 - 20 - 600 - 600 A

----7.5----pF

HEF4017B

5-stage Johnson decade counter

= 40 C T

amb

Min Max Min Max Min Max Min Max

= 25 C T

amb

= 85 C T

amb

= 125 C Unit

amb

10. Dynamic characteristics

Table 7. Dynamic characteristics

= 25 C; VSS = 0 V; for test circuit see Figure 10

amb

Symbol Parameter Conditions V

PHL

HIGH to LOW propagation delay

CP0, CP1  Q0 toQ9; see Figure 7

CP0, CP see Figure 7

MR  Q1 to Q9; see Figure 8

1  Q5-9;

Extrapolation formula

5 V 113 ns + (0.55 ns/pF)C 10 V 44 ns + (0.23 ns/pF)C 15 V 32 ns + (0.16 ns/pF)C

5 V 118 ns + (0.55 ns/pF)C 10 V 44 ns + (0.23 ns/pF)C 15 V 32 ns + (0.16 ns/pF)C

5 V 88 ns + (0.55 ns/pF)C 10 V 39 ns + (0.23 ns/pF)C 15 V 27 ns + (0.16 ns/pF)C

[1]

Min Typ Max Unit

- 140 280 ns

-55110ns

-4080ns

- 145 290 ns

-55110ns

-4080ns

- 115 230 ns

- 50 100 ns

-3570ns

Product data sheet Rev. 8 — 18 November 2011 7 of 18

NXP Semiconductors

HEF4017B

5-stage Johnson decade counter

Table 7. Dynamic characteristics

= 25 C; VSS = 0 V; for test circuit see Figure 10

amb

…continued

Symbol Parameter Conditions V

PLH

LOW to HIGH propagation delay

CP0, CP1  Q0 toQ9; see Figure 7

CP0, CP

1  Q5-9;

see Figure 7

MR  Q

5-9;

see Figure 8

MR  Q0; see Figure 8

transition time see Figure 7 5V

hold time CP0  CP1;

see Figure 9

1  CP0;

CP see Figure 9

pulse width CP0 input LOW;

minimum width; see Figure 8

1 input HIGH;

CP minimum width; see Figure 8

MR input HIGH; minimum width; see Figure 8

rec

recovery time MR input;

see Figure 8

max

maximum

see Figure 8 5V 6 12 - MHz

frequency

Extrapolation formula

5 V 98 ns + (0.55 ns/pF)C 10 V 39 ns + (0.23 ns/pF)C 15 V 32 ns + (0.16 ns/pF)C

5 V 83 ns + (0.55 ns/pF)C 10 V 34 ns + (0.23 ns/pF)C 15 V 27 ns + (0.16 ns/pF)C

5 V 103 ns + (0.55 ns/pF)C 10 V 44 ns + (0.23 ns/pF)C 15 V 32 ns + (0.16 ns/pF)C

[2]

10 ns + (1.00 ns/pF)C 10 V 9 ns + (0.42 ns/pF)C 15 V 6 ns + (0.28 ns/pF)C

[1]

Min Typ Max Unit

- 125 250 ns

- 50 100 ns

-4080ns

- 125 250 ns

- 50 100 ns

-4080ns

- 110 220 ns

-4590ns

-3570ns

- 130 260 ns

- 55 105 ns

-4075ns

- 60 120 ns

-3060ns

-2040ns

5 V 90 45 - ns 10 V 40 20 - ns 15 V 20 10 - ns

5 V 80 40 - ns 10 V 40 20 - ns 15 V 30 10 - ns

5 V 80 40 - ns 10 V 40 20 - ns 15 V 30 15 - ns

5 V 50 25 - ns 10 V 30 15 - ns 15 V 20 10 - ns

5 V 60 30 - ns 10 V 30 15 - ns 15 V 20 10 - ns

10 V 12 30 - MHz 15 V 15 30 - MHz

[1] The typical values of the propagation delay and transition times are calculated from the extrapolation formulas shown (CL in pF).

is the same as t

[2] t

Product data sheet Rev. 8 — 18 November 2011 8 of 18

THL

and t

TLH

NXP Semiconductors

CP0 input

Q1 - Q9 output

CP1 input

PLH

PHL

PLH

PHL

TLH

THL

001aaj305

Q0, Q5 - Q9 output

HEF4017B

5-stage Johnson decade counter

Table 8. Dynamic power dissipation P

PD can be calculated from the formulas shown. VSS = 0 V; tr = tf  20 ns; T

Symbol Parameter V

dynamic power dissipation

5V PD = 500  fi + (fo  CL)  V

10 V P

Typical formula for PD (W) where:

= 2200  fi + (fo  CL)  V

15 V PD = 6000  fi + (fo  CL)  V

11. Waveforms

amb

DD DD

= 25 C.

2 2

fi = input frequency in MHz; f

= output frequency in MHz;

CL = output load capacitance in pF; V

= supply voltage in V;

(C

 fo) = sum of the outputs.

Conditions: CP1 = LOW, while CP0 triggers on a LOW-to-HIGH transition. CP1 triggers on a HIGH-to-LOW transition; The shaded areas indicate where the output state is set by the input count. Measurement points given in Table 9

Fig 7. Waveforms showing the propagation delays for CP0, CP1 to Qn, Q5-9 outputs and the output transition

times

Product data sheet Rev. 8 — 18 November 2011 9 of 18

NXP Semiconductors

CP0 input

Q1 - Q9 output

MR input

CP1 input

1/f

max

rec

1/f

max

PLH

PHL

001aaj306

Q0, Q5 - Q9 output

001aae578

CP0 input

CP1 input

HEF4017B

5-stage Johnson decade counter

Conditions: CP1 = LOW, while CP0 triggers on a LOW-to-HIGH transition, tW and t

1 triggers on a HIGH-to-LOW transition.

are measured when CP0 = HIGH and

rec

The shaded areas indicate where the output state is set by the input count. Measurement points given in Table 9

Fig 8. Waveforms showing the minimum pulse width for CP0, CP1 and MR input; the maximum frequency for

CP0 and CP

Hold times are shown as positive values, but may be specified as negative values;

Fig 9. Waveforms showing hold times for CP0 to CP1 and CP1 to CP0

Table 9. Measurement points

Supply voltage Input Output V

5 V to 15 V 0.5V

Product data sheet Rev. 8 — 18 November 2011 10 of 18

Measurement points given in Table 9

1 input; the recovery time for MR and the MR input to Qn and Q5-9 output propagation delays

0.5V

NXP Semiconductors

10 %

90 %

10 %

90 %

0 V

negative

pulse

positive

pulse

0 V

90 %

10 %

90 %

10 %

001aaj781

001aag182

DUT

a. Input waveforms

HEF4017B

5-stage Johnson decade counter

b. Test circuit

Test data is given in Table 10. Definitions for test circuit: DUT = Device Under Test;

= load capacitance including jig and probe capacitance;

= termination resistance should be equal to the output impedance Zo of the pulse generator.

Fig 10. Test circuit for measuring switching times

Table 10. Test data

Supply voltage Input Load V

5 V to 15 V VSS or V

tr, t

 20 ns 50 pF

12. Application information

Some examples of applications for the HEF4017B are:

• Decade counter with decimal decoding

• 1 out of n decoding counter (when cascaded)

• Sequential controller

• Timer

Figure 11

shows a technique for extending the number of decoded output states for the

HEF4017B. Decoded outputs are sequential within each stage and from stage to stage,

Product data sheet Rev. 8 — 18 November 2011 11 of 18

with no dead time (except propagation delay).

NXP Semiconductors

001aae577

8 decoded

outputs

8 decoded

outputs

CP0 CP1

Q0 Q1 Q8 Q9

HEF4017B

- - - -

CP0 CP1

Q0 Q1 Q8 Q9

HEF4017B

- - - -

CP0 CP1

Q1 Q8 Q9

HEF4017B

- - - - - -

clock

first stage last stageintermediate stages

MR MR

9 decoded

outputs

Enabling the counter on CP1 when CP0 is HIGH, or on CP0 when CP1 is LOW, causes an extra count.

Fig 11. Counter expa ns io n

HEF4017B

5-stage Johnson decade counter

Product data sheet Rev. 8 — 18 November 2011 12 of 18

NXP Semiconductors

REFERENCES

OUTLINE VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC JEDEC JEITA

SOT38-4

95-01-14 03-02-13

(e )

seating plane

w M

pin 1 index

0 5 10 mm

scale

Note

1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.

UNIT

max.

(1) (1)

(1)

cD E e M

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

min.

max.

1.73

1.30

0.53

0.38

0.36

0.23

19.50

18.55

6.48

6.20

3.60

3.05

0.2542.54 7.62

8.25

7.80

10.0

8.3

0.764.2 0.51 3.2

inches

0.068

0.051

0.021

0.015

0.014

0.009

1.25

0.85

0.049

0.033

0.77

0.73

0.26

0.24

0.14

0.12

0.010.1 0.3

0.32

0.31

0.39

0.33

0.030.17 0.02 0.13

DIP16: plastic dual in-line package; 16 leads (300 mil)

SOT38-4

13. Package outline

HEF4017B

5-stage Johnson decade counter

Fig 12. Package outline SOT38-4 (DIP16)

Product data sheet Rev. 8 — 18 November 2011 13 of 18

NXP Semiconductors

w M

detail X

v M

(A )

pin 1 index

UNIT

max.

A2A3b

(1)E(1) (1)

eHELLpQZywv θ

REFERENCES

OUTLINE VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC JEDEC JEITA

inches

1.75

0.25

0.10

1.45

1.25

0.25

0.49

0.36

0.25

0.19

10.0

9.8

4.0

3.8

1.27

6.2

5.8

0.7

0.6

0.7

0.3

8 0

o o

0.25 0.1

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

Note

1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.

1.0

0.4

SOT109-1

99-12-27 03-02-19

076E07 MS-012

0.069

0.010

0.004

0.057

0.049

0.01

0.019

0.014

0.0100

0.0075

0.39

0.38

0.16

0.15

0.05

1.05

0.041

0.244

0.228

0.028

0.020

0.028

0.012

0.01

0.25

0.01 0.004

0.039

0.016

0 2.5 5 mm

scale

SO16: plastic small outline package; 16 leads; body width 3.9 mm

SOT109-1

HEF4017B

5-stage Johnson decade counter

Fig 13. Package outline SOT109-1 (SO16)

Product data sheet Rev. 8 — 18 November 2011 14 of 18

NXP Semiconductors

HEF4017B

5-stage Johnson decade counter

14. Revision history

Table 11. Revision history

Document ID Release date Data sheet status Change notice Supersedes

HEF4017B v.8 20111118 Product data sheet - HE F4017B v.7 Modifications:

HEF4017B v.7 20110914 Product data sheet - HEF4017B v.6 HEF4017B v.6 20091105 Product data sheet - HEF4017B v.5 HEF4017B v.5 20090709 Product data sheet - HEF4017B v.4 HEF4017B v.4 20081209 Product data sheet - HEF4017B_CNV v.3 HEF4017B_CNV v.3 19950101 Product specification - HEF4017B_CNV v.2 HEF4017B_CNV v.2 19950101 Product specification - -

• Legal pages updated.

• Changes in “General description” and “Features and benefits”.

• Section “Applications” removed.

Product data sheet Rev. 8 — 18 November 2011 15 of 18

NXP Semiconductors

HEF4017B

5-stage Johnson decade counter

15. Legal information

15.1 Data sheet status

Document status

Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification.

[1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) d escribed i n this docu ment may have changed si nce this d ocument was p ublished and may dif fer in case of multiple devices. The latest product statu s

information is available on the Internet at URL http://www.nxp.com.

[1][2]

Product status

[3]

Definition

15.2 Definitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to co nt ain det ailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.

Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet.

15.3 Disclaimers

Limited warranty and liability — Information in this document is believed to

be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information.

In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory.

Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semi conductors’ aggregat e and cumulative liabil ity towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors.

Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof.

Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environment al damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk.

Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification.

Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products.

NXP Semiconductors does not accept any liability related to any default , damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third part y customer(s). NXP does not accept any liability in this respect.

Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device.

Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer.

No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell product s that is open for accept ance or the gr ant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights.

Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities.

, unless otherwise

Product data sheet Rev. 8 — 18 November 2011 16 of 18

NXP Semiconductors

HEF4017B

5-stage Johnson decade counter

Non-automotive qualified products — Unless this data sheet expressly

states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It i s neit her qua lif ied nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications.

In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, custome r (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond

NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, da mages or failed produ ct claims result ing from custome r design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications.

15.4 Trademarks

Notice: All referenced brands, prod uct names, service names and trademarks are the property of their respective owners.

16. Contact information

For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com

Product data sheet Rev. 8 — 18 November 2011 17 of 18

NXP Semiconductors

17. Contents

1 General description. . . . . . . . . . . . . . . . . . . . . . 1

2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1

3 Ordering information. . . . . . . . . . . . . . . . . . . . . 1

4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2

5 Pinning information. . . . . . . . . . . . . . . . . . . . . . 3

5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3

6 Functional description . . . . . . . . . . . . . . . . . . . 4

7 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5

8 Recommended operating conditions. . . . . . . . 6

9 Static characteristics. . . . . . . . . . . . . . . . . . . . . 6

10 Dynamic characteristics . . . . . . . . . . . . . . . . . . 7

11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

12 Application information. . . . . . . . . . . . . . . . . . 11

13 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 13

14 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 15

15 Legal information. . . . . . . . . . . . . . . . . . . . . . . 16

15.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 16

15.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

15.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 16

15.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 17

16 Contact information. . . . . . . . . . . . . . . . . . . . . 17

17 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

HEF4017B

5-stage Johnson decade counter

Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 18 November 2011

Document identifier: HEF4017B

NXP HEF 4017BT NXP Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual

1. General description

2. Features and benefits

3. Ordering information

4. Functional diagram

5. Pinning information

5.1 Pinning

5.2 Pin description

6. Functional description

7. Limiting values

8. Recommended operating conditions

9. Static characteristics

10. Dynamic characteristics

11. Waveforms

12. Application information

13. Package outline

14. Revision history

15. Legal information

15.1 Data sheet status

15.2 Definitions

15.3 Disclaimers

15.4 Trademarks

16. Contact information

17. Contents