HEF4017B
5-stage Johnson decade counter
Rev. 8 — 18 November 2011 Product data sheet
1. General description
The HEF4017B is a 5-stage Johnson decade c ounter with ten spike-free decoded active
HIGH outputs (Q0 to Q9), an active LOW carry output from the most significant flip-flop
(Q
5-9), active HIGH and active LOW clock inputs (CP0, CP1) and an overriding
asynchronous master reset input (MR).
The counter is advanced by either a LOW-to-H IGH trans ition a t CP0 whil e CP
a HIGH-to-LOW transition at CP
When cascading counters, the Q
6, 7, 8, and 9, can be used to drive the CP0 input of the next counter. A HIGH on MR
resets the counter to zero (Q0 = Q
inputs (CP0, CP
Automatic counter code correction is provided by an internal circuit: following any illegal
code the counter returns to a proper counting mode within 11 clock pulses.
Schmitt trigger action makes the clock inputs highly tolerant of slower rise and fall times.
It operates over a recommended V
(usually ground). Unused inputs must be connected to V
2. Features and benefits
Automatic counter correction
Tolerant of slow clock rise and fall times
Fully static operation
5 V, 10 V, and 15 V pa rametric ratings
Standardized symmetrical output characteristics
Specifie d from 40 C to +125 C
Complies with JEDEC standard JESD 13-B
1).
1 is LOW or
1 while CP0 is HIGH (see Table 3).
5-9 output, which is LOW while the counter is in states 5,
5-9 = HIGH; Q1 to Q9 = LOW) independent of the clock
power supply range of 3 V to 15 V referenced to VSS
DD
, VSS, or another input.
DD
3. Ordering information
Table 1. Ordering information
All types operate from
Type number Package
Name Description Version
HEF4017BP DIP16 plastic dual in-line package; 16 leads (300 mil) SOT38-4
HEF4017BT SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1
40
C to +125C
NXP Semiconductors
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DECODING AND OUTPUT CIRCUITRY
5-STAGE JOHNSON COUNTER
Q0
CP0
MR
15
14
13
CP1
3
Q12Q24Q37Q410Q51Q65Q76Q89Q9
Q5-9
11
12
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FF
1
D
CP
RD
Q
Q
FF
2
D
CP
RD
Q
Q
FF
3
D
CP
RD
Q
Q
FF
4
D
CP
RD
Q
Q
FF
5
D
CP
RD
Q
Q
Q0
CP1
CP0
MR
Q1 Q2 Q3
Q4 Q5 Q6 Q7 Q8 Q9 Q5-9
4. Functional diagram
Fig 1. Functional diagram
HEF4017B
5-stage Johnson decade counter
Fig 2. Logic diagram
HEF4017B All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 8 — 18 November 2011 2 of 18
NXP Semiconductors
Q9
Q5-9
11
12
Q8 9
MR15
14
13
CP0
CP1
Q7 6
Q6
Q5 1
5
Q4
Q3 7
10
Q2 4
Q1 2
Q0 3
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9
CT≥5
11
12
8
9
CT = 0
CTRDIV10/DEC
15
13
14
7
6
6
5
1
5
4
3
7
10
2
4
1
2
0
3
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&
HEF4017B
Q5 V
DD
Q1 MR
Q0 CP0
Q2 CP1
Q6 Q5-9
Q7 Q9
Q3 Q4
V
SS
Q8
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1
2
3
4
5
6
7
8
10
9
12
11
14
13
16
15
5-stage Johnson decade counter
Fig 3. Logic symbol Fig 4. IEE logic symbol
5. Pinning information
HEF4017B
Fig 5. Pin configuration
Table 2. Pin description
Symbol Pin Description
Q0 to Q9 3, 2, 4, 7, 10, 1, 5, 6, 9, 11 decoded output
HEF4017B All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 8 — 18 November 2011 3 of 18
V
SS
5-9 12 carry output (active LOW)
Q
1 13 clock input (HIGH-to-LOW edge-triggered)
CP
5.1 Pinning
5.2 Pin description
8 ground supply voltage
NXP Semiconductors
HEF4017B
5-stage Johnson decade counter
Table 2. Pin description
Symbol Pin Description
CP0 14 clock input (LOW-to-HIGH edge-triggered)
MR 15 master reset input
V
DD
16 supply voltage
…continued
6. Functional description
Table 3. Function table
MR CP0 CP1 Operation
HXXQ0 = Q
LH counter advances
L L counter advances
L L X no change
L X H no change
LH no change
L L no change
[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care;
= positive-going transition; = negative-going transition.
[1]
5-9 = H; Q1 to Q9 = L
HEF4017B All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 8 — 18 November 2011 4 of 18
NXP Semiconductors
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CP0 INPUT
CP1 INPUT
MR INPUT
Q0 OUTPUT
Q1 OUTPUT
Q2 OUTPUT
Q3 OUTPUT
Q4 OUTPUT
Q5 OUTPUT
Q6 OUTPUT
Q7 OUTPUT
Q8 OUTPUT
Q9 OUTPUT
Q5-9 OUTPUT
HEF4017B
5-stage Johnson decade counter
Fig 6. Timing diagram
7. Limiting values
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
V
DD
I
IK
V
I
I
OK
I
I/O
supply voltage 0.5 +18 V
input clamping current VI< 0.5 V or VI>VDD + 0.5 V - 10 mA
input voltage 0.5 VDD + 0.5 V
output clamping current VO< 0.5 V or VO>VDD + 0.5 V - 10 mA
input/output current - 10 mA
HEF4017B All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 8 — 18 November 2011 5 of 18
NXP Semiconductors
HEF4017B
5-stage Johnson decade counter
Table 4. Limiting values
…continued
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
I
DD
T
stg
T
amb
P
tot
supply current - 50 mA
storage temperature 65 +150 C
ambient temperature 40 +125 C
total power dissipation T
= 40 C to +125 C
amb
DIP16 package
SO16 package
[1]
-750mW
[2]
-500mW
P power dissipation per output - 100 mW
[1] For DIP16 package: P
[2] For SO16 package: P
derates linearly with 12 mW/K above 70 C.
tot
derates linearly with 8 mW/K above 70 C.
tot
8. Recommended operating conditions
Table 5. Recommended operating conditions
Symbol Parameter Conditions Min Typ Max Unit
V
DD
V
I
T
amb
supply voltage 3 - 15 V
input voltage 0 - V
ambient temperature in free air 40 - +125 C
t/V input transition rise and fall rate V
DD
= 5 V --3.75s/V
DD
V
= 10 V --0.5s/V
DD
= 15 V --0.08s/V
V
DD
V
9. Static characteristics
Table 6. Static characteristics
= 0 V; VI = VSS or VDD unless otherwise specified.
V
SS
Symbol Parameter Conditions V
V
IH
HIGH-level
input voltage
V
IL
LOW-level
input voltage
V
OH
HIGH-level
output voltage
V
OL
LOW-level
output voltage
IO < 1 A 5 V 3.5 - 3.5 - 3.5 - 3.5 - V
10 V 7.0 - 7.0 - 7.0 - 7.0 - V
15 V 11.0 - 11.0 - 11.0 - 11.0 - V
IO < 1 A 5V -1.5-1.5-1.5-1.5V
10V -3.0-3.0-3.0-3.0V
15V -4.0-4.0-4.0-4.0V
IO < 1 A;
VI=VSS or V
DD
10 V 9.95 - 9.95 - 9.95 - 9.95 - V
15 V 14.95 - 14.95 - 14.95 - 14.95 - V
IO < 1 A;
I=VSS
or V
DD
10 V - 0.05 - 0.05 - 0.05 - 0.05 V
V
15 V - 0.05 - 0.05 - 0.05 - 0.05 V
DD
= 40 C T
amb
= 25 C T
amb
= 85 C T
amb
= 125 C Unit
amb
T
Min Max Min Max Min Max Min Max
5 V 4.95 - 4.95 - 4.95 - 4.95 - V
5 V - 0.05 - 0.05 - 0.05 - 0.05 V
HEF4017B All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 8 — 18 November 2011 6 of 18
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