NXP Chip Errata User Manual

NXP Semiconductors

Chip Errata

Document Number: IMXRT1015CE

Rev. 2, 01/2021

Chip Errata for the i.MX RT1015

This document details the silicon errata known at the time of publication for the i.MX RT1015 multimedia
crossover processors.

Table 1 provides a revision history for this document.

,

Table 1. Document Revision History

Rev.

Number

Rev. 2 01/2021 • Added the following errata:

Rev. 1 06/2019 • Added the following errata:

Rev. 0 01/2019 • Initial version

Date Substantive Changes

– ERR050143

• Removed the following errata:
– ERR007265 (replace ERR007265 with ERR050143)

• Updated the Figure 1, "Revision Level to Part Marking Cross-Reference,"

– ERR011572
– ERR050101
– ERR050130
– ERR050144
– ERR050194

© 2019-2021 NXP B.V.

Figure 1 provides a cross-reference to match the revision code to the revision level marked on the device.

Temperature (Tj)

+

Consumer: 0 to + 95 °C D

Industrial: -40 to +105 °C C

Core Frequency $

400 MHz 4

500 MHz 5

600 MHz 6

Package Type VV

196MAPBGA, 12 x 12 mm, 0.8 mm pitch VJ

196MAPBGA, 10 x 10 mm, 0.65 mm pitch VL

144LQFP, 20 x 20 mm, 0.5 mm pitch AG

100LQFP, 14 x 14 mm, 0.5 mm pitch AF

80LQFP, 12 x 12 mm, 0.5 mm pitch AE

Qualification Level M

Prototype Samples P

Mass Production M

Special S

Part # series XX

i.MX RT RT

Tie %

Standard Feature 1

Full Feature 2

4MB Flash SIP 4

Enhanced Feature 5

Far Field AFE (e.g. for Alexa Voice Service) A

Facial Recognition F

Local Voice Control L

M IMX X X @ % + VV $ A

Family

@

First Generation RT family 1

Reserved 2-8

##

Sub-Family ##

RT101x 01

RT102x 02

RT105x 05

RT106x 06

Silicon Rev A

A0 A

A1 B

For details on the Arm® configuration used on this chip (including Arm module revisions), please see the
“Platform configuration” section of the “Arm Cortex®-M7 Platform” chapter of the i.MX RT1015
Crossover Processor Reference Manual (IMXRT1015RM).

2 NXP Semiconductors

Figure 1. Revision Level to Part Marking Cross-Reference

Chip Errata for the i.MX RT1015, Rev. 2, 01/2021

Table 2 summarizes errata on the i.MX RT1015.

Table 2. Summary of Silicon Errata

Errata Name

ADC

ERR011164

ERR006223

ERR050143

ERR011572

ERR011207

ERR011377

ERR050130 PIT: Temporary incorrect value reported in LMTR64H register in lifetimer mode No fix scheduled 10

ADC: ADC_ETC fails to clear the ADC_ETC request signals automatically after
receiving DMA ack

CCM

CCM: Failure to resume from Wait/Stop mode with power gating No fix scheduled

CCM: SoC will enter low power mode before the Arm CPU executes WFI when
improper low power sequence is used

Cortex-M7

Cortex-M7: Write-Trough stores and loads may return incorrect data No fix scheduled

FlexSPI

FlexSPI: When FLEXSPI_AHBCR[PREFETCHEN] is set, incorrect data can be
returned in rare conditions

FlexSPI: FlexSPI DLL lock status bit not accurate due to timing issue No fix scheduled

PIT

Solution

No fix scheduled

No fix scheduled

No fix scheduled

Page

4

5

6

7

8

9

QTMR

ERR050194 QTMR: Overflow flag and related interrupt cannot be generated when the timer

is configured as upward count mode

SAI

ERR011096

ERR011150

ERR050144 SAI: Setting FCONT = 1 when TMR > 0 may not function correctly No fix scheduled 14

ERR011165

ERR006281

ERR050101

SAI: The internal bit clock cannot be generated when BCI = 1 No fix scheduled

SAI: Internally generated receive or transmit BCLK cannot be re-enabled if it is
first disabled when RCR2[DIV] or TCR2[DIV] > 0

SNVS

SNVS: Invalid ECC check failure No fix scheduled

USB

USB: Incorrect DP/DN state when only VBUS is applied No fix scheduled

USB: Endpoint conflict issue in device mode Fix in next revision

No fix scheduled 11

12

No fix scheduled

13

15

16

17

Chip Errata for the i.MX RT1015, Rev. 2, 01/2021

NXP Semiconductors 3

ERR011164

ERR011164 ADC: ADC_ETC fails to clear the ADC_ETC request signals

automatically after receiving DMA ack

Description:

If enable ADC_ETC to trigger DMA transfer, the DMA transfer data send ack out. It does not clear
the request signals automatically and continue to trigger DMA.

Projected Impact:

This issue can lead to DMA failure when working with ADC_ETC.

Workarounds:

Configuring two DMA channels for ADC_ETC data transfer. The first DMA channel with low
priority triggered by ADC_ETC request is to transfer ADC_ETC data. The second DMA channel
with high priority links to the first channel is to clear request of ADC_ETC by writing
DMA_CTRL register. Both channel’s priority need to be higher than any channel used by other
peripherals. This solution is result in DMA to transfer ADC_ETC data twice for one request signal
and application need handle the redundant data properly.

Proposed Solution:

No fix scheduled

Software Status:

Software workaround is not in SDK.

Chip Errata for the i.MX RT1015, Rev. 2, 01/2021

4 NXP Semiconductors

ERR006223 CCM: Failure to resume from Wait/Stop mode with power gating

Description:

When entering Wait/Stop mode with power gating of the Arm core(s), if an interrupt arrives during
the power-down sequence, the system could enter an unexpected state and fail to resume.

Projected Impact:

Device might fail to resume from low-power state.

Workarounds:

Use REG_BYPASS_COUNTER (RBC) to hold off interrupts when the PGC unit is in the middle
of the power-down sequence. The counter needs to be set/cleared only when there are no interrupts
pending. The counter needs to be enabled as close to the WFI (Wait For Interrupt) state as possible.

The following equation can be used to aid determination of the RBC counter value:

The PREG_BYPASS_COUNT value is equal or greater than 2.

Proposed Solution:

ERR006223

No fix scheduled

Software Status:

Software workaround is in SDK.

Chip Errata for the i.MX RT1015, Rev. 2, 01/2021

NXP Semiconductors 5

ERR050143

ERR050143 CCM: SoC will enter low power mode before the Arm CPU

executes WFI when improper low power sequence is used

Description:

When software tries to enter the low power mode with the following sequence, SoC enters the low
power mode before the Arm CPU executes the WFI instructions.

• Set CCM_CLPCR[1:0] to 2’b00

• Arm CPU enters WFI

• Arm CPU wakes up from an interrupt event, which is masked by GPC or not visible to GPC,
such as an interrupt from local timer.

• Set CCM_CLPCR[1:0] to 2’b01 or 2’b10

• Arm CPU executes WFI

Before the last step, SoC enters the WAIT mode if CCM_CLPCR[1:0] is set to 2’b01, or enters

the STOP mode if CCM_CLPCR[1:0] is set to 2’b10.

Workarounds:

Software workaround:

1. Trigger IRQ #41 (IOMUX), which is always pending by setting IOMUXC_GPR_GPR1[12] bit

2. Unmask IRQ #41 in GPC before setting the CCM low power mode

3. Mask IRQ #41 right after the CCM low power mode is set (set CCM_CLPCR[1:0])

Proposed Solution:

No fix scheduled

Software Status:

Software workaround is in SDK

Chip Errata for the i.MX RT1015, Rev. 2, 01/2021

6 NXP Semiconductors