
BT137S-600D
4Q Triac
12 June 2014 Product data sheet
1. General description
Planar passivated very sensitive gate four quadrant triac in a SOT428 (DPAK)
surface-mountable plastic package intended for use in general purpose bidirectional
switching and phase control applications, where high sensitivity is required in all four
quadrants. This very sensitive gate "series D" triac is intended to be interfaced directly to
microcontrollers, logic integrated circuits and other low power gate trigger circuits.
2. Features and benefits
Direct triggering from low power drivers and logic ICs
•
High blocking voltage capability
•
Low holding current for low current loads and lowest EMI at commutation
•
Planar passivated for voltage ruggedness and reliability
•
Surface-mountable package
•
Triggering in all four quadrants
•
Very sensitive gate
•
3. Applications
General purpose motor control
•
General purpose switching
•
4. Quick reference data
Table 1. Quick reference data
Symbol Parameter Conditions Min Typ Max Unit
V
DRM
I
TSM
I
T(RMS)
Static characteristics
GT
repetitive peak offstate voltage
non-repetitive peak onstate current
RMS on-state current full sine wave; Tmb ≤ 102 °C; Fig. 1;
gate trigger current
full sine wave; T
tp = 20 ms; Fig. 4; Fig. 5
Fig. 2; Fig. 3
VD = 12 V; IT = 0.1 A; T2+ G+;
Tj = 25 °C
VD = 12 V; IT = 0.1 A; T2+ G-;
Tj = 25 °C; Fig. 7
j(init)
= 25 °C;
- - 600 V
- - 65 A
- - 8 A
- 2.5 5 mAI
- 3.5 5 mA
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NXP Semiconductors
BT137S-600D
4Q Triac
Symbol Parameter Conditions Min Typ Max Unit
VD = 12 V; IT = 0.1 A; T2- G-;
Tj = 25 °C; Fig. 7
- 3.5 5 mA
VD = 12 V; IT = 0.1 A; T2- G+;
- 6.5 10 mA
Tj = 25 °C; Fig. 7
I
H
holding current VD = 12 V; Tj = 25 °C; Fig. 9 - 1.5 10 mA
5. Pinning information
Table 2. Pinning information
Pin Symbol Description Simplified outline Graphic symbol
1 T1 main terminal 1
2 T2 main terminal 2
3 G gate
mb T2 mounting base; main
terminal 2
DPAK (SOT428)
6. Ordering information
Table 3. Ordering information
PackageType number
Name Description Version
BT137S-600D DPAK plastic single-ended surface-mounted package (DPAK); 3 leads
(one lead cropped)
SOT428
BT137S-600D All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved
Product data sheet 12 June 2014 2 / 13

NXP Semiconductors
BT137S-600D
4Q Triac
7. Limiting values
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
V
DRM
I
T(RMS)
TSM
repetitive peak off-state voltage - 600 V
RMS on-state current full sine wave; Tmb ≤ 102 °C; Fig. 1;
- 8 A
Fig. 2; Fig. 3
non-repetitive peak on-state
current
full sine wave; T
tp = 20 ms; Fig. 4; Fig. 5
j(init)
= 25 °C;
- 65 AI
I2t I2t for fusing
dIT/dt rate of rise of on-state current
I
P
P
T
T
GM
GM
G(AV)
stg
j
peak gate current - 2 A
peak gate power - 5 W
average gate power over any 20 ms period - 0.5 W
storage temperature -40 150 °C
junction temperature - 125 °C
full sine wave; T
j(init)
= 25 °C;
- 71 A
tp = 16.7 ms
tp = 10 ms; SIN - 21
IT = 12 A; IG = 0.2 A; dIG/dt = 0.2 A/µs;
- 50 A/µs
T2+ G+
IT = 12 A; IG = 0.2 A; dIG/dt = 0.2 A/µs;
- 50 A/µs
T2+ G-
IT = 12 A; IG = 0.2 A; dIG/dt = 0.2 A/µs;
- 50 A/µs
T2- G-
IT = 12 A; IG = 0.2 A; dIG/dt = 0.2 A/µs;
- 10 A/µs
T2- G+
A2s
BT137S-600D All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved
Product data sheet 12 June 2014 3 / 13

NXP Semiconductors
Tmb(°C)
- 50 1501000 50
003aae689
4
6
2
8
10
I
T(RMS)
(A)
0
003aae692
0
5
10
15
20
25
10
- 2
10
- 1
1 10
surge duration (s)
I
T(RMS)
(A)
003aae690
4
8
12
P
tot
(W)
0
I
T(RMS)
(A)
0 1084 62
α
= 180
°
120°
90°
60°
30
°
BT137S-600D
4Q Triac
Fig. 1. RMS on-state current as a function of mounting
base temperature; maximum values
f = 50 Hz
Tmb ≤ 102 °C
Fig. 2. RMS on-state current as a function of surge
duration; maximum values
α = conduction angle
a = form factor = I
T(RMS)/IT(AV)
Fig. 3. Total power dissipation as a function of RMS on-state current; maximum values
BT137S-600D All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved
Product data sheet 12 June 2014 4 / 13