NXP BST 82 SMD Datasheet

DISCRETE SEMICONDUCTORS

DATA SH EET

BST82

N-channel enhancement mode
vertical D-MOS transistor

Product specification
File under Discrete Semiconductors, SC13b

April 1995

Philips Semiconductors Product specification

N-channel enhancement mode vertical
D-MOS transistor

DESCRIPTION

N-channel enhancement mode
vertical D-MOS transistor in SOT23
envelope and designed for use as
Surface Mounted Device (SMD) in
thin and thick-film circuits for
telephone ringer and for application
with relay, high-speed and
line-transformer drivers.

FEATURES

• Direct interface to C-MOS, TTL,
etc.

• High-speed switching

• No second breakdown

• Low R

DS(on)

QUICK REFERENCE DATA

Drain-source voltage V
Drain-source voltage (non-repetitive peak;

≤ 2 ms)

t

p

Gate-source voltage (open drain) ±V
Drain current (DC) I
Total power dissipation up to T
Drain-source ON-resistance

ID= 150 mA; VGS=5 V R

Transfer admittance

= 175 mA; VDS=5 V  Yfs typ. 150 mS

I

D

PINNING - SOT23

1 = gate
2 = source
3 = drain

=25°CP

amb

DS

V

DS(SM)

D

tot

DS(on)

GSO

BST82

max. 80 V
max. 100 V

max. 20 V
max. 175 mA
max. 300 mW

typ.
max.

710Ω

Ω

PIN CONFIGURATION

handbook, halfpage

Marking: 02p

3

12

Top view

MSB003

Fig.1 Simplified outline and symbol.

handbook, 2 columns

g

MBB076 - 1

d

s

April 1995 2

Philips Semiconductors Product specification

N-channel enhancement mode vertical
D-MOS transistor

RATINGS

Limiting values in accordance with the Absolute Maximum System (IEC 134)

Drain-source voltage V
Drain-source voltage (non-repetitive peak; t

≤ 2 ms) V

p

Gate-source voltage (open drain) ±V
Drain current (DC) I
Drain current (peak) I
Total power dissipation up to T

= 25 °C (note 1) P

amb

Storage temperature range T
Junction temperature T

THERMAL RESISTANCE

From junction to ambient (note 1) R

Note

1. Transistors mounted on a ceramic substrate of 7 mm x 5 mm x 0.7 mm.

DS
DS(SM)

GSO
D
DM

tot
stg
j

th j-a

BST82

max. 80 V
max. 100 V
max. 20 V
max. 175 mA
max. 600 mA
max. 300 mW

−65 to + 150 °C

max. 150 °C

= 430 K/W

April 1995 3

Philips Semiconductors Product specification

N-channel enhancement mode vertical
D-MOS transistor

CHARACTERISTICS

T

=25°C unless otherwise specified

j

Drain-source breakdown voltage

I

=10µA; VGS=0 V

D

(BR)DSS

Drain-source leakage current

VDS= 60 V; VGS=0 I

DSS

Gate-source leakage current

VGS= 20 V; VDS=0 I

GSS

Gate-source cut-off voltage

ID= 1 mA; VDS=V

GS

V

(P)GS

Drain-source ON-resistance

= 150 mA; VGS=5 V R

I

D

DS(on)

Transfer admittance

I

= 175 mA; VDS= 5 V  Yfs typ. 150 mS

D

Input capacitance at f = 1 MHz

V

= 10 V; VGS=0 C

DS

iss

min. 80 V

max. 1.0 µA

max. 100 nA

min.
max.

typ.
max.

typ.
max.

BST82

1.5

3.5VV

710Ω

Ω

1530pF

pF

Output capacitance at f = 1 MHz

= 10 V; VGS=0 C

V

DS

Feedback capacitance at f = 1 MHz

V

= 10 V; VGS= 0 C

DS

Switching times (see Figs 2 and 3)

ID= 175 mA; VDD= 50 V; VGS= 0 to 10 V t

oss

rss

typ.
max.

typ.
max.

on

t

off

typ.
max.

typ.
max.

1320pF

pF

36pF

pF

410ns

ns

410ns

ns

April 1995 4

Philips Semiconductors Product specification

N-channel enhancement mode vertical
D-MOS transistor

handbook, halfpage

10 V

0 V

50 Ω

VDD = 50 V

I

D

MSA631

handbook, halfpage

INPUT

OUTPUT

10 %

t

on

90 %

90 %

t

off

BST82

10 %

MBB692

3

10

handbook, halfpage

I

D

(mA)

2

10

10

Fig.2 Switching times test circuit.

MDA762

VGS = 10 V

468

8 V

R

DSon

6 V

5 V

(Ω)

Fig.3 Input and output waveforms.

8

VGS (V)

MDA732

5 V

handbook, halfpage

100 2

1

I

D

(A)

0.8

0.6

0.4

0.2

0

010

246

VDS = 10 V

Fig.4 Tj=25°C; typical values.

April 1995 5

Fig.5 Tj=25°C; typical values.

Philips Semiconductors Product specification

N-channel enhancement mode vertical
D-MOS transistor

8

VDS (V)

MDA763

9 V
8 V

7 V

6 V

5 V

4 V

3 V

handbook, halfpage

1

I

D

(A)

0.8

0.6

0.4

0.2

0

010

VGS = 10 V

246

400

handbook, halfpage

P

tot

(mW)

300

200

100

0

0 50 100

150

T

amb

BST82

MDA769

200

(°C)

handbook, halfpage

3

k

2.5

2

1.5

1

0.5

−50 0 50

Fig.8

Fig.6 Tj=25°C; typical values.

100

Tj (°C)

DS (on)

at T

j

at 25 °C

;=

R

---------------------------------------------

k

R

DS (on)

typ. values at 150 mA/5 V.

MDA735

150

1.2

handbook, halfpage

k

1.1

1

0.9

0.8

0.7

−50 0 50

Fig.9

Fig.7 Power derating curve.

100

GS th()

at 25 °C

at T

j

;=

V

---------------------------------------------

k

V

GS th()

V

at 1 mA; typical values.

GS(th)

MDA736

Tj (°C)

150

April 1995 6

Philips Semiconductors Product specification

N-channel enhancement mode vertical
D-MOS transistor

50

handbook, halfpage

C

(pF)

40

30

20

10

0

010 30

20

MDA737

C

iss

C

oss

C

rss

V

(V)

DS

BST82

Fig.10 Tj=25°C; VGS= 0; f = 1 MHz; typical values.

April 1995 7

Philips Semiconductors Product specification

N-channel enhancement mode vertical

BST82

D-MOS transistor

PACKAGE OUTLINES

Plastic surface mounted package; 3 leads SOT23

D

3

E

H

E

AB

X

v M

A

12

e

1

DIMENSIONS (mm are the original dimensions)

A

1

0.1

b

p

0.48

0.15

0.38

0.09

IEC JEDEC EIAJ

UNIT

mm

A

1.1

0.9

OUTLINE
VERSION

SOT23

max.

b

p

e

cD

3.0

2.8

w M

B

0 1 2 mm

scale

e

0.95

H

1

2.5

2.1

E

1.4

1.9

1.2

REFERENCES

e

Q

A

A

1

c

L

p

detail X

L

Qwv

p

E

0.55

0.45

0.15

0.45

0.2

0.1

EUROPEAN

PROJECTION

ISSUE DATE

97-02-28

April 1995 8

Philips Semiconductors Product specification

N-channel enhancement mode vertical

BST82

D-MOS transistor

DEFINITIONS

Data sheet status

Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.

Application information

Where application information is given, it is advisory and does not form part of the specification.

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.

April 1995 9

Philips Semiconductors Product specification

N-channel enhancement mode vertical
D-MOS transistor

NOTES

BST82

April 1995 10

Philips Semiconductors Product specification

N-channel enhancement mode vertical
D-MOS transistor

NOTES

BST82

April 1995 11

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Printed in The Netherlands 137107/00/01/pp12 Date of release: April 1995 Document order number: 9397 750 02499