NXP AN13234, RT10 Application Note
AN13234
How to Enable SWO Trace for i.MX RT10xx Series
Rev. 0 — 04/2021
Contents
1 Introduction
The i.MX RT10xx series are processors featuring NXP’s advanced
implementation of the Arm® Cortex®-M7 core, which can provide good CPU
performance and real-time response. One of the advantage of the Cortex-M7
core is that it contains Instrumentation Trace Macrocell (ITM) in the CoreSight
architecture. ITM is a novel trace method for MCU debugging and it supports
the Serial Wire Output (SWO) trace.
This application note introduces the principle and advantages of SWO trace. It
provides guidance on how to enable the SWO trace with i.MX RT10xx Series,
including the hardware and software configurations. Also this document
describes the steps for using the basic SWO trace feature (ITM debug output)
based on different IDEs.
2 SWO trace overview
2.1 CoreSight components
1 Introduction......................................1
2 SWO trace overview........................1
2.1 CoreSight components................ 1
2.2 Serial Wire Output (SWO)............2
2.3 Instrumentation Trace Macrocell
2.4 Debug probes.............................. 4
3 Project and hardware modifications
3.1 MIMXRT1010-EVK...................... 5
3.2 MIMXRT1020-EVK...................... 6
3.3 MIMXRT1050-EVK...................... 7
3.4 MIMXRT1060-EVK...................... 7
3.5 MIMXRT1060-EVKB....................7
4 Using SWO with IAR....................... 8
5 Using SWO with Keil..................... 12
6 Conclusion.....................................16
7 References....................................17
8 Revision history.............................17
Application Note
(ITM)............................................ 4
required to enable SWO Trace....... 5
CoreSight is an architecture used to debug and trace by Arm. The architecture consists of several useful components. Figure 1
shows a typical CoreSight architecture, which includes two Arm processors, one DSP module and a number of other components.
There are three paths in the below environment: trace path, debug path and trigger path. This document focuses on the debug
path, which includes ITM module and SWO module.
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SWO trace overview
Figure 1. A typical CoreSight architecture
2.2 Serial Wire Output (SWO)
Serial Wire Output (SWO) is a single pin trace interface that is part of the Cortex-M CoreSight architecture. It acts as a bridge
between the on-chip trace data to Trace Port Analyzer (TPA).
The SWO trace provides access to the memory of a running target without interrupting the target. It is available on CortexM3/M4/M7 based MCUs. Figure 2 shows the block diagram of SWO. In addition to the standard Serial Wire Debug (SWD)
connection, SWO trace requires just one extra pin.
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Figure 2. SWO block diagram
SWO trace overview
The SWO trace interface is a TPIU-like device that supports a limited subset of the full TPIU functionality. SWO trace features are
described as below:
• Sending debug messages as strings
• Recording interrupt entry/exit
• Recording function entry/exit
• Periodic PC (Program Counter) value sampling
• Event notification
• Variable or memory cell change over time
One of the most common usage of SWO trace is using SWO to print debug messages from the target, as described in Using SWO
with IAR and Using SWO with Keil.
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SWO trace overview
Figure 3. SWO pin
NOTE
SWO pin is multiplexed with JTAG_TDO pin, as shown in Figure 3. This means the Serial Wire Debug (SWD) mode
must be used, not the JTAG mode.
2.3 Instrumentation Trace Macrocell (ITM)
ITM generates trace information as packets and it provides a mechanism for sending data from the target to debugger via the
SWO stream. Trace data from ITM is forwarded to the SWO interface and then SWO transports the data streams to the Trace
Port Analyzer.
ITM supports 32 stimulus channels which allow different software to output data to different ports, so that the debugging target is
able to separate different packets. Among the 32 ports, Port0 is designated for outputting debug information. Different from the
UART-based output, ITM output does not cause significant latency to the application, because there is a FIFO that buffers the
output data inside ITM block.
ITM is used to:
• support printf style debugging
• trace OS and application events
• emit diagnostic system information
2.4 Debug probes
There are a number of debug solutions for i.MX RT10xx series MCUs, such as CMSIS DAP, J-Link and PE micro. However, not
every debug solution supports SWO trace. The SWO trace function can be used with several common compatible debug probe
such as:
• LinkServer LPC-Link2
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Project and hardware modifications required to enable SWO Trace
LPC-Link2 is an extensible, stand-alone debug probe that can be configured to support various development tools and IDEs
using a variety of different downloadable firmware images. It has also been built into many LPCXpresso development boards
and some MIMXRT-EVK boards.
LinkServer debug connections allow SWO trace to be started and stopped while the target is running. That means the SWO
trace using LPC-Link2 debug solution has no effect on the MCU performance. The powerful features of SWO trace have been
tested with LPC-Link2 firmware based on MCUXpresso IDE. For more information, see
MCUXpresso IDE SWO Trace Guide
• SEGGER J-Link
J-Link is a debug probe supporting a large number of MCU cores. Regarding to the SWO trace with J-Link debug solution,
the target must be halted when starting or stopping the SWO trace.
The correct target clock speed must be sampled to allow the internal sampling rates to be calculated correctly. The steps for
using SWO trace with J-Link debug probe based on different toolchains will be clarified explicitly in Using SWO with IAR and
Using SWO with Keil.
3 Project and hardware modifications required to enable SWO Trace
The default project examples in SDK and some original EVK boards do not enable SWO trace features. To enable the SWO trace,
several project changes and hardware modifications are required. This chapter lists the modifications for enabling SWO trace
based on the following i.MX RT platforms:
• MIMXRT1010-EVK
.
• MIMXRT1020-EVK
• MIMXRT1050-EVK
• MIMXRT1060-EVK
• MIMXRT1060-EVKB
NOTE
The source code changes are performed based on the latest SDK (version 2.9.1).
3.1 MIMXRT1010-EVK
1. Modifying pin_mux.c
Within a project, select the board subfolder, locate the pin_mux.c file and add the below lines in the
BOARD_InitPins function:
IOMUXC_SetPinMux( /* Add these lines*/
IOMUXC_GPIO_AD_09_ARM_TRACE_SWO,
0U);
IOMUXC_SetPinConfig( /* Add these lines*/
IOMUXC_GPIO_AD_09_ARM_TRACE_SWO,
0x00F9U);
2. Modifying
Within a project, select the board subfolder, locate the clock_config.c file and modify the lines in the
BOARD_BootClockRUN function as below:
clock_config.c
/* Disable TRACE clock gate. */ /* Locate these entries*/
CLOCK_DisableClock(kCLOCK_Trace);
/* Set TRACE_PODF. */
CLOCK_SetDiv(kCLOCK_TraceDiv, 3);
/* Set Trace clock source. */
CLOCK_SetMux(kCLOCK_TraceMux, 0);
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Project and hardware modifications required to enable SWO Trace
CLOCK_EnableClock(kCLOCK_Trace); /* Make these edits*/
/* Set TRACE_PODF. */
CLOCK_SetDiv(kCLOCK_TraceDiv, 0); /* Make these edits*/
/* Set Trace clock source. */
CLOCK_SetMux(kCLOCK_TraceMux, 0); /* Make these edits*/
3.2 MIMXRT1020-EVK
1. Connect SWO pin and JTAG-TDO pin
Connect SWO (J19-3) and JTAG-TDO (J16-13).
2. DNP R116
JTAG-TDO pin is reused as a ENET-RESET signal. There is a capacitor (C137) that affects the signal, so remove R116,
as shown in Figure 4.
Figure 4. Hardware modification on MIMXRT1020-EVK
3. Modifying pin_mux.c
Within a project, select the board subfolder, locate the pin_mux.c file and add the below lines in the
BOARD_InitPins function:
IOMUXC_SetPinMux( /* Add these lines*/
IOMUXC_GPIO_AD_B0_11_ARM_CM7_TRACE_SWO,
0U);
IOMUXC_SetPinConfig( /* Add these lines*/
IOMUXC_GPIO_AD_B0_11_ARM_CM7_TRACE_SWO,
0x00F9U);
4. Modifying clock_config.c
Same as the clock modifications of MIMXRT1010-EVK in MIMXRT1010-EVK.
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