NXP AN13036 Application Note

AN13036

Introduction to Boundary Scan of LPC5500

Rev. 0 — 30 October 2020

1 Overview

This document focuses on the procedure of entering boundary scan mode for
the board-level test. It provides the setup sequence and script examples to
ensure first-pass success.

Engineers should understand the standard for the test access port and
boundary scan architecture from IEEE 1149.1.

1.1 Boundary scan

Boundary scan is a method for testing interconnects on PCBs and internal IC
sub-blocks. It is defined in the IEEE 1149.1 standard.

In boundary scan test, each primary input and output signal on a device is
supplemented with a multi-purpose memory element called a boundary scan
cell. These cells are connected to a shift register, which is referred to as the
boundary scan register. This register can be used to read and write port states.

In normal mode, these cells are transparent, and the core is connected to the
ports. In boundary scan mode, the core is isolated from the ports and the port
signals are controlled by the JTAG interface.

Application Note

Contents

1 Overview......................................... 1

1.1 Boundary scan.............................1

1.2 JTAG Test Access Port (TAP)..... 2

1.3 BSDL introduction........................3

1.4 Downloading LPC55(S)xx BSDL

file................................................ 4

2 Setting up BSDL scan environment

........................................................ 4

2.1 JTAG tool.....................................4

2.2 Installing software........................ 4

2.3 Hardware connection diagram.....5

2.4 Setting LPC55(S)xx into boundary

scan mode................................... 6

3 BSDL file validation using JTAG Live

controller and JTAG Live Buzzer.... 7

3.1 Creating a new project by JTAG

Live Buzz..................................... 8

3.2 Infrastructure test.......................12

4 Reference......................................15

The following figure shows the principle of boundary scan chain.

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Overview

Figure 1. Boundary scan principle

1.2 JTAG Test Access Port (TAP)

The JTAG TAP is a general-purpose port and it can provide access to many test support functions built into the component. It has
four or five signals, as described in the following table. The TAP controller can be used for boundary scan as aforementioned by
using the JTAG pins.

Table 1. JTAG pin signal description

Signal Name I/O Type Description

TCK Input The test clock input provides the clock for the test logic.

Table continues on the next page...

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Overview

Table 1. JTAG pin signal description (continued)

Signal Name I/O Type Description

TMS Input The value of the signal presented as TMS at the time of a rising edge at TCK

determines the next state of the TAP controller.

TDI Input Serial test instructions and data are received by the test logic.

TDO Output Serial output for test instructions and data from the test logic.

TRST_N Input Optional active low signal to reset the TAP controller.

1.3 BSDL introduction

BSDL files are based on the syntax and grammar of VHDL (Very high-speed integrated-circuit Hardware Description Language).
They describe those aspects of the boundary scan implementation that are not defined by the standard. For example, it provides
the length of the instruction register (which is set by the device manufacturer), but not the length of the ID register (which the
standard mandates is 32 bits long). It gives information on which boundary scan cells connect to each pin, details of various
registers, and a description of the boundary scan cells themselves.

The following figure shows the main elements of a BSDL file (for simplicity, not all features are shown).

Figure 2. Main elements of a BSDL file

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Setting up BSDL scan environment

For more details about BSDL, see https://www.xjtag.com/about-jtag/bsdl-files/bsdl-and-svf-file-formats/.

1.4 Downloading LPC55(S)xx BSDL file

Users can download BSDL files from the following links:

LPC55(S)6x: https://www.nxp.com/downloads/en/bsdl/LPC55S6X-BSDL.zip

LPC55(S)2x: https://www.nxp.com/downloads/en/bsdl/LPC55S2X-BSDL.zip

LPC55(S)1x: https://www.nxp.com/downloads/en/bsdl/LPC55S1X-BSDL.zip

For the latest part, users can download the BSDL file from “Design Tools & Files” item in the “Tools & Software” quick link on this
part’s dedicate website in nxp.com.

2 Setting up BSDL scan environment

2.1 JTAG tool

In this application note, JTAG Live controller is used, which is USB connected and powered and features a single test access port
in JTAG Technologies standard pin-out. It offers a maximum programable TCK speed of 6 MHz and features programmable output
voltage and input thresholds. Users can purchase JTAG Live controller through the following link:

https://www.jtaglive.com/product/low-cost-usb-jtag-live-controller-interface/

The following figure shows the JTAG Live controller.

Figure 3. JTAG Live Controller

2.2 Installing software

The JTAG Live controller needs coordinate with PC software “JTAG Live Buzz”. The JTAG Live Buzz is downloadable from the
website JTAGLive.com.

The free software can be downloaded when the user provides registration to the site.

https://www.jtaglive.com/product/jtag-live-buzz/

Select the Download for free for the JTAG Live Buzz.

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Setting up BSDL scan environment

Figure 4. Download JTAG Live Buzz

2.3 Hardware connection diagram

The JTAG Live controller consists of:

• Universal debugger hardware

• Debug cable specific to the processor architecture

The following figure shows the schematic diagram of hardware connection

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