NXP AN10609-3 Technical data

AN10609_3

PN532 C106 application note

Rev. 1.2 — January 5, 2010 Application note

Document information

Info Content Keywords PN532C106, PN532 v1.6, Low Battery mode Abstract This document described

- functionalities of PN532

- changes between PN532C104 and PN532C106

NXP Semiconductors

PN532 C106 application note

Revision history

Rev Date Description

1.0 March 10, 2008 First draft of AN10609_2, PN532 application note, C106 appendix.

It is based on AN10609_1 rev 1.1

1.1 September 7, 2009 update on application diagrams: RX path

1.2 January 5, 2010 Merge PN532 C104 and PN532 C106 application note

Add PN532 C106 SPI workaround, add SPI waveforms

Add how to use PN532 to read new Mifare cards.

AN10609_3

Contact information

For additional information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com

Application note Rev. 1.2 — 1/14/2010 2 of 75

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1. Introduction

The PN532 is a highly integrated transmission module for contactless communication at

13.56 MHz including microcontroller functionality based on a 80C51 core with 40 Kbytes of ROM and 1 Kbyte of RAM.

The PN532 combines a modulation and demodulation concept completely integrated for different kinds of contactless communication methods and protocols at 13.56 MHz (particularly Near Field Communication NFC), with an easy-to-use firmware for the different supported modes and the required host interfaces.

The PN532 includes a switch to power an external SAM connected to S2C interface. It is controlled by the embedded firmware.

AN10609_3

PN532 C106 application note

HOST

CONTROLLER

Interface with host controller : SPI or I2C or HSU. Possibly one or two additional lines (H_REQ, IRQ).

PN532

antenna

RF communication

Fig 1. Simplified system view

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This document intends to allow the customer getting quickly started with the PN532. It summarizes commands needed to use the PN532 as a reader, as a card, or in a NFC peer-to-peer communication. It gives an overview on possible interfaces with the host controller.

Detailed description of the PN532 firmware can be found in the PN532 User manual (cf. References table below).

Full description of the PN532 IC can be found in the PN532 Datasheet.

This document underlines differences between PN532C104 (p revious version not produced anymore) and PN532C106.

The PN532C106 main differences compared with PN532C104:

“Low battery” mode is the start up mode of PN532C106. It is described page 21.

AN10609_3

PN532 C106 application note

- Possible host interface: HSU, I2C or SPI mode 0 (no more SPI mode 1, 2, 3)

- “Low battery” mode

References

Ref.number Document name

1 PN532 C106 user manual UM0701-02 2 PN532 Product Datasheet 115430.pdf 3 NFC Transmission Module Antenna and RF

100720.pdf

Design Guide 4 Desfire cards specification M075031.pdf 5 Mifare cards specification http://www.nxp.com/products/identification/datasheets/ 6 ISO/IEC 14443 specification (T=CL) ISO/IEC 14443-3 specification

ISO/IEC 14443-4 specification

7 NFCIP-1 specification ISO/IEC 18092 or ECMA340 specification

Glossary

NFC Near Field Communication HSU High Speed UART SMX Philips SmartMX (Memory Extension) PCR Power, Clock and Reset controller SAM Secure Access Module MINT Multiple Interfaces PMU Power Management Unit DEP Data Exchange Protocol (see reference 7)

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Pin correspondence: In the documents the following correspondence can be used in

the names of the pins:

AN10609_3

PN532 C106 application note

PN532 Datasheet name Application Note name

(C104 or C106) (C104 or C106)

P70_IRQ IRQ

P32_INT0 H_REQ

P50_SCL SCL

HSU_RX T_RX

HSU_TX T_TX

IC correspondence: In the documents the following correspondence can be used in the names of the IC:

Commercial Name Application Note name

PN5321A3HN/C106 PN532C106

P5CN072 SMX

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2. Interfaces with the host controller

2.1 PN532 block diagram

The PN532 is based on an 8051 core, with 40 Kbytes of ROM and 1Kbyte of RAM. The chip contains a contactless UART, a contactless front end, a “PCR” block that controls clocks and power.

It can be connected to the host controller in I2C, SPI or HSU (High Speed UART). One or two more lines (IRQ and H_REQ) can be added. The interface is selectable using I0 and I1 pins.

A SAM companion chip can be attached using S2C interface. A part of the IC can be powered directly from a mobile battery (VBAT between 2.7V and

5.4V). The Pad power supply (PVDD) must be between 1.6V and 3.6V. The SAM power supply SVDD is provided by the PN532.

AN10609_3

PN532 C106 application note

SCK or P72

MISO or P71

MOSI or SDA

or D- or Tx NSS or SCL

or D+ or Rx

RSTPD

SVDD (output)

power for SAM interface

VDD (1.6 V to 3.6V)

VBAT (2.7 to 5.4V)

P30 P31

HSU

MINT

LDO, power on reset

FIFO

SPI

Power

switch, regulator,

RS232

I2C

8051

PCR

(Power Clock and

Reset controller)

OSC 27.12MHz

Xtal

IRQP32 P33

ROM

40 kbyte

RAM

1 kbyte

I0 I1

ContactLess

UART

FIFO, Mifare

Classic Unit, Frame

generation and

check

ContactLess

Front End

RF Detector,

Demod, Antenna

driver

TX1 TX2

SIGIN

SIGOUT

P34

RX

LOADMOD

Fig 2. PN532 block diagram

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2.2 Hardware changes compared to PN532C104

2.2.1 Hardware configuration pins

At start up, the normal mode must be selected by connecting P35 and IRQ as defined below. The two other modes (RF field on and Emu Joiner) are special modes useful only for tests purposes.

No external resistors are required on P35 and IRQ pins.

Interface Selection Pin P35 IRQ

Normal mode 1 1

Normal mode 1 0

EmuJoiner 0 1

RF field On 0 0

(pin #19) (pin #25)

DVDD/VBAT PVDD

DVDD/VBAT GND

GND PVDD

GND GND

AN10609_3

PN532 C106 application note

Three interfaces are available: I2C, SPI and HSU (high speed UART). The interface is selectable by hardware (pin I0 and I1).

Interface Selection Pin I0 I1

(pin #16) (pin #17)

HSU 0 0

GND GND

I2C 1 0

DVDD GND

SPI 0 1

GND DVDD

The embedded software manages the communication with the host controller (I2C, SPI, or HSU interface, protocol on the host link) and the communication on the RF side.

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2.2.1.1 Additional lines (IRQ and H_REQ)

P31 is not used to choose between handshake or standard mode: PN532C106 implements only handshake mode, whatever P31 configuration (It can be let not connected).

2.2.1.2 SPI

Only SPI mode 0 is implemented in PN532C106. Consequently, P30 (pin 24) and P33 (pin 33) states don’t configure anymore the SPI mode. They can be let not connected

To stay in LowVbat mode, NSS must be kept in high state even when PVDD is not present (NSS low is a wake up condition).

2.3 Host link protocol

No changes compared to PN532C104. Refer to [1] and [8]

The protocol used on host link is fully described in the PN532 User manual (cf. References table on page 4)

AN10609_3

PN532 C106 application note

2.3.1 Standard frame

A basic exchange consists in a command frame sent by the host controller to the PN532, an ACK frame sent by the PN532 as soon as the command is correctly received, and a response frame, read by the host controller (polling mechanism or use of IRQ).

Fig 3. Normal exchange between host controller and the PN532

I

0 1

R Q

PN532Controller

C

o

m

a

n

d

P

a

c

k

e

t

K

C

A

et

k

c

a

P

e

s

n

o

p

s

e

R

A

C

K

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Command and response frame structure is shown in figure 3.

Fig 4. Information frame

¾ PREAMBLE 1 byte ¾ START CODE 2 bytes (00h and FFh)

AN10609_3

PN532 C106 application note

0000 LENFF TFILCS PD0 PD1 ……... DCSPDn 00

Postamble Packet Data Checksum Packet Data Specific PN532 Frame Identifier Packet Length Checksum Packet Length Start of Packet Code Preamble

¾ LEN 1 byte indicating the number of bytes in the data field

(TFI and PD0 to PDn)

¾ LCS 1 Packet Length Checksum LCS byte that satisfies the relation:

Lower byte of [LEN + LCS] = 00h

¾ TFI 1 byte the PN532 Frame Identifier, the value of this byte depends

on the way of the message

- D4h in case of a frame from the system controller to the the PN532

- D5h in case of a frame from the the PN532 to the system controller ¾ DATA LEN-1 bytes of Packet Data Information

The first byte PD0 is the Command Code

¾ DCS 1 Data Checksum DCS byte that satisfies the relation:

Lower byte of [TFI + PD0 + PD1 + … + PDn + DCS] = 00h

¾ POSTAMBLE 1 byte

ACK frame is described in figure 4.

0000 FF

FF00 00

Postamble ACK Packet Code Start of Packet Code Preamble

Fig 5. ACK frame

List of available commands (PD0 byte) is provided in paragraph

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3.2 on page 26.

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2.3.2 Extended frame

The information frame has an extended definition allowing exchanging more data between the host controller and the the PN532 (theoretically up to 64kB). In the firmware implementation of the the PN532, the maximum length of the packet data is limited to 264 bytes (265 bytes with TFI included).

The structure of this frame is the following:

AN10609_3

PN532 C106 application note

0000 FF TFILCS PD0 PD1 ……... DCSPDn 00

FF LEN

M

L

Normal Packet Length Checksum : Fixed to FF value Normal Packet Length : Fixed to FF value

Postamble Packet Data Checksum Packet Data Specific TFI Packet Length Checksum Packet Length Start of Packet Code Preamble

Fig 6. Extended Information frame

The normal LEN and LCS fields are fixed to the 0xFF value, which is normally considered as an erroneous frame, due to the fact that the checksum does not fit.

The real length is then coded in the two following bytes LEN

(MSByte) and LEN

M L

(LSByte) with: LENGTH = LEN

x 256 + LEN

M L

coding the number of bytes in the data field (TFI and

PD0 to PDn) ¾ LCS 1 Packet Length Checksum LCS byte that satisfies the relation:

Lower byte of [LEN

+ LEN + LCS] = 0x00,

M L

¾ DATA LENGTH-1 bytes of Packet Data Information

The first byte PD0 is the Command Code.

The host controller, for sending frame whose length is less than 255 bytes, can also use this type of frame. But, the the PN532 always uses the suitable type of frame, depending on the length (Normal Information Frame for frame <= 255 bytes and Extended Information Frame for frame > 255 bytes).

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2.4 Typical application diagrams

AN10609_3

PN532 C106 application note

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conductors

2.4.1 I2C application diagram

DVDD

100 nF

To antenna

DVDD

100 nF

To antenna

4.7 µF

100 nF

560nH

2.7 k

100 nF

1 nF

AN10609_3

PN532 C106 application note

DVDD

10 µF

100 nF

VBAT

1

D

G

N

T

G

N

TX1

TVDD

TX2

TGND2

AVDD

VMID

RX

2

3

1

D

4

5 6

7

8 9

10

Test point

LOADMOD

1 k

To SMX To SMX To SMX

VBAT

DVDD

RSTPDN

39 38 37 36 35 34 33 32 3140

AUX1

AUX2

AGND

Test point

27.12 MHz

100 nF

SVDD

XTAL1

SIGIN

PN532

XTAL2

DVDD

47 k

To SMX

SIGOUT

I0

P34

I1

NC

P33

P32

P31

30

SCK

29

MISO

28

MOSI

27

NSS

26

RSTOUTN

25

IRQ

24

P30

23

PVDD

22

NC3

21

NC2

20191817161514131211

P35

NC1

TESTEN

DVDD)

connected to

NC (internally

HREQ

NC NC

NC

PVDDPVDD

3.3 k 3.3k

SDA SCL

To host controller. Low state = reset. High state = functional mode. RSTPD_N must not exceed min(VBAT, 3.6V) (e.g. use a resistor

PVDD

100 nF

bridge on VBAT)

To Host controller

start up high (PVDD) or low

22 pF

Fig 7. I2C PN532C106 application diagram

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2.4.2 SPI communication

2.4.2.1 SPI and LowVbat mode

Using Low Vbat functionality and SPI interface requires the following work around.

1. In case LowVbat functionality is not required

Always keep PVDD (and Vbat) present. Proceed as described in paragraph 2.5.2

2. In case LowVbat functionality is required

The interface pins will be used to achieve LowVbat mode. Therefore they must be connected to the host controller.

Before switching off the host controller, change I0 to 1 and I1 to 0 (this put the PN532 in I2C configuration)

Host sends a reset pulse (minimum 20ns, see datasheet p209) to PN532 via RSTPD_N Wait a time off (2ms, see datasheet p209) The PN532 will go in LowVbat mode and stays in this mode (25µA)

AN10609_3

PN532 C106 application note

Î An external reader can communicate with the SMX as a card

To wake up the PN532 (to exit LowVbat mode) and recover SPI communication

Host controller change I0 to 0 and I1 to 1 (restore SPI configuration) Host controller sends a reset pulse (minimum 20ns) to PN532 via RSTPD_N Wait a time off (2 ms) Host controller sets NSS wake-up (high to low, CSN) Î SPI communication can be performed (e.g. send command SAMConfiguration ’14 01’ to

switch to standard mode).

When changing I0 and I1, the internal configuration of pins 27, 28, 29, 30 (interface lines) is changed. See table in paragraph 2.4.4 Default pin configuration.

Warning: It is also possible to switch to I0 and I1 to 0 (HSU). The advantage is that only I1 need to be toggle. But in this mode, pin 28 MOSI/TX is strongly push pulled to high by PN532, which can prevent the communication between the host controller and other chips on the SPI bus.

2.4.2.2 SPI application diagram

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DVDD

100 nF

To antenna

DVDD

100 nF

To antenna

4.7 µF

100 nF

560nH

2.7 k

100 nF

1 nF

AN10609_3

PN532 C106 application note

DVDD

10 µF

100 nF

VBAT

1

D

G

N

T

G

N

TX1

TVDD

TX2

TGND2

AVDD VMID

RX

2

3

1

D

4

5 6

7

8 9

10

Test point

LOADMOD

1 k

To SMX To SMX To SMX

VBAT

DVDD

RSTPDN

39 38 37 36 35 34 33 32 3140

AUX1

AUX2

AGND

Test point

27.12 MHz

100 nF

SVDD

XTAL1

SIGIN

PN532

XTAL2

47 k

To SMX

SIGOUT

I0I

NC

P34

P33

P32

P31

30

SCK

29

MISO

28

MOSI

27

NSS

26

RSTOUTN

25

IRQ

24

P30

23

PVDD

22

NC3

21

NC2

20191817161514131211

1

N

5 3

E

C

T

P

1

N S E T

o

lly

t

a

)

d

n

r

e

D

t

e

c

t

D

e

V

in

n

(

D

n

C

o c

N

NC

To host controller. Low state = reset. High

state = functional mode. RSTPD_N must not

exceed min(VBAT, 3.6V) (e.g. use resistor

bridge on VBAT)

To Host controller

To Host controller To Host controller

To Host controller

PVDD

start up high (PVDD) or low

100 nF

22 pF

Fig 8. SPI PN532C106 application diagram

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To Host controller

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2.4.2.3 SPI communication details

The PN532 is slave. A Status byte (Bit 0 of Status byte) indicates if the PN532 is ready to give a response or not. First byte sent on MOSI by the host controller indicates which operation will be performed:

xxxx xx10 : Read (by the host) Status byte xxxx xx01 : Write data (transmission from the host to the PN532) xxxx xx11 : Read data (transmission from the PN532 to the host) After having sent a command, the host controller must wait for bit 0 of Status byte equals 1 before reading

the data from the PN532. Bytes are transmitted LSB first. NSS must be toggle as shown in the user manual (reference 1) or in the next figures.

2.4.2.4 SPI waveforms

SPI waveforms for GetFirmware version command (example with SPI freq. 500 kHz).

AN10609_3

PN532 C106 application note

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AN10609_3

PN532 C106 application note

Fig 9. Write the command.

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AN10609_3

PN532 C106 application note

Fig 10. Read the Status.

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AN10609_3

PN532 C106 application note

Fig 11. Read the ACK frame.

Fig 12. Read the Status.

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AN10609_3

PN532 C106 application note

Fig 13. Read the Response frame.

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Application note 19 of 75

Rev 1.2 — 1/14/2010

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2.4.3 HSU application diagram

DVDD

100 nF

To antenna

DVDD

100 nF

To antenna

4.7 µF

100 nF

560nH

2.7 k

100 nF

1 nF

VBAT

1 k

DVDD

100 nF

D

G

LOADMOD

T

D

G

N

TX1

TVDD

TX2

TGND2

AVDD VMID

RX

AN10609_3

PN532 C106 application note

To host controller. Low state = reset. High state = functional mode. RSTPD_N must not exceed min(VBAT, 3.6V) (e.g. use a resistor

PVDD

100 nF

bridge on VBAT)

To Host controller

start up high (PVDD) or low

100 nF

SVDD

XTAL1

SIGIN

PN532

XTAL2

47 k

To SMX

SIGOUT

I0I

NC

P34

P33

P32

P31

30

SCK

29

MISO

28

MOSI

27

NSS

26

RSTOUTN

25

IRQ

24

P30

23

PVDD

22

NC3

21

NC2

20191817161514131211

1

N

5 3

E

C

T

P

1

N S E T

o

lly

t

a

)

d

n

r

e

D

t

e

c

t

D

e

V

in

n

(

D

n

C

o c

N

HREQ

NC NC

Tx Rx

NC

To SMX To SMX To S MX

10 µF

VBAT

DVDD

RSTPDN

39 38 37 36 35 34 33 32 3140

1

D

N

2

3

1

4 5

6 7 8 9

10

AUX1

AUX2

AGND

Test point

27.12 MHz

22 pF

Fig 14. HSU PN532C106 application diagram

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PN532 C106 application note

AN10609_3

2.4.4 Default pin configuration

Consequently, the default pin configuration is as described in the PN532 datasheet. (The default pin configuration is not changed by the PN532C106 firmware).

Pin Configuration Additional information

I0 Input Connect directly to DVDD or to GND (no need of I1

PVDD Power pin Externally supplied regulated voltage, 1.6V to 3.6V RSTPD_N Input NFC reset signal. (Low state = reset)

P30 / UART_RX Quasi bi directional No need of external resistor. P31 / UART_TX P32_INT0 P33_INT1 P34 / SIC_CLK P35

external resistor)

RSTPD_N must never exceed min(3.6 V, VBAT)

When connected to the P5CN072, to be used in Virtual Card mode, P34 / SIC_CLK shall be connected to P5CN072 I02

P70_IRQ Quasi bi directional No need of external resistor.

In the Application Note P70_IRQ will be written as IRQ when used as interrupt line.

In I2C mode: Quasi bi directional No need of external resistor. MISO / P71

MOSI / SDA / HSU_TX

NSS / P50_SCL / HSU_RX

In SPI: Push pull No need of external resistor In HSU: Quasi bi directional No need of external resistor In I2C mode: Quasi bi directional No need of external resistor. SCK / P72 In SPI: Input No need of external resistor. In HSU: Quasi bi directional No need of external resistor In I2C mode: Open drain Use pull up, 1k/V. E.g. for PVDD = 3.3V, 3.3 k pull-up. In SPI: Input No need of external resistor In HSU: Push pull No need of external resistor In I2C mode: Open drain Use pull up, 1k/V. E.g. for PVDD = 3.3V, 3.3 k pull-up. In SPI: Input

Use resistor bridge or LDO and pull up to be able

• to keep NSS high even when PVDD = 0 (to stay in LowV

• to force a low state to wake up.

mode)

BAT

In HSU: Input No need of external resistor

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AN10609_3

PN532 C106 application note

2.5 How to start the PN532C106?

2.5.1 LowVbat mode (PN532C106 start up default mode)

PN532C106 starts in “Low Vbat” mode. In this mode, the PN532C106 is in virtual card mode when an external field is present, and in power down mode otherwise. In this mode, an external reader can communicate with the SMX (connected to PN532C106 via its S2C interface).

¾ No interrupt (IRQ) will be returned by PN532C106 to its host controller. ¾ The host controller cannot wake up PN532 using HREQ/P32 line (pin 32).

This mode is functional even if PVDD = 0V. (V

LowV

diagram and power consumption:

BAT

between 2.7V and 5.5V)

BAT

Power-up the VBAT

of the PN532 C106

(PVDD = baseband supply

has no influence)

The PN532 is configured in the so-called

LowVbat mode

The functional mode of the PN532 is

Soft Power Down mode.

Its current consumption is ar ound 20uA.

PN532 C106 goes out of external fie l d

PN532 C106 goes into external RF field

The PN532 is configured in th e so-called

LowVbat mode

The functional mode of the PN532 in the field is

Card Emualtion mode.

Its current consumption is around 20mA .

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PN532 C106 application note

AN10609_3

2.5.2 To go out Low Vbat mode (i.e. to wake up PN532C106 after start up)

To go out “Low Vbat” mode, there are three conditions

• PVDD must be present.

• More over, to wake up the PN532C106, the host controller must

• In I2C

Send PN532 I2C address (48h). The PN532 will stretch low the SCL line during 1 ms (can be less depending on the quartz). The host controller shall wait for the end of the stretching.

• In SPI

Set NSS low during 1 ms (can be less depending on the quartz)

• In HSU

Send a preamble 55 55 00 00 00 00 00 FF then Len LCS ….

• The ho st controller must send one of the following commands (using the wake up conditions described just above)

− Either it wants to stay in virtual card mode. Then it shall send a command to

enable the interrupt generation (IRQ) by PN532C106. (The IRQ warns the host

controller that a transaction occurred between an external reader and the SMX). The command to send is “SAM Configuration” with parameter Mode = virtual (02h) and parameter IRQ use = yes (either put value 01h or omit the parameter). So the command is ‘14 02 00’ (or ‘14 02 00 01’)

− Or it wants to go to normal mode. Then it shall send “SAM Configuration” with

parameter Mode = normal (01h). So the command is ‘14 01’

Once woken up, any command can be send like in PN532C104 (with handshake mode)

NB: As soon as PVDD is present, the host controller must send a command to enable the interrupt generation (IRQ) by PN532C106. (The IRQ warns the host controller that a transaction occurred between an external reader and the SMX). The command to send is “SAM Configuration” with parameter Mode = virtual

(02h) and parameter IRQ use = yes (either put value 01h or omit the parameter) 14 02 00 (or 14 02 00 01)

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NXP AN10609-3 Technical data

Specifications and Main Features

Frequently Asked Questions

User Manual

1. Introduction

2. Interfaces with the host controller

2.1 PN532 block diagram

2.2 Hardware changes compared to PN532C104

2.2.1 Hardware configuration pins

2.2.1.1 Additional lines (IRQ and H_REQ)

2.2.1.2 SPI

2.3 Host link protocol

2.3.1 Standard frame

2.3.2 Extended frame

2.4 Typical application diagrams

2.4.1 I2C application diagram

2.4.2 SPI communication

2.4.2.1 SPI and LowVbat mode

2.4.2.2 SPI application diagram

2.4.2.3 SPI communication details

2.4.2.4 SPI waveforms

2.4.3 HSU application diagram

2.4.4 Default pin configuration

2.5 How to start the PN532C106?

2.5.1 LowVbat mode (PN532C106 start up default mode)

2.5.2 To go out Low Vbat mode (i.e. to wake up PN532C106 after start up)