Data sheet acquired from Harris Semiconductor
/
SCHS126A
February 1998 - Revised May 2000
CD54/74HC03,
CD54/74HCT03
High Speed CMOS Logic
Quad 2-Input NAND Gate with Open Drain
[ /Title
(CD74H
C03,
CD74H
CT03)
Subject
(High
Speed
CMOS
Logic
Quad 2Input
Features
• Buffered Inputs
• Typical Propagation Delay: 8ns at V
C
= 15pF, TA = 25oC
L
• Output Pull-up to 10V
• Fanout (Over Temperature Range)
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• HC Types
- 2V to 6V Operation
- High Noise Immunity: N
= 30%, NIH = 30% of V
IL
at VCC = 5V
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
V
= 0.8V (Max), VIH = 2V (Min)
IL
- CMOS Input Compatibility, I
≤ 1µA at VOL, V
l
CC
= 5V,
o
C to 125oC
OH
Description
The ’HC03and ’HCT03 logic gates utilize silicon gate CMOS
technology to achieve operating speeds similar to LSTTL
gates with the low power consumption of standard CMOS
integrated circuits. All devices have the ability to drive 10
LSTTL loads. The HCT logic family is functionally as well as
pin compatible with the standard LS logic family.
These open drain NAND gates can drive into resistive loads
to output voltages as high as 10V. Minimum values of R
required versus load voltage are shown in Figure 2.
Ordering Information
TEMP. RANGE
CC
PART NUMBER
CD54HC03F -55 to 125 14 Ld CERDIP
CD54HC03F3A -55 to 125 14 Ld CERDIP
CD74HC03E -55 to 125 14 Ld PDIP
CD74HC03M -55 to 125 14 Ld SOIC
CD54HCT03F3A -55 to 125 14 Ld CERDIP
CD74HCT03E -55 to 125 14 Ld PDIP
CD74HCT03M -55 to 125 14 Ld SOIC
NOTES:
1. When ordering, use the entire part number. Add the suffix 96 to
obtain the variant in the tape and reel.
2. Wafer and die for this part number is available which meets all
electrical specifications. Please contact your local TI sales office
or customer service for ordering information.
(oC) PACKAGE
L
Pinout
CD54HC03, CD54HCT03
(CERDIP)
CD74HC03, CD74HCT03
(PDIP, SOIC)
TOP VIEW
1A
1
2
1B
3
1Y
4
2A
5
2B
6
2Y
7
GND
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright
© 2000, Texas Instruments Incorporated
14
V
CC
4B
13
12
4A
4Y
11
3B
10
3A
9
3Y
8
1
Functional Diagram
CD54/74HC03, CD54/74HCT03
1
1A
2
1B
4
2A
5
2B
9
3A
10
3B
12
4A
13
4B
AB Y
L L Z (Note 4) H (Note 3)
H L Z (Note 4) H (Note 3)
L H Z (Note 4) H (Note 3)
HHLL
NOTES:
3. Requires pull-up (RL to VL)
4. Without pull-up (high impedance)
TRUTH TABLE
3
6
8
11
GND = 7
V
CC
1Y
2Y
3Y
4Y
= 14
Logic Symbol
nA
nB
nY
2
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