NXP 74HC 86D NXP Datasheet

74HC86; 74HCT86

Quad 2-input EXCLUSIVE-OR gate

Rev. 3 — 27 August 2012 Product data sheet

1. General description

The 74HC86; 74HCT86 are high-speed Si-gate CMOS devices that comply with JEDEC
standard no. 7A. They are pin compatible with Low-power Schottky TTL (LSTTL).

The 74HC86; 74HCT86 provides a 2-input EXCLUSIVE-OR function.

2. Features and benefits

 Input levels:

 For 74HC86: CMOS level
 For 74HCT86: TTL level

 ESD protection:

 HBM JESD22-A114F exceeds 2000 V

 MM JESD22-A115-A exceeds 200 V
 Multiple package options
 Specifie d from 40 C to +85 C and from 40 C to +125 C

3. Ordering information

Table 1. Ordering information

Type number Package

Temperature range Name Description Version

74HC86N 40 C to +125 C DIP14 plastic dual in-line package; 14 leads (300 mil) SOT27-1
74HCT86N
74HC86D 40 C to +125 C SO14 plastic small outline package; 14 leads; body width
74HCT86D
74HC86DB 40 C to +125 C SSOP14 plastic shrink small outline package; 14 leads; body
74HCT86DB
74HC86PW 40 C to +125 C TSSOP14 plastic thin shrink small outline package; 14 leads;
74HCT86PW

SOT108-1

3.9 mm
SOT337-1

width 5.3 mm

SOT402-1

body width 4.4 mm

NXP Semiconductors

mna787

1A
1B

1Y

2

1

3

2A
2B

2Y

5

4

6

3A
3B

3Y

10

9

8

4A
4B

4Y

13

12

11

mna788

Y

A

B

mna786

3

=1

=1

=1

=1

2

1

6

5

4

8

10

9

11

13

12

4. Functional diagram

Fig 1. Logic symbol

74HC86; 74HCT86

Quad 2-input EXCLUSIVE-OR gate

Fig 2. Logic diagram (one gate) Fig 3. IEC logic symbol

74HC_HCT86 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.

Product data sheet Rev. 3 — 27 August 2012 2 of 16

NXP Semiconductors

86

1A V

CC

1B 4B

1Y 4A

2A 4Y

2B 3B

2Y 3A

GND 3Y

001aad103

1

2

3

4

5

6

7 8

10

9

12

11

14

13

5. Pinning information

5.1 Pinning

Fig 4. Pin configuration DIP14, SO14 and (T)SSOP14

74HC86; 74HCT86

Quad 2-input EXCLUSIVE-OR gate

5.2 Pin description

Table 2. Pin description

Symbol Pin Description

1A to 4A 1, 4, 9, 12 data input
1B to 4B 2, 5, 10, 13 data input
1Y to 4Y 3, 6, 8, 11 data output
GND 7 ground (0 V)
V

CC

14 supply voltage

6. Functional description

Table 3. Function table

Input nA Input nB Output nY

LLL
LHH
HLH
HHL

[1] H = HIGH voltage level;

L = LOW voltage level.

[1]

74HC_HCT86 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.

Product data sheet Rev. 3 — 27 August 2012 3 of 16

NXP Semiconductors

7. Limiting values

74HC86; 74HCT86

Quad 2-input EXCLUSIVE-OR gate

Table 4. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).

Symbol Parameter Conditions Min Max Unit

V
I

IK

I

OK

I

O

I

CC

I

GND

T
P

CC

stg
tot

supply voltage 0.5 +7 V
input clamping current VI < 0.5 V or VI>VCC+0.5 V
output clamping current VO< 0.5 V or VO>VCC+0.5V

[1]

- 20 mA

[1]

- 20 mA
output current 0.5 V < VO < VCC+0.5V - 25 mA
supply current - 50 mA
ground current 50 - mA
storage temperature 65 +150 C
total power dissipation

[2]

DIP14 package - 750 mW
SO14, and (T)SSOP14

- 500 mW

packages

[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For DIP14 package: P

For SO14 package: P
For (T)SSOP14 packages: P

derates linearly with 12 mW/K above 70 C.

tot

derates linearly with 8 mW/K above 70 C.

tot

derates linearly with 5.5 mW/K above 60 C.

tot

8. Recommended operating conditions

Table 5. Recommended operating conditions

Voltages are referenced to GND (ground = 0 V)

Symbol Parameter Conditions 74HC86 74HCT86 Unit

Min Typ Max Min Typ Max

V

CC

V

I

V

O

T

amb

t/V input transition rise and fall rate V

supply voltage 2.0 5.0 6.0 4.5 5.0 5.5 V
input voltage 0 - V
output voltage 0 - V

0- VCCV

CC

0- VCCV

CC

ambient temperature 40 +25 +125 40 +25 +125 C

= 2.0 V - - 625 - - - ns/V

CC

= 4.5 V - 1.67 139 - 1.67 139 ns/V

V

CC

= 6.0 V--83---ns/V

V

CC

74HC_HCT86 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.

Product data sheet Rev. 3 — 27 August 2012 4 of 16

NXP Semiconductors

9. Static characteristics

74HC86; 74HCT86

Quad 2-input EXCLUSIVE-OR gate

Table 6. Static characteristics

At recommended operating conditions; voltages are referenced to GND (ground = 0 V).

Symbol Parameter Conditions 25 C 40 C to +85 C 40 C to +125 C Unit

Min Typ Max Min Max Min Max

74HC86

V

IH

HIGH-level
input voltage

V

IL

LOW-level
input voltage

V

OH

HIGH-level
output voltage

V

OL

LOW-level
output voltage

I

I

input leakage
current

I

CC

supply current VI = VCC or GND; IO=0A;

VCC = 2.0 V 1.5 1.2 - 1.5 - 1.5 - V

= 4.5 V 3.15 2.4 - 3.15 - 3.15 - V

V

CC

= 6.0 V 4.2 3.2 - 4.2 - 4.2 - V

V

CC

VCC = 2.0 V - 0.8 0.5 - 0.5 - 0.5 V

= 4.5 V - 2.1 1.35 - 1.35 - 1.35 V

V

CC

= 6.0 V - 2.8 1.8 - 1.8 - 1.8 V

V

CC

VI = VIH or V

IL

IO = 20 A; VCC = 2.0 V 1.9 2.0 - 1.9 - 1.9 - V

= 20 A; VCC = 4.5 V 4.4 4.5 - 4.4 - 4.4 - V

I

O

= 20 A; VCC = 6.0 V 5.9 6.0 - 5.9 - 5.9 - V

I

O

= 4.0 mA; VCC = 4.5 V 3.98 4.32 - 3.84 - 3.7 - V

I

O

= 5.2 mA; VCC = 6.0 V 5.48 5.81 - 5.34 - 5.2 - V

I

O

VI = VIH or V

IL

IO = 20 A; VCC = 2.0 V - 0 0.1 - 0.1 - 0.1 V
I

= 20 A; VCC = 4.5 V - 0 0.1 - 0.1 - 0.1 V

O

= 20 A; VCC = 6.0 V - 0 0.1 - 0.1 - 0.1 V

I

O

= 4.0 mA; VCC = 4.5 V - 0.15 0.26 - 0.33 - 0.4 V

I

O

= 5.2 mA; VCC = 6.0 V - 0.16 0.26 - 0.33 - 0.4 V

I

O

VI = VCC or GND;

=6.0V

V

CC

--0.1 - 1-1 A

--2.0- 20 - 40A

VCC=6.0V

C

I

input

-3.5- - - - -pF

capacitance

74HCT86

V

IH

HIGH-level

VCC = 4.5 V to 5.5 V 2.0 1.6 - 2.0 - 2.0 - V

input voltage

V

IL

LOW-level

VCC = 4.5 V to 5.5 V - 1.2 0.8 - 0.8 - 0.8 V

input voltage

V

OH

HIGH-level
output voltage

V

OL

LOW-level
output voltage

I

I

input leakage
current

VI = VIH or VIL; VCC = 4.5 V

= 20 A 4.4 4.5 - 4.4 - 4.4 - V

I

O

= 4.0 mA 3.98 4.32 - 3.84 - 3.7 - V

I

O

VI = VIH or VIL; VCC = 4.5 V

= 20 A - 0 0.1 - 0.1 - 0.1 V

I

O

= 5.2 mA - 0.15 0.26 - 0.33 - 0.4 V

I

O

VI = VCC or GND;

=5.5V

V

CC

--0.1 - 1-1 A

74HC_HCT86 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.

Product data sheet Rev. 3 — 27 August 2012 5 of 16

NXP Semiconductors

74HC86; 74HCT86

Quad 2-input EXCLUSIVE-OR gate

Table 6. Static characteristics

…continued

At recommended operating conditions; voltages are referenced to GND (ground = 0 V).

Symbol Parameter Conditions 25 C 40 C to +85 C 40 C to +125 C Unit

Min Typ Max Min Max Min Max

I

CC

supply current VI = VCC or GND; IO=0A;

--2.0- 20 - 40A

VCC=5.5V

I

CC

additional
supply current

per input pin;
VI=VCC 2.1 V; IO=0A;
other inputs at V

or GND;

CC

- 100 360 - 450 - 490 A

VCC= 4.5 V to5.5 V

C

I

input

-3.5- - - - -pF

capacitance

10. Dynamic characteristics

Table 7. Dynamic characteristics

GND = 0 V; C

= 50 pF; for load circuit see Figure 6.

L

Symbol Parameter Conditions 25 C 40 C to +125 C Unit

74HC86

t

pd

t

t

C

PD

propagation delay nA, nB to nY; see Figure 5

transition time see Figure 5

power dissipation
capacitance

VCC = 2.0 V - 39 120 150 180 ns

= 4.5 V - 14 24 30 36 ns

V

CC

= 5.0 V; CL=15pF - 11 - - - ns

V

CC

= 6.0 V - 11 20 26 31 ns

V

CC

VCC = 2.0 V - 19 75 95 110 ns

= 4.5 V - 7 15 19 22 ns

V

CC

= 6.0 V - 6 13 16 19 ns

V

CC

per package; VI=GNDtoV

CC

Min Typ Max Max

(85 C)

[1]

[2]

[3]

-30- - -pF

Max

(125 C)

74HC_HCT86 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.

Product data sheet Rev. 3 — 27 August 2012 6 of 16

NXP Semiconductors

001aai814

nA, nB input

V

I

GND

V

OH

V

OL

nY output

t

THL

t

TLH

V

M

V

M

V

X

V

Y

t

PHL

t

PLH

74HC86; 74HCT86

Quad 2-input EXCLUSIVE-OR gate

Table 7. Dynamic characteristics …continued

GND = 0 V; CL= 50 pF; for load circuit see Figure 6.

Symbol Parameter Conditions 25 C 40 C to +125 C Unit

74HCT86

t

pd

t

t

C

PD

propagation delay nA, nB to nY; see Figure 5

VCC = 4.5 V - 17 32 40 48 ns

= 5.0 V; CL=15pF - 14 - - - ns

V

CC

transition time VCC = 4.5 V; see Figure 5
power dissipation

capacitance

per package;
VI=GNDtoVCC 1.5 V

Min Typ Max Max

(85 C)

[1]

[2]

- 7 15 19 22 ns

[3]

-30- - -pF

Max

(125 C)

[1] tpd is the same as t
[2] t

is the same as t

t

[3] C

is used to determine the dynamic power dissipation (PD in W):

PD

P
f

i

f

o

C
V

 V

D=CPD

= input frequency in MHz;
= output frequency in MHz;

= output load capacitance in pF;

L

= supply voltage in V;

CC

PHL

and t

THL

2

 fi N+ (CL V

CC

N = number of inputs switching;

2

 V

 (C

L

 fo) = sum of outputs.

CC

11. Waveforms

and t

TLH

PLH

.

.

2

 fo) where:

CC

Measurement points are given in Table 9.
V

and VOH are typical voltage output levels that occur with the output load.

OL

Fig 5. Input to output propagation delay s

Table 8. Measurement points

Type Input Output

V

M

74HC86 0.5V

CC

74HCT86 1.3 V 1.3 V 0.1V

74HC_HCT86 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.

Product data sheet Rev. 3 — 27 August 2012 7 of 16

V

M

0.5V

CC

V

X

0.1V

CC
CC

V

Y

0.9V

0.9V

CC
CC

NXP Semiconductors

001aah768

t

W

t

W

t

r

t

r

t

f

V

M

V

I

negative

pulse

GND

V

I

positive

pulse

GND

10 %

90 %

90 %

10 %

V

M

V

M

V

M

t

f

V

CC

DUT

R

T

V

I

V

O

C

L

G

Test data is given in Table 9.
Definitions test circuit:

= termination resistance should be equal to output impedance Zo of the pulse generator.

R

T

C

= load capacitance including jig and probe capacitance.

L

Fig 6. Load circuitry for measuring switching times

74HC86; 74HCT86

Quad 2-input EXCLUSIVE-OR gate

Table 9. Test data

Type Input Load Test

V

I

74HC86 V

CC

74HCT86 3.0 V 6.0 ns 15 pF, 50 pF t

74HC_HCT86 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.

Product data sheet Rev. 3 — 27 August 2012 8 of 16

tr, t

f

C

L

6.0 ns 15 pF, 50 pF t

PLH
PLH

, t

PHL

, t

PHL

NXP Semiconductors

UNIT

A

max.

1 2

(1) (1)

b

1

cD

(1)

Z

Ee M

H

L

REFERENCES

OUTLINE
VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC JEDEC JEITA

mm

inches

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

SOT27-1

99-12-27
03-02-13

A

min.

A

max.

b

max.

w

M

E

e

1

1.73

1.13

0.53

0.38

0.36

0.23

19.50

18.55

6.48

6.20

3.60

3.05

0.2542.54 7.62

8.25

7.80

10.0

8.3

2.24.2 0.51 3.2

0.068

0.044

0.021

0.015

0.77

0.73

0.014

0.009

0.26

0.24

0.14

0.12

0.010.1 0.3

0.32

0.31

0.39

0.33

0.0870.17 0.02 0.13

050G04 MO-001 SC-501-14

M

H

c

(e )

1

M

E

A

L

seating plane

A

1

w M

b

1

e

D

A

2

Z

14

1

8

7

b

E

pin 1 index

0 5 10 mm

scale

Note

1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.

DIP14: plastic dual in-line package; 14 leads (300 mil)

SOT27-1

12. Package outline

74HC86; 74HCT86

Quad 2-input EXCLUSIVE-OR gate

Fig 7. Package outline SOT27-1 (DIP14)

74HC_HCT86 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.

Product data sheet Rev. 3 — 27 August 2012 9 of 16

NXP Semiconductors

UNIT

A

max.

A1A2A

3

b

p

cD

(1)E(1)

(1)

eHELLpQZywv θ

REFERENCES

OUTLINE
VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC JEDEC JEITA

mm

inches

1.75

0.25

0.10

1.45

1.25

0.25

0.49

0.36

0.25

0.19

8.75

8.55

4.0

3.8

1.27

6.2

5.8

0.7

0.6

0.7

0.3

8
0

o
o

0.25 0.1

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

Note

1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.

1.0

0.4

SOT108-1

X

w M

θ

A

A

1

A

2

b

p

D

H

E

L

p

Q

detail X

E

Z

e

c

L

v M

A

(A )

3

A

7

8

1

14

y

076E06 MS-012

pin 1 index

0.069

0.010

0.004

0.057

0.049

0.01

0.019

0.014

0.0100

0.0075

0.35

0.34

0.16

0.15

0.05

1.05

0.041

0.244

0.228

0.028

0.024

0.028

0.012

0.01

0.25

0.01 0.004

0.039

0.016

99-12-27
03-02-19

0 2.5 5 mm

scale

SO14: plastic small outline package; 14 leads; body width 3.9 mm

SOT108-1

74HC86; 74HCT86

Quad 2-input EXCLUSIVE-OR gate

Fig 8. Package outline SOT108-1 (SO14)

74HC_HCT86 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.

Product data sheet Rev. 3 — 27 August 2012 10 of 16

NXP Semiconductors

UNIT A1A2A3b

p

cD

(1)E(1)

eHELLpQZywv θ

REFERENCES

OUTLINE
VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC JEDEC JEITA

mm

0.21

0.05

1.80

1.65

0.25

0.38

0.25

0.20

0.09

6.4

6.0

5.4

5.2

0.65 1.25 0.2

7.9

7.6

1.03

0.63

0.9

0.7

1.4

0.9

8
0

o
o

0.13 0.1

DIMENSIONS (mm are the original dimensions)

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

SOT337-1

99-12-27
03-02-19

(1)

w M

b

p

D

H

E

E

Z

e

c

v M

A

X

A

y

1

7

14

8

θ

A

A

1

A

2

L

p

Q

detail X

L

(A )

3

MO-150

pin 1 index

0 2.5 5 mm

scale

SSOP14: plastic shrink small outline package; 14 leads; body width 5.3 mm

SOT337-1

A

max.

2

74HC86; 74HCT86

Quad 2-input EXCLUSIVE-OR gate

Fig 9. Package outline SOT337-1 (SSOP14)

74HC_HCT86 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.

Product data sheet Rev. 3 — 27 August 2012 11 of 16

NXP Semiconductors

UNIT A1A2A

3

b

p

cD

(1)E(2) (1)

eHELLpQZywv θ

REFERENCES

OUTLINE
VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC JEDEC JEITA

mm

0.15

0.05

0.95

0.80

0.30

0.19

0.2

0.1

5.1

4.9

4.5

4.3

0.65

6.6

6.2

0.4

0.3

0.72

0.38

8
0

o
o

0.13 0.10.21

DIMENSIONS (mm are the original dimensions)

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

0.75

0.50

SOT402-1 MO-153

99-12-27
03-02-18

w M

b

p

D

Z

e

0.25

17

14

8

θ

A

A

1

A

2

L

p

Q

detail X

L

(A )

3

H

E

E

c

v M

A

X

A

y

0 2.5 5 mm

scale

TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm

SOT402-1

A

max.

1.1

pin 1 index

74HC86; 74HCT86

Quad 2-input EXCLUSIVE-OR gate

Fig 10. Package outline SOT402-1 (TSSOP14)

74HC_HCT86 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.

Product data sheet Rev. 3 — 27 August 2012 12 of 16

NXP Semiconductors

13. Abbreviations

74HC86; 74HCT86

Quad 2-input EXCLUSIVE-OR gate

Table 10. Abbreviations

Acronym Description

CMOS Complementary Metal-Oxide Semiconductor
DUT Device Under Test
ESD ElectroStatic Discharge
HBM Human Body Model
LSTTL Low-power Schottky Transistor-Transistor Logic
MM Machine Model
TTL Transistor-Transistor Logic

14. Revision history

Table 11. Revision history

Document ID Release da te Data sheet status Change notice Supersedes

74HC_HCT86 v.3 20120827 Product data sheet - 74HC_HCT86_CNV v.2
Modifications:

74HC_HCT86_CNV v.2 19970918 Product specification - -

• The format of this data sheet has been redesigned to comply with the new identity guidelines

of NXP Semiconductors.

• Legal texts have been adapted to the new company name where appropriate.

74HC_HCT86 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.

Product data sheet Rev. 3 — 27 August 2012 13 of 16

NXP Semiconductors

74HC86; 74HCT86

Quad 2-input EXCLUSIVE-OR gate

15. Legal information

15.1 Data sheet status

Document status

Objective [short] data sheet Development This document contains data from the objective specification for product development.
Preliminary [short] data sheet Qualification This document contains data from the preliminary specification.
Product [short] data sheet Production This document contains the product specification.

[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of device(s) d escribed i n this docu ment may have changed si nce this d ocument was p ublished and may dif fer in case of multiple devices. The latest product statu s

information is available on the Internet at URL http://www.nxp.com.

[1][2]

Product status

[3]

Definition

15.2 Definitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to co nt ain det ailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.

Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.

15.3 Disclaimers

Limited warranty and liability — Information in this document is believed to

be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.

In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.

Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semi conductors’ aggregat e and cumulative liabil ity towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.

Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.

74HC_HCT86 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.

Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the cust omer’s own
risk.

Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.

Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.

NXP Semiconductors does not accept any liability related to any default ,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third part y
customer(s). NXP does not accept any liability in this respect.

Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.

Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.

No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell product s that is open for accept ance or the gr ant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.

, unless otherwise

Product data sheet Rev. 3 — 27 August 2012 14 of 16

NXP Semiconductors

74HC86; 74HCT86

Quad 2-input EXCLUSIVE-OR gate

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior
authorization from competent authorities.

Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It i s neit her qua lif ied nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.

In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, custome r
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond

NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, da mages or failed produ ct claims result ing from custome r design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.

Translations — A non-English (t ranslated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.

15.4 Trademarks

Notice: All referenced brands, prod uct names, service names and trademarks
are the property of their respective owners.

16. Contact information

For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [e-mail]

74HC_HCT86 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.

Product data sheet Rev. 3 — 27 August 2012 15 of 16

NXP Semiconductors

17. Contents

1 General description. . . . . . . . . . . . . . . . . . . . . . 1

2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1

3 Ordering information. . . . . . . . . . . . . . . . . . . . . 1

4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2

5 Pinning information. . . . . . . . . . . . . . . . . . . . . . 3

5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3

6 Functional description . . . . . . . . . . . . . . . . . . . 3

7 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4

8 Recommended operating conditions. . . . . . . . 4

9 Static characteristics. . . . . . . . . . . . . . . . . . . . . 5

10 Dynamic characteristics . . . . . . . . . . . . . . . . . . 6

11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9

13 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 13

14 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 13

15 Legal information. . . . . . . . . . . . . . . . . . . . . . . 14

15.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 14

15.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

15.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

15.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 15

16 Contact information. . . . . . . . . . . . . . . . . . . . . 15

17 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

74HC86; 74HCT86

Quad 2-input EXCLUSIVE-OR gate

Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.

© NXP B.V. 2012. All rights reserved.

For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [e-mail]

Date of release: 27 August 2012

Document identifier: 74HC_HCT86