NXP 74HC 73N NXP Datasheet

74HC73

Dual JK flip-flop with reset; negative-edge trigger

Rev. 03 — 12 November 2004 Product data sheet

1. General description

The 74HC73 is a high-speed Si-gate CMOS device and is pin compatible with low-power
Schottky TTL (LSTTL). The 74HC73 is specified in compliance with JEDEC
standard no. 7A.

The 74HC is a dual negative-edge triggered JK flip-flop featuring individual J, K, clock
(nCP) and reset (nR) inputs; also complementary nQ and nQ outputs.

The J and K inputs must be stable one set-up time prior to the HIGH-to-LOW clock
transition for predictable operation.

The reset (nR) is an asynchronous active LOW input. When LOW, it overrides the clock
and data inputs, forcing the nQ output LOW and the nQ output HIGH.

Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock
rise and fall times.

2. Features

■ Low-power dissipation

■ Complies with JEDEC standard no. 7A

■ ESD protection:

◆ HBM EIA/JESD22-A114-B exceeds 2000 V

◆ MM EIA/JESD22-A115-A exceeds 200 V.

■ Multiple package options

■ Specified from −40 °Cto+80°C and from −40 °C to +125 °C.

Philips Semiconductors

3. Quick reference data

Table 1: Quick reference data

GND = 0 V; T

Symbol Parameter Conditions Min Typ Max Unit

, t

t

PHL

f

max

C

I

C

PD

amb

PLH

74HC73

Dual JK flip-flop with reset; negative-edge trigger

=25°C; tr=tf= 6 ns.

propagation delay CL= 15 pF; VCC=5 V - -

CP to nQ - 16 - ns

n

CP to nQ - 16 - ns

n

R to nQ, nQ - 15 - ns

n

maximum clock
frequency

input capacitance - 3.5 - pF
power dissipation

capacitance per flip-flop

CL= 15 pF; VCC= 5 V - 77 - MHz

VI= GND to V

CC

[1]

-30-pF

[1] CPD is used to determine the dynamic power dissipation (PD in µW).

PD=CPD× V
fi= input frequency in MHz;
fo= output frequency in MHz;
CL= output load capacitance in pF;
VCC= supply voltage in V;
N =number of inputs switching;
∑(CL× V

2

× fi× N+∑(CL× V

CC

2

× fo) = sum of outputs.

CC

2

× fo) where:

CC

4. Ordering information

Table 2: Ordering information

Type number Package

Temperature range Name Description Version

74HC73N −40 °C to +125 °C DIP14 plastic dual in-line package; 14 leads (300 mil) SOT27-1
74HC73D −40 °C to +125 °C SO14 plastic small outline package; 14 leads; body width 3.9 mm SOT108-1
74HC73DB −40 °C to +125 °C SSOP14 plastic shrink small outline package; 14 leads; body width

5.3 mm

74HC73PW −40 °C to +125 °C TSSOP14 plastic thin shrink small outline package; 14 leads; body

width 4.4 mm

SOT337-1

SOT402-1

9397 750 13815 © Koninklijke Philips Electronics N.V. 2004. All rights reserved.

Product data sheet Rev. 03 — 12 November 2004 2 of 21

Philips Semiconductors

5. Functional diagram

74HC73

Dual JK flip-flop with reset; negative-edge trigger

Fig 1. Functional diagram

1J14

J

2J7

CP

K

1R

FF

R

2R

26

1CP1
2CP5

1K3
2K

10

1Q 12

Q

2Q 9

1Q 13

Q

2Q 8

001aab979

R

R

001aab981

1Q 121J14

Q

1Q 13

Q

2Q 92J7

Q

2Q 8

Q

4

1J

1

C1

3

1K

2

R

7

1J

5

C1

10

1K

6

R

001aab980

12

13

9

8

J

1CP1

1K3

1R2

2CP5

2K10

2R6

FF1

CP

K

J

FF2

CP

K

Fig 2. Logic symbol Fig 3. IEC logic symbol

9397 750 13815 © Koninklijke Philips Electronics N.V. 2004. All rights reserved.

Product data sheet Rev. 03 — 12 November 2004 3 of 21

Philips Semiconductors

74HC73

Dual JK flip-flop with reset; negative-edge trigger

K

J

R

CP

Fig 4. Logic diagram (one flip-flop)

6. Pinning information

6.1 Pinning

C

C

C

C

1CP 1J

1R 1Q

1K 1Q

C

C

1

2

3

14

13

12

C

C

001aab982

C

Q

C

Q

4

V

CC

5

2CP 2K

6

2R 2Q

7 8

2J 2Q

73

001aab978

Fig 5. Pin configuration

6.2 Pin description

Table 3: Pin description

Symbol Pin Description

CP 1 clock input for flip-flop 1 (HIGH-to-LOW, edge-triggered)

1

R 2 asynchronous reset input for flip-flop 1 (active LOW)

1
1K 3 synchronous K input for flip-flop 1
V

CC

CP 5 clock input for flip-flop 2 (HIGH-to-LOW, edge-triggered)

2

R 6 asynchronous reset input for flip-flop 2 (active LOW)

2
2J 7 synchronous J input for flip-flop 2

Q 8 complement flip-flop 2 output

2
2Q 9 true flip-flop 2 output
2K 10 synchronous K input for flip-flop 2

4 positive supply voltage

11

GND

10

9

9397 750 13815 © Koninklijke Philips Electronics N.V. 2004. All rights reserved.

Product data sheet Rev. 03 — 12 November 2004 4 of 21

Philips Semiconductors

74HC73

Dual JK flip-flop with reset; negative-edge trigger

Table 3: Pin description

Symbol Pin Description

GND 11 ground (0 V)
1Q 12 true flip-flop 1 output

Q 13 complement flip-flop 1 output

1
1J 14 synchronous J input for flip-flop 1

7. Functional description

7.1 Function table

Table 4: Function table

Input Output Operating mode
nR nCP nJ nK nQ nQ

L X X X L H asynchronous reset
H ↓ hh

[1] H = HIGH voltage level;

h = HIGH voltage level one set-up time prior to the HIGH-to-LOW CP transition;
L = LOW voltage level;
I = LOW voltage level one set-up time prior to the HIGH-to-LOW CP transition;
q = state of referenced output one set-up time prior to the HIGH-to-LOW CP transition;
X = don’t care;
↓ = HIGH-to-LOW CP transition.

…continued

[1]

q q toggle
l h L H load 0 (reset)
h l H L load 1 (set)
llq

q hold (no change)

8. Limiting values

Table 5: Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to
GND (ground = 0 V).

Symbol Parameter Conditions Min Max Unit

V

CC

I

IK

I

OK

I

O

, I

I

CC

T

stg

P

tot

[1] Above 70 °C: P
[2] Above 70 °C: P

9397 750 13815 © Koninklijke Philips Electronics N.V. 2004. All rights reserved.

Product data sheet Rev. 03 — 12 November 2004 5 of 21

supply voltage −0.5 +7 V
input diode current VI < −0.5 V or VI>VCC+ 0.5 V - ±20 mA
output diode current VO< −0.5 V or VO>VCC+ 0.5 V - ±20 mA
output source or sink

VO = −0.5 V to VCC+ 0.5 V - ±25 mA

current

GNDVCC

or GND current - ±50 mA
storage temperature −65 +150 °C
power dissipation

[1]

DIP14 package
SO14, SSOP14 and

- 750 mW

[2]

- 500 mW

TSSOP14 packages

derates linearly with 12 mW/K.

tot

derates linearly with 8 mW/K.

tot

Philips Semiconductors

74HC73

Dual JK flip-flop with reset; negative-edge trigger

9. Recommended operating conditions

Table 6: Recommended operating conditions

Symbol Parameter Conditions Min Typ Max Unit

V
V
V
t

T

, t

r

amb

CC
I
O

f

supply voltage 2.0 5.0 6.0 V
input voltage 0 - V
output voltage 0 - V
input rise and fall

times except for
n

CP

ambient

= 2.0 V - - 1000 ns

V

CC

= 4.5 V - 6.0 500 ns

V

CC

= 6.0 V - - 400 ns

V

CC

−40 - +125 °C

CC
CC

V
V

temperature

10. Static characteristics

Table 7: Static characteristics

At recommended operating conditions; voltages are referenced to GND (ground = 0 V).

Symbol Parameter Conditions Min Typ Max Unit

=25°C

T

amb

V

IH

V

IL

V

OH

V

OL

I

LI

I

CC

C

I

HIGH-level input voltage VCC= 2.0 V 1.5 1.2 - V

= 4.5 V 3.15 2.4 - V

V

CC

= 6.0 V 4.2 3.2 - V

V

CC

LOW-level input voltage VCC= 2.0 V - 0.8 0.5 V

= 4.5 V - 2.1 1.35 V

V

CC

= 6.0 V - 2.8 1.8 V

V

CC

HIGH-level output voltage VI=VIHor V

IL

IO= −20 µA; VCC= 2.0 V 1.9 2.0 - V

= −20 µA; VCC= 4.5 V 4.4 4.5 - V

I

O

= −20 µA; VCC= 6.0 V 5.9 6.0 - V

I

O

= −4 mA; VCC= 4.5 V 3.98 4.32 - V

I

O

= −5.2 mA; VCC= 6.0 V 5.48 5.81 - V

I

O

LOW-level output voltage VI=VIHor V

IL

IO=20µA; VCC= 2.0 V - 0 0.1 V

=20µA; VCC= 4.5 V - 0 0.1 V

I

O

=20µA; VCC= 6.0 V - 0 0.1 V

I

O

= 4 mA; VCC= 4.5 V - 0.15 0.26 V

I

O

= 5.2 mA; VCC= 6.0 V - 0.16 0.26 V

I

O

input leakage current VI=VCCor GND; VCC= 6.0 V - - ±0.1 µA
quiescent supply current VI=VCCor GND; IO= 0 A; VCC= 6.0 V - - 4.0 µA
input capacitance - 3.5 - pF

9397 750 13815 © Koninklijke Philips Electronics N.V. 2004. All rights reserved.

Product data sheet Rev. 03 — 12 November 2004 6 of 21

Philips Semiconductors

74HC73

Dual JK flip-flop with reset; negative-edge trigger

Table 7: Static characteristics

…continued

At recommended operating conditions; voltages are referenced to GND (ground = 0 V).

Symbol Parameter Conditions Min Typ Max Unit

T

= −40 °C to +85 °C

amb

V

IH

V

IL

V

OH

HIGH-level input voltage VCC= 2.0 V 1.5 - - V

= 4.5 V 3.15 - - V

V

CC

= 6.0 V 4.2 - - V

V

CC

LOW-level input voltage VCC= 2.0 V - - 0.5 V

= 4.5 V - - 1.35 V

V

CC

= 6.0 V - - 1.8 V

V

CC

HIGH-level output voltage VI=VIHor V

IL

IO= −20 µA; VCC= 2.0 V 1.9 - - V

= −20 µA; VCC= 4.5 V 4.4 - - V

I

O

= −20 µA; VCC= 6.0 V 5.9 - - V

I

O

= −4 mA; VCC= 4.5 V 3.84 - - V

I

O

= −5.2 mA; VCC= 6.0 V 5.34 - - V

I

O

V

OL

LOW-level output voltage VI=VIHor V

IL

IO=20µA; VCC= 2.0 V - - 0.1 V

=20µA; VCC= 4.5 V - - 0.1 V

I

O

=20µA; VCC= 6.0 V - - 0.1 V

I

O

= 4 mA; VCC= 4.5 V - - 0.33 V

I

O

= 5.2 mA; VCC= 6.0 V - - 0.33 V

I

O

I

LI

I

CC

input leakage current VI=VCCor GND; VCC= 6.0 V - - ±1.0 µA
quiescent supply current VI=VCCor GND; IO= 0 A; VCC= 6.0 V - - 40.0 µA

9397 750 13815 © Koninklijke Philips Electronics N.V. 2004. All rights reserved.

Product data sheet Rev. 03 — 12 November 2004 7 of 21

Philips Semiconductors

74HC73

Dual JK flip-flop with reset; negative-edge trigger

Table 7: Static characteristics

…continued

At recommended operating conditions; voltages are referenced to GND (ground = 0 V).

Symbol Parameter Conditions Min Typ Max Unit

T

= −40 °C to +125 °C

amb

V

IH

V

IL

V

OH

HIGH-level input voltage VCC= 2.0 V 1.5 - - V

= 4.5 V 3.15 - - V

V

CC

= 6.0 V 4.2 - - V

V

CC

LOW-level input voltage VCC= 2.0 V - - 0.5 V

= 4.5 V - - 1.35 V

V

CC

= 6.0 V - - 1.8 V

V

CC

HIGH-level output voltage VI=VIHor V

IL

IO= −20 µA; VCC= 2.0 V 1.9 - - V

= −20 µA; VCC= 4.5 V 4.4 - - V

I

O

= −20 µA; VCC= 6.0 V 5.9 - - V

I

O

= −4 mA; VCC= 4.5 V 3.7 - - V

I

O

= −5.2 mA; VCC= 6.0 V 5.2 - - V

I

O

V

OL

LOW-level output voltage VI=VIHor V

IL

IO=20µA; VCC= 2.0 V - - 0.1 V

=20µA; VCC= 4.5 V - - 0.1 V

I

O

=20µA; VCC= 6.0 V - - 0.1 V

I

O

= 4 mA; VCC= 4.5 V - - 0.4 V

I

O

= 5.2 mA; VCC= 6.0 V - - 0.4 V

I

O

I

LI

I

CC

input leakage current VI=VCCor GND; VCC= 6.0 V - - ±1.0 µA
quiescent supply current VI=VCCor GND; IO= 0 A; VCC= 6.0 V - - 80.0 µA

9397 750 13815 © Koninklijke Philips Electronics N.V. 2004. All rights reserved.

Product data sheet Rev. 03 — 12 November 2004 8 of 21

Philips Semiconductors

74HC73

Dual JK flip-flop with reset; negative-edge trigger

11. Dynamic characteristics

Table 8: Dynamic characteristics

GND = 0 V; tr=tf= 6 ns; CL= 50 pF; see Figure 8.

Symbol Parameter Conditions Min Typ Max Unit

= 25 °C

T

amb

, t

t

PHL

t

THL

t

W

t

rem

t

su

propagation delay nCP to nQ see Figure 6

PLH

propagation delay n

propagation delay n

, t

output transition time see Figure 6

TLH

CP to nQ see Figure 6

R to nQ, nQ see Figure 7

nCP clock pulse width HIGH or LOW seeFigure 6

R reset pulse width HIGH or LOW see Figure 7

n

removal time nR to nCP see Figure 7

set-up time nJ, nK to nCP see Figure 6

= 2.0 V - 52 160 ns

V

CC

= 4.5 V - 19 32 ns

V

CC

= 6.0 V - 15 27 ns

V

CC

= 5.0 V; CL=15pF - 16 - ns

V

CC

= 2.0 V - 52 160 ns

V

CC

= 4.5 V - 19 32 ns

V

CC

= 6.0 V - 15 27 ns

V

CC

= 5.0 V; CL=15pF - 16 - ns

V

CC

= 2.0 V - 50 145 ns

V

CC

= 4.5 V - 18 29 ns

V

CC

= 6.0 V - 14 25 ns

V

CC

= 5.0 V; CL=15pF - 15 - ns

V

CC

= 2.0 V - 19 75 ns

V

CC

= 4.5 V - 7 15 ns

V

CC

= 6.0 V - 6 13 ns

V

CC

= 2.0 V 80 22 - ns

V

CC

= 4.5 V 16 8 - ns

V

CC

= 6.0 V 14 6 - ns

V

CC

= 2.0 V 80 22 - ns

V

CC

= 4.5 V 16 8 - ns

V

CC

= 6.0 V 14 6 - ns

V

CC

= 2.0 V 80 22 - ns

V

CC

= 4.5 V 16 8 - ns

V

CC

= 6.0 V 14 6 - ns

V

CC

= 2.0 V 80 22 - ns

V

CC

= 4.5 V 16 8 - ns

V

CC

= 6.0 V 14 6 - ns

V

CC

9397 750 13815 © Koninklijke Philips Electronics N.V. 2004. All rights reserved.

Product data sheet Rev. 03 — 12 November 2004 9 of 21

Philips Semiconductors

74HC73

Dual JK flip-flop with reset; negative-edge trigger

Table 8: Dynamic characteristics

…continued

GND = 0 V; tr=tf= 6 ns; CL= 50 pF; see Figure 8.

Symbol Parameter Conditions Min Typ Max Unit

t

f

C

h

max

PD

hold time nJ, nK to nCP see Figure 6

= 2.0 V 3 −8- ns

V

CC

= 4.5 V 3 −3- ns

V

CC

= 6.0 V 3 −2- ns

V

CC

maximum clock frequency see Figure 6

= 2.0 V 6.0 23 - MHz

V

CC

= 4.5 V 30 70 - MHz

V

CC

= 6.0 V 35 83 - MHz

V

CC

= 5.0 V; CL= 15 pF - 77 - MHz

V

CC

power dissipation capacitance per

VI= GND to V

CC

[1]

-30-pF

flip-flop

= −40 °C to +85 °C

T

amb

, t

t

PHL

t

THL

t

W

t

rem

propagation delay nCP to nQ see Figure 6

PLH

propagation delay n

propagation delay n

, t

output transition time see Figure 6

TLH

CP to nQ see Figure 6

R to nQ, nQ see Figure 7

nCP clock pulse width HIGH or LOW seeFigure 6

R reset pulse width HIGH or LOW see Figure 7

n

removal time nR to nCP see Figure 7

= 2.0 V - - 200 ns

V

CC

= 4.5 V - - 40 ns

V

CC

= 6.0 V - - 34 ns

V

CC

= 2.0 V - - 200 ns

V

CC

= 4.5 V - - 40 ns

V

CC

= 6.0 V - - 34 ns

V

CC

= 2.0 V - - 180 ns

V

CC

= 4.5 V - - 36 ns

V

CC

= 6.0 V - - 31 ns

V

CC

= 2.0 V - - 95 ns

V

CC

= 4.5 V - - 19 ns

V

CC

= 6.0 V - - 16 ns

V

CC

= 2.0 V 100 - - ns

V

CC

= 4.5 V 20 - - ns

V

CC

= 6.0 V 17 - - ns

V

CC

= 2.0 V 100 - - ns

V

CC

= 4.5 V 20 - - ns

V

CC

= 6.0 V 17 - - ns

V

CC

= 2.0 V 100 - - ns

V

CC

= 4.5 V 20 - - ns

V

CC

= 6.0 V 17 - - ns

V

CC

9397 750 13815 © Koninklijke Philips Electronics N.V. 2004. All rights reserved.

Product data sheet Rev. 03 — 12 November 2004 10 of 21

Philips Semiconductors

74HC73

Dual JK flip-flop with reset; negative-edge trigger

Table 8: Dynamic characteristics

…continued

GND = 0 V; tr=tf= 6 ns; CL= 50 pF; see Figure 8.

Symbol Parameter Conditions Min Typ Max Unit

t

su

t

h

f

max

T

t

PHL

t

THL

t

W

amb

set-up time nJ, nK to nCP see Figure 6

hold time nJ, nK to nCP see Figure 6

maximum clock frequency see Figure 6

= −40 °C to +125 °C

, t

propagation delay nCP to nQ see Figure 6

PLH

propagation delay n

propagation delay n

, t

output transition time see Figure 6

TLH

CP to nQ see Figure 6

R to nQ, nQ see Figure 7

nCP clock pulse width HIGH or LOW seeFigure 6

R reset pulse width HIGH or LOW see Figure 7

n

= 2.0 V 100 - - ns

V

CC

= 4.5 V 20 - - ns

V

CC

= 6.0 V 17 - - ns

V

CC

= 2.0 V 3 - - ns

V

CC

= 4.5 V 3 - - ns

V

CC

= 6.0 V 3 - - ns

V

CC

= 2.0 V 4.8 - - MHz

V

CC

= 4.5 V 24 - - MHz

V

CC

= 6.0 V 28 - - MHz

V

CC

= 2.0 V - - 240 ns

V

CC

= 4.5 V - - 48 ns

V

CC

= 6.0 V - - 41 ns

V

CC

= 2.0 V - - 240 ns

V

CC

= 4.5 V - - 48 ns

V

CC

= 6.0 V - - 41 ns

V

CC

= 2.0 V - - 220 ns

V

CC

= 4.5 V - - 44 ns

V

CC

= 6.0 V - - 38 ns

V

CC

= 2.0 V - - 110 ns

V

CC

= 4.5 V - - 22 ns

V

CC

= 6.0 V - - 19 ns

V

CC

= 2.0 V 120 - - ns

V

CC

= 4.5 V 24 - - ns

V

CC

= 6.0 V 20 - - ns

V

CC

= 2.0 V 120 - - ns

V

CC

= 4.5 V 24 - - ns

V

CC

= 6.0 V 20 - - ns

V

CC

9397 750 13815 © Koninklijke Philips Electronics N.V. 2004. All rights reserved.

Product data sheet Rev. 03 — 12 November 2004 11 of 21

Philips Semiconductors

74HC73

Dual JK flip-flop with reset; negative-edge trigger

Table 8: Dynamic characteristics

…continued

GND = 0 V; tr=tf= 6 ns; CL= 50 pF; see Figure 8.

Symbol Parameter Conditions Min Typ Max Unit

t

rem

t

su

t

h

f

max

[1] CPD is used to determine the dynamic power dissipation (PD in µW).

removal time nR to nCP see Figure 7

set-up time nJ, nK to nCP see Figure 6

hold time nJ, nK to nCP see Figure 6

maximum clock frequency see Figure 6

PD=CPD× V
fi= input frequency in MHz;
fo= output frequency in MHz;
CL= output load capacitance in pF;
VCC= supply voltage in V;
N = number of inputs switching;
∑(CL× V

2

× fi× N+∑(CL× V

CC

2

× fo) = sum of outputs.

CC

2

× fo) where:

CC

= 2.0 V 120 - - ns

V

CC

= 4.5 V 24 - - ns

V

CC

= 6.0 V 20 - - ns

V

CC

= 2.0 V 120 - - ns

V

CC

= 4.5 V 24 - - ns

V

CC

= 6.0 V 20 - - ns

V

CC

= 2.0 V 3 - - ns

V

CC

= 4.5 V 3 - - ns

V

CC

= 6.0 V 3 - - ns

V

CC

= 2.0 V 4.0 - - MHz

V

CC

= 4.5 V 20 - - MHz

V

CC

= 6.0 V 24 - - MHz

V

CC

9397 750 13815 © Koninklijke Philips Electronics N.V. 2004. All rights reserved.

Product data sheet Rev. 03 — 12 November 2004 12 of 21

Philips Semiconductors

12. Waveforms

74HC73

Dual JK flip-flop with reset; negative-edge trigger

nJ, nK
input

nCP input

nQ output

nQ output

V

M

t

t

su

h

1/f

max

V

M

t

W

t

PHL

V

M

t

THL

V

M

t

TLH

t

PLH

t

su

t

t

t

h

t

PLH

TLH

THL

t

PHL

001aab983

The shaded areas indicate when the input is permitted to change for predictable output
performance.

VM= 0.5 × VI.

Fig 6. Waveforms showing the clock (nCP) to output (nQ, nQ) propagation delays, the

clock pulse width, the J and K to n

CP set-up and hold times, the output transition

times and the maximum clock frequency

V

t

rem

001aab984

M

nCP input

nR input

nQ output

nQ input

t

PLH

t

W

V

M

t

PHL

VM= 0.5 × VI.

Fig 7. Waveforms showing the reset (nR) input to output (nQ, nQ) propagation delays

and the reset pulse width and the n

9397 750 13815 © Koninklijke Philips Electronics N.V. 2004. All rights reserved.

Product data sheet Rev. 03 — 12 November 2004 13 of 21

R to nCP removal time

Philips Semiconductors

Fig 8. Load circuitry for switching times

Table 9: Test data

Supply Input Load
V

CC

2.0 V V

4.5 V V

6.0 V V

5.0 V V

74HC73

Dual JK flip-flop with reset; negative-edge trigger

V

CC

V

PULSE

GENERATOR

Test data is given in Table 9.
Definitions for test circuit:
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
CL = Load capacitance including jig and probe capacitance.

V

I

CC
CC
CC
CC

I

D.U.T.

R

T

tr, t

6 ns 50 pF
6 ns 50 pF
6 ns 50 pF
6 ns 15 pF

V

O

C

L

mna101

f

C

L

9397 750 13815 © Koninklijke Philips Electronics N.V. 2004. All rights reserved.

Product data sheet Rev. 03 — 12 November 2004 14 of 21

Philips Semiconductors

13. Package outline

74HC73

Dual JK flip-flop with reset; negative-edge trigger

DIP14: plastic dual in-line package; 14 leads (300 mil)

D

seating plane

L

Z

14

pin 1 index

e

b

SOT27-1

M

E

A

2

A

A

1

w M

b

1

8

E

c

(e )

1

M

H

1

0 5 10 mm

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

A

UNIT

mm

inches

Note

1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.

max.

OUTLINE
VERSION

SOT27-1

A

min.

A

1 2

max.

IEC JEDEC JEITA

050G04 MO-001 SC-501-14

b

1.73

1.13

0.068

0.044

b

1

0.53

0.38

0.021

0.015

REFERENCES

cD

0.36

0.23

0.014

0.009

scale

(1) (1)

19.50

18.55

0.77

0.73

7

M

L

Ee M

6.48

6.20

0.26

0.24

e

1

3.60

8.25

3.05

7.80

0.14

0.32

0.12

0.31

EUROPEAN

PROJECTION

H

E

10.0

8.3

0.39

0.33

w

max.

0.2542.54 7.62

0.010.1 0.3

0.0870.17 0.02 0.13

ISSUE DATE

99-12-27
03-02-13

(1)

Z

2.24.2 0.51 3.2

Fig 9. Package outline SOT27-1 (DIP14)

9397 750 13815 © Koninklijke Philips Electronics N.V. 2004. All rights reserved.

Product data sheet Rev. 03 — 12 November 2004 15 of 21

Philips Semiconductors

74HC73

Dual JK flip-flop with reset; negative-edge trigger

SO14: plastic small outline package; 14 leads; body width 3.9 mm

D

c

y

Z

14

pin 1 index

1

e

8

A

2

7

w M

b

p

SOT108-1

E

H

E

A

1

detail X

A

X

v M

A

Q

(A )

L

p

L

A

3

θ

0 2.5 5 mm

scale

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

mm

OUTLINE
VERSION

SOT108-1

A

max.

1.75

0.069

A1A2A

0.25

1.45

0.10

1.25

0.010

0.057

0.004

0.049

IEC JEDEC JEITA

076E06 MS-012

0.25

0.01

b

3

p

0.49

0.25

0.36

0.19

0.019

0.0100

0.014

0.0075

UNIT

inches

Note

1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.

(1)E(1)

cD

8.75

8.55

0.35

0.34

REFERENCES

eHELLpQZywv θ

4.0

3.8

0.16

0.15

1.27

0.05

6.2

5.8

0.244

0.228

1.05

0.041

1.0

0.4

0.039

0.016

0.7

0.25

0.6

0.028

0.01 0.004

0.024

EUROPEAN

PROJECTION

0.25 0.1

0.01

(1)

0.7

0.3

0.028

0.012

ISSUE DATE

99-12-27
03-02-19

o

8

o

0

Fig 10. Package outline SOT108-1 (SO14)

9397 750 13815 © Koninklijke Philips Electronics N.V. 2004. All rights reserved.

Product data sheet Rev. 03 — 12 November 2004 16 of 21

Philips Semiconductors

74HC73

Dual JK flip-flop with reset; negative-edge trigger

SSOP14: plastic shrink small outline package; 14 leads; body width 5.3 mm

D

c

y

Z
14

pin 1 index

8

A

2

A

E

H

E

1

SOT337-1

A

X

v M

A

Q

(A )

L

p

L

A

3

θ

p

7

b

p

cD

0.20

6.4

0.09

6.0

REFERENCES

MO-150

w M

0 2.5 5 mm

scale

(1)E(1)

eHELLpQZywv θ

5.4

5.2

7.9

0.65 1.25 0.2

7.6

1.03

0.63

detail X

0.9

0.7

0.13 0.1

EUROPEAN

PROJECTION

(1)

1.4

0.9

ISSUE DATE

99-12-27
03-02-19

o

8

o

0

1

e

DIMENSIONS (mm are the original dimensions)

mm

OUTLINE
VERSION

SOT337-1

A

max.

2

0.21

0.05

1.80

1.65

IEC JEDEC JEITA

0.25

0.38

0.25

UNIT A1A2A3b

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

Fig 11. Package outline SOT337-1 (SSOP14)

9397 750 13815 © Koninklijke Philips Electronics N.V. 2004. All rights reserved.

Product data sheet Rev. 03 — 12 November 2004 17 of 21

Philips Semiconductors

74HC73

Dual JK flip-flop with reset; negative-edge trigger

TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm

D

c

y

Z

14

pin 1 index

8

17

w M

b

e

p

A

2

A

1

E

H

E

L

detail X

SOT402-1

A

X

v M

A

Q

(A )

3

A

θ

L

p

0 2.5 5 mm

scale

DIMENSIONS (mm are the original dimensions)

UNIT A1A2A3b

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

A

max.

0.15

mm

1.1

OUTLINE
VERSION

SOT402-1 MO-153

0.05

0.95

0.25

0.80

IEC JEDEC JEITA

p

0.30

0.19

(1)E(2) (1)

cD

0.2

5.1

0.1

4.9

REFERENCES

eHELLpQZywv θ

4.5

4.3

0.65

6.6

6.2

0.75

0.50

0.4

0.3

EUROPEAN

PROJECTION

0.13 0.10.21

0.72

0.38

ISSUE DATE

99-12-27
03-02-18

o

8

o

0

Fig 12. Package outline SOT402-1 (TSSOP14)

9397 750 13815 © Koninklijke Philips Electronics N.V. 2004. All rights reserved.

Product data sheet Rev. 03 — 12 November 2004 18 of 21

Philips Semiconductors

Dual JK flip-flop with reset; negative-edge trigger

74HC73

14. Revision history

Table 10: Revision history

Document ID Release

date

74HC73_3 20041112 Product data sheet - 9397 750 13815 74HC_HCT73_CNV_2
Modifications:

• The format of this data sheet has been redesigned to comply with the current presentation

and information standard of Philips Semiconductors.

• Removed type number 74HCT73.

• Inserted family specification.

74HC_HCT73_CNV_2 19970911 Product specification - - 74HC_HCT73_1
74HC_HCT73_1 19901201 Product specification - - -

Data sheet status Change notice Doc. number Supersedes

9397 750 13815 © Koninklijke Philips Electronics N.V. 2004. All rights reserved.

Product data sheet Rev. 03 — 12 November 2004 19 of 21

Philips Semiconductors

15. Data sheet status

74HC73

Dual JK flip-flop with reset; negative-edge trigger

Level Data sheet status

I Objective data Development This data sheet contains data from the objective specification for product development. Philips

II Preliminary data Qualification Thisdatasheetcontainsdatafromthepreliminary specification. Supplementary data will be published

III Product data Production This data sheet contains data from the product specification. Philips Semiconductors reserves the

[1] Please consult the most recently issued data sheet before initiating or completing a design.
[2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at

URL http://www.semiconductors.philips.com.

[3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.

[1]

Product status

16. Definitions

Short-form specification — The data in a short-form specification is

extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.

Limiting values definition — Limiting values given are in accordance with
the Absolute Maximum Rating System (IEC 60134). Stress above one or
more of the limiting values may cause permanent damage to the device.
These are stress ratings only and operation of the device at these or at any
other conditions above those given in the Characteristics sections of the
specification is not implied. Exposure to limiting values for extended periods
may affect device reliability.

Application information — Applications that are described herein for any
of these products are for illustrative purposes only. Philips Semiconductors
make no representation or warranty that such applications will be suitable for
the specified use without further testing or modification.

[2] [3]

Definition

Semiconductors reserves the right to change the specification in any manner without notice.

at a later date. Philips Semiconductors reserves the right to change the specification without notice, in
order to improve the design and supply the best possible product.

right to make changes at any time in order to improvethe design, manufacturing and supply.Relevant
changes will be communicated via a Customer Product/Process Change Notification (CPCN).

17. Disclaimers

Life support — These products are not designed for use in life support

appliances, devices, or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors
customers using or selling these products for use in such applications do so
at their own risk and agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.

Right to make changes — Philips Semiconductors reserves the right to
make changes in the products - including circuits, standard cells, and/or
software - described or contained herein in order to improve design and/or
performance. When the product is in full production (status ‘Production’),
relevant changes will be communicated via a Customer Product/Process
Change Notification (CPCN). Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no
license or title under any patent, copyright, or mask work right to these
products, andmakesno representations or warranties that these products are
free from patent, copyright, or mask work right infringement, unless otherwise
specified.

18. Contact information

For additional information, please visit: http://www.semiconductors.philips.com
For sales office addresses, send an email to: [e-mail]

9397 750 13815 © Koninklijke Philips Electronics N.V. 2004. All rights reserved.

Product data sheet Rev. 03 — 12 November 2004 20 of 21

Philips Semiconductors

19. Contents

1 General description. . . . . . . . . . . . . . . . . . . . . . 1

2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

3 Quick reference data . . . . . . . . . . . . . . . . . . . . . 2

4 Ordering information. . . . . . . . . . . . . . . . . . . . . 2

5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3

6 Pinning information. . . . . . . . . . . . . . . . . . . . . . 4

6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4

7 Functional description . . . . . . . . . . . . . . . . . . . 5

7.1 Function table. . . . . . . . . . . . . . . . . . . . . . . . . . 5

8 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5

9 Recommended operating conditions. . . . . . . . 6

10 Static characteristics. . . . . . . . . . . . . . . . . . . . . 6

11 Dynamic characteristics . . . . . . . . . . . . . . . . . . 9

12 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

13 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 15

14 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 19

15 Data sheet status. . . . . . . . . . . . . . . . . . . . . . . 20

16 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

17 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

18 Contact information . . . . . . . . . . . . . . . . . . . . 20

74HC73

Dual JK flip-flop with reset; negative-edge trigger

© Koninklijke Philips Electronics N.V. 2004

All rights are reserved. Reproduction in whole or in part is prohibited without the prior
written consent of the copyright owner. The information presented in this document does
not form part of any quotation or contract, is believed to be accurate and reliable and may
be changed without notice. No liability will be accepted by the publisher for any
consequence of its use. Publication thereof does not convey nor imply any license under
patent- or other industrial or intellectual property rights.

Published in The Netherlands

Date of release: 12 November 2004

Document number: 9397 750 13815

This datasheet has been download from:

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Datasheets for electronics components.