74HC73
Dual JK flip-flop with reset; negative-edge trigger
Rev. 03 — 12 November 2004 Product data sheet
1. General description
The 74HC73 is a high-speed Si-gate CMOS device and is pin compatible with low-power
Schottky TTL (LSTTL). The 74HC73 is specified in compliance with JEDEC
standard no. 7A.
The 74HC is a dual negative-edge triggered JK flip-flop featuring individual J, K, clock
(nCP) and reset (nR) inputs; also complementary nQ and nQ outputs.
The J and K inputs must be stable one set-up time prior to the HIGH-to-LOW clock
transition for predictable operation.
The reset (nR) is an asynchronous active LOW input. When LOW, it overrides the clock
and data inputs, forcing the nQ output LOW and the nQ output HIGH.
Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock
rise and fall times.
2. Features
■ Low-power dissipation
■ Complies with JEDEC standard no. 7A
■ ESD protection:
◆ HBM EIA/JESD22-A114-B exceeds 2000 V
◆ MM EIA/JESD22-A115-A exceeds 200 V.
■ Multiple package options
■ Specified from −40 °Cto+80°C and from −40 °C to +125 °C.
Philips Semiconductors
3. Quick reference data
Table 1: Quick reference data
GND = 0 V; T
Symbol Parameter Conditions Min Typ Max Unit
, t
t
PHL
f
max
C
I
C
PD
amb
PLH
74HC73
Dual JK flip-flop with reset; negative-edge trigger
=25°C; tr=tf= 6 ns.
propagation delay CL= 15 pF; VCC=5 V - -
CP to nQ - 16 - ns
n
CP to nQ - 16 - ns
n
R to nQ, nQ - 15 - ns
n
maximum clock
frequency
input capacitance - 3.5 - pF
power dissipation
capacitance per flip-flop
CL= 15 pF; VCC= 5 V - 77 - MHz
VI= GND to V
CC
[1]
-30-pF
[1] CPD is used to determine the dynamic power dissipation (PD in µW).
PD=CPD× V
fi= input frequency in MHz;
fo= output frequency in MHz;
CL= output load capacitance in pF;
VCC= supply voltage in V;
N =number of inputs switching;
∑(CL× V
2
× fi× N+∑(CL× V
CC
2
× fo) = sum of outputs.
CC
2
× fo) where:
CC
4. Ordering information
Table 2: Ordering information
Type number Package
Temperature range Name Description Version
74HC73N −40 °C to +125 °C DIP14 plastic dual in-line package; 14 leads (300 mil) SOT27-1
74HC73D −40 °C to +125 °C SO14 plastic small outline package; 14 leads; body width 3.9 mm SOT108-1
74HC73DB −40 °C to +125 °C SSOP14 plastic shrink small outline package; 14 leads; body width
5.3 mm
74HC73PW −40 °C to +125 °C TSSOP14 plastic thin shrink small outline package; 14 leads; body
width 4.4 mm
SOT337-1
SOT402-1
9397 750 13815 © Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet Rev. 03 — 12 November 2004 2 of 21
Philips Semiconductors
5. Functional diagram
74HC73
Dual JK flip-flop with reset; negative-edge trigger
Fig 1. Functional diagram
1J14
J
2J7
CP
K
1R
FF
R
2R
26
1CP1
2CP5
1K3
2K
10
1Q 12
Q
2Q 9
1Q 13
Q
2Q 8
001aab979
R
R
001aab981
1Q 121J14
Q
1Q 13
Q
2Q 92J7
Q
2Q 8
Q
4
1J
1
C1
3
1K
2
R
7
1J
5
C1
10
1K
6
R
001aab980
12
13
9
8
J
1CP1
1K3
1R2
2CP5
2K10
2R6
FF1
CP
K
J
FF2
CP
K
Fig 2. Logic symbol Fig 3. IEC logic symbol
9397 750 13815 © Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet Rev. 03 — 12 November 2004 3 of 21
Philips Semiconductors
74HC73
Dual JK flip-flop with reset; negative-edge trigger
K
J
R
CP
Fig 4. Logic diagram (one flip-flop)
6. Pinning information
6.1 Pinning
C
C
C
C
1CP 1J
1R 1Q
1K 1Q
C
C
1
2
3
14
13
12
C
C
001aab982
C
Q
C
Q
4
V
CC
5
2CP 2K
6
2R 2Q
7 8
2J 2Q
73
001aab978
Fig 5. Pin configuration
6.2 Pin description
Table 3: Pin description
Symbol Pin Description
CP 1 clock input for flip-flop 1 (HIGH-to-LOW, edge-triggered)
1
R 2 asynchronous reset input for flip-flop 1 (active LOW)
1
1K 3 synchronous K input for flip-flop 1
V
CC
CP 5 clock input for flip-flop 2 (HIGH-to-LOW, edge-triggered)
2
R 6 asynchronous reset input for flip-flop 2 (active LOW)
2
2J 7 synchronous J input for flip-flop 2
Q 8 complement flip-flop 2 output
2
2Q 9 true flip-flop 2 output
2K 10 synchronous K input for flip-flop 2
4 positive supply voltage
11
GND
10
9
9397 750 13815 © Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet Rev. 03 — 12 November 2004 4 of 21
Philips Semiconductors
74HC73
Dual JK flip-flop with reset; negative-edge trigger
Table 3: Pin description
Symbol Pin Description
GND 11 ground (0 V)
1Q 12 true flip-flop 1 output
Q 13 complement flip-flop 1 output
1
1J 14 synchronous J input for flip-flop 1
7. Functional description
7.1 Function table
Table 4: Function table
Input Output Operating mode
nR nCP nJ nK nQ nQ
L X X X L H asynchronous reset
H ↓ hh
[1] H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the HIGH-to-LOW CP transition;
L = LOW voltage level;
I = LOW voltage level one set-up time prior to the HIGH-to-LOW CP transition;
q = state of referenced output one set-up time prior to the HIGH-to-LOW CP transition;
X = don’t care;
↓ = HIGH-to-LOW CP transition.
…continued
[1]
q q toggle
l h L H load 0 (reset)
h l H L load 1 (set)
llq
q hold (no change)
8. Limiting values
Table 5: Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to
GND (ground = 0 V).
Symbol Parameter Conditions Min Max Unit
V
CC
I
IK
I
OK
I
O
, I
I
CC
T
stg
P
tot
[1] Above 70 °C: P
[2] Above 70 °C: P
9397 750 13815 © Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet Rev. 03 — 12 November 2004 5 of 21
supply voltage −0.5 +7 V
input diode current VI < −0.5 V or VI>VCC+ 0.5 V - ±20 mA
output diode current VO< −0.5 V or VO>VCC+ 0.5 V - ±20 mA
output source or sink
VO = −0.5 V to VCC+ 0.5 V - ±25 mA
current
GNDVCC
or GND current - ±50 mA
storage temperature −65 +150 °C
power dissipation
[1]
DIP14 package
SO14, SSOP14 and
- 750 mW
[2]
- 500 mW
TSSOP14 packages
derates linearly with 12 mW/K.
tot
derates linearly with 8 mW/K.
tot
Philips Semiconductors
74HC73
Dual JK flip-flop with reset; negative-edge trigger
9. Recommended operating conditions
Table 6: Recommended operating conditions
Symbol Parameter Conditions Min Typ Max Unit
V
V
V
t
T
, t
r
amb
CC
I
O
f
supply voltage 2.0 5.0 6.0 V
input voltage 0 - V
output voltage 0 - V
input rise and fall
times except for
n
CP
ambient
= 2.0 V - - 1000 ns
V
CC
= 4.5 V - 6.0 500 ns
V
CC
= 6.0 V - - 400 ns
V
CC
−40 - +125 °C
CC
CC
V
V
temperature
10. Static characteristics
Table 7: Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Typ Max Unit
=25°C
T
amb
V
IH
V
IL
V
OH
V
OL
I
LI
I
CC
C
I
HIGH-level input voltage VCC= 2.0 V 1.5 1.2 - V
= 4.5 V 3.15 2.4 - V
V
CC
= 6.0 V 4.2 3.2 - V
V
CC
LOW-level input voltage VCC= 2.0 V - 0.8 0.5 V
= 4.5 V - 2.1 1.35 V
V
CC
= 6.0 V - 2.8 1.8 V
V
CC
HIGH-level output voltage VI=VIHor V
IL
IO= −20 µA; VCC= 2.0 V 1.9 2.0 - V
= −20 µA; VCC= 4.5 V 4.4 4.5 - V
I
O
= −20 µA; VCC= 6.0 V 5.9 6.0 - V
I
O
= −4 mA; VCC= 4.5 V 3.98 4.32 - V
I
O
= −5.2 mA; VCC= 6.0 V 5.48 5.81 - V
I
O
LOW-level output voltage VI=VIHor V
IL
IO=20µA; VCC= 2.0 V - 0 0.1 V
=20µA; VCC= 4.5 V - 0 0.1 V
I
O
=20µA; VCC= 6.0 V - 0 0.1 V
I
O
= 4 mA; VCC= 4.5 V - 0.15 0.26 V
I
O
= 5.2 mA; VCC= 6.0 V - 0.16 0.26 V
I
O
input leakage current VI=VCCor GND; VCC= 6.0 V - - ±0.1 µA
quiescent supply current VI=VCCor GND; IO= 0 A; VCC= 6.0 V - - 4.0 µA
input capacitance - 3.5 - pF
9397 750 13815 © Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet Rev. 03 — 12 November 2004 6 of 21
Philips Semiconductors
74HC73
Dual JK flip-flop with reset; negative-edge trigger
Table 7: Static characteristics
…continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Typ Max Unit
T
= −40 °C to +85 °C
amb
V
IH
V
IL
V
OH
HIGH-level input voltage VCC= 2.0 V 1.5 - - V
= 4.5 V 3.15 - - V
V
CC
= 6.0 V 4.2 - - V
V
CC
LOW-level input voltage VCC= 2.0 V - - 0.5 V
= 4.5 V - - 1.35 V
V
CC
= 6.0 V - - 1.8 V
V
CC
HIGH-level output voltage VI=VIHor V
IL
IO= −20 µA; VCC= 2.0 V 1.9 - - V
= −20 µA; VCC= 4.5 V 4.4 - - V
I
O
= −20 µA; VCC= 6.0 V 5.9 - - V
I
O
= −4 mA; VCC= 4.5 V 3.84 - - V
I
O
= −5.2 mA; VCC= 6.0 V 5.34 - - V
I
O
V
OL
LOW-level output voltage VI=VIHor V
IL
IO=20µA; VCC= 2.0 V - - 0.1 V
=20µA; VCC= 4.5 V - - 0.1 V
I
O
=20µA; VCC= 6.0 V - - 0.1 V
I
O
= 4 mA; VCC= 4.5 V - - 0.33 V
I
O
= 5.2 mA; VCC= 6.0 V - - 0.33 V
I
O
I
LI
I
CC
input leakage current VI=VCCor GND; VCC= 6.0 V - - ±1.0 µA
quiescent supply current VI=VCCor GND; IO= 0 A; VCC= 6.0 V - - 40.0 µA
9397 750 13815 © Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet Rev. 03 — 12 November 2004 7 of 21
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