INTEGRATED CIRCUITS
DATA SH EET
For a complete data sheet, please also download:
•The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
•The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
•The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT595
8-bit serial-in/serial or parallel-out
shift register with output latches;
3-state
Product specification
Supersedes data of September 1993
File under Integrated Circuits, IC06
1998 Jun 04
Philips Semiconductors Product specification
8-bit serial-in/serial or parallel-out shift
register with output latches; 3-state
FEATURES
• 8-bit serial input
• 8-bit serial or parallel output
• Storage register with 3-state outputs
• Shift register with direct clear
• 100 MHz (typ) shift out frequency
• Output capability:
– parallel outputs; bus driver
– serial output; standard
• ICC category: MSI.
APPLICATIONS
• Serial-to-parallel data conversion
• Remote control holding register.
74HC/HCT595
DESCRIPTION
The 74HC/HCT595 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The “595” is an 8-stage serial shift register with a storage
register and 3-state outputs. The shift register and storage
register have separate clocks.
Data is shifted on the positive-going transitions of the
SHCP input. The data in each register is transferred to the
storage register on a positive-going transition of the ST
input. If both clocks are connected together, the shift
register will always be one clock pulse ahead of the
storage register.
The shift register has a serial input (DS) and a serial
standard output (Q7’) for cascading. It is also provided with
asynchronous reset (active LOW) for all 8 shift register
stages. The storage register has 8 parallel 3-state bus
driver outputs. Data in the storage register appears at the
output whenever the output enable input (OE) is LOW.
CP
QUICK REFERENCE DATA
GND = 0 V; T
=25°C; tr=tf= 6 ns.
amb
SYMBOL PARAMETER CONDITIONS
HC HCT
t
PHL/tPLH
propagation delay CL= 15 pF; VCC=5V
SH
to Q7’ 1621ns
CP
to Q
ST
CP
n
17 20 ns
MR to Q7’ 1419ns
f
max
C
I
C
PD
maximum clock frequency SHCP, ST
CP
100 57 MHz
input capacitance 3.5 3.5 pF
power dissipation capacitance per package notes 1 and 2 115 130 pF
Notes
1. C
is used to determine the dynamic power dissipation (PD in µW):
PD
PD=CPD× V
2
× fi+∑ (CL× V
CC
2
× fo) where:
CC
fi= input frequency in MHz
fo= output frequency in MHz
∑(CL× V
2
× fo) = sum of outputs
CC
CL= output load capacitance in pF
VCC= supply voltage in V
2. For HC the condition is VI= GND to VCC; for HCT the condition is VI= GND to VCC− 1.5 V.
TYP.
UNIT
1998 Jun 04 2
Philips Semiconductors Product specification
8-bit serial-in/serial or parallel-out shift
74HC/HCT595
register with output latches; 3-state
ORDERING INFORMATION
TYPE NUMBER
NAME DESCRIPTION VERSION
74HC595N DIP16 plastic dual in-line package; 16 leads (300 mil); long body SOT38-1
74HC595D SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1
74HC595DB SSOP16 plastic shrink small outline package; 16 leads; body width 5.3 mm SOT338-1
74HC595PW TSSOP16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1
74HCT595N DIP16 plastic dual in-line package; 16 leads (300 mil); long body SOT38-1
74HCT595D SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1
PINNING
SYMBOL PIN DESCRIPTION
Q
0
to Q
7
15, 1 to 7 parallel data output
GND 8 ground (0 V)
’ 9 serial data output
Q
7
MR 10 master reset (active LOW)
SH
CP
ST
CP
OE 13 output enable (active LOW)
D
S
V
CC
PACKAGE
11 shift register clock input
12 storage register clock input
14 serial data input
16 positive supply voltage
handbook, halfpage
Q
Q
Q
Q
Q
Q
Q
GND
1
1
2
2
3
3
4
4
5
6
7
595
5
6
7
8
MLA001
16
V
CC
Q
15
0
D
14
S
OE
13
ST
12
CP
SH
11
CP
MR
10
Q7'
9
Fig.1 Pin configuration.
1998 Jun 04 3
handbook, halfpage
11 12
SH
ST
CP
CP
Q7'
Q
0
Q
1
Q
14
D
S
2
Q
3
Q
4
Q
5
Q
6
Q
7
OEMR
1310
Fig.2 Logic symbol.
9
15
1
2
3
4
5
6
7
MLA002
Philips Semiconductors Product specification
8-bit serial-in/serial or parallel-out shift
register with output latches; 3-state
ST
SH
OE
CP
MR
CP
D
13
12
10
R
11
14
S
SRG8
C1/
1D 2D
Fig.3 IEC logic symbol.
handbook, halfpage
EN3
C2
3
MSA698
74HC/HCT595
15
Q
0
1
Q
1
2
Q
2
3
Q
3
4
Q
4
5
Q
5
6
Q
6
7
Q
7
9
Q7'
handbook, full pagewidth
D
14
S
SH
CP
11
MR
10
ST
12
OE
13
8-STAGE SHIFT REGISTER
CP
8-BIT STORAGE REGISTER
3-STATE OUTPUTS
Q7'
Q
0
Q
1
Q
2
Q
3
Q
4
Q
5
Q
6
Q
7
MLA003
9
15
1
2
3
4
5
6
7
Fig.4 Functional diagram.
1998 Jun 04 4
Philips Semiconductors Product specification
8-bit serial-in/serial or parallel-out shift
register with output latches; 3-state
handbook, full pagewidth
D
S
SH
CP
MR
STAGE 0 STAGES 1 TO 6 STAGE 7
DCPQ
FF0
R
DCPQ
LATCH
DQ
DCPQ
FF7
R
DCPQ
LATCH
74HC/HCT595
Q
'
7
ST
CP
OE
Q
0
Q
Q
1
2
Fig.5 Logic diagram.
Q
Q
Q
3
Q
4
5
6
Q
MLA010
7
1998 Jun 04 5
Philips Semiconductors Product specification
8-bit serial-in/serial or parallel-out shift
74HC/HCT595
register with output latches; 3-state
FUNCTION TABLE
INPUTS OUTPUTS
SH
CP
ST
OE MR D
CP
Q7’Q
S
N
X X L L X L NC a LOW level on MR only affects the shift registers
X ↑ L L X L L empty shift register loaded into storage register
X X H L X L Z shift register clear. Parallel outputs in high-impedance
OFF-state
↑ XLHHQ
’ NC logic high level shifted into shift register stage 0. Contents
6
of all shift register stages shifted through, e.g. previous
state of stage 6 (internal Q
(Q7’)
X ↑ LHXNCQ
’ contents of shift register stages (internal Qn’) are
n
transferred to the storage register and parallel output
stages
↑↑LHXQ
’Qn’ contents of shift register shifted through. Previous
6
contents of the shift register is transferred to the storage
register and the parallel output stages.
FUNCTON
’) appears on the serial output
6
Notes
1. H = HIGH voltage level; L = LOW voltage level
↑ = LOW-to-HIGH transition; ↓ = HIGH-to-LOW transition
Z = high-impedance OFF-state; NC = no change
X = don’t care.
1998 Jun 04 6
Philips Semiconductors Product specification
8-bit serial-in/serial or parallel-out shift
register with output latches; 3-state
handbook, full pagewidth
SH
CP
D
S
ST
CP
MR
74HC/HCT595
OE
Q
Q
Q
Q
Q7'
0
high-impedance OFF-state
1
6
7
MLA005 - 1
Fig.6 Timing diagram.
1998 Jun 04 7
Philips Semiconductors Product specification
8-bit serial-in/serial or parallel-out shift
register with output latches; 3-state
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see chapter
Output capability: parallel outputs, bus driver, serial output, standard ICC category: MSI.
AC CHARACTERISTICS FOR 74HC
GND = 0 V; t
= 6 ns; CL=50pF.
r=tf
SYMBOL PARAMETER
t
PHL/tPLH
propagation delay
SHCP to Q7’
t
PHL/tPLH
t
PHL
propagation delay
STCP to Q
n
propagation delay
MR to Q7’
t
PZH/tPZL
3-state output
enable time
t
PHZ/tPLZ
OE to Q
3-state output
n
disable time
OE to Q
t
W
shift clock pulse
n
width HIGH or
LOW
t
W
storage clock
pulse width HIGH
or LOW
t
W
master reset
pulse width LOW
t
su
t
su
set-up time DS to
SH
CP
set-up time SH
to ST
CP
CP
“74HC/HCT/HCU/HCMOS Logic Family Specifications”
T
(°C)
amb
+25 −40 to +85 −40 to +125
min typ max min max min max
− 52 160 − 200 − 240 ns 2.0 Fig.7
− 19 32 − 40 − 48 4.5
− 15 27 − 34 − 41 6.0
− 55 175 − 220 − 265 ns 2.0 Fig.8
− 20 35 − 44 − 53 4.5
− 16 30 − 37 − 45 6.0
− 47 175 − 220 − 265 ns 2.0 Fig.10
− 17 35 − 44 − 53 4.5
− 14 30 − 37 − 45 6.0
− 47 150 − 190 − 225 ns 2.0 Fig.11
− 17 30 − 38 − 45 4.5
− 14 26 − 33 − 38 6.0
− 41 150 − 190 − 225 ns 2.0 Fig.11
− 15 30 − 38 − 45 4.5
− 12 26 − 33 − 38 6.0
75 17 − 95 − 110 − ns 2.0 Fig.7
15 6 − 19 − 22 − 4.5
13 5 − 16 − 19 − 6.0
75 11 − 95 − 110 − ns 2.0 Fig.8
15 4 − 19 − 22 − 4.5
13 3 − 16 − 19 − 6.0
75 17 − 95 − 110 − ns 2.0 Fig.10
15 6.0 − 19 − 22 − 4.5
13 5.0 − 16 − 19 − 6.0
50 11 − 65 − 75 − ns 2.0 Fig.9
10 4.0 − 13 − 15 − 4.5
9.0 3.0 − 11 − 13 − 6.0
75 22 − 95 − 110 − ns 2.0 Fig.8
15 8 − 19 − 22 − 4.5
13 7 − 16 − 19 − 6.0
74HC/HCT595
.
TEST CONDITION
UNIT
V
CC
WAVEFORMS
(V)
1998 Jun 04 8
Philips Semiconductors Product specification
8-bit serial-in/serial or parallel-out shift
register with output latches; 3-state
SYMBOL PARAMETER
t
h
t
rem
f
max
hold time DS to
SH
CP
removal time MR
to SH
CP
maximum clock
pulse frequency
SHCP or ST
CP
min typ max min max min max
3 −6 − 3 − 3 − ns 2.0 Fig.9
3 −2 − 3 − 3 − 4.5
3 −2 − 3 − 3 − 6.0
50 −19 − 65 − 75 − ns 2.0 Fig.10
10 −7 − 13 − 15 − 4.5
9 −6 − 11 − 13 − 6.0
930− 4.8 − 4 − MHz 2.0 Figs 7 and 8
30 91 − 24 − 20 − 4.5
35 108 − 28 − 24 − 6.0
+25 −40 to +85 −40 to +125
T
amb
(°C)
74HC/HCT595
TEST CONDITION
UNIT
V
CC
WAVEFORMS
(V)
1998 Jun 04 9
Philips Semiconductors Product specification
8-bit serial-in/serial or parallel-out shift
74HC/HCT595
register with output latches; 3-state
DC CHARACTERISTICS FOR 74HCT
For the DC characteristics see chapter
Output capability: parallel outputs, bus driver; serial output, standard ICC category: MSI.
Note to HCT types
The value of additional quiescent supply current (∆I
To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below.
GND = 0 V; t
INPUT UNIT LOAD COEFFICIENT
= 6 ns; CL=50pF.
r=tf
D
S
MR 1.50
SH
CP
ST
CP
OE 1.50
“74HC/HCT/HCU/HCMOS Logic Family Specifications”
) for a unit load of 1 is given in the family specifications.
CC
0.25
1.50
1.50
.
1998 Jun 04 10
Philips Semiconductors Product specification
8-bit serial-in/serial or parallel-out shift
register with output latches; 3-state
AC CHARACTERISTICS FOR 74HCT
GND = 0 V; t
SYMBOL PARAMETER
/ t
t
PHL
PLH
t
/ t
PHL
PLH
t
PHL
t
/ t
PZH
PZL
t
/ t
PHZ
PLZ
t
W
t
W
t
W
t
su
t
su
t
h
= 6 ns; CL=50pF.
r=tf
propagation delay
SHCP to Q7’
propagation delay
STCP to Q
n
propagation delay
MR to Q7’
3-state output enable
time OE to Q
n
3-state output disable
time OE to Q
n
shift clock pulse
width HIGH or LOW
storage clock pulse width
HIGH or LOW
master reset
pulse width LOW
set-up time DS to
SH
SP
set-up time SH
to ST
CP
hold time DS to SH
CP
CP
+25 −40 to +85 −40 to +125
min typ max min max min max
− 25 42 − 53 − 63 ns 4.5 Fig.7
− 24 40 − 50 − 60 ns 4.5 Fig.8
− 23 40 − 50 − 60 ns 4.5 Fig.10
− 21 35 − 44 − 53 ns 4.5 Fig.11
− 18 30 − 38 − 45 ns 4.5 Fig.11
16 6 − 20 − 24 − ns 4.5 Fig.7
16 5 − 20 − 24 − ns 4.5 Fig.8
20 8 − 25 − 30 − ns 4.5 Fig.10
16 5 − 20 − 24 − ns 4.5 Fig.9
16 8 − 20 − 24 − ns 4.5 Fig.8
3 −2 − 3 − 3 − ns 4.5 Fig.9
T
amb
(°C)
74HC/HCT595
TEST CONDITION
UNIT
V
CC
WAVEFORMS
(V)
t
rem
f
max
removal time MR
to SH
CP
maximum clock
10 −7 − 13 − 15 − ns 4.5 Fig.10
30 52 − 24 − 20 − MHz 4.5 Figs 7 and 8
pulse frequency
SHCP or ST
CP
1998 Jun 04 11
Philips Semiconductors Product specification
8-bit serial-in/serial or parallel-out shift
register with output latches; 3-state
AC WAVEFORMS
handbook, full pagewidth
(1)
SH
Q7' OUTPUT
(1) HC: VM= 50%; VI= GND to V
HCT: VM= 1.3 V; VI= GND to 3 V.
CP
INPUT
CC
V
M
t
W
t
PLH
74HC/HCT595
1/f
max
t
PHL
t
TLH
90%
10%
(1)
V
M
t
THL
MSA699
Fig.7 Waveforms showing the clock (SHCP) to output (Q7’) propagation delays, the shift clock pulse width and
maximum shift clock frequency.
handbook, full pagewidth
(1)
SH
(1) HC: VM= 50%; VI= GND to V
HCT: VM= 1.3 V; VI= GND to 3 V.
INPUT
CP
ST
INPUT
CP
Qn OUTPUT
CC
V
M
t
su
(1)
V
M
t
W
t
PLH
(1)
V
M
1/f
max
t
PHL
MSA700
Fig.8 Waveforms showing the storage clock (STCP) to output (Qn) propagation delays, the storage clock pulse
width and the shift clock to storage clock set-up time.
1998 Jun 04 12
Philips Semiconductors Product specification
8-bit serial-in/serial or parallel-out shift
register with output latches; 3-state
handbook, full pagewidth
SHCP INPUT
DS INPUT
Q7' OUTPUT
(1)
V
M
t
su
(1)
V
M
74HC/HCT595
t
t
h
(1)
V
M
su
t
h
MLB196
(1) HC: VM= 50%; VI= GND to V
HCT: VM= 1.3 V; VI= GND to 3 V.
handbook, full pagewidth
CC
Fig.9 Waveforms showing the data set-up and hold times for the DS input.
(1)
MR INPUT
SH
INPUT
CP
Q7' OUTPUT
V
M
t
rem
(1)
V
M
(1)
V
M
MLB197
t
PHL
t
W
(1) HC: VM= 50%; VI= GND to V
HCT: VM= 1.3 V; VI= GND to 3 V.
CC
Fig.10 Waveforms showing the master reset (MR) pulse width, the master reset to output (Q7’) propagation delay
and the master reset to shift clock (SHCP) removal time.
1998 Jun 04 13
Philips Semiconductors Product specification
8-bit serial-in/serial or parallel-out shift
register with output latches; 3-state
90%
V
M
t
outputs
enabled
t
r
(1)
PLZ
t
PHZ
handbook, full pagewidth
OE INPUT
10%
Qn OUTPUT
LOW-to-OFF
OFF-to-LOW
Qn OUTPUT
HIGH-to-OFF
OFF-to-HIGH
10%
90%
outputs
disabled
t
PZL
t
PZH
74HC/HCT595
t
f
(1)
V
M
(1)
V
M
outputs
enabled
MSA697
(1) HC: VM= 50%; VI= GND to V
HCT: VM= 1.3 V; VI= GND to 3 V.
Fig.11 Waveforms showing the 3-state enable and disable times for input OE.
CC
1998 Jun 04 14
Philips Semiconductors Product specification
8-bit serial-in/serial or parallel-out shift
register with output latches; 3-state
PACKAGE OUTLINES
DIP16: plastic dual in-line package; 16 leads (300 mil); long body
D
seating plane
L
Z
16
e
b
b
1
9
A
w M
74HC/HCT595
SOT38-1
M
E
A
2
A
1
c
(e )
1
M
H
pin 1 index
1
0 5 10 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
UNIT
mm
inches
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
A
max.
4.7 0.51 3.7
OUTLINE
VERSION
SOT38-1
min.
A
1 2
max.
0.15
IEC JEDEC EIAJ
050G09 MO-001AE
b
1.40
1.14
0.055
0.045
b
0.53
0.38
0.021
0.015
1
cEe M
0.32
0.23
0.013
0.009
REFERENCES
D
21.8
21.4
0.86
0.84
8
scale
(1) (1)
6.48
6.20
0.26
0.24
E
(1)
Z
e
0.30
1
0.15
0.13
M
L
3.9
3.4
E
8.25
7.80
0.32
0.31
EUROPEAN
PROJECTION
9.5
8.3
0.37
0.33
w
H
0.2542.54 7.62
0.010.100.0200.19
ISSUE DATE
92-10-02
95-01-19
max.
2.2
0.087
1998 Jun 04 15
Philips Semiconductors Product specification
8-bit serial-in/serial or parallel-out shift
register with output latches; 3-state
SO16: plastic small outline package; 16 leads; body width 3.9 mm
D
c
y
Z
16
9
74HC/HCT595
SOT109-1
E
H
E
A
X
v M
A
pin 1 index
1
e
0 2.5 5 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
mm
A
max.
1.75
0.069
A
1
0.25
0.10
0.010
0.004
A2A
1.45
1.25
0.057
0.049
0.25
0.01
b
3
p
0.49
0.25
0.36
0.19
0.0100
0.019
0.0075
0.014
UNIT
inches
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
(1)E(1) (1)
cD
10.0
9.8
0.39
0.38
8
b
p
scale
eHELLpQZywv θ
4.0
1.27
3.8
0.16
0.050
0.15
w M
6.2
5.8
0.244
0.228
A
2
1.05
0.041
Q
A
1
detail X
1.0
0.7
0.4
0.6
0.028
0.039
0.020
0.016
(A )
L
p
L
0.25 0.1
0.25
0.01
0.01 0.004
A
3
θ
0.7
0.3
0.028
0.012
o
8
o
0
OUTLINE
VERSION
SOT109-1
IEC JEDEC EIAJ
076E07S MS-012AC
REFERENCES
1998 Jun 04 16
EUROPEAN
PROJECTION
ISSUE DATE
95-01-23
97-05-22
Philips Semiconductors Product specification
8-bit serial-in/serial or parallel-out shift
register with output latches; 3-state
SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm
D
c
y
Z
16
9
E
H
E
74HC/HCT595
SOT338-1
A
X
v M
A
pin 1 index
1
e
DIMENSIONS (mm are the original dimensions)
UNIT A
mm
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
A
max.
2.0
1
0.21
0.05
A2A3b
1.80
0.25
1.65
p
0.38
0.25
8
b
p
cD
0.20
6.4
0.09
6.0
w M
0 2.5 5 mm
scale
(1)E(1)
eHELLpQZywv θ
5.4
0.65 1.25
5.2
7.9
7.6
Q
A
2
A
1
detail X
1.03
0.9
0.63
0.7
(A )
L
p
L
3
θ
0.130.2 0.1
A
(1)
1.00
0.55
o
8
o
0
OUTLINE
VERSION
SOT338-1
IEC JEDEC EIAJ
REFERENCES
MO-150AC
1998 Jun 04 17
EUROPEAN
PROJECTION
ISSUE DATE
94-01-14
95-02-04
Philips Semiconductors Product specification
8-bit serial-in/serial or parallel-out shift
register with output latches; 3-state
TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm
E
H
E
16
D
c
y
Z
9
74HC/HCT595
SOT403-1
A
X
v M
A
pin 1 index
18
w M
b
e
DIMENSIONS (mm are the original dimensions)
UNIT A1A2A3b
mm
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
A
max.
0.15
0.05
0.95
0.25
0.80
IEC JEDEC EIAJ
1.10
OUTLINE
VERSION
SOT403-1 MO-153
p
0.30
0.19
p
0 2.5 5 mm
scale
(1)E(2) (1)
cD
0.2
5.1
0.1
4.9
REFERENCES
eHELLpQZywv θ
4.5
0.65
4.3
A
6.6
6.2
Q
(A )
2
A
1
L
p
L
detail X
0.75
0.4
0.50
0.3
EUROPEAN
PROJECTION
3
A
θ
0.13 0.10.21.0
0.40
0.06
ISSUE DATE
94-07-12
95-04-04
o
8
o
0
1998 Jun 04 18
Philips Semiconductors Product specification
8-bit serial-in/serial or parallel-out shift
register with output latches; 3-state
SOLDERING
Introduction
There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our
“Data Handbook IC26; Integrated Circuit Packages”
(order code 9398 652 90011).
DIP
S
OLDERING BY DIPPING OR BY WAVE
The maximum permissible temperature of the solder is
260 °C; solder at this temperature must not be in contact
with the joint for more than 5 seconds. The total contact
time of successive solder waves must not exceed
5 seconds.
The device may be mounted up to the seating plane, but
the temperature of the plastic body must not exceed the
specified maximum storage temperature (T
printed-circuit board has been pre-heated, forced cooling
may be necessary immediately after soldering to keep the
temperature within the permissible limit.
R
EPAIRING SOLDERED JOINTS
Apply a low voltage soldering iron (less than 24 V) to the
lead(s) of the package, below the seating plane or not
more than 2 mm above it. If the temperature of the
soldering iron bit is less than 300 °C it may remain in
contact for up to 10 seconds. If the bit temperature is
between 300 and 400 °C, contact may be up to 5 seconds.
stg max
). If the
74HC/HCT595
SO, SSOP and TSSOP
R
EFLOW SOLDERING
Reflow soldering techniques are suitable for all SO, SSOP
and TSSOP packages.
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
Several techniques exist for reflowing; for example,
thermal conduction by heated belt. Dwell times vary
between 50 and 300 seconds depending on heating
method.
Typical reflow temperatures range from 215 to 250 °C.
Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 minutes at
45 °C.
W
AVE SOLDERING
Wave soldering can be used for all SO packages. Wave
soldering is not recommended for SSOP and TSSOP
packages, because of the likelihood of solder bridging due
to closely-spaced leads and the possibility of incomplete
solder penetration in multi-lead devices.
If wave soldering is used - and cannot be avoided for
SSOP and TSSOP packages - the following conditions
must be observed:
• A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave) soldering
technique should be used.
• The longitudinal axis of the package footprint must be
parallel to the solder flow and must incorporate solder
thieves at the downstream end.
1998 Jun 04 19
Philips Semiconductors Product specification
8-bit serial-in/serial or parallel-out shift
register with output latches; 3-state
Even with these conditions:
• Only consider wave soldering SSOP packages that
have a body width of 4.4 mm, that is
SSOP16 (SOT369-1) or SSOP20 (SOT266-1).
• Do not consider wave soldering TSSOP packages
with 48 leads or more, that is TSSOP48 (SOT362-1)
and TSSOP56 (SOT364-1).
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
6 seconds. Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
74HC/HCT595
R
EPAIRING SOLDERED JOINTS
Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320 °C.
DEFINITIONS
Data sheet status
Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
1998 Jun 04 20
This datasheet has been download from:
www.datasheetcatalog.com
Datasheets for electronics components.
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