Product specification
Supersedes data of 1997 Aug 27
2003 May 16
Philips SemiconductorsProduct specification
Dual 4-channel analog multiplexer,
demultiplexer
FEATURES
• Wide analog input voltage range from −5 V to +5 V
• Low ON-resistance:
–80Ω(typical) at VCC− VEE= 4.5 V
–70Ω(typical) at VCC− VEE= 6.0 V
–60Ω(typical) at VCC− VEE= 9.0 V
• Logic level translation: to enable 5 V logic to
communicate with ±5 V analog signals
• Typical “break before make” built in
• Complies with JEDEC standard no. 8-1 A
• ESD protection:
– HBM EIA/JESD22-A114-A exceeds 2000 V
– MM EIA/JESD22-A115-A exceeds 200 V.
• Specified from −40 to +85 °C and −40 to +125 °C.
APPLICATIONS
• Analog multiplexing and demultiplexing
• Digital multiplexing and demultiplexing
• Signal gating.
74HC4052; 74HCT4052
DESCRIPTION
The 74HC4052/74HCT4052 are high-speed Si-gate
CMOS devices and are pin compatible with the
HEF4052B. Theyare specified in compliance with JEDEC
standard no. 7A.
The 74HC4052/74HCT4052 are dual 4-channel analog
multiplexers or demultiplexers with common select logic.
Each multiplexer has four independent inputs/outputs
(pinsnY0 to nY3) and acommoninput/output (pin nZ). The
common channel select logics include two digital select
inputs (pins S0 and S1) and an active LOW enable input
(pin E). When pin E = LOW, one of the four switches is
selected (low-impedance ON-state) with pins S0 and S1.
When pin E = HIGH, all switches are in the
high-impedance OFF-state, independent of pins S0 and
S1.
VCC and GND are the supply voltage pins for the digital
control inputs (pins S0, S1, and E). The VCC to GND
ranges are 2.0 to 10.0 V for 74HC4052 and 4.5 to 5.5 V
for 74HCT4052. The analog inputs/outputs (pins nY0 to
nY3and nZ) can swingbetween VCCasa positive limit and
VEEas a negative limit. VCC− VEEmay not exceed 10.0 V.
For operation as a digital multiplexer/demultiplexer, VEEis
connected to GND (typically ground).
FUNCTION TABLE
ES1S0
LLLnY0 and nZ
LLHnY1 and nZ
LHLnY2 and nZ
LHHnY3 and nZ
HXXnone
Note
1. H = HIGH voltage level
L = LOW voltage level
X = don’t care.
INPUT
(1)
CHANNEL BETWEEN
2003 May 162
Philips SemiconductorsProduct specification
Dual 4-channel analog multiplexer,
demultiplexer
QUICK REFERENCE DATA
VEE= GND = 0 V; T
SYMBOLPARAMETERCONDITIONS
t
PZH/tPZL
t
PHZ/tPLZ
C
I
C
PD
C
S
turn-on time E or Sn to V
turn-off time E or Sn to V
input capacitance3.53.5pF
power dissipation capacitance per switch notes 1 and 25757pF
maximum switch capacitanceindependent (Y)55pF
Notes
1. C
is used to determine the dynamic power dissipation (PDin µW).
PD
PD=CPD× V
fi= input frequency in MHz;
fo= output frequency in MHz;
CL= output load capacitance in pF;
CS= maximum switch capacitance in pF;
VCC= supply voltage in Volts;
N = total load switching outputs;
Σ[(CL+CS)×V
2. For 74HC4052 the condition is VI= GND to V
For 74HCT4052 the condition is VI= GND to VCC− 1.5 V.
=25°C; tr=tf= 6 ns.
amb
2
× fi× N+Σ[(CL+CS)×V
CC
2
× fo] = sum of the outputs.
CC
os
CL= 15 pF; RL=1kΩ;
VCC=5V
os
CL= 15 pF; RL=1kΩ;
VCC=5V
common (Z)1212pF
2
× fo] where:
CC
CC
74HC4052; 74HCT4052
TYPICAL
UNIT
74HC4052 74HCT4052
2818ns
2113ns
ORDERING INFORMATION
PACKAGE
TYPE NUMBER
TEMPERATURE
RANGE
PINSPACKAGEMATERIALCODE
74HC4052D−40 to +125 °C16SO16plasticSOT109-3
74HCT4052D−40 to +125 °C16SO16plasticSOT109-3
74HC4052DB−40 to +125 °C16SSOP16plasticSOT338-1
74HCT4052DB−40 to +125 °C16SSOP16plasticSOT338-1
74HC4052N−40 to +125 °C16DIP16plasticSOT38-9
74HCT4052N−40 to +125 °C16DIP16plasticSOT38-9
74HC4052PW−40 to +125 °C16TSSOP16plasticSOT403-1
74HC4052BQ−40 to +125 °C16DHVQFN16plasticSOT763-1
74HCT4052BQ−40 to +125 °C16DHVQFN16plasticSOT763-1
2003 May 163
Philips SemiconductorsProduct specification
Dual 4-channel analog multiplexer,
demultiplexer
PINNING
PINSYMBOLDESCRIPTION
12Y0independent input or output
22Y2independent input or output
32Zcommon input or output
42Y3independent input or output
52Y1independent input or output
6
7V
8GNDground (0 V)
9S1select logic input
10S0select logic input
111Y3independent input or output
121Y0independent input or output
131Zcommon input or output
141Y1independent input or output
151Y2independent input or output
16V
Eenable input (active LOW)
EE
CC
74HC4052; 74HCT4052
negative supply voltage
positive supply voltage
handbook, halfpage
2Y0
2Y2
2Z
2Y3
2Y1
V
EE
GND
1
2
3
4
4052
5
6
E
7
8
MNB039
16
V
15
1Y2
14
1Y1
13
1Z
12
1Y0
11
1Y3
10
S0
9
S1
Fig.1Pin configuration DIP16, SO16 and
(T)SSOP16.
CC
V
handbook, halfpage
2
2Y2
3
2Z
4
2Y3
5
2Y1
E
611
7
V
EE
Top view
(1) The die substrate is attached to this pad using conductive die
attach material. It can not be used as a supply pin or input.
2Y0
CC
116
(1)
GND
8
9
GND
S1
MNB061
15
1Y2
14
1Y1
13
1Z
12
1Y0
1Y3
S0
10
Fig.2 Pin configuration DHVQFN16.
2003 May 164
Philips SemiconductorsProduct specification
Dual 4-channel analog multiplexer,
demultiplexer
S0
S1
E
13
1Z
2Z
1Y0
12
1Y1
14
1Y2
15
1Y3
11
2Y0
2Y1
2Y2
2Y3
3
1
5
2
4
MNB040
handbook, halfpage
10
9
6
Fig.3 Logic symbol.
handbook, halfpage
74HC4052; 74HCT4052
10
0
0
1
G4
4 ×
MDX
3
MNB041
1
0
5
1
2
2
4
3
12
14
15
11
9
6
3
13
Fig.4 IEC logic symbol.
handbook, full pagewidth
S0
S1
V
CC
16
10
LOGIC
LEVEL
CONVERSION
9
6
E
GND
1 - OF - 4
DECODER
78
V
EE
13
12
14
15
11
MNB042
1Z
1Y0
1Y1
1Y2
1Y3
1
2Y0
5
2Y1
2
2Y2
4
2Y3
3
2Z
Fig.5 Functional diagram.
2003 May 165
Philips SemiconductorsProduct specification
Dual 4-channel analog multiplexer,
74HC4052; 74HCT4052
demultiplexer
handbook, full pagewidth
V
CC
V
CC
V
CC
V
from
logic
EE
Fig.6 Schematic diagram (one switch).
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to VEE= GND
(ground = 0 V); note 1.
nYn
nZ
V
EE
V
CC
V
EE
MNB043
SYMBOLPARAMETERCONDITIONSMIN.MAX.UNIT
V
CC
I
IK
I
SK
I
S
I
EE
I
CC;IGND
T
stg
P
tot
P
S
supply voltage−0.5+11.0V
input diode currentVI<−0.5 V or VI> VCC+ 0.5 V−±20mA
switch diode currentVS<−0.5 V or VS> VCC+ 0.5 V−±20mA
switch current−0.5 V < VS< VCC+ 0.5 V−±25mA
VEE current−±20mA
VCC or GND current−±50mA
storage temperature−65+150°C
power dissipationT
= −40 to +125 °C; note−500mW
amb
power dissipation per switch−100mW
Notes
1. To avoid drawing V
current out of pins nZ, when switch current flows in pins nYn, the voltage drop across the
CC
bidirectional switch must not exceed 0.4 V. If the switch current flows into pins nZ, no VCC current will flow out of
pins nYn. In this case thereis no limit for the voltage drop across theswitch, but the voltages at pins nYn and nZmay
not exceed VCC or VEE.
2. For DIP16 packages: above 70 °C derate linearly with 12 mW/K.
For SO16 packages: above 70 °C derate linearly with 8 mW/K.
For SSOP16 and TSSOP16 packages: above 60 °C derate linearly with 5.5 mW/K.
For DHVQFN16 packages: above 60 °C derate linearly with 4.5 mW/K.
input rise and fall timesVCC= 2.0 V−6.01000−6.0500ns
V
= 4.5 V−6.0500−6.0500ns
CC
V
= 6.0 V−6.0400−6.0500ns
CC
V
= 10.0 V−6.0250−6.0500ns
CC
74HC4052; 74HCT4052
74HC405274HCT4052
MIN.TYP.MAX.MIN.TYP.MAX.
2.05.010.02.05.010.0V
GND−V
CC
EE
−V
CC
V
EE
−V
−40+25+85−40+25+85°C
−40−+125−40−+125°C
CC
CC
UNIT
V
V
12
handbook, halfpage
VCC − GND
(V)
8
4
0
operating area
0412
8
VCC − VEE (V)
MNB044
Fig.7Guaranteed operating area as a function of
the supply voltages for 74HC4052.
12
handbook, halfpage
VCC − GND
(V)
10
8
6
4
2
0
04 128
operating area
VCC − VEE (V)
MNB045
Fig.8Guaranteed operating area as a function of
the supply voltages for 74HCT4052.
2003 May 167
Philips SemiconductorsProduct specification
Dual 4-channel analog multiplexer,
74HC4052; 74HCT4052
demultiplexer
DC CHARACTERISTICS
Family 74HC4052
Visis the input voltage at pins nYn or nZ, whichever is assigned as an input; Vosis the output voltage at pins nZ or nYn,
whichever is assigned as an output; voltages are referenced to GND (ground = 0 V).
SYMBOLPARAMETER
T
= −40 to +85 °C; note 1
amb
V
IH
HIGH-level input
voltage
V
IL
LOW-level input
voltage
I
LI
I
S(OFF)
input leakage currentVI=VCCor GND6.00−−±1.0µA
analog switch
OFF-state current
I
S(ON)
analog switch
ON-state current
I
CC
quiescent supply
current
VI=VIHor VIL;
VS =VCC− VEE; see Fig.9
per channel10.00−−±1.0µA
all channels10.00−−±2.0µA
VI=VIHor VIL;
VS =VCC− VEE; see Fig.10
VI=VCCor GND;
Vis=VEEor VCC;
Vos=VCCor V
TEST CONDITIONS
OTHERV
2.0−1.51.2−V
4.5−3.152.4−V
6.0−4.23.2−V
9.0−6.34.7−V
2.0−−0.80.5V
4.5−−2.11.35V
6.0−−2.81.8V
9.0−−4.32.7V
10.00−−±2.0µA
10.00−−±2.0µA
6.00−−80.0µA
10.00−−160.0 µA
EE
(V)VEE(V)
CC
MIN. TYP. MAX. UNIT
2003 May 168
Philips SemiconductorsProduct specification
Dual 4-channel analog multiplexer,
demultiplexer
SYMBOLPARAMETER
T
= −40 to +125 °C
amb
V
IH
V
IL
I
LI
I
S(OFF)
I
S(ON)
I
CC
Note
1. All typical values are measured at T
HIGH-level input
voltage
LOW-level input
voltage
input leakage currentVI=VCCor GND6.00−−±1.0µA
analog switch
OFF-state current
VI=VIHor VIL;
VS =VCC− VEE; see Fig.9
per channel10.00−−±1.0µA
all channels10.00−−±2.0µA
analog switch
ON-state current
quiescent supply
current
VI=VIHor VIL;
VS =VCC− VEE; see Fig.10
VI=VCCor GND;
Vis=VEEor VCC;
Vos=VCCor V
=25°C.
amb
TEST CONDITIONS
OTHERV
2.0−1.5−−V
4.5−3.15−− V
6.0−4.2−−V
9.0−6.3−−V
2.0−−−0.5V
4.5−−−1.35V
6.0−−−1.8V
9.0−−−2.7V
10.00−−±2.0µA
10.00−−±2.0µA
6.00−−160µA
10.00−−320.0 µA
EE
(V)VEE(V)
CC
74HC4052; 74HCT4052
MIN. TYP. MAX. UNIT
2003 May 169
Philips SemiconductorsProduct specification
Dual 4-channel analog multiplexer,
74HC4052; 74HCT4052
demultiplexer
Family 74HCT4052
Visis the input voltage at pins nYn or nZ, whichever is assigned as an input; Vosis the output voltage at pins nZ or nYn,
whichever is assigned as an output; voltages are referenced to GND (ground = 0 V).
SYMBOLPARAMETER
= −40 to +85 °C; note 1
T
amb
V
IH
HIGH-level input
voltage
V
IL
LOW-level input
voltage
I
LI
I
S(OFF)
input leakage currentVI=VCCor GND5.50−−±1.0µA
analog switch
OFF-state current
I
S(ON)
analog switch
ON-state current
I
CC
quiescent supply
current
∆I
CC
additional quiescent
supply current per
input
T
= −40 to +125 °C
amb
V
IH
HIGH-level input
voltage
V
IL
LOW-level input
voltage
I
LI
I
S(OFF)
input leakage currentVI=VCCor GND5.50−−±1.0µA
analog switch
OFF-state current
I
S(ON)
analog switch
ON-state current
I
CC
quiescent supply
current
∆I
CC
additional quiescent
supply current per
input
VI=VIHor VIL;
VS =VCC− VEE; see Fig.9
per channel10.00−−±1.0µA
all channels10.00−−±2.0µA
VI=VIHor VIL;
VS =VCC− VEE; see Fig.10
VI=VCCor GND;
Vis=VEEor VCC;
Vos=VCCor V
VI=VCC− 2.1 V;otherinputs
at VCC or GND
VI=VIHor VIL;
VS =VCC− VEE; see Fig.9
per channel10.00−−±1.0µA
all channels10.00−−±2.0µA
VI=VIHor VIL;
VS =VCC− VEE; see Fig.10
VI=VCCor GND;
Vis=VEEor VCC;
Vos=VCCor V
VI=VCC− 2.1 V;otherinputs
at VCC or GND
TEST CONDITIONS
OTHERV
4.5 to 5.5 −2.01.6−V
4.5 to 5.5 −−1.20.8V
10.00−−±2.0µA
5.50−−80.0µA
5.0−5.0−−160.0 µA
EE
4.5 to 5.5 0−45202.5 µA
4.5 to 5.5 −2.0−− V
4.5 to 5.5 −−−0.8V
10.00−−±2.0µA
5.50−−160.0 µA
5.0−5.0−−320.0 µA
EE
4.5 to 5.5 0−−220.5 µA
(V)VEE(V)
CC
MIN. TYP. MAX. UNIT
Note
1. All typical values are measured at T
amb
=25°C.
2003 May 1610
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