Product specification
Supersedes data of 1997 Aug 26
2003 Jun 30
Philips SemiconductorsProduct specification
Quad 2-input NAND gate74HC00; 74HCT00
FEATURES
• Complies with JEDEC standard no. 8-1A
• ESD protection:
HBM EIA/JESD22-A114-A exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V
• Specified from −40 to +85 °C and −40 to +125 °C.
DESCRIPTION
The 74HC00/74HCT00 are high-speed Si-gate CMOS
devices and are pin compatible with low power Schottky
TTL (LSTTL). They are specified in compliance with
JEDEC standard no. 7A.
The 74HC00/74HCT00 provide the 2-input NAND
function.
QUICK REFERENCE DATA
GND = 0 V; T
=25°C; tr=tf= 6 ns.
amb
SYMBOLPARAMETERCONDITIONS
t
PHL/tPLH
C
I
C
PD
propagation delay nA, nB to nYCL= 15 pF; VCC= 5 V710ns
input capacitance3.53.5pF
power dissipation capacitance per gate notes 1 and 22222pF
Notes
1. C
is used to determine the dynamic power dissipation (PDin µW).
PD
PD=CPD× V
2
× fi× N+Σ(CL× V
CC
2
× fo) where:
CC
fi= input frequency in MHz;
fo= output frequency in MHz;
= output load capacitance in pF;
C
L
VCC= supply voltage in Volts;
N = total load switching outputs;
Σ(CL× V
2
× fo) = sum of the outputs.
CC
2. For 74HC00 the condition is VI= GND to VCC.
For 74HCT00 the condition is VI= GND to VCC− 1.5 V.
TYPICAL
UNIT
74HC0074HCT00
FUNCTION TABLE
See note 1.
INPUTOUTPUT
nAnBnY
LLH
LHH
HLH
HHL
Note
1. H = HIGH voltage level;
L = LOW voltage level.
2003 Jun 302
Philips SemiconductorsProduct specification
Quad 2-input NAND gate74HC00; 74HCT00
ORDERING INFORMATION
PACKAGE
TYPE NUMBER
74HC00N−40to+125°C14DIP14plasticSOT27-1
74HCT00N−40 to +125 °C14DIP14plasticSOT27-1
74HC00D−40to+125°C14SO14plasticSOT108-1
74HCT00D−40 to +125 °C14SO14plasticSOT108-1
74HC00DB−40 to +125 °C14SSOP14plasticSOT337-1
74HCT00DB−40 to +125 °C14SSOP14plasticSOT337-1
74HC00PW−40 to +125 °C14TSSOP14plasticSOT402-1
74HCT00PW−40 to +125 °C14TSSOP14plasticSOT402-1
74HC00BQ−40 to +125 °C14DHVQFN14plasticSOT762-1
74HCT00BQ−40 to +125 °C14DHVQFN14plasticSOT762-1
In accordance with theAbsolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V).
SYMBOLPARAMETERCONDITIONSMIN.MAX.UNIT
V
CC
I
IK
I
OK
I
O
supply voltage−0.5+7.0V
input diode currentVI< −0.5 V or VI>VCC+ 0.5 V−±20mA
output diode currentVO< −0.5 V or VO>VCC+ 0.5 V−±20mA
output source or sink
−0.5V<VO<VCC+ 0.5 V−±25mA
current
I
, I
CC
T
stg
P
tot
GNDVCC
or GND current−±50mA
storage temperature−65+150°C
power dissipationT
= −40 to +125 °C; note 1−500mW
amb
Note
1. For DIP14 packages: above 70 °C derate linearly with 12 mW/K.
For SO14 packages: above 70 °C derate linearly with 8 mW/K.
For SSOP14 and TSSOP14 packages: above 60 °C derate linearly with 5.5 mW/K.
For DHVQFN14 packages: above 60 °C derate linearly with 4.5 mW/K.
2003 Jun 305
Philips SemiconductorsProduct specification
Quad 2-input NAND gate74HC00; 74HCT00
DC CHARACTERISTICS
Type 74HC00
At recommended operating conditions; voltages are referenced to GND (ground=0V).
SYMBOLPARAMETER
T
= −40 to +85 °C; note 1
amb
V
IH
V
IL
V
OH
V
OL
I
LI
I
OZ
I
CC
HIGH-level input voltage2.01.51.2−V
LOW-level input voltage2.0−0.80.5V
HIGH-level output voltageVI=VIH or V
LOW-level output voltageVI=VIH or V
input leakage currentVI=VCC or GND6.0−−±1.0µA
3-state output OFF current VI=VIH or VIL;
quiescent supply currentVI=VCC or GND; IO= 0 6.0−−20µA
TEST CONDITIONS
MIN.TYP.MAX.UNIT
OTHERV
CC
(V)
4.53.152.4−V
6.04.23.2−V
4.5−2.11.35V
6.0−2.81.8V
IL
IO= −20 µA2.01.92.0−V
I
= −20 µA4.54.44.5−V
O
I
= −20 µA6.05.96.0−V
O
I
= −4.0 mA4.53.844.32−V
O
I
= −5.2 mA6.05.345.81−V
O
IL
IO=20µA2.0−00.1V
I
=20µA4.5−00.1V
O
I
=20µA6.0−00.1V
O
I
= 4.0 mA4.5−0.150.33V
O
I
= 5.2 mA6.0−0.160.33V
O
6.0−−±.5.0µA
VO=VCC or GND
2003 Jun 306
Philips SemiconductorsProduct specification
Quad 2-input NAND gate74HC00; 74HCT00
SYMBOLPARAMETER
T
= −40 to +125 °C
amb
V
IH
V
IL
V
OH
V
OL
I
LI
I
OZ
I
CC
HIGH-level input voltage2.01.5−−V
LOW-level input voltage2.0−−0.5V
HIGH-level output voltageVI=VIH or V
LOW-level output voltageVI=VIH or V
input leakage currentVI=VCC or GND6.0−−±1.0µA
3-state output OFF current VI=VIH or VIL;
quiescent supply currentVI=VCC or GND; IO= 0 6.0−−40µA
Note
1. All typical values are measured at T
TEST CONDITIONS
MIN.TYP.MAX.UNIT
OTHERV
CC
(V)
4.53.15−−V
6.04.2−−V
4.5−−1.35V
6.0−−1.8V
IL
IO= −20 µA2.01.9−−V
I
=−20 µA4.54.4−−V
O
I
=−20 µA6.05.9−−V
O
=−4.0 mA4.53.7−−V
I
O
I
=−5.2 mA6.05.2−−V
O
IL
IO=20µA2.0−−0.1V
I
=20µA4.5−−0.1V
O
=20µA6.0−−0.1V
I
O
I
= 4.0 mA4.5−−0.4V
O
I
= 5.2 mA6.0−−0.4V
O
6.0−−±10.0µA
VO=VCC or GND
=25°C.
amb
2003 Jun 307
Philips SemiconductorsProduct specification
Quad 2-input NAND gate74HC00; 74HCT00
Type 74HCT00
At recommended operating conditions; voltages are referenced to GND (ground=0V).
SYMBOLPARAMETER
T
= −40 to +85 °C; note 1
amb
V
IH
V
IL
V
OH
V
OL
I
LI
I
OZ
I
CC
∆I
CC
T
= −40 to +125 °C
amb
V
IH
V
IL
V
OH
V
OL
I
LI
I
OZ
I
CC
∆I
CC
HIGH-level input voltage4.5 to 5.52.01.6−V
LOW-level input voltage4.5 to 5.5−1.20.8V
HIGH-level output voltageVI=VIH or V
LOW-level output voltageVI=VIH or V
input leakage currentVI=VCC or GND5.5−−±1.0µA
3-state output OFF currentVI=VIHor VIL;
quiescent supply currentVI=VCC or GND;
additional supply current per inputVI=VCC− 2.1 V;
HIGH-level input voltage4.5 to 5.52.0−−V
LOW-level input voltage4.5 to 5.5−−0.8V
HIGH-level output voltageVI=VIH or V
LOW-level output voltageVI=VIH or V
input leakage currentVI=VCCor GND5.5−−±1.0µA
3-state output OFF currentVI=VIH or VIL;
quiescent supply currentVI=VCC or GND;
additional supply current per inputVI=VCC− 2.1 V;
TEST CONDITIONS
MIN.TYP.MAX.UNIT
OTHERV
IL
CC
(V)
IO= −20 µA4.54.44.5−V
I
= −4.0 mA4.53.844.32−V
O
IL
IO=20µA4.5−00.1V
= 4.0 mA4.5−0.150.33V
I
O
5.5−−±5.0µA
VO=VCCor GND;
IO=0
5.5−−20µA
IO=0
4.5 to 5.5−150675µA
IO=0
IL
IO= −20 µA4.54.4−−V
I
=−4.0 mA4.53.7−−V
O
IL
IO=20µA4.5−−0.1V
I
= 4.0 mA4.5−−0.4V
O
5.5−−±10µA
VO=VCCor GND;
IO=0
5.5−−40µA
IO=0
4.5 to 5.5−−735µA
IO=0
Note
1. All typical values are measured at T
amb
=25°C.
2003 Jun 308
Philips SemiconductorsProduct specification
Quad 2-input NAND gate74HC00; 74HCT00
AC CHARACTERISTICS
Type 74HC00
GND = 0 V; tr=tf= 6 ns; CL=50pF.
SYMBOLPARAMETER
T
= −40 to +85 °C; note 1
amb
t
PHL/tPLH
t
THL/tTLH
T
amb
t
PHL/tPLH
t
THL/tTLH
propagation delay nA, nB to nYsee Fig.62.0−25115ns
output transition time2.0−1995ns
= −40 to +125 °C
propagation delay nA, nB to nYsee Fig.62.0−−135ns
output transition time2.0−−110ns
Note
1. All typical values are measured at T
amb
TEST CONDITIONS
MIN.TYP.MAX.UNIT
WAVEFORMSV
CC
(V)
see Fig.64.5−923ns
see Fig.66.0−720ns
4.5−719ns
6.0−616ns
see Fig.64.5−−27ns
see Fig.66.0−−23ns
4.5−−22ns
6.0−−19ns
=25°C.
Type 74HCT00
GND = 0 V; tr=tf= 6 ns; CL=50pF
SYMBOLPARAMETER
T
= −40 to +85 °C; note 1
amb
t
PHL/tPLH
t
THL/tTLH
T
amb
t
PHL/tPLH
t
THL/tTLH
propagation delay nA, nB to nYsee Fig.64.5−1224ns
output transition time4.5−−29ns
= −40 to +125 °C
propagation delay nA, nB to nYsee Fig.64.5−−29ns
output transition time4.5−−22ns
Note
1. All typical values are measured at T
amb
=25°C.
TEST CONDITIONS
WAVEFORMSV
CC
MIN.TYPMAX.UNIT
(V)
2003 Jun 309
Philips SemiconductorsProduct specification
Quad 2-input NAND gate74HC00; 74HCT00
AC WAVEFORMS
handbook, halfpage
74HC00: VM= 50%; VI= GND to VCC.
74HCT00: VM= 1.3 V; VI= GND to 3 V.
Fig.6 Waveforms showing the input (nA, nB) to output (nY) propagation delays.
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
UNIT
mm
inches
Note
1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.
max.
OUTLINE
VERSION
SOT27-1
A
min.
A
12
max.
IEC JEDEC JEITA
050G04MO-001SC-501-14
b
1.73
1.13
0.068
0.044
b
0.53
0.38
0.021
0.015
1
cD
0.36
0.23
0.014
0.009
REFERENCES
(1)(1)
19.50
18.55
0.77
0.73
EeM
6.48
6.20
0.26
0.24
2003 Jun 3011
M
e
L
1
3.60
3.05
0.14
0.12
E
8.25
7.80
0.32
0.31
EUROPEAN
PROJECTION
10.0
8.3
0.39
0.33
H
0.2542.547.62
ISSUE DATE
w
0.010.10.3
99-12-27
03-02-13
max.
2.24.20.513.2
0.0870.170.020.13
(1)
Z
Philips SemiconductorsProduct specification
Quad 2-input NAND gate74HC00; 74HCT00
SO14: plastic small outline package; 14 leads; body width 3.9 mm
D
c
y
Z
14
pin 1 index
1
e
8
A
7
w M
b
p
SOT108-1
E
H
E
2
A
1
L
detail X
A
X
v M
A
Q
(A )
A
3
θ
L
p
02.55 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
UNIT
mm
inches
A
max.
1.75
0.069
A
1
0.25
0.10
0.010
0.004
A2A
1.45
1.25
0.057
0.049
0.25
0.01
b
3
p
0.49
0.25
0.36
0.19
0.019
0.0100
0.014
0.0075
(1)E(1)
cD
8.75
8.55
0.35
0.34
eHELLpQZywv θ
4.0
1.27
3.8
0.16
0.15
0.05
0.244
0.228
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
OUTLINE
VERSION
SOT108-1
IEC JEDEC JEITA
076E06 MS-012
REFERENCES
2003 Jun 3012
6.2
5.8
1.05
0.041
1.0
0.4
0.039
0.016
0.7
0.25
0.6
0.028
0.010.004
0.024
EUROPEAN
PROJECTION
0.250.1
0.01
(1)
0.7
0.3
0.028
0.012
ISSUE DATE
99-12-27
03-02-19
o
8
o
0
Philips SemiconductorsProduct specification
Quad 2-input NAND gate74HC00; 74HCT00
SSOP14: plastic shrink small outline package; 14 leads; body width 5.3 mm
D
c
y
Z
14
pin 1 index
8
A
2
A
E
H
E
1
SOT337-1
A
X
v M
A
Q
(A )
L
p
L
A
3
θ
p
7
b
p
cD
0.20
0.09
REFERENCES
MO-150
w M
02.55 mm
scale
(1)E(1)
6.4
5.4
6.0
0.651.250.2
5.2
1
e
DIMENSIONS (mm are the original dimensions)
mm
OUTLINE
VERSION
SOT337-1
A
max.
2
0.21
0.05
1.80
1.65
IEC JEDEC JEITA
0.25
0.38
0.25
UNITA1A2A3b
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
2003 Jun 3013
detail X
eHELLpQZywv θ
7.9
7.6
1.03
0.63
0.9
0.7
EUROPEAN
PROJECTION
0.130.1
(1)
1.4
0.9
ISSUE DATE
99-12-27
03-02-19
o
8
o
0
Philips SemiconductorsProduct specification
Quad 2-input NAND gate74HC00; 74HCT00
TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm
D
c
y
Z
14
pin 1 index
8
17
w
b
e
p
M
A
2
A
1
E
H
E
L
detail X
SOT402-1
A
X
v
M
A
Q
(A )
3
A
θ
L
p
02.55 mm
scale
DIMENSIONS (mm are the original dimensions)
UNITA1A2A
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
A
max.
0.15
mm
1.1
OUTLINE
VERSION
SOT402-1 MO-153
0.05
0.95
0.80
IEC JEDEC JEITA
0.25
b
3
p
0.30
0.19
(1)E(2)(1)
cD
0.2
5.1
4.5
0.1
REFERENCES
4.9
4.3
0.65
2003 Jun 3014
eHELLpQZywv θ
6.6
6.2
0.75
0.50
0.4
0.3
EUROPEAN
PROJECTION
0.130.10.21
0.72
0.38
ISSUE DATE
99-12-27
03-02-18
o
8
o
0
Philips SemiconductorsProduct specification
Quad 2-input NAND gate74HC00; 74HCT00
DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;
14 terminals; body 2.5 x 3 x 0.85 mm
A
D
B
A
A
E
1
SOT762-1
c
terminal 1
index area
terminal 1
index area
L
1
E
h
14
DIMENSIONS (mm are the original dimensions)
(1)
A
UNIT
mm
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
max.
A
0.05
0.00
b
1
0.30
0.18
e
26
13
c
0.2
e
1
b
9
D
h
02.55 mm
D
3.1
2.9
(1)
1.65
1.35
(1)
E
2.6
2.4
E
1.15
0.85
h
D
h
v
w
7
e
8
scale
0.51
detail X
C
M
ACCB
M
e
L
1
0.5
2
0.3
y
w
0.1v0.05
C
1
ye
y
0.050.1
1
y
X
OUTLINE
VERSION
SOT762-1MO-241- - -- - -
IEC JEDEC JEITA
REFERENCES
2003 Jun 3015
EUROPEAN
PROJECTION
ISSUE DATE
02-10-17
03-01-27
Philips SemiconductorsProduct specification
Quad 2-input NAND gate74HC00; 74HCT00
DATA SHEET STATUS
LEVEL
DATA SHEET
STATUS
(1)
PRODUCT
STATUS
(2)(3)
DEFINITION
IObjective dataDevelopmentThis data sheet contains data from the objective specification for product
development. Philips Semiconductors reserves the right to change the
specification in any manner without notice.
IIPreliminary data QualificationThis data sheet contains data from the preliminary specification.
Supplementary data will be published at a later date. Philips
Semiconductors reserves the right to change the specification without
notice, in order to improve the design and supply the best possible
product.
IIIProduct dataProductionThis data sheet contains data from the product specification. Philips
Semiconductors reserves the right to make changes at any time in order
to improve the design, manufacturing and supply. Relevant changes will
be communicated via a Customer Product/Process Change Notification
(CPCN).
Notes
1. Please consult the most recently issued data sheet before initiating or completing a design.
2. The product status of the device(s) described in this data sheet may have changed since this data sheet was
published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.
3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
DEFINITIONS
DISCLAIMERS
Short-form specification The data in a short-form
specification is extracted from a full data sheet with the
same type number and title. For detailed information see
the relevant data sheet or data handbook.
Limiting values definition Limiting values given are in
accordance with the Absolute Maximum Rating System
(IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device.
These are stress ratings only and operation of the device
attheseorat any other conditions above those given in the
Characteristics sections of the specification is not implied.
Exposure to limiting values for extended periods may
affect device reliability.
Application information Applications that are
described herein for any of these products are for
illustrative purposes only. Philips Semiconductors make
norepresentationorwarrantythatsuchapplicationswillbe
suitable for the specified use without further testing or
modification.
Life support applications These products are not
designed for use in life support appliances, devices, or
systems where malfunction of these products can
reasonably be expected to result in personal injury.Philips
Semiconductorscustomersusingorsellingtheseproducts
for use in such applications do so at their own risk and
agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
Right to make changes Philips Semiconductors
reserves the right to make changes in the products including circuits, standard cells, and/or software described or contained herein in order to improve design
and/or performance. When the product is in full production
(status ‘Production’), relevant changes will be
communicated via a Customer Product/Process Change
Notification (CPCN). Philips Semiconductors assumes no
responsibility or liability for the use of any of these
products, conveys no licence or title under any patent,
copyright, or mask work right to these products, and
makes no representations or warranties that these
products are free from patent, copyright, or mask work
right infringement, unless otherwise specified.
2003 Jun 3016
Philips Semiconductors – a w orldwide compan y
Contact information
For additional information please visit http://www.semiconductors.philips.com.Fax: +31 40 27 24825
For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands613508/03/pp17 Date of release: 2003 Jun 30Document order number: 9397 750 11258
SCA75
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